xref: /onnv-gate/usr/src/uts/common/sys/pci.h (revision 10923:df470fd79c3c)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
51865Sdilpreet  * Common Development and Distribution License (the "License").
61865Sdilpreet  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
229284SCasper.Dik@Sun.COM  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #ifndef	_SYS_PCI_H
270Sstevel@tonic-gate #define	_SYS_PCI_H
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #ifdef	__cplusplus
300Sstevel@tonic-gate extern "C" {
310Sstevel@tonic-gate #endif
320Sstevel@tonic-gate 
330Sstevel@tonic-gate /*
340Sstevel@tonic-gate  * PCI Configuration Header offsets
350Sstevel@tonic-gate  */
360Sstevel@tonic-gate #define	PCI_CONF_VENID		0x0	/* vendor id, 2 bytes */
370Sstevel@tonic-gate #define	PCI_CONF_DEVID		0x2	/* device id, 2 bytes */
380Sstevel@tonic-gate #define	PCI_CONF_COMM		0x4	/* command register, 2 bytes */
390Sstevel@tonic-gate #define	PCI_CONF_STAT		0x6	/* status register, 2 bytes */
400Sstevel@tonic-gate #define	PCI_CONF_REVID		0x8	/* revision id, 1 byte */
410Sstevel@tonic-gate #define	PCI_CONF_PROGCLASS	0x9	/* programming class code, 1 byte */
420Sstevel@tonic-gate #define	PCI_CONF_SUBCLASS	0xA	/* sub-class code, 1 byte */
430Sstevel@tonic-gate #define	PCI_CONF_BASCLASS	0xB	/* basic class code, 1 byte */
440Sstevel@tonic-gate #define	PCI_CONF_CACHE_LINESZ	0xC	/* cache line size, 1 byte */
450Sstevel@tonic-gate #define	PCI_CONF_LATENCY_TIMER	0xD	/* latency timer, 1 byte */
460Sstevel@tonic-gate #define	PCI_CONF_HEADER		0xE	/* header type, 1 byte */
470Sstevel@tonic-gate #define	PCI_CONF_BIST		0xF	/* builtin self test, 1 byte */
480Sstevel@tonic-gate 
490Sstevel@tonic-gate /*
500Sstevel@tonic-gate  * Header type 0 offsets
510Sstevel@tonic-gate  */
520Sstevel@tonic-gate #define	PCI_CONF_BASE0		0x10	/* base register 0, 4 bytes */
530Sstevel@tonic-gate #define	PCI_CONF_BASE1		0x14	/* base register 1, 4 bytes */
540Sstevel@tonic-gate #define	PCI_CONF_BASE2		0x18	/* base register 2, 4 bytes */
550Sstevel@tonic-gate #define	PCI_CONF_BASE3		0x1c	/* base register 3, 4 bytes */
560Sstevel@tonic-gate #define	PCI_CONF_BASE4		0x20	/* base register 4, 4 bytes */
570Sstevel@tonic-gate #define	PCI_CONF_BASE5		0x24	/* base register 5, 4 bytes */
580Sstevel@tonic-gate #define	PCI_CONF_CIS		0x28	/* Cardbus CIS Pointer */
590Sstevel@tonic-gate #define	PCI_CONF_SUBVENID	0x2c	/* Subsystem Vendor ID */
600Sstevel@tonic-gate #define	PCI_CONF_SUBSYSID	0x2e	/* Subsystem ID */
610Sstevel@tonic-gate #define	PCI_CONF_ROM		0x30	/* ROM base register, 4 bytes */
620Sstevel@tonic-gate #define	PCI_CONF_CAP_PTR	0x34	/* capabilities pointer, 1 byte */
630Sstevel@tonic-gate #define	PCI_CONF_ILINE		0x3c	/* interrupt line, 1 byte */
640Sstevel@tonic-gate #define	PCI_CONF_IPIN		0x3d	/* interrupt pin, 1 byte */
650Sstevel@tonic-gate #define	PCI_CONF_MIN_G		0x3e	/* minimum grant, 1 byte */
660Sstevel@tonic-gate #define	PCI_CONF_MAX_L		0x3f	/* maximum grant, 1 byte */
670Sstevel@tonic-gate 
680Sstevel@tonic-gate /*
690Sstevel@tonic-gate  * PCI to PCI bridge configuration space header format
700Sstevel@tonic-gate  */
710Sstevel@tonic-gate #define	PCI_BCNF_PRIBUS		0x18	/* primary bus number */
720Sstevel@tonic-gate #define	PCI_BCNF_SECBUS		0x19	/* secondary bus number */
730Sstevel@tonic-gate #define	PCI_BCNF_SUBBUS		0x1a	/* subordinate bus number */
740Sstevel@tonic-gate #define	PCI_BCNF_LATENCY_TIMER	0x1b
750Sstevel@tonic-gate #define	PCI_BCNF_IO_BASE_LOW	0x1c
760Sstevel@tonic-gate #define	PCI_BCNF_IO_LIMIT_LOW	0x1d
770Sstevel@tonic-gate #define	PCI_BCNF_SEC_STATUS	0x1e
780Sstevel@tonic-gate #define	PCI_BCNF_MEM_BASE	0x20
790Sstevel@tonic-gate #define	PCI_BCNF_MEM_LIMIT	0x22
800Sstevel@tonic-gate #define	PCI_BCNF_PF_BASE_LOW	0x24
810Sstevel@tonic-gate #define	PCI_BCNF_PF_LIMIT_LOW	0x26
820Sstevel@tonic-gate #define	PCI_BCNF_PF_BASE_HIGH	0x28
830Sstevel@tonic-gate #define	PCI_BCNF_PF_LIMIT_HIGH	0x2c
840Sstevel@tonic-gate #define	PCI_BCNF_IO_BASE_HI	0x30
850Sstevel@tonic-gate #define	PCI_BCNF_IO_LIMIT_HI	0x32
860Sstevel@tonic-gate #define	PCI_BCNF_CAP_PTR	0x34
870Sstevel@tonic-gate #define	PCI_BCNF_ROM		0x38
880Sstevel@tonic-gate #define	PCI_BCNF_ILINE		0x3c
890Sstevel@tonic-gate #define	PCI_BCNF_IPIN		0x3d
900Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL		0x3e
910Sstevel@tonic-gate 
920Sstevel@tonic-gate #define	PCI_BCNF_BASE_NUM	0x2
930Sstevel@tonic-gate 
940Sstevel@tonic-gate /*
950Sstevel@tonic-gate  * PCI to PCI bridge control register (0x3e) format
960Sstevel@tonic-gate  */
970Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_PARITY_ENABLE	0x1
980Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_SERR_ENABLE	0x2
996313Skrishnae #define	PCI_BCNF_BCNTRL_ISA_ENABLE	0x4
1003499Srugrat #define	PCI_BCNF_BCNTRL_VGA_ENABLE	0x8
1010Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_MAST_AB_MODE	0x20
1020Sstevel@tonic-gate #define	PCI_BCNF_BCNTRL_DTO_STAT	0x400
1030Sstevel@tonic-gate 
1042284Srw148561 #define	PCI_BCNF_BCNTRL_RESET		0x0040
1052284Srw148561 #define	PCI_BCNF_BCNTRL_B2B_ENAB	0x0080
1062284Srw148561 
1070Sstevel@tonic-gate #define	PCI_BCNF_IO_MASK	0xf0
1080Sstevel@tonic-gate #define	PCI_BCNF_MEM_MASK	0xfff0
1090Sstevel@tonic-gate 
1100Sstevel@tonic-gate /*
1110Sstevel@tonic-gate  * Header type 2 (Cardbus) offsets
1120Sstevel@tonic-gate  */
1130Sstevel@tonic-gate #define	PCI_CBUS_SOCK_REG	0x10	/* Cardbus socket regs, 4 bytes */
1149284SCasper.Dik@Sun.COM #define	PCI_CBUS_CAP_PTR	0x14	/* Capability ptr, 1 byte */
1159284SCasper.Dik@Sun.COM #define	PCI_CBUS_RESERVED1	0x15	/* Reserved, 1 byte */
1160Sstevel@tonic-gate #define	PCI_CBUS_SEC_STATUS	0x16	/* Secondary status, 2 bytes */
1170Sstevel@tonic-gate #define	PCI_CBUS_PCI_BUS_NO	0x18	/* PCI bus number, 1 byte */
1180Sstevel@tonic-gate #define	PCI_CBUS_CBUS_NO	0x19	/* Cardbus bus number, 1 byte */
1190Sstevel@tonic-gate #define	PCI_CBUS_SUB_BUS_NO	0x1a	/* Subordinate bus number, 1 byte */
1200Sstevel@tonic-gate #define	PCI_CBUS_LATENCY_TIMER	0x1b	/* Cardbus latency timer, 1 byte */
1210Sstevel@tonic-gate #define	PCI_CBUS_MEM_BASE0	0x1c	/* Memory base reg 0, 4 bytes */
1220Sstevel@tonic-gate #define	PCI_CBUS_MEM_LIMIT0	0x20	/* Memory limit reg 0, 4 bytes */
1230Sstevel@tonic-gate #define	PCI_CBUS_MEM_BASE1	0x24	/* Memory base reg 1, 4 bytes */
1240Sstevel@tonic-gate #define	PCI_CBUS_MEM_LIMIT1	0x28	/* Memory limit reg 1, 4 bytes */
1250Sstevel@tonic-gate #define	PCI_CBUS_IO_BASE0	0x2c	/* IO base reg 0, 4 bytes */
1260Sstevel@tonic-gate #define	PCI_CBUS_IO_LIMIT0	0x30	/* IO limit reg 0, 4 bytes */
1270Sstevel@tonic-gate #define	PCI_CBUS_IO_BASE1	0x34	/* IO base reg 1, 4 bytes */
1280Sstevel@tonic-gate #define	PCI_CBUS_IO_LIMIT1	0x38	/* IO limit reg 1, 4 bytes */
1290Sstevel@tonic-gate #define	PCI_CBUS_ILINE		0x3c	/* interrupt line, 1 byte */
1300Sstevel@tonic-gate #define	PCI_CBUS_IPIN		0x3d	/* interrupt pin, 1 byte */
1310Sstevel@tonic-gate #define	PCI_CBUS_BRIDGE_CTRL	0x3e	/* Bridge control, 2 bytes */
1320Sstevel@tonic-gate #define	PCI_CBUS_SUBVENID	0x40	/* Subsystem Vendor ID, 2 bytes */
1330Sstevel@tonic-gate #define	PCI_CBUS_SUBSYSID	0x42	/* Subsystem ID, 2 bytes */
1340Sstevel@tonic-gate #define	PCI_CBUS_LEG_MODE_ADDR	0x44	/* PCCard 16bit IF legacy mode addr */
1350Sstevel@tonic-gate 
1360Sstevel@tonic-gate #define	PCI_CBUS_BASE_NUM	0x1	/* number of base registers */
1370Sstevel@tonic-gate 
1380Sstevel@tonic-gate /*
1390Sstevel@tonic-gate  * PCI command register bits
1400Sstevel@tonic-gate  */
1410Sstevel@tonic-gate #define	PCI_COMM_IO		0x1	/* I/O access enable */
1420Sstevel@tonic-gate #define	PCI_COMM_MAE		0x2	/* memory access enable */
1430Sstevel@tonic-gate #define	PCI_COMM_ME		0x4	/* master enable */
1440Sstevel@tonic-gate #define	PCI_COMM_SPEC_CYC	0x8
1450Sstevel@tonic-gate #define	PCI_COMM_MEMWR_INVAL	0x10
1460Sstevel@tonic-gate #define	PCI_COMM_PALETTE_SNOOP	0x20
1470Sstevel@tonic-gate #define	PCI_COMM_PARITY_DETECT	0x40
1480Sstevel@tonic-gate #define	PCI_COMM_WAIT_CYC_ENAB	0x80
1490Sstevel@tonic-gate #define	PCI_COMM_SERR_ENABLE	0x100
1500Sstevel@tonic-gate #define	PCI_COMM_BACK2BACK_ENAB	0x200
1510Sstevel@tonic-gate #define	PCI_COMM_INTX_DISABLE	0x400	/* INTx emulation disable */
1520Sstevel@tonic-gate 
1530Sstevel@tonic-gate /*
1540Sstevel@tonic-gate  * PCI Interrupt pin value
1550Sstevel@tonic-gate  */
1560Sstevel@tonic-gate #define	PCI_INTA	1
1570Sstevel@tonic-gate #define	PCI_INTB	2
1580Sstevel@tonic-gate #define	PCI_INTC	3
1590Sstevel@tonic-gate #define	PCI_INTD	4
1600Sstevel@tonic-gate 
1610Sstevel@tonic-gate /*
1620Sstevel@tonic-gate  * PCI status register bits
1630Sstevel@tonic-gate  */
1640Sstevel@tonic-gate #define	PCI_STAT_INTR		0x8	/* Interrupt state */
1650Sstevel@tonic-gate #define	PCI_STAT_CAP		0x10	/* Implements Capabilities */
1660Sstevel@tonic-gate #define	PCI_STAT_66MHZ		0x20	/* 66 MHz capable */
1670Sstevel@tonic-gate #define	PCI_STAT_UDF		0x40	/* UDF supported */
1680Sstevel@tonic-gate #define	PCI_STAT_FBBC		0x80	/* Fast Back-to-Back Capable */
1690Sstevel@tonic-gate #define	PCI_STAT_S_PERROR	0x100	/* Data Parity Reported */
1700Sstevel@tonic-gate #define	PCI_STAT_DEVSELT	0x600	/* Device select timing */
1710Sstevel@tonic-gate #define	PCI_STAT_S_TARG_AB	0x800	/* Signaled Target Abort */
1720Sstevel@tonic-gate #define	PCI_STAT_R_TARG_AB	0x1000	/* Received Target Abort */
1730Sstevel@tonic-gate #define	PCI_STAT_R_MAST_AB	0x2000	/* Received Master Abort */
1740Sstevel@tonic-gate #define	PCI_STAT_S_SYSERR	0x4000	/* Signaled System Error */
1750Sstevel@tonic-gate #define	PCI_STAT_PERROR		0x8000	/* Detected Parity Error */
1760Sstevel@tonic-gate 
1770Sstevel@tonic-gate /*
1780Sstevel@tonic-gate  * DEVSEL timing values
1790Sstevel@tonic-gate  */
1800Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_FAST	0x0000
1810Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_MEDIUM	0x0200
1820Sstevel@tonic-gate #define	PCI_STAT_DEVSELT_SLOW	0x0400
1830Sstevel@tonic-gate 
1840Sstevel@tonic-gate /*
1850Sstevel@tonic-gate  * BIST values
1860Sstevel@tonic-gate  */
1870Sstevel@tonic-gate #define	PCI_BIST_SUPPORTED	0x80
1880Sstevel@tonic-gate #define	PCI_BIST_GO		0x40
1890Sstevel@tonic-gate #define	PCI_BIST_RESULT_M	0x0f
1900Sstevel@tonic-gate #define	PCI_BIST_RESULT_OK	0x00
1910Sstevel@tonic-gate 
1920Sstevel@tonic-gate /*
1930Sstevel@tonic-gate  * PCI class codes
1940Sstevel@tonic-gate  */
1950Sstevel@tonic-gate #define	PCI_CLASS_NONE		0x0	/* class code for pre-2.0 devices */
1960Sstevel@tonic-gate #define	PCI_CLASS_MASS		0x1	/* Mass storage Controller class */
1970Sstevel@tonic-gate #define	PCI_CLASS_NET		0x2	/* Network Controller class */
1980Sstevel@tonic-gate #define	PCI_CLASS_DISPLAY	0x3	/* Display Controller class */
1990Sstevel@tonic-gate #define	PCI_CLASS_MM		0x4	/* Multimedia Controller class */
2000Sstevel@tonic-gate #define	PCI_CLASS_MEM		0x5	/* Memory Controller class */
2010Sstevel@tonic-gate #define	PCI_CLASS_BRIDGE	0x6	/* Bridge Controller class */
2020Sstevel@tonic-gate #define	PCI_CLASS_COMM		0x7	/* Communications Controller class */
2030Sstevel@tonic-gate #define	PCI_CLASS_PERIPH	0x8	/* Peripheral Controller class */
2040Sstevel@tonic-gate #define	PCI_CLASS_INPUT		0x9	/* Input Device class */
2050Sstevel@tonic-gate #define	PCI_CLASS_DOCK		0xa	/* Docking Station class */
2060Sstevel@tonic-gate #define	PCI_CLASS_PROCESSOR	0xb	/* Processor class */
2070Sstevel@tonic-gate #define	PCI_CLASS_SERIALBUS	0xc	/* Serial Bus class */
2080Sstevel@tonic-gate #define	PCI_CLASS_WIRELESS	0xd	/* Wireless Controller class */
2090Sstevel@tonic-gate #define	PCI_CLASS_INTIO		0xe	/* Intelligent IO Controller class */
2100Sstevel@tonic-gate #define	PCI_CLASS_SATELLITE	0xf	/* Satellite Communication class */
2110Sstevel@tonic-gate #define	PCI_CLASS_CRYPT		0x10	/* Encrytion/Decryption class */
2120Sstevel@tonic-gate #define	PCI_CLASS_SIGNAL	0x11	/* Signal Processing class */
2130Sstevel@tonic-gate 
2140Sstevel@tonic-gate /*
2150Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
2160Sstevel@tonic-gate  */
2170Sstevel@tonic-gate #define	PCI_NONE_NOTVGA		0x0	/* All devices except VGA compatible */
2180Sstevel@tonic-gate #define	PCI_NONE_VGA		0x1	/* VGA compatible */
2190Sstevel@tonic-gate 
2200Sstevel@tonic-gate /*
2210Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x1 (mass storage controllers)
2220Sstevel@tonic-gate  */
2230Sstevel@tonic-gate #define	PCI_MASS_SCSI		0x0	/* SCSI bus Controller */
2240Sstevel@tonic-gate #define	PCI_MASS_IDE		0x1	/* IDE Controller */
2253070Sanish #define	PCI_MASS_FD		0x2	/* Floppy disk Controller */
2260Sstevel@tonic-gate #define	PCI_MASS_IPI		0x3	/* IPI bus Controller */
2270Sstevel@tonic-gate #define	PCI_MASS_RAID		0x4	/* RAID Controller */
2280Sstevel@tonic-gate #define	PCI_MASS_ATA		0x5	/* ATA Controller */
2290Sstevel@tonic-gate #define	PCI_MASS_SATA		0x6	/* Serial ATA */
2303070Sanish #define	PCI_MASS_SAS		0x7	/* Serial Attached SCSI (SAS) Cntrlr */
2310Sstevel@tonic-gate #define	PCI_MASS_OTHER		0x80	/* Other Mass Storage Controller */
2320Sstevel@tonic-gate 
2330Sstevel@tonic-gate /*
2340Sstevel@tonic-gate  * programming interface for IDE (subclass 1)
2350Sstevel@tonic-gate  */
2360Sstevel@tonic-gate #define	PCI_IDE_IF_NATIVE_PRI	0x1	/* primary channel is native */
2370Sstevel@tonic-gate #define	PCI_IDE_IF_PROG_PRI	0x2	/* primary can operate in either mode */
2380Sstevel@tonic-gate #define	PCI_IDE_IF_NATIVE_SEC	0x4	/* secondary channel is native */
2390Sstevel@tonic-gate #define	PCI_IDE_IF_PROG_SEC	0x8	/* sec. can operate in either mode */
2400Sstevel@tonic-gate #define	PCI_IDE_IF_MASK		0xf	/* programming interface mask */
2410Sstevel@tonic-gate 
2420Sstevel@tonic-gate 
2430Sstevel@tonic-gate /*
2440Sstevel@tonic-gate  * programming interface for ATA (subclass 5)
2450Sstevel@tonic-gate  */
2460Sstevel@tonic-gate #define	PCI_ATA_IF_SINGLE_DMA	0x20	/* ATA controller with single DMA */
2470Sstevel@tonic-gate #define	PCI_ATA_IF_CHAINED_DMA	0x30	/* ATA controller with chained DMA */
2480Sstevel@tonic-gate 
2490Sstevel@tonic-gate /*
2503070Sanish  * programming interface for ATA (subclass 6) for SATA
2513070Sanish  */
2523070Sanish #define	PCI_SATA_VS_INTERFACE	0x0	/* SATA Ctlr Vendor Specific Intfc */
2533070Sanish #define	PCI_SATA_AHCI_INTERFACE	0x1	/* SATA Ctlr AHCI 1.0 Interface */
2543070Sanish #define	PCI_SATA_SSB_INTERFACE	0x2	/* Serial Storage Bus Interface */
2553070Sanish 
2563070Sanish /*
2573070Sanish  * programming interface for ATA (subclass 7) for SAS
2583070Sanish  */
2593070Sanish #define	PCI_SAS_CONTROLLER	0x0	/* SAS Controller */
2603070Sanish #define	PCI_SAS_BUS_INTERFACE	0x1	/* Serial Storage Bus Interface */
2613070Sanish 
2623070Sanish /*
2630Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x2 (Network controllers)
2640Sstevel@tonic-gate  */
2650Sstevel@tonic-gate #define	PCI_NET_ENET		0x0	/* Ethernet Controller */
2660Sstevel@tonic-gate #define	PCI_NET_TOKEN		0x1	/* Token Ring Controller */
2670Sstevel@tonic-gate #define	PCI_NET_FDDI		0x2	/* FDDI Controller */
2680Sstevel@tonic-gate #define	PCI_NET_ATM		0x3	/* ATM Controller */
2690Sstevel@tonic-gate #define	PCI_NET_ISDN		0x4	/* ISDN Controller */
2700Sstevel@tonic-gate #define	PCI_NET_WFIP		0x5	/* WorldFip Controller */
2710Sstevel@tonic-gate #define	PCI_NET_PICMG		0x6	/* PICMG 2.14 Multi Computing */
2720Sstevel@tonic-gate #define	PCI_NET_OTHER		0x80	/* Other Network Controller */
2730Sstevel@tonic-gate 
2740Sstevel@tonic-gate /*
2750Sstevel@tonic-gate  * PCI Sub-class codes - base class 03 (display controllers)
2760Sstevel@tonic-gate  */
2770Sstevel@tonic-gate #define	PCI_DISPLAY_VGA		0x0	/* VGA device */
2780Sstevel@tonic-gate #define	PCI_DISPLAY_XGA		0x1	/* XGA device */
2790Sstevel@tonic-gate #define	PCI_DISPLAY_3D		0x2	/* 3D controller */
2800Sstevel@tonic-gate #define	PCI_DISPLAY_OTHER	0x80	/* Other Display Device */
2810Sstevel@tonic-gate 
2820Sstevel@tonic-gate /*
2830Sstevel@tonic-gate  * programming interface for display for display class (subclass 0) VGA ctrlrs
2840Sstevel@tonic-gate  */
2850Sstevel@tonic-gate #define	PCI_DISPLAY_IF_VGA	0x0	/* VGA compatible */
2860Sstevel@tonic-gate #define	PCI_DISPLAY_IF_8514	0x1	/* 8514 compatible */
2870Sstevel@tonic-gate 
2880Sstevel@tonic-gate /*
2890Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x4 (multi-media devices)
2900Sstevel@tonic-gate  */
2910Sstevel@tonic-gate #define	PCI_MM_VIDEO		0x0	/* Video device */
2920Sstevel@tonic-gate #define	PCI_MM_AUDIO		0x1	/* Audio device */
2930Sstevel@tonic-gate #define	PCI_MM_TELEPHONY	0x2	/* Computer Telephony device */
2943070Sanish #define	PCI_MM_MIXED_MODE	0x3	/* Mixed Mode device */
2950Sstevel@tonic-gate #define	PCI_MM_OTHER		0x80	/* Other Multimedia Device */
2960Sstevel@tonic-gate 
2970Sstevel@tonic-gate /*
2980Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x5 (memory controllers)
2990Sstevel@tonic-gate  */
3000Sstevel@tonic-gate #define	PCI_MEM_RAM		0x0	/* RAM device */
3010Sstevel@tonic-gate #define	PCI_MEM_FLASH		0x1	/* FLASH device */
3020Sstevel@tonic-gate #define	PCI_MEM_OTHER		0x80	/* Other Memory Controller */
3030Sstevel@tonic-gate 
3040Sstevel@tonic-gate /*
3050Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x6 (Bridge devices)
3060Sstevel@tonic-gate  */
3070Sstevel@tonic-gate #define	PCI_BRIDGE_HOST		0x0	/* Host/PCI Bridge */
3080Sstevel@tonic-gate #define	PCI_BRIDGE_ISA		0x1	/* PCI/ISA Bridge */
3090Sstevel@tonic-gate #define	PCI_BRIDGE_EISA		0x2	/* PCI/EISA Bridge */
3100Sstevel@tonic-gate #define	PCI_BRIDGE_MC		0x3	/* PCI/MC Bridge */
3110Sstevel@tonic-gate #define	PCI_BRIDGE_PCI		0x4	/* PCI/PCI Bridge */
3120Sstevel@tonic-gate #define	PCI_BRIDGE_PCMCIA	0x5	/* PCI/PCMCIA Bridge */
3130Sstevel@tonic-gate #define	PCI_BRIDGE_NUBUS	0x6	/* PCI/NUBUS Bridge */
3140Sstevel@tonic-gate #define	PCI_BRIDGE_CARDBUS	0x7	/* PCI/CARDBUS Bridge */
3150Sstevel@tonic-gate #define	PCI_BRIDGE_RACE		0x8	/* RACE-way Bridge */
3160Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI	0x9	/* Semi-transparent PCI/PCI Bridge */
3170Sstevel@tonic-gate #define	PCI_BRIDGE_IB		0xA	/* InfiniBand/PCI host Bridge */
3183070Sanish #define	PCI_BRIDGE_AS		0xB	/* AS/PCI host Bridge */
3190Sstevel@tonic-gate #define	PCI_BRIDGE_OTHER	0x80	/* PCI/Other Bridge Device */
3200Sstevel@tonic-gate 
3210Sstevel@tonic-gate /*
3220Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
3230Sstevel@tonic-gate  */
3240Sstevel@tonic-gate #define	PCI_BRIDGE_PCI_IF_PCI2PCI	0x0	/* PCI-PCI bridge */
3250Sstevel@tonic-gate #define	PCI_BRIDGE_PCI_IF_SUBDECODE	0x1	/* Subtractive Decode */
3260Sstevel@tonic-gate 						/* PCI/PCI bridge */
3270Sstevel@tonic-gate 
3280Sstevel@tonic-gate /*
3290Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge
3300Sstevel@tonic-gate  */
3310Sstevel@tonic-gate #define	PCI_BRIDGE_RACE_IF_TRANSPARENT	0x0	/* Transport mode */
3320Sstevel@tonic-gate #define	PCI_BRIDGE_RACE_IF_ENDPOINT	0x1	/* Endpoint mode */
3330Sstevel@tonic-gate 
3340Sstevel@tonic-gate /*
3350Sstevel@tonic-gate  * programming interface for Bridges class 0x6 (subclass 09)
3360Sstevel@tonic-gate  * Semi-transparent PCI-to-PCI bridge
3370Sstevel@tonic-gate  */
3380Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI_IF_PRIMARY	0x40	/* primary PCI side bus */
3390Sstevel@tonic-gate 						/* facing system processor */
3400Sstevel@tonic-gate #define	PCI_BRIDGE_STPCI_IF_SECONDARY	0x80	/* secondary PCI side bus */
3410Sstevel@tonic-gate 						/* facing system processor */
3420Sstevel@tonic-gate 
3430Sstevel@tonic-gate /*
3443070Sanish  * programming interface for Bridges class 0x6 (subclass 0B) AS bridge
3453070Sanish  */
3463070Sanish #define	PCI_BRIDGE_AS_CUSTOM_INTFC	0x0	/* Custom interface */
3473070Sanish #define	PCI_BRIDGE_AS_PORTAL_INTFC	0x1	/* ASI-SIG Portal Interface */
3483070Sanish 
3493070Sanish /*
3500Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x7 (communication devices)
3510Sstevel@tonic-gate  */
3520Sstevel@tonic-gate #define	PCI_COMM_GENERIC_XT	0x0	/* XT Compatible Serial Controller */
3530Sstevel@tonic-gate #define	PCI_COMM_PARALLEL	0x1	/* Parallel Port Controller */
3540Sstevel@tonic-gate #define	PCI_COMM_MSC		0x2	/* Multiport Serial Controller */
3550Sstevel@tonic-gate #define	PCI_COMM_MODEM		0x3	/* Modem Controller */
3560Sstevel@tonic-gate #define	PCI_COMM_GPIB		0x4	/* GPIB Controller */
3570Sstevel@tonic-gate #define	PCI_COMM_SMARTCARD	0x5	/* Smart Card Controller */
3580Sstevel@tonic-gate #define	PCI_COMM_OTHER		0x80	/* Other Communications Controller */
3590Sstevel@tonic-gate 
3600Sstevel@tonic-gate /*
3610Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x0 (Serial)
3620Sstevel@tonic-gate  */
3630Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_GENERIC	0x0	/* Generic XT-compat serial */
3640Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16450	0x1	/* 16450-compat serial ctrlr */
3650Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16550	0x2	/* 16550-compat serial ctrlr */
3660Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16650	0x3	/* 16650-compat serial ctrlr */
3670Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16750	0x4	/* 16750-compat serial ctrlr */
3680Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16850	0x5	/* 16850-compat serial ctrlr */
3690Sstevel@tonic-gate #define	PCI_COMM_SERIAL_IF_16950	0x6	/* 16950-compat serial ctrlr */
3700Sstevel@tonic-gate 
3710Sstevel@tonic-gate /*
3720Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x1 (Parallel)
3730Sstevel@tonic-gate  */
3740Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_GENERIC	0x0	/* Generic Parallel port */
3750Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_BIDIRECT	0x1	/* Bi-directional Parallel */
3760Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_ECP	0x2	/* ECP 1.X Parallel port */
3770Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_1284	0x3	/* IEEE 1284 Parallel port */
3780Sstevel@tonic-gate #define	PCI_COMM_PARALLEL_IF_1284_TARG	0xFE	/* IEEE 1284 target device */
3790Sstevel@tonic-gate 
3800Sstevel@tonic-gate /*
3810Sstevel@tonic-gate  * Programming interfaces for class 0x7 / subclass 0x3 (Modem)
3820Sstevel@tonic-gate  */
3830Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_GENERIC	0x0	/* Generic Modem */
3840Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16450	0x1	/* Hayes 16450-compat Modem */
3850Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16550	0x2	/* Hayes 16550-compat Modem */
3860Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16650	0x3	/* Hayes 16650-compat Modem */
3870Sstevel@tonic-gate #define	PCI_COMM_MODEM_IF_HAYES_16750	0x4	/* Hayes 16750-compat Modem */
3880Sstevel@tonic-gate 
3890Sstevel@tonic-gate /*
3900Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x8
3910Sstevel@tonic-gate  */
3920Sstevel@tonic-gate #define	PCI_PERIPH_PIC		0x0	/* Generic PIC */
3930Sstevel@tonic-gate #define	PCI_PERIPH_DMA		0x1	/* Generic DMA Controller */
3940Sstevel@tonic-gate #define	PCI_PERIPH_TIMER	0x2	/* Generic System Timer Controller */
3950Sstevel@tonic-gate #define	PCI_PERIPH_RTC		0x3	/* Generic RTC Controller */
3963070Sanish #define	PCI_PERIPH_HPC		0x4	/* Generic PCI Hot-Plug Controller */
3973070Sanish #define	PCI_PERIPH_SD_HC	0x5	/* SD Host Controller */
3983070Sanish #define	PCI_PERIPH_IOMMU	0x6	/* IOMMU */
3990Sstevel@tonic-gate #define	PCI_PERIPH_OTHER	0x80	/* Other System Peripheral */
4000Sstevel@tonic-gate 
4010Sstevel@tonic-gate /*
4020Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller)
4030Sstevel@tonic-gate  */
4040Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_GENERIC	0x0	/* Generic 8259 APIC */
4050Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_ISA		0x1	/* ISA PIC */
4060Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_EISA		0x2	/* EISA PIC */
4070Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_IO_APIC	0x10	/* I/O APIC interrupt ctrlr */
4080Sstevel@tonic-gate #define	PCI_PERIPH_PIC_IF_IOX_APIC	0x20	/* I/O(x) APIC intr ctrlr */
4090Sstevel@tonic-gate 
4100Sstevel@tonic-gate /*
4110Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
4120Sstevel@tonic-gate  */
4130Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_GENERIC	0x0	/* Generic 8237 DMA ctrlr */
4140Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_ISA		0x1	/* ISA DMA ctrlr */
4150Sstevel@tonic-gate #define	PCI_PERIPH_DMA_IF_EISA		0x2	/* EISA DMA ctrlr */
4160Sstevel@tonic-gate 
4170Sstevel@tonic-gate /*
4180Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x2 (timer)
4190Sstevel@tonic-gate  */
4200Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_GENERIC	0x0	/* Generic 8254 system timer */
4210Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_ISA		0x1	/* ISA system timers */
4220Sstevel@tonic-gate #define	PCI_PERIPH_TIMER_IF_EISA	0x2	/* EISA system timers (two) */
4233070Sanish #define	PCI_PERIPH_TIMER_IF_HPET	0x3	/* High Perf Event timer */
4240Sstevel@tonic-gate 
4250Sstevel@tonic-gate /*
4260Sstevel@tonic-gate  * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock)
4270Sstevel@tonic-gate  */
4280Sstevel@tonic-gate #define	PCI_PERIPH_RTC_IF_GENERIC	0x0	/* Generic RTC controller */
4290Sstevel@tonic-gate #define	PCI_PERIPH_RTC_IF_ISA		0x1	/* ISA RTC controller */
4300Sstevel@tonic-gate 
4310Sstevel@tonic-gate /*
4320Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x9
4330Sstevel@tonic-gate  */
4340Sstevel@tonic-gate #define	PCI_INPUT_KEYBOARD	0x0	/* Keyboard Controller */
4350Sstevel@tonic-gate #define	PCI_INPUT_DIGITIZ	0x1	/* Digitizer (Pen) */
4360Sstevel@tonic-gate #define	PCI_INPUT_MOUSE		0x2	/* Mouse Controller */
4370Sstevel@tonic-gate #define	PCI_INPUT_SCANNER	0x3	/* Scanner Controller */
4380Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT	0x4	/* Gameport Controller */
4390Sstevel@tonic-gate #define	PCI_INPUT_OTHER		0x80	/* Other Input Controller */
4400Sstevel@tonic-gate 
4410Sstevel@tonic-gate /*
4420Sstevel@tonic-gate  * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller)
4430Sstevel@tonic-gate  */
4440Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT_IF_GENERIC	0x00	/* Generic controller */
4450Sstevel@tonic-gate #define	PCI_INPUT_GAMEPORT_IF_LEGACY	0x10	/* Legacy controller */
4460Sstevel@tonic-gate 
4470Sstevel@tonic-gate /*
4483070Sanish  * PCI Sub-class codes - base class 0xA
4490Sstevel@tonic-gate  */
4500Sstevel@tonic-gate #define	PCI_DOCK_GENERIC	0x00	/* Generic Docking Station */
4510Sstevel@tonic-gate #define	PCI_DOCK_OTHER		0x80	/* Other Type of Docking Station */
4520Sstevel@tonic-gate 
4530Sstevel@tonic-gate /*
4543070Sanish  * PCI Sub-class codes - base class 0xB
4550Sstevel@tonic-gate  */
4560Sstevel@tonic-gate #define	PCI_PROCESSOR_386	0x0	/* 386 */
4570Sstevel@tonic-gate #define	PCI_PROCESSOR_486	0x1	/* 486 */
4580Sstevel@tonic-gate #define	PCI_PROCESSOR_PENT	0x2	/* Pentium */
4590Sstevel@tonic-gate #define	PCI_PROCESSOR_ALPHA	0x10	/* Alpha */
4600Sstevel@tonic-gate #define	PCI_PROCESSOR_POWERPC	0x20	/* PowerPC */
4610Sstevel@tonic-gate #define	PCI_PROCESSOR_MIPS	0x30	/* MIPS */
4620Sstevel@tonic-gate #define	PCI_PROCESSOR_COPROC	0x40	/* Co-processor */
4633070Sanish #define	PCI_PROCESSOR_OTHER	0x80	/* Other processors */
4640Sstevel@tonic-gate 
4650Sstevel@tonic-gate /*
4663070Sanish  * PCI Sub-class codes - base class 0xC (Serial Controllers)
4670Sstevel@tonic-gate  */
4680Sstevel@tonic-gate #define	PCI_SERIAL_FIRE		0x0	/* FireWire (IEEE 1394) */
4690Sstevel@tonic-gate #define	PCI_SERIAL_ACCESS	0x1	/* ACCESS.bus */
4700Sstevel@tonic-gate #define	PCI_SERIAL_SSA		0x2	/* SSA */
4710Sstevel@tonic-gate #define	PCI_SERIAL_USB		0x3	/* Universal Serial Bus */
4720Sstevel@tonic-gate #define	PCI_SERIAL_FIBRE	0x4	/* Fibre Channel */
4730Sstevel@tonic-gate #define	PCI_SERIAL_SMBUS	0x5	/* System Management Bus */
4740Sstevel@tonic-gate #define	PCI_SERIAL_IB		0x6	/* InfiniBand */
4750Sstevel@tonic-gate #define	PCI_SERIAL_IPMI		0x7	/* IPMI */
4760Sstevel@tonic-gate #define	PCI_SERIAL_SERCOS	0x8	/* SERCOS Interface Std (IEC 61491) */
4770Sstevel@tonic-gate #define	PCI_SERIAL_CANBUS	0x9	/* CANbus */
4783070Sanish #define	PCI_SERIAL_OTHER	0x80	/* Other Serial Bus Controllers */
4793070Sanish 
4803070Sanish /*
4813070Sanish  * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
4823070Sanish  */
4833070Sanish #define	PCI_SERIAL_FIRE_WIRE  		0x00	/* IEEE 1394 (Firewire) */
4843070Sanish #define	PCI_SERIAL_FIRE_1394_HCI 	0x10	/* 1394 OpenHCI Host Cntrlr */
4850Sstevel@tonic-gate 
4860Sstevel@tonic-gate /*
4870Sstevel@tonic-gate  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
4880Sstevel@tonic-gate  */
4890Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_UHCI 		0x00	/* UHCI Compliant */
4900Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_OHCI 		0x10	/* OHCI Compliant */
4910Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_EHCI 		0x20	/* EHCI Compliant */
4920Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_GENERIC 	0x80	/* no specific HCD */
4930Sstevel@tonic-gate #define	PCI_SERIAL_USB_IF_DEVICE 	0xFE	/* not a HCD */
4940Sstevel@tonic-gate 
4950Sstevel@tonic-gate /*
4960Sstevel@tonic-gate  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
4970Sstevel@tonic-gate  */
4980Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_SMIC 	0x0	/* SMIC Interface */
4990Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_KBD 		0x1	/* Keyboard Ctrl Style Intfc */
5000Sstevel@tonic-gate #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
5010Sstevel@tonic-gate 
5020Sstevel@tonic-gate /*
5033070Sanish  * PCI Sub-class codes - base class 0xD (Wireless controllers)
5040Sstevel@tonic-gate  */
5050Sstevel@tonic-gate #define	PCI_WIRELESS_IRDA		0x0	/* iRDA Compatible Controller */
5060Sstevel@tonic-gate #define	PCI_WIRELESS_IR			0x1	/* Consumer IR Controller */
5070Sstevel@tonic-gate #define	PCI_WIRELESS_RF			0x10	/* RF Controller */
5080Sstevel@tonic-gate #define	PCI_WIRELESS_BLUETOOTH		0x11	/* Bluetooth Controller */
5090Sstevel@tonic-gate #define	PCI_WIRELESS_BROADBAND		0x12	/* Broadband Controller */
5100Sstevel@tonic-gate #define	PCI_WIRELESS_80211A		0x20	/* Ethernet 802.11a 5 GHz */
5110Sstevel@tonic-gate #define	PCI_WIRELESS_80211B		0x21	/* Ethernet 802.11b 2.4 GHz */
5120Sstevel@tonic-gate #define	PCI_WIRELESS_OTHER		0x80	/* Other Wireless Controllers */
5130Sstevel@tonic-gate 
5140Sstevel@tonic-gate /*
5153070Sanish  * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
5160Sstevel@tonic-gate  */
5173070Sanish #define	PCI_WIRELESS_IR_CONSUMER 	0x00	/* Consumer IR Controller */
5183070Sanish #define	PCI_WIRELESS_IR_UWB_RC 		0x10	/* UWB Radio Controller */
5193070Sanish 
5203070Sanish /*
5213070Sanish  * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
5223070Sanish  */
5233070Sanish #define	PCI_INTIO_MSG_FIFO		0x0	/* Message FIFO at off 40h */
5240Sstevel@tonic-gate #define	PCI_INTIO_I20			0x1	/* I20 Arch Spec 1.0 */
5250Sstevel@tonic-gate 
5260Sstevel@tonic-gate /*
5273070Sanish  * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
5280Sstevel@tonic-gate  */
5290Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_TV		0x01	/* TV */
5300Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_AUDIO	0x02	/* Audio */
5310Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_VOICE	0x03	/* Voice */
5320Sstevel@tonic-gate #define	PCI_SATELLITE_COMM_DATA		0x04	/* DATA */
5333070Sanish #define	PCI_SATELLITE_COMM_OTHER	0x80	/* Other Satelite Comm Cntrlr */
5340Sstevel@tonic-gate 
5350Sstevel@tonic-gate /*
5360Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
5370Sstevel@tonic-gate  */
5380Sstevel@tonic-gate #define	PCI_CRYPT_NETWORK		0x00	/* Network and Computing */
5390Sstevel@tonic-gate #define	PCI_CRYPT_ENTERTAINMENT		0x10	/* Entertainment en/decrypt */
5400Sstevel@tonic-gate #define	PCI_CRYPT_OTHER			0x80	/* Other en/decryption ctrlrs */
5410Sstevel@tonic-gate 
5420Sstevel@tonic-gate /*
5430Sstevel@tonic-gate  * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
5440Sstevel@tonic-gate  */
5450Sstevel@tonic-gate #define	PCI_SIGNAL_DPIO			0x00	/* DPIO modules */
5460Sstevel@tonic-gate #define	PCI_SIGNAL_PERF_COUNTERS	0x01	/* Performance counters */
5470Sstevel@tonic-gate #define	PCI_SIGNAL_COMM_SYNC		0x10	/* Comm. synchronization plus */
5480Sstevel@tonic-gate 						/* time and freq test ctrlr */
5490Sstevel@tonic-gate #define	PCI_SIGNAL_MANAGEMENT		0x20	/* Management card */
5500Sstevel@tonic-gate #define	PCI_SIGNAL_OTHER		0x80	/* DSP/DAP controller */
5510Sstevel@tonic-gate 
5520Sstevel@tonic-gate /* PCI header decode */
5530Sstevel@tonic-gate #define	PCI_HEADER_MULTI	0x80	/* multi-function device */
5540Sstevel@tonic-gate #define	PCI_HEADER_ZERO		0x00	/* type zero PCI header */
5550Sstevel@tonic-gate #define	PCI_HEADER_ONE		0x01	/* type one PCI header */
5560Sstevel@tonic-gate #define	PCI_HEADER_TWO		0x02	/* type two PCI header */
5570Sstevel@tonic-gate #define	PCI_HEADER_PPB		PCI_HEADER_ONE  /* type one PCI to PCI Bridge */
5580Sstevel@tonic-gate #define	PCI_HEADER_CARDBUS	PCI_HEADER_TWO	/* type one PCI header */
5590Sstevel@tonic-gate 
5600Sstevel@tonic-gate #define	PCI_HEADER_TYPE_M	0x7f  /* type mask for header */
5610Sstevel@tonic-gate 
5620Sstevel@tonic-gate /*
5630Sstevel@tonic-gate  * Base register bit definitions.
5640Sstevel@tonic-gate  */
5650Sstevel@tonic-gate #define	PCI_BASE_SPACE_M    0x1  /* memory space indicator */
5660Sstevel@tonic-gate #define	PCI_BASE_SPACE_IO   0x1   /* IO space */
5670Sstevel@tonic-gate #define	PCI_BASE_SPACE_MEM  0x0   /* memory space */
5680Sstevel@tonic-gate 
5690Sstevel@tonic-gate #define	PCI_BASE_TYPE_MEM   0x0   /* 32-bit memory address */
5700Sstevel@tonic-gate #define	PCI_BASE_TYPE_LOW   0x2   /* less than 1Mb address */
5710Sstevel@tonic-gate #define	PCI_BASE_TYPE_ALL   0x4   /* 64-bit memory address */
5720Sstevel@tonic-gate #define	PCI_BASE_TYPE_RES   0x6   /* reserved */
5730Sstevel@tonic-gate 
5740Sstevel@tonic-gate #define	PCI_BASE_TYPE_M		0x00000006  /* type indicator mask */
5750Sstevel@tonic-gate #define	PCI_BASE_PREF_M		0x00000008  /* prefetch mask */
5760Sstevel@tonic-gate #define	PCI_BASE_M_ADDR_M	0xfffffff0  /* memory address mask */
5770Sstevel@tonic-gate #define	PCI_BASE_IO_ADDR_M	0xfffffffe  /* I/O address mask */
5780Sstevel@tonic-gate 
5790Sstevel@tonic-gate #define	PCI_BASE_ROM_ADDR_M	0xfffff800  /* ROM address mask */
5800Sstevel@tonic-gate #define	PCI_BASE_ROM_ENABLE	0x00000001  /* ROM decoder enable */
5810Sstevel@tonic-gate 
5820Sstevel@tonic-gate /*
5830Sstevel@tonic-gate  * Capabilities linked list entry offsets
5840Sstevel@tonic-gate  */
5850Sstevel@tonic-gate #define	PCI_CAP_ID		0x0	/* capability identifier, 1 byte */
5860Sstevel@tonic-gate #define	PCI_CAP_NEXT_PTR	0x1	/* next entry pointer, 1 byte */
587881Sjohnny #define	PCI_CAP_ID_REGS_OFF	0x2	/* cap id register offset */
5880Sstevel@tonic-gate #define	PCI_CAP_MAX_PTR		0x30	/* maximum number of cap pointers */
5890Sstevel@tonic-gate #define	PCI_CAP_PTR_OFF		0x40	/* minimum cap pointer offset */
5900Sstevel@tonic-gate #define	PCI_CAP_PTR_MASK	0xFC	/* mask for capability pointer */
5910Sstevel@tonic-gate 
5920Sstevel@tonic-gate /*
5930Sstevel@tonic-gate  * Capability identifier values
5940Sstevel@tonic-gate  */
5950Sstevel@tonic-gate #define	PCI_CAP_ID_PM		0x1	/* power management entry */
5960Sstevel@tonic-gate #define	PCI_CAP_ID_AGP		0x2	/* AGP supported */
5970Sstevel@tonic-gate #define	PCI_CAP_ID_VPD		0x3	/* VPD supported */
5980Sstevel@tonic-gate #define	PCI_CAP_ID_SLOT_ID	0x4	/* Slot Identification supported */
5990Sstevel@tonic-gate #define	PCI_CAP_ID_MSI		0x5	/* MSI supported */
6000Sstevel@tonic-gate #define	PCI_CAP_ID_cPCI_HS	0x6	/* CompactPCI Host Swap supported */
6010Sstevel@tonic-gate #define	PCI_CAP_ID_PCIX		0x7	/* PCI-X supported */
6020Sstevel@tonic-gate #define	PCI_CAP_ID_HT		0x8	/* HyperTransport supported */
6030Sstevel@tonic-gate #define	PCI_CAP_ID_VS		0x9	/* Vendor Specific */
6040Sstevel@tonic-gate #define	PCI_CAP_ID_DEBUG_PORT	0xA	/* Debug Port supported */
6050Sstevel@tonic-gate #define	PCI_CAP_ID_cPCI_CRC	0xB	/* CompactPCI central resource ctrl */
606*10923SEvan.Yan@Sun.COM #define	PCI_CAP_ID_PCI_HOTPLUG	0xC	/* PCI Hot Plug (SHPC) supported */
6073070Sanish #define	PCI_CAP_ID_P2P_SUBSYS	0xD	/* PCI bridge Sub-system ID */
6080Sstevel@tonic-gate #define	PCI_CAP_ID_AGP_8X	0xE	/* AGP 8X supported */
6090Sstevel@tonic-gate #define	PCI_CAP_ID_SECURE_DEV	0xF	/* Secure Device supported */
6100Sstevel@tonic-gate #define	PCI_CAP_ID_PCI_E	0x10	/* PCI Express supported */
6110Sstevel@tonic-gate #define	PCI_CAP_ID_MSI_X	0x11	/* MSI-X supported */
6123070Sanish #define	PCI_CAP_ID_SATA		0x12	/* SATA Data/Index Config supported */
6133070Sanish #define	PCI_CAP_ID_FLR		0x13	/* Function Level Reset supported */
6140Sstevel@tonic-gate 
6150Sstevel@tonic-gate /*
6160Sstevel@tonic-gate  * Capability next entry pointer values
6170Sstevel@tonic-gate  */
6180Sstevel@tonic-gate #define	PCI_CAP_NEXT_PTR_NULL	0x0	/* no more entries in the list */
6190Sstevel@tonic-gate 
6200Sstevel@tonic-gate /*
6210Sstevel@tonic-gate  * PCI power management (PM) capability entry offsets
6220Sstevel@tonic-gate  */
6230Sstevel@tonic-gate #define	PCI_PMCAP		0x2	/* PM capabilities, 2 bytes */
6240Sstevel@tonic-gate #define	PCI_PMCSR		0x4	/* PM control/status reg, 2 bytes */
6250Sstevel@tonic-gate #define	PCI_PMCSR_BSE		0x6	/* PCI-PCI bridge extensions, 1 byte */
6260Sstevel@tonic-gate #define	PCI_PMDATA		0x7	/* PM data, 1 byte */
6270Sstevel@tonic-gate 
6280Sstevel@tonic-gate /*
6290Sstevel@tonic-gate  * PM capabilities values - 2 bytes
6300Sstevel@tonic-gate  */
6310Sstevel@tonic-gate #define	PCI_PMCAP_VER_1_0	0x1	/* PCI PM spec 1.0 */
6320Sstevel@tonic-gate #define	PCI_PMCAP_VER_1_1	0x2	/* PCI PM spec 1.1 */
6330Sstevel@tonic-gate #define	PCI_PMCAP_VER_MASK	0x7	/* version mask */
6340Sstevel@tonic-gate #define	PCI_PMCAP_PME_CLOCK	0x8	/* needs PCI clock for PME */
6350Sstevel@tonic-gate #define	PCI_PMCAP_DSI		0x20	/* needs device specific init */
6360Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_SELF	0x0	/* 0 aux current - self powered */
6370Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_55mA	0x40	/* 55 mA aux current */
6380Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_100mA	0x80	/* 100 mA aux current */
6390Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_160mA	0xc0	/* 160 mA aux current */
6400Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_220mA	0x100	/* 220 mA aux current */
6410Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_270mA	0x140	/* 270 mA aux current */
6420Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_320mA	0x180	/* 320 mA aux current */
6430Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_375mA	0x1c0	/* 375 mA aux current */
6440Sstevel@tonic-gate #define	PCI_PMCAP_AUX_CUR_MASK	0x1c0	/* 3.3Vaux aux current needs */
6450Sstevel@tonic-gate #define	PCI_PMCAP_D1		0x200	/* D1 state supported */
6460Sstevel@tonic-gate #define	PCI_PMCAP_D2		0x400	/* D2 state supported */
6470Sstevel@tonic-gate #define	PCI_PMCAP_D0_PME	0x800	/* PME from D0 */
6480Sstevel@tonic-gate #define	PCI_PMCAP_D1_PME	0x1000	/* PME from D1 */
6490Sstevel@tonic-gate #define	PCI_PMCAP_D2_PME	0x2000	/* PME from D2 */
6500Sstevel@tonic-gate #define	PCI_PMCAP_D3HOT_PME	0x4000	/* PME from D3hot */
6510Sstevel@tonic-gate #define	PCI_PMCAP_D3COLD_PME	0x8000	/* PME from D3cold */
6520Sstevel@tonic-gate #define	PCI_PMCAP_PME_MASK	0xf800	/* PME support mask */
6530Sstevel@tonic-gate 
6540Sstevel@tonic-gate /*
6550Sstevel@tonic-gate  * PM control/status values - 2 bytes
6560Sstevel@tonic-gate  */
6570Sstevel@tonic-gate #define	PCI_PMCSR_D0			0x0	/* power state D0 */
6580Sstevel@tonic-gate #define	PCI_PMCSR_D1			0x1	/* power state D1 */
6590Sstevel@tonic-gate #define	PCI_PMCSR_D2			0x2	/* power state D2 */
6600Sstevel@tonic-gate #define	PCI_PMCSR_D3HOT			0x3	/* power state D3hot */
6610Sstevel@tonic-gate #define	PCI_PMCSR_STATE_MASK		0x3	/* power state mask */
6620Sstevel@tonic-gate #define	PCI_PMCSR_PME_EN		0x100	/* enable PME assertion */
6630Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D0_PWR_C		0x0	/* D0 power consumed */
6640Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D1_PWR_C		0x200	/* D1 power consumed */
6650Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D2_PWR_C		0x400	/* D2 power consumed */
6660Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D3_PWR_C		0x600	/* D3 power consumed */
6670Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D0_PWR_D		0x800	/* D0 power dissipated */
6680Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D1_PWR_D		0xa00	/* D1 power dissipated */
6690Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D2_PWR_D		0xc00	/* D2 power dissipated */
6700Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_D3_PWR_D		0xe00	/* D3 power dissipated */
6710Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_COM_C		0x1000	/* common power consumption */
6720Sstevel@tonic-gate #define	PCI_PMCSR_DSEL_MASK		0x1e00	/* data select mask */
6730Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_UNKNOWN		0x0	/* data scale unknown */
6740Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_10		0x2000	/* data scale 0.1x */
6750Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_100		0x4000	/* data scale 0.01x */
6760Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_1_BY_1000	0x6000	/* data scale 0.001x */
6770Sstevel@tonic-gate #define	PCI_PMCSR_DSCL_MASK		0x6000	/* data scale mask */
6780Sstevel@tonic-gate #define	PCI_PMCSR_PME_STAT		0x8000	/* PME status */
6790Sstevel@tonic-gate 
6800Sstevel@tonic-gate /*
6810Sstevel@tonic-gate  * PM PMCSR PCI to PCI bridge support extension values - 1 byte
6820Sstevel@tonic-gate  */
6830Sstevel@tonic-gate #define	PCI_PMCSR_BSE_B2_B3	0x40	/* bridge D3hot -> secondary B2 */
6840Sstevel@tonic-gate #define	PCI_PMCSR_BSE_BPCC_EN	0x80	/* bus power/clock control enabled */
6850Sstevel@tonic-gate 
6860Sstevel@tonic-gate /*
6870Sstevel@tonic-gate  * PCI-X capability related definitions
6880Sstevel@tonic-gate  */
6890Sstevel@tonic-gate #define	PCI_PCIX_COMMAND	0x2	/* Command register offset */
6901865Sdilpreet #define	PCI_PCIX_STATUS		0x4	/* Status register offset */
6911865Sdilpreet #define	PCI_PCIX_ECC_STATUS	0x8	/* ECC Status register offset */
6921865Sdilpreet #define	PCI_PCIX_ECC_FST_AD	0xC	/* ECC First address register offset */
6931865Sdilpreet #define	PCI_PCIX_ECC_SEC_AD	0x10	/* ECC Second address register offset */
6941865Sdilpreet #define	PCI_PCIX_ECC_ATTR	0x14	/* ECC Attribute register offset */
6950Sstevel@tonic-gate 
6961865Sdilpreet /*
6971865Sdilpreet  * PCI-X bridge capability related definitions
6981865Sdilpreet  */
6993274Set142600 #define	PCI_PCIX_SEC_STATUS		0x2	/* Secondary Status offset */
7003274Set142600 #define	PCI_PCIX_SEC_STATUS_SCD		0x4	/* Split Completion Discarded */
7013274Set142600 #define	PCI_PCIX_SEC_STATUS_USC		0x8	/* Unexpected Split Complete */
7023274Set142600 #define	PCI_PCIX_SEC_STATUS_SCO		0x10	/* Split Completion Overrun */
7033274Set142600 #define	PCI_PCIX_SEC_STATUS_SRD		0x20	/* Split Completion Delayed */
7043274Set142600 #define	PCI_PCIX_SEC_STATUS_ERR_MASK	0x3C
7053274Set142600 
7063274Set142600 #define	PCI_PCIX_BDG_STATUS		0x4	/* Bridge Status offset */
7073274Set142600 #define	PCI_PCIX_BDG_STATUS_USC		0x80000
7083274Set142600 #define	PCI_PCIX_BDG_STATUS_SCO		0x100000
7093274Set142600 #define	PCI_PCIX_BDG_STATUS_SRD		0x200000
7103274Set142600 #define	PCI_PCIX_BDG_STATUS_ERR_MASK	0x380000
7113274Set142600 
7121865Sdilpreet #define	PCI_PCIX_UP_SPL_CTL	0x8	/* Upstream split ctrl reg offset */
7131865Sdilpreet #define	PCI_PCIX_DOWN_SPL_CTL	0xC	/* Downstream split ctrl reg offset */
7141865Sdilpreet #define	PCI_PCIX_BDG_ECC_STATUS	0x10	/* ECC Status register offset */
7151865Sdilpreet #define	PCI_PCIX_BDG_ECC_FST_AD	0x14	/* ECC First address register offset */
7161865Sdilpreet #define	PCI_PCIX_BDG_ECC_SEC_AD	0x18	/* ECC Second address register offset */
7171865Sdilpreet #define	PCI_PCIX_BDG_ECC_ATTR	0x1C	/* ECC Attribute register offset */
7181865Sdilpreet 
7191865Sdilpreet /*
7201865Sdilpreet  * PCIX capabilities values
7211865Sdilpreet  */
7220Sstevel@tonic-gate #define	PCI_PCIX_VER_MASK	0x3000	/* Bits 12 and 13 */
7230Sstevel@tonic-gate #define	PCI_PCIX_VER_0		0x0000	/* PCIX cap list item version 0 */
7240Sstevel@tonic-gate #define	PCI_PCIX_VER_1		0x1000	/* PCIX cap list item version 1 */
7250Sstevel@tonic-gate #define	PCI_PCIX_VER_2		0x2000	/* PCIX cap list item version 2 */
7260Sstevel@tonic-gate 
7271865Sdilpreet #define	PCI_PCIX_SPL_DSCD	0x40000 /* Split Completion Discarded */
7281865Sdilpreet #define	PCI_PCIX_UNEX_SPL	0x80000	/* Unexpected Split Completion */
7291865Sdilpreet #define	PCI_PCIX_RX_SPL_MSG	0x20000000 /* Recieved Spl Comp Error Message */
7301865Sdilpreet 
7311865Sdilpreet #define	PCI_PCIX_ECC_SEL	0x1	/* Secondary ECC register select */
7321865Sdilpreet #define	PCI_PCIX_ECC_EP		0x2	/* Error Present on other side */
7331865Sdilpreet #define	PCI_PCIX_ECC_S_CE	0x4	/* Addl Correctable ECC Error */
7341865Sdilpreet #define	PCI_PCIX_ECC_S_UE	0x8	/* Addl Uncorrectable ECC Error */
7351865Sdilpreet #define	PCI_PCIX_ECC_PHASE	0x70	/* ECC Error Phase */
7361865Sdilpreet #define	PCI_PCIX_ECC_CORR	0x80	/* ECC Error Corrected */
7371865Sdilpreet #define	PCI_PCIX_ECC_SYN	0xff00	/* ECC Error Syndrome */
7381865Sdilpreet #define	PCI_PCIX_ECC_FST_CMD	0xf0000	 /* ECC Error First Command */
7391865Sdilpreet #define	PCI_PCIX_ECC_SEC_CMD	0xf00000 /* ECC Error Second Command */
7401865Sdilpreet #define	PCI_PCIX_ECC_UP_ATTR	0xf000000 /* ECC Error Upper Attributes */
7411865Sdilpreet 
7421865Sdilpreet /*
7431865Sdilpreet  * PCIX ECC Phase Values
7441865Sdilpreet  */
7451865Sdilpreet #define	PCI_PCIX_ECC_PHASE_NOERR	0x0
7461865Sdilpreet #define	PCI_PCIX_ECC_PHASE_FADDR	0x1
7471865Sdilpreet #define	PCI_PCIX_ECC_PHASE_SADDR	0x2
7481865Sdilpreet #define	PCI_PCIX_ECC_PHASE_ATTR		0x3
7491865Sdilpreet #define	PCI_PCIX_ECC_PHASE_DATA32	0x4
7501865Sdilpreet #define	PCI_PCIX_ECC_PHASE_DATA64	0x5
7511865Sdilpreet 
7521865Sdilpreet /*
7531865Sdilpreet  * PCI-X Command Encoding
7541865Sdilpreet  */
7551865Sdilpreet #define	PCI_PCIX_CMD_INTR		0x0
7561865Sdilpreet #define	PCI_PCIX_CMD_SPEC		0x1
7571865Sdilpreet #define	PCI_PCIX_CMD_IORD		0x2
7581865Sdilpreet #define	PCI_PCIX_CMD_IOWR		0x3
7591865Sdilpreet #define	PCI_PCIX_CMD_DEVID		0x5
7601865Sdilpreet #define	PCI_PCIX_CMD_MEMRD_DW		0x6
7611865Sdilpreet #define	PCI_PCIX_CMD_MEMWR		0x7
7621865Sdilpreet #define	PCI_PCIX_CMD_MEMRD_BL		0x8
7631865Sdilpreet #define	PCI_PCIX_CMD_MEMWR_BL		0x9
7641865Sdilpreet #define	PCI_PCIX_CMD_CFRD		0xA
7651865Sdilpreet #define	PCI_PCIX_CMD_CFWR		0xB
7661865Sdilpreet #define	PCI_PCIX_CMD_SPL		0xC
7671865Sdilpreet #define	PCI_PCIX_CMD_DADR		0xD
7681865Sdilpreet #define	PCI_PCIX_CMD_MEMRDBL		0xE
7691865Sdilpreet #define	PCI_PCIX_CMD_MEMWRBL		0xF
7701865Sdilpreet 
7711865Sdilpreet #if defined(_BIT_FIELDS_LTOH)
7721865Sdilpreet typedef struct pcix_attr {
7731865Sdilpreet 	uint32_t	lbc	:8,
7741865Sdilpreet 			rid	:16,
7751865Sdilpreet 			tag	:5,
7761865Sdilpreet 			ro	:1,
7771865Sdilpreet 			ns	:1,
7781865Sdilpreet 			r	:1;
7791865Sdilpreet } pcix_attr_t;
7801865Sdilpreet #elif defined(_BIT_FIELDS_HTOL)
7811865Sdilpreet typedef struct pcix_attr {
7821865Sdilpreet 	uint32_t	r	:1,
7831865Sdilpreet 			ns	:1,
7841865Sdilpreet 			ro	:1,
7851865Sdilpreet 			tag	:5,
7861865Sdilpreet 			rid	:16,
7871865Sdilpreet 			lbc	:8;
7881865Sdilpreet } pcix_attr_t;
7891865Sdilpreet #else
7901865Sdilpreet #error "bit field not defined"
7911865Sdilpreet #endif
7921865Sdilpreet 
7931865Sdilpreet #define	PCI_PCIX_BSS_SPL_DSCD	0x4	/* Secondary split comp discarded */
7941865Sdilpreet #define	PCI_PCIX_BSS_UNEX_SPL	0x8	/* Secondary unexpected split comp */
7951865Sdilpreet #define	PCI_PCIX_BSS_SPL_OR	0x10	/* Secondary split comp overrun */
7961865Sdilpreet #define	PCI_PCIX_BSS_SPL_DLY	0x20	/* Secondary split comp delayed */
7971865Sdilpreet 
7980Sstevel@tonic-gate /*
799*10923SEvan.Yan@Sun.COM  * PCI Hotplug capability entry offsets
800*10923SEvan.Yan@Sun.COM  *
801*10923SEvan.Yan@Sun.COM  * SHPC based PCI hotplug controller registers accessed via the DWORD
802*10923SEvan.Yan@Sun.COM  * select and DATA registers in PCI configuration space relative to the
803*10923SEvan.Yan@Sun.COM  * PCI HP capibility pointer.
804*10923SEvan.Yan@Sun.COM  */
805*10923SEvan.Yan@Sun.COM #define	PCI_HP_DWORD_SELECT_OFF		0x2
806*10923SEvan.Yan@Sun.COM #define	PCI_HP_DWORD_DATA_OFF		0x4
807*10923SEvan.Yan@Sun.COM 
808*10923SEvan.Yan@Sun.COM #define	PCI_HP_BASE_OFFSET_REG		0x00
809*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOTS_AVAIL_I_REG	0x01
810*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOTS_AVAIL_II_REG	0x02
811*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CONFIGURATION_REG	0x03
812*10923SEvan.Yan@Sun.COM #define	PCI_HP_PROF_IF_SBCR_REG		0x04
813*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMMAND_STATUS_REG	0x05
814*10923SEvan.Yan@Sun.COM #define	PCI_HP_IRQ_LOCATOR_REG		0x06
815*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_LOCATOR_REG		0x07
816*10923SEvan.Yan@Sun.COM #define	PCI_HP_CTRL_SERR_INT_REG	0x08
817*10923SEvan.Yan@Sun.COM #define	PCI_HP_LOGICAL_SLOT_REGS	0x09
818*10923SEvan.Yan@Sun.COM #define	PCI_HP_VENDOR_SPECIFIC		0x28
819*10923SEvan.Yan@Sun.COM 
820*10923SEvan.Yan@Sun.COM /* Definitions used with the PCI_HP_SLOTS_AVAIL_I_REG register */
821*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_33MHZ_CONV_SPEED_SHIFT	0
822*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_66MHZ_PCIX_SPEED_SHIFT	8
823*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_100MHZ_PCIX_SPEED_SHIFT	16
824*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_133MHZ_PCIX_SPEED_SHIFT	24
825*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_SPEED_MASK			0x1F
826*10923SEvan.Yan@Sun.COM 
827*10923SEvan.Yan@Sun.COM /* Definitions used with the PCI_HP_SLOTS_AVAIL_II_REG register */
828*10923SEvan.Yan@Sun.COM #define	PCI_HP_AVAIL_66MHZ_CONV_SPEED_SHIFT	0
829*10923SEvan.Yan@Sun.COM 
830*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_PROF_IF_SBCR_REG register */
831*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_33MHZ_CONV_SPEED		0x0
832*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_66MHZ_CONV_SPEED		0x1
833*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_66MHZ_PCIX_SPEED		0x2
834*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_100MHZ_PCIX_SPEED		0x3
835*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_133MHZ_PCIX_SPEED		0x4
836*10923SEvan.Yan@Sun.COM #define	PCI_HP_SBCR_SPEED_MASK			0x7
837*10923SEvan.Yan@Sun.COM 
838*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_COMMAND_STATUS_REG register */
839*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_ERR_INVALID_SPEED	0x80000
840*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_ERR_INVALID_COMMAND	0x40000
841*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_ERR_MRL_OPEN		0x20000
842*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_ERR_MASK		0xe0000
843*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_CTRL_BUSY		0x10000
844*10923SEvan.Yan@Sun.COM #define	PCI_HP_COMM_STS_SET_SPEED		0x40
845*10923SEvan.Yan@Sun.COM 
846*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_CTRL_SERR_INT_REG register */
847*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_GLOBAL_IRQ_MASK		0x1
848*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_GLOBAL_SERR_MASK	0x2
849*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_CMD_COMPLETE_MASK	0x4
850*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_ARBITER_SERR_MASK	0x8
851*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_CMD_COMPLETE_IRQ	0x10000
852*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_ARBITER_IRQ		0x20000
853*10923SEvan.Yan@Sun.COM #define	PCI_HP_SERR_INT_MASK_ALL		0xf
854*10923SEvan.Yan@Sun.COM 
855*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_LOGICAL_SLOT_REGS register */
856*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_POWER_ONLY			0x1
857*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_ENABLED			0x2
858*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_DISABLED			0x3
859*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_STATE_MASK			0x3
860*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_MRL_STATE_MASK		0x100
861*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_66MHZ_CONV_CAPABLE		0x200
862*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CARD_EMPTY_MASK		0xc00
863*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_66MHZ_PCIX_CAPABLE		0x1000
864*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_100MHZ_PCIX_CAPABLE		0x2000
865*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_133MHZ_PCIX_CAPABLE		0x3000
866*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_PCIX_CAPABLE_MASK		0x3000
867*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_PCIX_CAPABLE_SHIFT		12
868*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_PRESENCE_DETECTED		0x10000
869*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_ISO_PWR_DETECTED		0x20000
870*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_ATTN_DETECTED		0x40000
871*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_MRL_DETECTED		0x80000
872*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_POWER_DETECTED		0x100000
873*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_PRESENCE_MASK		0x1000000
874*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_ISO_PWR_MASK		0x2000000
875*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_ATTN_MASK			0x4000000
876*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_MRL_MASK			0x8000000
877*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_POWER_MASK			0x10000000
878*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_MRL_SERR_MASK		0x20000000
879*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_POWER_SERR_MASK		0x40000000
880*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_MASK_ALL			0x5f000000
881*10923SEvan.Yan@Sun.COM 
882*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_IRQ_LOCATOR_REG register */
883*10923SEvan.Yan@Sun.COM #define	PCI_HP_IRQ_CMD_COMPLETE			0x1
884*10923SEvan.Yan@Sun.COM #define	PCI_HP_IRQ_SLOT_N_PENDING		0x2
885*10923SEvan.Yan@Sun.COM 
886*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_SERR_LOCATOR_REG register */
887*10923SEvan.Yan@Sun.COM #define	PCI_HP_IRQ_SERR_ARBITER_PENDING		0x1
888*10923SEvan.Yan@Sun.COM #define	PCI_HP_IRQ_SERR_SLOT_N_PENDING		0x2
889*10923SEvan.Yan@Sun.COM 
890*10923SEvan.Yan@Sun.COM /* Register bits used with the PCI_HP_SLOT_CONFIGURATION_REG register */
891*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CONFIG_MRL_SENSOR		0x40000000
892*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CONFIG_ATTN_BUTTON		0x80000000
893*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_SHIFT	16
894*10923SEvan.Yan@Sun.COM #define	PCI_HP_SLOT_CONFIG_PHY_SLOT_NUM_MASK	0x3FF
895*10923SEvan.Yan@Sun.COM 
896*10923SEvan.Yan@Sun.COM /*
8970Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
8980Sstevel@tonic-gate  */
8990Sstevel@tonic-gate #define	PCI_MSI_CTRL		0x02	/* MSI control register, 2 bytes */
9000Sstevel@tonic-gate #define	PCI_MSI_ADDR_OFFSET	0x04	/* MSI 32-bit msg address, 4 bytes */
9010Sstevel@tonic-gate #define	PCI_MSI_32BIT_DATA	0x08	/* MSI 32-bit msg data, 2 bytes */
9020Sstevel@tonic-gate #define	PCI_MSI_32BIT_MASK	0x0C	/* MSI 32-bit mask bits, 4 bytes */
9030Sstevel@tonic-gate #define	PCI_MSI_32BIT_PENDING	0x10	/* MSI 32-bit pending bits, 4 bytes */
9040Sstevel@tonic-gate 
9050Sstevel@tonic-gate /*
9060Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
9070Sstevel@tonic-gate  */
9080Sstevel@tonic-gate #define	PCI_MSI_64BIT_DATA	0x0C	/* MSI 64-bit msg data, 2 bytes */
9090Sstevel@tonic-gate #define	PCI_MSI_64BIT_MASKBITS	0x10	/* MSI 64-bit mask bits, 4 bytes */
9100Sstevel@tonic-gate #define	PCI_MSI_64BIT_PENDING	0x14	/* MSI 64-bit pending bits, 4 bytes */
9110Sstevel@tonic-gate 
9120Sstevel@tonic-gate /*
9130Sstevel@tonic-gate  * PCI Message Signalled Interrupts (MSI) capability masks and shifts
9140Sstevel@tonic-gate  */
9150Sstevel@tonic-gate #define	PCI_MSI_ENABLE_BIT	0x0001	/* MSI enable mask in MSI ctrl reg */
9160Sstevel@tonic-gate #define	PCI_MSI_MMC_MASK	0x000E	/* MMC mask in MSI ctrl reg */
9170Sstevel@tonic-gate #define	PCI_MSI_MMC_SHIFT	0x1	/* Shift for MMC bits */
9180Sstevel@tonic-gate #define	PCI_MSI_MME_MASK	0x0070	/* MME mask in MSI ctrl reg */
9190Sstevel@tonic-gate #define	PCI_MSI_MME_SHIFT	0x4	/* Shift for MME bits */
9200Sstevel@tonic-gate #define	PCI_MSI_64BIT_MASK	0x0080	/* 64bit support mask in MSI ctrl reg */
9210Sstevel@tonic-gate #define	PCI_MSI_PVM_MASK	0x0100	/* PVM support mask in MSI ctrl reg */
9220Sstevel@tonic-gate 
9230Sstevel@tonic-gate /*
9240Sstevel@tonic-gate  * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
9250Sstevel@tonic-gate  */
9260Sstevel@tonic-gate #define	PCI_MSIX_CTRL		0x02	/* MSI-X control register, 2 bytes */
9270Sstevel@tonic-gate #define	PCI_MSIX_TBL_OFFSET	0x04	/* MSI-X table offset, 4 bytes */
928965Sgovinda #define	PCI_MSIX_TBL_BIR_MASK	0x0007	/* MSI-X table BIR mask */
929965Sgovinda #define	PCI_MSIX_PBA_OFFSET	0x08	/* MSI-X pending bit array, 4 bytes */
930965Sgovinda #define	PCI_MSIX_PBA_BIR_MASK	0x0007	/* MSI-X PBA BIR mask */
9310Sstevel@tonic-gate 
9320Sstevel@tonic-gate #define	PCI_MSIX_TBL_SIZE_MASK	0x07FF	/* table size mask in MSI-X ctrl reg */
9330Sstevel@tonic-gate #define	PCI_MSIX_FUNCTION_MASK	0x4000	/* function mask in MSI-X ctrl reg */
9340Sstevel@tonic-gate #define	PCI_MSIX_ENABLE_BIT	0x8000	/* MSI-X enable mask in MSI-X ctl reg */
9350Sstevel@tonic-gate 
9360Sstevel@tonic-gate #define	PCI_MSIX_LOWER_ADDR_OFFSET	0	/* MSI-X lower addr offset */
9370Sstevel@tonic-gate #define	PCI_MSIX_UPPER_ADDR_OFFSET	4	/* MSI-X upper addr offset */
9380Sstevel@tonic-gate #define	PCI_MSIX_DATA_OFFSET		8	/* MSI-X data offset */
9390Sstevel@tonic-gate #define	PCI_MSIX_VECTOR_CTRL_OFFSET	12	/* MSI-X vector ctrl offset */
9400Sstevel@tonic-gate #define	PCI_MSIX_VECTOR_SIZE		16	/* MSI-X size of each vector */
9410Sstevel@tonic-gate 
9420Sstevel@tonic-gate /*
9430Sstevel@tonic-gate  * PCI Message Signalled Interrupts: other interesting constants
9440Sstevel@tonic-gate  */
9450Sstevel@tonic-gate #define	PCI_MSI_MAX_INTRS	32	/* maximum MSI interrupts supported */
9460Sstevel@tonic-gate #define	PCI_MSIX_MAX_INTRS	2048	/* maximum MSI-X interrupts supported */
9470Sstevel@tonic-gate 
9480Sstevel@tonic-gate /*
949881Sjohnny  * PCI Slot Id Capabilities, 2 bytes
950881Sjohnny  */
951881Sjohnny /* Byte 1: Expansion Slot Register (ESR), Byte 2: Chassis Number Register */
952881Sjohnny #define	PCI_CAPSLOT_ESR_NSLOTS_MASK	0x1F	/* Number of slots mask */
953881Sjohnny #define	PCI_CAPSLOT_ESR_FIC		0x20	/* First In Chassis bit */
954881Sjohnny #define	PCI_CAPSLOT_ESR_FIC_MASK	0x01	/* First In Chassis mask */
955881Sjohnny #define	PCI_CAPSLOT_ESR_FIC_SHIFT	5	/* First In Chassis shift */
956881Sjohnny #define	PCI_CAPSLOT_FIC(esr_reg)	((esr_reg) & PCI_CAPSLOT_ESR_FIC)
957881Sjohnny #define	PCI_CAPSLOT_NSLOTS(esr_reg)	((esr_reg) & \
958881Sjohnny 						PCI_CAPSLOT_ESR_NSLOTS_MASK)
959881Sjohnny 
960881Sjohnny /*
9619970SJimmy.Vetayases@Sun.COM  * HyperTransport Capabilities; each HT cap uses the same PCI cap id of
9629970SJimmy.Vetayases@Sun.COM  * PCI_CAP_ID_HT.  The header's upper 16-bits (command reg) contains an HT
9639970SJimmy.Vetayases@Sun.COM  * cap type reg at bits [15:11].  For Slave/Pri Interface and Host/Sec
9649970SJimmy.Vetayases@Sun.COM  * Interface types, only bits [15:13] are used.
9659970SJimmy.Vetayases@Sun.COM  */
9669970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_TYPE_MASK		0xF800
9679970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_TYPE_SLHOST_MASK	0xE000	/* SLPRI and HOSTSEC types */
9689970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_TYPE_SHIFT		11
9699970SJimmy.Vetayases@Sun.COM 
9709970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_SLPRI_ID		0x00
9719970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_HOSTSEC_ID		0x04
9729970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_SWITCH_ID		0x08
9739970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_INTCONF_ID		0x10
9749970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_REVID_ID		0x11
9759970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_UNITID_CLUMP_ID	0x12
9769970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ECFG_ID		0x13
9779970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_ID		0x14
9789970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_MSIMAP_ID		0x15
9799970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_DIRROUTE_ID		0x16
9809970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_VCSET_ID		0x17
9819970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_RETRYMODE_ID		0x18
9829970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_X86ENC_ID		0x19
9839970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_GEN3_ID		0x1A
9849970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_FUNCEXT_ID		0x1B
9859970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_PM_ID			0x1C
9869970SJimmy.Vetayases@Sun.COM 
9879970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_SLPRI_TYPE		/* 0x0000 */	\
9889970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_SLPRI_ID	<< PCI_HTCAP_TYPE_SHIFT)
9899970SJimmy.Vetayases@Sun.COM 
9909970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_HOSTSEC_TYPE		/* 0x2000 */	\
9919970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_HOSTSEC_ID	<< PCI_HTCAP_TYPE_SHIFT)
9929970SJimmy.Vetayases@Sun.COM 
9939970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_SWITCH_TYPE		/* 0x4000 */	\
9949970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_SWITCH_ID	<< PCI_HTCAP_TYPE_SHIFT)
9959970SJimmy.Vetayases@Sun.COM 
9969970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_INTCONF_TYPE		/* 0x8000 */	\
9979970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_INTCONF_ID	<< PCI_HTCAP_TYPE_SHIFT)
9989970SJimmy.Vetayases@Sun.COM 
9999970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_REVID_TYPE		/* 0x8800 */	\
10009970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_REVID_ID	<< PCI_HTCAP_TYPE_SHIFT)
10019970SJimmy.Vetayases@Sun.COM 
10029970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_UNITID_CLUMP_TYPE	/* 0x9000 */	\
10039970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_UNITID_CLUMP_ID	<< PCI_HTCAP_TYPE_SHIFT)
10049970SJimmy.Vetayases@Sun.COM 
10059970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ECFG_TYPE		/* 0x9800 */	\
10069970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_ECFG_ID	<< PCI_HTCAP_TYPE_SHIFT)
10079970SJimmy.Vetayases@Sun.COM 
10089970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_TYPE		/* 0xA000 */	\
10099970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_ADDRMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
10109970SJimmy.Vetayases@Sun.COM 
10119970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_MSIMAP_TYPE		/* 0xA800 */	\
10129970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_MSIMAP_ID	<< PCI_HTCAP_TYPE_SHIFT)
10139970SJimmy.Vetayases@Sun.COM 
10149970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_DIRROUTE_TYPE		/* 0xB000 */	\
10159970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_DIRROUTE_ID	<< PCI_HTCAP_TYPE_SHIFT)
10169970SJimmy.Vetayases@Sun.COM 
10179970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_VCSET_TYPE		/* 0xB800 */	\
10189970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_VCSET_ID	<< PCI_HTCAP_TYPE_SHIFT)
10199970SJimmy.Vetayases@Sun.COM 
10209970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_RETRYMODE_TYPE	/* 0xC000 */	\
10219970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_RETRYMODE_ID	<< PCI_HTCAP_TYPE_SHIFT)
10229970SJimmy.Vetayases@Sun.COM 
10239970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_X86ENC_TYPE		/* 0xC800 */	\
10249970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_X86ENC_ID	<< PCI_HTCAP_TYPE_SHIFT)
10259970SJimmy.Vetayases@Sun.COM 
10269970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_GEN3_TYPE		/* 0xD000 */	\
10279970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_GEN3_ID	<< PCI_HTCAP_TYPE_SHIFT)
10289970SJimmy.Vetayases@Sun.COM 
10299970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_FUNCEXT_TYPE		/* 0xD800 */	\
10309970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_FUNCEXT_ID	<< PCI_HTCAP_TYPE_SHIFT)
10319970SJimmy.Vetayases@Sun.COM 
10329970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_PM_TYPE		/* 0xE000 */	\
10339970SJimmy.Vetayases@Sun.COM 	(PCI_HTCAP_PM_ID	<< PCI_HTCAP_TYPE_SHIFT)
10349970SJimmy.Vetayases@Sun.COM 
10359970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_MSIMAP_ENABLE			0x0001
10369970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_MSIMAP_ENABLE_MASK		0x0001
10379970SJimmy.Vetayases@Sun.COM 
10389970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_MAPTYPE_MASK		0x600
10399970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_MAPTYPE_SHIFT		9
10409970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_NUMMAP_MASK		0xF
10419970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_40BIT_ID		0x0
10429970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_ADDRMAP_64BIT_ID		0x1
10439970SJimmy.Vetayases@Sun.COM 
10449970SJimmy.Vetayases@Sun.COM #define	PCI_HTCAP_FUNCEXT_LEN_MASK		0xFF
10459970SJimmy.Vetayases@Sun.COM 
10469970SJimmy.Vetayases@Sun.COM 
10479970SJimmy.Vetayases@Sun.COM /*
10480Sstevel@tonic-gate  * other interesting PCI constants
10490Sstevel@tonic-gate  */
10500Sstevel@tonic-gate #define	PCI_BASE_NUM	6	/* num of base regs in configuration header */
10510Sstevel@tonic-gate #define	PCI_BAR_SZ_32	4	/* size of 32 bit base addr reg in bytes */
10520Sstevel@tonic-gate #define	PCI_BAR_SZ_64	8	/* size of 64 bit base addr reg in bytes */
10530Sstevel@tonic-gate #define	PCI_BASE_SIZE	4	/* size of base reg in bytes */
10540Sstevel@tonic-gate #define	PCI_CONF_HDR_SIZE	256	/* configuration header size */
1055881Sjohnny #define	PCI_MAX_BUS_NUM		256		/* Maximum PCI buses allowed */
10562767Sanish #define	PCI_MAX_DEVICES		32		/* Max PCI devices allowed */
10572767Sanish #define	PCI_MAX_FUNCTIONS	8		/* Max PCI functions allowed */
10582767Sanish #define	PCI_MAX_CHILDREN	PCI_MAX_DEVICES * PCI_MAX_FUNCTIONS
10590Sstevel@tonic-gate #define	PCI_CLK_33MHZ	(33 * 1000 * 1000)	/* 33MHz clock speed */
10600Sstevel@tonic-gate #define	PCI_CLK_66MHZ	(66 * 1000 * 1000)	/* 66MHz clock speed */
10610Sstevel@tonic-gate #define	PCI_CLK_133MHZ	(133 * 1000 * 1000)	/* 133MHz clock speed */
10620Sstevel@tonic-gate 
10630Sstevel@tonic-gate /*
10641865Sdilpreet  * pci bus range definition
10651865Sdilpreet  */
10661865Sdilpreet typedef struct pci_bus_range {
10671865Sdilpreet 	uint32_t lo;
10681865Sdilpreet 	uint32_t hi;
10691865Sdilpreet } pci_bus_range_t;
10701865Sdilpreet 
10711865Sdilpreet /*
10721865Sdilpreet  * The following typedef is used to represent an entry in the "ranges"
10731865Sdilpreet  * property of a pci hostbridge device node.
10741865Sdilpreet  */
10751865Sdilpreet typedef struct pci_ranges {
10761865Sdilpreet 	uint32_t child_high;
10771865Sdilpreet 	uint32_t child_mid;
10781865Sdilpreet 	uint32_t child_low;
10791865Sdilpreet 	uint32_t parent_high;
10801865Sdilpreet 	uint32_t parent_low;
10811865Sdilpreet 	uint32_t size_high;
10821865Sdilpreet 	uint32_t size_low;
10831865Sdilpreet } pci_ranges_t;
10841865Sdilpreet 
10851865Sdilpreet /*
10861865Sdilpreet  * The following typedef is used to represent an entry in the "ranges"
10871865Sdilpreet  * property of a pci-pci bridge device node.
10881865Sdilpreet  */
10891865Sdilpreet typedef struct {
10901865Sdilpreet 	uint32_t child_high;
10911865Sdilpreet 	uint32_t child_mid;
10921865Sdilpreet 	uint32_t child_low;
10931865Sdilpreet 	uint32_t parent_high;
10941865Sdilpreet 	uint32_t parent_mid;
10951865Sdilpreet 	uint32_t parent_low;
10961865Sdilpreet 	uint32_t size_high;
10971865Sdilpreet 	uint32_t size_low;
10981865Sdilpreet } ppb_ranges_t;
10991865Sdilpreet 
11001865Sdilpreet /*
11010Sstevel@tonic-gate  * This structure represents one entry of the 1275 "reg" property and
11020Sstevel@tonic-gate  * "assigned-addresses" property for a PCI node.  For the "reg" property, it
11030Sstevel@tonic-gate  * may be one of an arbitrary length array for devices with multiple address
11040Sstevel@tonic-gate  * windows.  For the "assigned-addresses" property, it denotes an assigned
11050Sstevel@tonic-gate  * physical address on the PCI bus.  It may be one entry of the six entries
11060Sstevel@tonic-gate  * for devices with multiple base registers.
11070Sstevel@tonic-gate  *
11080Sstevel@tonic-gate  * The physical address format is:
11090Sstevel@tonic-gate  *
11100Sstevel@tonic-gate  *             Bit#:  33222222 22221111 11111100 00000000
11110Sstevel@tonic-gate  *                    10987654 32109876 54321098 76543210
11120Sstevel@tonic-gate  *
11139427SMax.Zhen@Sun.COM  * pci_phys_hi cell:  npt000ss bbbbbbbb dddddfff rrrrrrrr
11140Sstevel@tonic-gate  * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
11150Sstevel@tonic-gate  * pci_phys_low cell: llllllll llllllll llllllll llllllll
11160Sstevel@tonic-gate  *
11170Sstevel@tonic-gate  * n          is 0 if the address is relocatable, 1 otherwise
11180Sstevel@tonic-gate  * p          is 1 if the addressable region is "prefetchable", 0 otherwise
11199427SMax.Zhen@Sun.COM  * t          is 1 if the address is aliased (for non-relocatable I/O), below
11209427SMax.Zhen@Sun.COM  *	      1MB (for mem), or below 64 KB (for relocatable I/O).
11219427SMax.Zhen@Sun.COM  * ss         is the type code, denoting which address space
11220Sstevel@tonic-gate  * bbbbbbbb   is the 8-bit bus number
11230Sstevel@tonic-gate  * ddddd      is the 5-bit device number
11240Sstevel@tonic-gate  * fff        is the 3-bit function number
11250Sstevel@tonic-gate  * rrrrrrrr   is the 8-bit register number
11269427SMax.Zhen@Sun.COM  *	      should be zero for non-relocatable, when ss is 01, or 10
11270Sstevel@tonic-gate  * hh...hhh   is the 32-bit unsigned number
11280Sstevel@tonic-gate  * ll...lll   is the 32-bit unsigned number
11290Sstevel@tonic-gate  *
11300Sstevel@tonic-gate  * The physical size format is:
11310Sstevel@tonic-gate  *
11320Sstevel@tonic-gate  * pci_size_hi cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
11330Sstevel@tonic-gate  * pci_size_low cell: llllllll llllllll llllllll llllllll
11340Sstevel@tonic-gate  *
11350Sstevel@tonic-gate  * hh...hhh   is the 32-bit unsigned number
11360Sstevel@tonic-gate  * ll...lll   is the 32-bit unsigned number
11370Sstevel@tonic-gate  */
11380Sstevel@tonic-gate struct pci_phys_spec {
11390Sstevel@tonic-gate 	uint_t pci_phys_hi;		/* child's address, hi word */
11400Sstevel@tonic-gate 	uint_t pci_phys_mid;		/* child's address, middle word */
11410Sstevel@tonic-gate 	uint_t pci_phys_low;		/* child's address, low word */
11420Sstevel@tonic-gate 	uint_t pci_size_hi;		/* high word of size field */
11430Sstevel@tonic-gate 	uint_t pci_size_low;		/* low word of size field */
11440Sstevel@tonic-gate };
11450Sstevel@tonic-gate 
11460Sstevel@tonic-gate typedef struct pci_phys_spec pci_regspec_t;
11470Sstevel@tonic-gate 
11480Sstevel@tonic-gate /*
11490Sstevel@tonic-gate  * PCI masks for pci_phy_hi of PCI 1275 address cell.
11500Sstevel@tonic-gate  */
11510Sstevel@tonic-gate #define	PCI_REG_REG_M		0xff		/* register mask */
11520Sstevel@tonic-gate #define	PCI_REG_FUNC_M		0x700		/* function mask */
11530Sstevel@tonic-gate #define	PCI_REG_DEV_M		0xf800		/* device mask */
11540Sstevel@tonic-gate #define	PCI_REG_BUS_M		0xff0000	/* bus number mask */
11550Sstevel@tonic-gate #define	PCI_REG_ADDR_M		0x3000000	/* address space mask */
11560Sstevel@tonic-gate #define	PCI_REG_ALIAS_M		0x20000000	/* aliased bit mask */
11570Sstevel@tonic-gate #define	PCI_REG_PF_M		0x40000000	/* prefetch bit mask */
11580Sstevel@tonic-gate #define	PCI_REG_REL_M		0x80000000	/* relocation bit mask */
11590Sstevel@tonic-gate #define	PCI_REG_BDFR_M		0xffffff	/* bus, dev, func, reg mask */
11603743Saa72041 #define	PCI_REG_EXTREG_M	0xF0000000	/* extended config bits mask */
11610Sstevel@tonic-gate 
11620Sstevel@tonic-gate #define	PCI_REG_FUNC_SHIFT	8		/* Offset of function bits */
11630Sstevel@tonic-gate #define	PCI_REG_DEV_SHIFT	11		/* Offset of device bits */
11640Sstevel@tonic-gate #define	PCI_REG_BUS_SHIFT	16		/* Offset of bus bits */
11650Sstevel@tonic-gate #define	PCI_REG_ADDR_SHIFT	24		/* Offset of address bits */
11663743Saa72041 #define	PCI_REG_EXTREG_SHIFT	28		/* Offset of ext. config bits */
11670Sstevel@tonic-gate 
11680Sstevel@tonic-gate #define	PCI_REG_REG_G(x)	((x) & PCI_REG_REG_M)
11690Sstevel@tonic-gate #define	PCI_REG_FUNC_G(x)	(((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT)
11700Sstevel@tonic-gate #define	PCI_REG_DEV_G(x)	(((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)
11710Sstevel@tonic-gate #define	PCI_REG_BUS_G(x)	(((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT)
11720Sstevel@tonic-gate #define	PCI_REG_ADDR_G(x)	(((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT)
11730Sstevel@tonic-gate #define	PCI_REG_BDFR_G(x)	((x) & PCI_REG_BDFR_M)
11740Sstevel@tonic-gate 
11750Sstevel@tonic-gate /*
11760Sstevel@tonic-gate  * PCI bit encodings of pci_phys_hi of PCI 1275 address cell.
11770Sstevel@tonic-gate  */
11780Sstevel@tonic-gate #define	PCI_ADDR_MASK		PCI_REG_ADDR_M
11790Sstevel@tonic-gate #define	PCI_ADDR_CONFIG		0x00000000	/* configuration address */
11800Sstevel@tonic-gate #define	PCI_ADDR_IO		0x01000000	/* I/O address */
11810Sstevel@tonic-gate #define	PCI_ADDR_MEM32		0x02000000	/* 32-bit memory address */
11820Sstevel@tonic-gate #define	PCI_ADDR_MEM64		0x03000000	/* 64-bit memory address */
11830Sstevel@tonic-gate #define	PCI_ALIAS_B		PCI_REG_ALIAS_M	/* aliased bit */
11840Sstevel@tonic-gate #define	PCI_PREFETCH_B		PCI_REG_PF_M	/* prefetch bit */
11850Sstevel@tonic-gate #define	PCI_RELOCAT_B		PCI_REG_REL_M	/* non-relocatable bit */
11860Sstevel@tonic-gate #define	PCI_CONF_ADDR_MASK	0x00ffffff	/* mask for config address */
11870Sstevel@tonic-gate 
11880Sstevel@tonic-gate #define	PCI_HARDDEC_8514 2	/* number of reg entries for 8514 hard-decode */
11890Sstevel@tonic-gate #define	PCI_HARDDEC_VGA	3	/* number of reg entries for VGA hard-decode */
11900Sstevel@tonic-gate #define	PCI_HARDDEC_IDE	4	/* number of reg entries for IDE hard-decode */
11910Sstevel@tonic-gate #define	PCI_HARDDEC_IDE_PRI 2	/* number of reg entries for IDE primary */
11920Sstevel@tonic-gate #define	PCI_HARDDEC_IDE_SEC 2	/* number of reg entries for IDE secondary */
11930Sstevel@tonic-gate 
11940Sstevel@tonic-gate /*
11950Sstevel@tonic-gate  * PCI Expansion ROM Header Format
11960Sstevel@tonic-gate  */
11970Sstevel@tonic-gate #define	PCI_ROM_SIGNATURE		0x0	/* ROM Signature 0xaa55 */
11980Sstevel@tonic-gate #define	PCI_ROM_ARCH_UNIQUE_START	0x2	/* Start of processor unique */
11990Sstevel@tonic-gate #define	PCI_ROM_PCI_DATA_STRUCT_PTR	0x18	/* Ptr to PCI Data Structure */
12000Sstevel@tonic-gate 
12010Sstevel@tonic-gate /*
12020Sstevel@tonic-gate  * PCI Data Structure
12030Sstevel@tonic-gate  *
12040Sstevel@tonic-gate  * The PCI Data Structure is located within the first 64KB
12050Sstevel@tonic-gate  * of the ROM image and must be DWORD aligned.
12060Sstevel@tonic-gate  */
12070Sstevel@tonic-gate #define	PCI_PDS_SIGNATURE	0x0	/* Signature, the string 'PCIR' */
12080Sstevel@tonic-gate #define	PCI_PDS_VENDOR_ID	0x4	/* Vendor Identification */
12090Sstevel@tonic-gate #define	PCI_PDS_DEVICE_ID	0x6	/* Device Identification */
12100Sstevel@tonic-gate #define	PCI_PDS_VPD_PTR		0x8	/* Pointer to Vital Product Data */
12110Sstevel@tonic-gate #define	PCI_PDS_PDS_LENGTH	0xa	/* PCI Data Structure Length */
12120Sstevel@tonic-gate #define	PCI_PDS_PDS_REVISION	0xc	/* PCI Data Structure Revision */
12130Sstevel@tonic-gate #define	PCI_PDS_CLASS_CODE	0xd	/* Class Code */
12140Sstevel@tonic-gate #define	PCI_PDS_IMAGE_LENGTH	0x10	/* Image Length in 512 byte units */
12150Sstevel@tonic-gate #define	PCI_PDS_CODE_REVISON	0x12	/* Revision Level of Code/Data */
12160Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE	0x14	/* Code Type */
12170Sstevel@tonic-gate #define	PCI_PDS_INDICATOR	0x15	/* Indicates if image is last in ROM */
12180Sstevel@tonic-gate 
12190Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
12200Sstevel@tonic-gate #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
12210Sstevel@tonic-gate 
12223249Sgovinda /*
12233249Sgovinda  * we recognize the non transparent bridge child nodes with the
12243249Sgovinda  * following property. This is specific to an implementation only.
12253249Sgovinda  * This property is specific to AP nodes only.
12263249Sgovinda  */
12273249Sgovinda #define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
12283249Sgovinda 
12293249Sgovinda /*
12303249Sgovinda  * If a bridge device provides its own config space access services,
12313249Sgovinda  * and supports a hotplug/hotswap bus below at any level, then
12323249Sgovinda  * the following property must be defined for the node either by
12333249Sgovinda  * the driver or the OBP.
12343249Sgovinda  */
12353249Sgovinda #define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
12363249Sgovinda 
12370Sstevel@tonic-gate #ifdef	__cplusplus
12380Sstevel@tonic-gate }
12390Sstevel@tonic-gate #endif
12400Sstevel@tonic-gate 
12410Sstevel@tonic-gate #endif	/* _SYS_PCI_H */
1242