13859Sml29623 /* 23859Sml29623 * CDDL HEADER START 33859Sml29623 * 43859Sml29623 * The contents of this file are subject to the terms of the 53859Sml29623 * Common Development and Distribution License (the "License"). 63859Sml29623 * You may not use this file except in compliance with the License. 73859Sml29623 * 83859Sml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 93859Sml29623 * or http://www.opensolaris.org/os/licensing. 103859Sml29623 * See the License for the specific language governing permissions 113859Sml29623 * and limitations under the License. 123859Sml29623 * 133859Sml29623 * When distributing Covered Code, include this CDDL HEADER in each 143859Sml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 153859Sml29623 * If applicable, add the following below this CDDL HEADER, with the 163859Sml29623 * fields enclosed by brackets "[]" replaced with your own identifying 173859Sml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 183859Sml29623 * 193859Sml29623 * CDDL HEADER END 203859Sml29623 */ 213859Sml29623 /* 22*6439Sml29623 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 233859Sml29623 * Use is subject to license terms. 243859Sml29623 */ 253859Sml29623 263859Sml29623 #ifndef _SYS_NXGE_NXGE_MAC_H 273859Sml29623 #define _SYS_NXGE_NXGE_MAC_H 283859Sml29623 293859Sml29623 #pragma ident "%Z%%M% %I% %E% SMI" 303859Sml29623 313859Sml29623 #ifdef __cplusplus 323859Sml29623 extern "C" { 333859Sml29623 #endif 343859Sml29623 353859Sml29623 #include <nxge_mac_hw.h> 363859Sml29623 #include <npi_mac.h> 373859Sml29623 383859Sml29623 #define NXGE_MTU_DEFAULT_MAX 1522 /* 0x5f2 */ 39*6439Sml29623 #define NXGE_DEFAULT_MTU 1500 /* 0x5dc */ 40*6439Sml29623 #define NXGE_MIN_MAC_FRAMESIZE 64 41*6439Sml29623 #define NXGE_MAX_MAC_FRAMESIZE NXGE_MTU_DEFAULT_MAX 42*6439Sml29623 /* 43*6439Sml29623 * Maximum MTU: maximum frame size supported by the 44*6439Sml29623 * hardware (9216) - (22). 45*6439Sml29623 * (22 = ether header size (including VLAN) - CRC size (4)). 46*6439Sml29623 */ 47*6439Sml29623 #define NXGE_EHEADER_VLAN_CRC (sizeof (struct ether_header) + ETHERFCSL + 4) 48*6439Sml29623 #define NXGE_MAXIMUM_MTU (TX_JUMBO_MTU - NXGE_EHEADER_VLAN_CRC) 493859Sml29623 503859Sml29623 #define NXGE_XMAC_TX_INTRS (ICFG_XMAC_TX_ALL & \ 513859Sml29623 ~(ICFG_XMAC_TX_FRAME_XMIT |\ 523859Sml29623 ICFG_XMAC_TX_BYTE_CNT_EXP |\ 533859Sml29623 ICFG_XMAC_TX_FRAME_CNT_EXP)) 543859Sml29623 #define NXGE_XMAC_RX_INTRS (ICFG_XMAC_RX_ALL & \ 553859Sml29623 ~(ICFG_XMAC_RX_FRAME_RCVD |\ 563859Sml29623 ICFG_XMAC_RX_OCT_CNT_EXP |\ 573859Sml29623 ICFG_XMAC_RX_HST_CNT1_EXP |\ 583859Sml29623 ICFG_XMAC_RX_HST_CNT2_EXP |\ 593859Sml29623 ICFG_XMAC_RX_HST_CNT3_EXP |\ 603859Sml29623 ICFG_XMAC_RX_HST_CNT4_EXP |\ 613859Sml29623 ICFG_XMAC_RX_HST_CNT5_EXP |\ 623859Sml29623 ICFG_XMAC_RX_HST_CNT6_EXP |\ 633859Sml29623 ICFG_XMAC_RX_BCAST_CNT_EXP |\ 643859Sml29623 ICFG_XMAC_RX_MCAST_CNT_EXP |\ 653859Sml29623 ICFG_XMAC_RX_HST_CNT7_EXP)) 663859Sml29623 #define NXGE_BMAC_TX_INTRS (ICFG_BMAC_TX_ALL & \ 673859Sml29623 ~(ICFG_BMAC_TX_FRAME_SENT |\ 683859Sml29623 ICFG_BMAC_TX_BYTE_CNT_EXP |\ 693859Sml29623 ICFG_BMAC_TX_FRAME_CNT_EXP)) 703859Sml29623 #define NXGE_BMAC_RX_INTRS (ICFG_BMAC_RX_ALL & \ 713859Sml29623 ~(ICFG_BMAC_RX_FRAME_RCVD |\ 723859Sml29623 ICFG_BMAC_RX_FRAME_CNT_EXP |\ 733859Sml29623 ICFG_BMAC_RX_BYTE_CNT_EXP)) 743859Sml29623 753859Sml29623 typedef enum { 763859Sml29623 LINK_NO_CHANGE, 773859Sml29623 LINK_IS_UP, 783859Sml29623 LINK_IS_DOWN 793859Sml29623 } nxge_link_state_t; 803859Sml29623 813859Sml29623 /* Common MAC statistics */ 823859Sml29623 833859Sml29623 typedef struct _nxge_mac_stats { 843859Sml29623 /* 853859Sml29623 * MTU size 863859Sml29623 */ 873859Sml29623 uint32_t mac_mtu; 883859Sml29623 uint16_t rev_id; 893859Sml29623 903859Sml29623 /* 913859Sml29623 * Transciever state informations. 923859Sml29623 */ 933859Sml29623 uint32_t xcvr_inits; 943859Sml29623 xcvr_inuse_t xcvr_inuse; 953859Sml29623 uint32_t xcvr_portn; 963859Sml29623 uint32_t xcvr_id; 973859Sml29623 uint32_t serdes_inits; 983859Sml29623 uint32_t serdes_portn; 993859Sml29623 uint32_t cap_autoneg; 1003859Sml29623 uint32_t cap_10gfdx; 1013859Sml29623 uint32_t cap_10ghdx; 1023859Sml29623 uint32_t cap_1000fdx; 1033859Sml29623 uint32_t cap_1000hdx; 1043859Sml29623 uint32_t cap_100T4; 1053859Sml29623 uint32_t cap_100fdx; 1063859Sml29623 uint32_t cap_100hdx; 1073859Sml29623 uint32_t cap_10fdx; 1083859Sml29623 uint32_t cap_10hdx; 1093859Sml29623 uint32_t cap_asmpause; 1103859Sml29623 uint32_t cap_pause; 1113859Sml29623 1123859Sml29623 /* 1133859Sml29623 * Advertised capabilities. 1143859Sml29623 */ 1153859Sml29623 uint32_t adv_cap_autoneg; 1163859Sml29623 uint32_t adv_cap_10gfdx; 1173859Sml29623 uint32_t adv_cap_10ghdx; 1183859Sml29623 uint32_t adv_cap_1000fdx; 1193859Sml29623 uint32_t adv_cap_1000hdx; 1203859Sml29623 uint32_t adv_cap_100T4; 1213859Sml29623 uint32_t adv_cap_100fdx; 1223859Sml29623 uint32_t adv_cap_100hdx; 1233859Sml29623 uint32_t adv_cap_10fdx; 1243859Sml29623 uint32_t adv_cap_10hdx; 1253859Sml29623 uint32_t adv_cap_asmpause; 1263859Sml29623 uint32_t adv_cap_pause; 1273859Sml29623 1283859Sml29623 /* 1293859Sml29623 * Link partner capabilities. 1303859Sml29623 */ 1313859Sml29623 uint32_t lp_cap_autoneg; 1323859Sml29623 uint32_t lp_cap_10gfdx; 1333859Sml29623 uint32_t lp_cap_10ghdx; 1343859Sml29623 uint32_t lp_cap_1000fdx; 1353859Sml29623 uint32_t lp_cap_1000hdx; 1363859Sml29623 uint32_t lp_cap_100T4; 1373859Sml29623 uint32_t lp_cap_100fdx; 1383859Sml29623 uint32_t lp_cap_100hdx; 1393859Sml29623 uint32_t lp_cap_10fdx; 1403859Sml29623 uint32_t lp_cap_10hdx; 1413859Sml29623 uint32_t lp_cap_asmpause; 1423859Sml29623 uint32_t lp_cap_pause; 1433859Sml29623 1443859Sml29623 /* 1453859Sml29623 * Physical link statistics. 1463859Sml29623 */ 1473859Sml29623 uint32_t link_T4; 1483859Sml29623 uint32_t link_speed; 1493859Sml29623 uint32_t link_duplex; 1503859Sml29623 uint32_t link_asmpause; 1513859Sml29623 uint32_t link_pause; 1523859Sml29623 uint32_t link_up; 1533859Sml29623 1543859Sml29623 /* Promiscous mode */ 1553859Sml29623 boolean_t promisc; 1563859Sml29623 } nxge_mac_stats_t; 1573859Sml29623 1583859Sml29623 /* XMAC Statistics */ 1593859Sml29623 1603859Sml29623 typedef struct _nxge_xmac_stats { 1613859Sml29623 uint32_t tx_frame_cnt; 1623859Sml29623 uint32_t tx_underflow_err; 1633859Sml29623 uint32_t tx_maxpktsize_err; 1643859Sml29623 uint32_t tx_overflow_err; 1653859Sml29623 uint32_t tx_fifo_xfr_err; 1663859Sml29623 uint64_t tx_byte_cnt; 1673859Sml29623 uint32_t rx_frame_cnt; 1683859Sml29623 uint32_t rx_underflow_err; 1693859Sml29623 uint32_t rx_overflow_err; 1703859Sml29623 uint32_t rx_crc_err_cnt; 1713859Sml29623 uint32_t rx_len_err_cnt; 1723859Sml29623 uint32_t rx_viol_err_cnt; 1733859Sml29623 uint64_t rx_byte_cnt; 1743859Sml29623 uint64_t rx_hist1_cnt; 1753859Sml29623 uint64_t rx_hist2_cnt; 1763859Sml29623 uint64_t rx_hist3_cnt; 1773859Sml29623 uint64_t rx_hist4_cnt; 1783859Sml29623 uint64_t rx_hist5_cnt; 1793859Sml29623 uint64_t rx_hist6_cnt; 1803859Sml29623 uint64_t rx_hist7_cnt; 1813859Sml29623 uint64_t rx_broadcast_cnt; 1823859Sml29623 uint64_t rx_mult_cnt; 1833859Sml29623 uint32_t rx_frag_cnt; 1843859Sml29623 uint32_t rx_frame_align_err_cnt; 1853859Sml29623 uint32_t rx_linkfault_err_cnt; 1863859Sml29623 uint32_t rx_remotefault_err; 1873859Sml29623 uint32_t rx_localfault_err; 1883859Sml29623 uint32_t rx_pause_cnt; 1893859Sml29623 uint32_t tx_pause_state; 1903859Sml29623 uint32_t tx_nopause_state; 1913859Sml29623 uint32_t xpcs_deskew_err_cnt; 1923859Sml29623 uint32_t xpcs_ln0_symbol_err_cnt; 1933859Sml29623 uint32_t xpcs_ln1_symbol_err_cnt; 1943859Sml29623 uint32_t xpcs_ln2_symbol_err_cnt; 1953859Sml29623 uint32_t xpcs_ln3_symbol_err_cnt; 1963859Sml29623 } nxge_xmac_stats_t, *p_nxge_xmac_stats_t; 1973859Sml29623 1983859Sml29623 /* BMAC Statistics */ 1993859Sml29623 2003859Sml29623 typedef struct _nxge_bmac_stats { 2013859Sml29623 uint64_t tx_frame_cnt; 2023859Sml29623 uint32_t tx_underrun_err; 2033859Sml29623 uint32_t tx_max_pkt_err; 2043859Sml29623 uint64_t tx_byte_cnt; 2053859Sml29623 uint64_t rx_frame_cnt; 2063859Sml29623 uint64_t rx_byte_cnt; 2073859Sml29623 uint32_t rx_overflow_err; 2083859Sml29623 uint32_t rx_align_err_cnt; 2093859Sml29623 uint32_t rx_crc_err_cnt; 2103859Sml29623 uint32_t rx_len_err_cnt; 2113859Sml29623 uint32_t rx_viol_err_cnt; 2123859Sml29623 uint32_t rx_pause_cnt; 2133859Sml29623 uint32_t tx_pause_state; 2143859Sml29623 uint32_t tx_nopause_state; 2153859Sml29623 } nxge_bmac_stats_t, *p_nxge_bmac_stats_t; 2163859Sml29623 2173859Sml29623 typedef struct _hash_filter_t { 2183859Sml29623 uint_t hash_ref_cnt; 2193859Sml29623 uint16_t hash_filter_regs[NMCFILTER_REGS]; 2203859Sml29623 uint32_t hash_bit_ref_cnt[NMCFILTER_BITS]; 2213859Sml29623 } hash_filter_t, *p_hash_filter_t; 2223859Sml29623 2233859Sml29623 typedef struct _nxge_mac { 2243859Sml29623 uint8_t portnum; 2253859Sml29623 nxge_port_t porttype; 2263859Sml29623 nxge_port_mode_t portmode; 2273859Sml29623 nxge_linkchk_mode_t linkchkmode; 2283859Sml29623 boolean_t is_jumbo; 2293859Sml29623 uint32_t tx_config; 2303859Sml29623 uint32_t rx_config; 2313859Sml29623 uint32_t xif_config; 2323859Sml29623 uint32_t tx_iconfig; 2333859Sml29623 uint32_t rx_iconfig; 2343859Sml29623 uint32_t ctl_iconfig; 2353859Sml29623 uint16_t minframesize; 2363859Sml29623 uint16_t maxframesize; 2373859Sml29623 uint16_t maxburstsize; 2383859Sml29623 uint16_t ctrltype; 2393859Sml29623 uint16_t pa_size; 2403859Sml29623 uint8_t ipg[3]; 2413859Sml29623 struct ether_addr mac_addr; 2423859Sml29623 struct ether_addr alt_mac_addr[MAC_MAX_ALT_ADDR_ENTRY]; 2433859Sml29623 struct ether_addr mac_addr_filter; 2443859Sml29623 uint16_t hashtab[MAC_MAX_HASH_ENTRY]; 2453859Sml29623 hostinfo_t hostinfo[MAC_MAX_HOST_INFO_ENTRY]; 2463859Sml29623 nxge_mac_stats_t *mac_stats; 2473859Sml29623 nxge_xmac_stats_t *xmac_stats; 2483859Sml29623 nxge_bmac_stats_t *bmac_stats; 249*6439Sml29623 uint32_t default_mtu; 2503859Sml29623 } nxge_mac_t; 2513859Sml29623 2523859Sml29623 #ifdef __cplusplus 2533859Sml29623 } 2543859Sml29623 #endif 2553859Sml29623 2563859Sml29623 #endif /* _SYS_NXGE_NXGE_MAC_H */ 257