1*3859Sml29623 /* 2*3859Sml29623 * CDDL HEADER START 3*3859Sml29623 * 4*3859Sml29623 * The contents of this file are subject to the terms of the 5*3859Sml29623 * Common Development and Distribution License (the "License"). 6*3859Sml29623 * You may not use this file except in compliance with the License. 7*3859Sml29623 * 8*3859Sml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*3859Sml29623 * or http://www.opensolaris.org/os/licensing. 10*3859Sml29623 * See the License for the specific language governing permissions 11*3859Sml29623 * and limitations under the License. 12*3859Sml29623 * 13*3859Sml29623 * When distributing Covered Code, include this CDDL HEADER in each 14*3859Sml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*3859Sml29623 * If applicable, add the following below this CDDL HEADER, with the 16*3859Sml29623 * fields enclosed by brackets "[]" replaced with your own identifying 17*3859Sml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 18*3859Sml29623 * 19*3859Sml29623 * CDDL HEADER END 20*3859Sml29623 */ 21*3859Sml29623 /* 22*3859Sml29623 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23*3859Sml29623 * Use is subject to license terms. 24*3859Sml29623 */ 25*3859Sml29623 26*3859Sml29623 #ifndef _SYS_NXGE_NXGE_ESPC_HW_H 27*3859Sml29623 #define _SYS_NXGE_NXGE_ESPC_HW_H 28*3859Sml29623 29*3859Sml29623 #pragma ident "%Z%%M% %I% %E% SMI" 30*3859Sml29623 31*3859Sml29623 #ifdef __cplusplus 32*3859Sml29623 extern "C" { 33*3859Sml29623 #endif 34*3859Sml29623 35*3859Sml29623 #include <nxge_defs.h> 36*3859Sml29623 37*3859Sml29623 /* EPC / SPC Registers offsets */ 38*3859Sml29623 #define ESPC_PIO_EN_REG 0x040000 39*3859Sml29623 #define ESPC_PIO_EN_MASK 0x0000000000000001ULL 40*3859Sml29623 #define ESPC_PIO_STATUS_REG 0x040008 41*3859Sml29623 42*3859Sml29623 /* EPC Status Register */ 43*3859Sml29623 #define EPC_READ_INITIATE (1ULL << 31) 44*3859Sml29623 #define EPC_READ_COMPLETE (1 << 30) 45*3859Sml29623 #define EPC_WRITE_INITIATE (1 << 29) 46*3859Sml29623 #define EPC_WRITE_COMPLETE (1 << 28) 47*3859Sml29623 #define EPC_EEPROM_ADDR_BITS 0x3FFFF 48*3859Sml29623 #define EPC_EEPROM_ADDR_SHIFT 8 49*3859Sml29623 #define EPC_EEPROM_ADDR_MASK (EPC_EEPROM_ADDR_BITS << EPC_EEPROM_ADDR_SHIFT) 50*3859Sml29623 #define EPC_EEPROM_DATA_MASK 0xFF 51*3859Sml29623 52*3859Sml29623 #define EPC_RW_WAIT 10 /* TBD */ 53*3859Sml29623 54*3859Sml29623 #define ESPC_NCR_REG 0x040020 /* Count 128, step 8 */ 55*3859Sml29623 #define ESPC_REG_ADDR(reg) (FZC_PROM + (reg)) 56*3859Sml29623 57*3859Sml29623 #define ESPC_NCR_REGN(n) ((ESPC_REG_ADDR(ESPC_NCR_REG)) + n*8) 58*3859Sml29623 #define ESPC_NCR_VAL_MASK 0x00000000FFFFFFFFULL 59*3859Sml29623 60*3859Sml29623 #ifdef __cplusplus 61*3859Sml29623 } 62*3859Sml29623 #endif 63*3859Sml29623 64*3859Sml29623 #endif /* _SYS_NXGE_NXGE_ESPC_HW_H */ 65