1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_DMA_I8237A_H 28*0Sstevel@tonic-gate #define _SYS_DMA_I8237A_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 37*0Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 38*0Sstevel@tonic-gate /* All Rights Reserved */ 39*0Sstevel@tonic-gate 40*0Sstevel@tonic-gate #define D37A_MAX_CHAN 8 41*0Sstevel@tonic-gate #define D37A_DFR_ALIGN 0xf 42*0Sstevel@tonic-gate #define D37A_MIN_CHAN 0x0 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate /* 45*0Sstevel@tonic-gate * Defines for PC AT DMA controllers. 46*0Sstevel@tonic-gate */ 47*0Sstevel@tonic-gate 48*0Sstevel@tonic-gate /* 49*0Sstevel@tonic-gate * The PC/AT has two Intel 8237A-5 DMA controllers that provide 8 channels 50*0Sstevel@tonic-gate */ 51*0Sstevel@tonic-gate #define DMA_0WCNT 0x01 /* Channel word count */ 52*0Sstevel@tonic-gate #define DMA_1WCNT 0x03 /* Channel word count */ 53*0Sstevel@tonic-gate #define DMA_2WCNT 0x05 /* Channel word count */ 54*0Sstevel@tonic-gate #define DMA_3WCNT 0x07 /* Channel word count */ 55*0Sstevel@tonic-gate #define DMA_4WCNT 0xC2 /* (RESERVED) Channel word count */ 56*0Sstevel@tonic-gate #define DMA_5WCNT 0xC6 /* Channel word count */ 57*0Sstevel@tonic-gate #define DMA_6WCNT 0xCA /* Channel word count */ 58*0Sstevel@tonic-gate #define DMA_7WCNT 0xCE /* Channel word count */ 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate #define DMA_0ADR 0x00 /* Channel address register */ 61*0Sstevel@tonic-gate #define DMA_1ADR 0x02 /* Channel address register */ 62*0Sstevel@tonic-gate #define DMA_2ADR 0x04 /* Channel address register */ 63*0Sstevel@tonic-gate #define DMA_3ADR 0x06 /* Channel address register */ 64*0Sstevel@tonic-gate #define DMA_4ADR 0xC0 /* (RESERVED) Channel address register */ 65*0Sstevel@tonic-gate #define DMA_5ADR 0xC4 /* Channel address register */ 66*0Sstevel@tonic-gate #define DMA_6ADR 0xC8 /* Channel address register */ 67*0Sstevel@tonic-gate #define DMA_7ADR 0xCC /* Channel address register */ 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate /* 70*0Sstevel@tonic-gate * The Intel DMA controllers are augmented with 8-bit page registers 71*0Sstevel@tonic-gate * for each channel, allowing access to a 16MB address space. 72*0Sstevel@tonic-gate */ 73*0Sstevel@tonic-gate #define DMA_0PAGE 0x87 /* Channel 0 address extension reg */ 74*0Sstevel@tonic-gate #define DMA_1PAGE 0x83 /* Channel 1 address extension reg */ 75*0Sstevel@tonic-gate #define DMA_2PAGE 0x81 /* Channel 2 address extension reg */ 76*0Sstevel@tonic-gate #define DMA_3PAGE 0x82 /* Channel 3 address extension reg */ 77*0Sstevel@tonic-gate #define DMA_4PAGE 0 /* dummy address for dma chan. 4 page reg. */ 78*0Sstevel@tonic-gate #define DMA_5PAGE 0x8B /* Channel 5 address extension reg */ 79*0Sstevel@tonic-gate #define DMA_6PAGE 0x89 /* Channel 6 address extension reg */ 80*0Sstevel@tonic-gate #define DMA_7PAGE 0x8A /* Channel 7 address extension reg */ 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate /* 83*0Sstevel@tonic-gate * The EISA has an 8-bit high-page register for each channel 84*0Sstevel@tonic-gate * for access to a 32-bit address space. 85*0Sstevel@tonic-gate */ 86*0Sstevel@tonic-gate #define DMA_0HPG 0x487 /* port address for dma channel 0 */ 87*0Sstevel@tonic-gate /* high page reg */ 88*0Sstevel@tonic-gate #define DMA_1HPG 0x483 /* port address for dma channel 1 */ 89*0Sstevel@tonic-gate /* high page reg */ 90*0Sstevel@tonic-gate #define DMA_2HPG 0x481 /* port address for dma channel 2 */ 91*0Sstevel@tonic-gate /* high page reg */ 92*0Sstevel@tonic-gate #define DMA_3HPG 0x482 /* port address for dma channel 3 */ 93*0Sstevel@tonic-gate /* high page reg */ 94*0Sstevel@tonic-gate #define DMA_4HPG 0 /* dummy address for dma channel 4 */ 95*0Sstevel@tonic-gate /* high page reg */ 96*0Sstevel@tonic-gate #define DMA_5HPG 0x48B /* port address for dma channel 5 */ 97*0Sstevel@tonic-gate /* high page reg */ 98*0Sstevel@tonic-gate #define DMA_6HPG 0x489 /* port address for dma channel 6 */ 99*0Sstevel@tonic-gate /* high page reg */ 100*0Sstevel@tonic-gate #define DMA_7HPG 0x48A /* port address for dma channel 7 */ 101*0Sstevel@tonic-gate /* high page reg */ 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate /* 104*0Sstevel@tonic-gate * The EISA has an 8-bit high-count register for each channel 105*0Sstevel@tonic-gate * for xfer sizes up to 16MB. 106*0Sstevel@tonic-gate */ 107*0Sstevel@tonic-gate #define DMA_0XCNT 0x401 /* chan. 0 base and current count high */ 108*0Sstevel@tonic-gate #define DMA_1XCNT 0x403 /* chan. 1 base and current count high */ 109*0Sstevel@tonic-gate #define DMA_2XCNT 0x405 /* chan. 2 base and current count high */ 110*0Sstevel@tonic-gate #define DMA_3XCNT 0x407 /* chan. 3 base and current count high */ 111*0Sstevel@tonic-gate #define DMA_4XCNT 0 /* dummy chan. 4 base and current count high */ 112*0Sstevel@tonic-gate #define DMA_5XCNT 0x4C6 /* chan. 5 base and current count high */ 113*0Sstevel@tonic-gate #define DMA_6XCNT 0x4CA /* chan. 6 base and current count high */ 114*0Sstevel@tonic-gate #define DMA_7XCNT 0x4CE /* chan. 7 base and current count high */ 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate /* 117*0Sstevel@tonic-gate * I/O port addresses for controller 1 118*0Sstevel@tonic-gate */ 119*0Sstevel@tonic-gate #define DMAC1_CMD 0x08 /* Command reg */ 120*0Sstevel@tonic-gate #define DMAC1_REQ 0x09 /* request reg */ 121*0Sstevel@tonic-gate #define DMAC1_STAT 0x08 /* Status reg */ 122*0Sstevel@tonic-gate #define DMAC1_MASK 0x0A /* Mask set/reset register */ 123*0Sstevel@tonic-gate #define DMAC1_MODE 0x0B /* Mode reg */ 124*0Sstevel@tonic-gate #define DMAC1_CLFF 0x0C /* Clear byte pointer first/last flip-flop */ 125*0Sstevel@tonic-gate #define DMA1RTRWMC 0x0D /* read temp reg/write master clear */ 126*0Sstevel@tonic-gate #define DMA1CMR 0x0E /* clear mask register */ 127*0Sstevel@tonic-gate #define DMAC1_ALLMASK 0x0F /* Mask all registers */ 128*0Sstevel@tonic-gate #define DMAC1_SCM 0x40A /* set chain mode */ 129*0Sstevel@tonic-gate #define DMAC1_EWM 0x40B /* extended write mode */ 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate /* 132*0Sstevel@tonic-gate * I/O port addresses for controller 2 133*0Sstevel@tonic-gate */ 134*0Sstevel@tonic-gate #define DMAC2_CMD 0xD0 /* Command reg */ 135*0Sstevel@tonic-gate #define DMAC2_STAT 0xD0 /* Status reg */ 136*0Sstevel@tonic-gate #define DMAC2_REQ 0xD2 /* request reg */ 137*0Sstevel@tonic-gate #define DMAC2_MASK 0xD4 /* Mask set/reset register */ 138*0Sstevel@tonic-gate #define DMAC2_MODE 0xD6 /* Mode reg */ 139*0Sstevel@tonic-gate #define DMAC2_CLFF 0xD8 /* Clear byte pointer first/last flip-flop */ 140*0Sstevel@tonic-gate #define DMA2RTRWMC 0xDA /* read temp reg/write master clear */ 141*0Sstevel@tonic-gate #define DMA2CMR 0xDC /* clear mask register */ 142*0Sstevel@tonic-gate #define DMAC2_ALLMASK 0xDE /* Mask all registers */ 143*0Sstevel@tonic-gate #define DMAC2_SCM 0x4D4 /* set chain mode */ 144*0Sstevel@tonic-gate #define DMAC2_EWM 0x4D6 /* extended write mode */ 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate /* 147*0Sstevel@tonic-gate * Write-only Command register definitions. 148*0Sstevel@tonic-gate */ 149*0Sstevel@tonic-gate #define DMACMD_MEM_TO_MEM 0x01 /* memory-to-memory copy (1=enable) */ 150*0Sstevel@tonic-gate #define DMACMD_CHAN_HOLD 0x02 /* Channel 0 address hold (1=enable) */ 151*0Sstevel@tonic-gate #define DMACMD_CTLR_ENABLE 0x04 /* Controller disable (0=enabled) */ 152*0Sstevel@tonic-gate #define DMACMD_TIMING 0x08 /* normal/compressed timing (0=nrml) */ 153*0Sstevel@tonic-gate #define DMACMD_FIX_PRIO 0x10 /* fixed/rotating priority (0=fixed) */ 154*0Sstevel@tonic-gate #define DMACMD_WRT_SELECT 0x20 /* late/ext write selection (1=ext) */ 155*0Sstevel@tonic-gate #define DMACMD_DREQ_LEVEL 0x40 /* DREQ sense active (0=actv. high) */ 156*0Sstevel@tonic-gate #define DMACMD_DACK_LEVEL 0x80 /* DACK sense active (0=actv. low) */ 157*0Sstevel@tonic-gate 158*0Sstevel@tonic-gate /* 159*0Sstevel@tonic-gate * Initialization value for DMA controller. 160*0Sstevel@tonic-gate */ 161*0Sstevel@tonic-gate #define DMA_CTLR_INIT ~(DMACMD_MEM_TO_MEM | DMACMD_CHAN_HOLD | \ 162*0Sstevel@tonic-gate DMACMD_CTLR_ENABLE | DMACMD_TIMING | \ 163*0Sstevel@tonic-gate DMACMD_FIX_PRIO | DMACMD_WRT_SELECT | \ 164*0Sstevel@tonic-gate DMACMD_DREQ_LEVEL | DMACMD_DACK_LEVEL) 165*0Sstevel@tonic-gate 166*0Sstevel@tonic-gate /* 167*0Sstevel@tonic-gate * Write-only Mode register. There is actually a 6-bit Mode register 168*0Sstevel@tonic-gate * associated with each channel. These are written one at a time, with 169*0Sstevel@tonic-gate * the channel number indicated by the low-order 2 bits. 170*0Sstevel@tonic-gate */ 171*0Sstevel@tonic-gate 172*0Sstevel@tonic-gate #define DMAMODE_CHAN 0x03 /* Mask for the "channel select" bits. */ 173*0Sstevel@tonic-gate /* These indicate channel 0-3 */ 174*0Sstevel@tonic-gate #define DMAMODE_VERF 0x00 /* Verify Transfer */ 175*0Sstevel@tonic-gate #define DMAMODE_READ 0x04 /* Read Transfer */ 176*0Sstevel@tonic-gate #define DMAMODE_WRITE 0x08 /* Write Transfer */ 177*0Sstevel@tonic-gate /* Note: Above settings for bits 2-3 are */ 178*0Sstevel@tonic-gate /* "don't care" if bits 6-7 indicate */ 179*0Sstevel@tonic-gate /* cascade mode */ 180*0Sstevel@tonic-gate #define DMAMODE_AUTO 0x10 /* enable Autoinitialization on completion */ 181*0Sstevel@tonic-gate #define DMAMODE_DECR 0x20 /* Address Decrement. If 0, address incr */ 182*0Sstevel@tonic-gate #define DMAMODE_DEMAND 0x00 /* Select Demand mode */ 183*0Sstevel@tonic-gate /* Each DREQ causes transfers at full speed */ 184*0Sstevel@tonic-gate /* until DREQ goes inactive (after which it */ 185*0Sstevel@tonic-gate /* can be resumed) or either terminal-count */ 186*0Sstevel@tonic-gate /* happens or EOP is asserted */ 187*0Sstevel@tonic-gate #define DMAMODE_SINGLE 0x40 /* Select Single mode */ 188*0Sstevel@tonic-gate /* Each DREQ causes a single byte/word xfer */ 189*0Sstevel@tonic-gate #define DMAMODE_BLOCK 0x80 /* Select Block mode */ 190*0Sstevel@tonic-gate /* Each DREQ causes transfers at full speed */ 191*0Sstevel@tonic-gate /* until terminal count or EOP */ 192*0Sstevel@tonic-gate #define DMAMODE_CASC 0xC0 /* Select Cascade mode. On the PC-AT, this */ 193*0Sstevel@tonic-gate /* should be set for DMA 2 channel 0 ONLY */ 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate 196*0Sstevel@tonic-gate #define EISA_DMAIS 0x40a /* interrupt status register */ 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate #define DMA_MSK 0x0A /* Mask, enable disk, disable others */ 199*0Sstevel@tonic-gate #define DMA_CLEAR 0x1A /* Master clear */ 200*0Sstevel@tonic-gate #define IOCR 0x56 /* IO controller */ 201*0Sstevel@tonic-gate 202*0Sstevel@tonic-gate /* 203*0Sstevel@tonic-gate * DMA Channels. d_chan field of dmareq. 204*0Sstevel@tonic-gate */ 205*0Sstevel@tonic-gate 206*0Sstevel@tonic-gate /* 8 bit channels */ 207*0Sstevel@tonic-gate #define DMAE_CH0 0 /* Channel 0 */ 208*0Sstevel@tonic-gate #define DMAE_CH1 1 /* Channel 1 */ 209*0Sstevel@tonic-gate #define DMAE_CH2 2 /* Channel 2 */ 210*0Sstevel@tonic-gate #define DMAE_CH3 3 /* Channel 3 */ 211*0Sstevel@tonic-gate #define DMAE_CH4 4 /* Channel 4 */ 212*0Sstevel@tonic-gate /* 16 bit channels */ 213*0Sstevel@tonic-gate #define DMAE_CH5 5 /* Channel 5 */ 214*0Sstevel@tonic-gate #define DMAE_CH6 6 /* Channel 6 */ 215*0Sstevel@tonic-gate #define DMAE_CH7 7 /* Channel 7 */ 216*0Sstevel@tonic-gate 217*0Sstevel@tonic-gate /* 218*0Sstevel@tonic-gate * DMA Masks. 219*0Sstevel@tonic-gate */ 220*0Sstevel@tonic-gate #define DMA_SETMSK 4 /* Set mask bit */ 221*0Sstevel@tonic-gate #define DMA_CLRMSK 0 /* Clear mask bit */ 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate /* dma_alloc modes */ 224*0Sstevel@tonic-gate #define DMA_BLOCK 0 /* blocking task time allocation */ 225*0Sstevel@tonic-gate #define DMA_NBLOCK 1 /* non-blocking task time allocation */ 226*0Sstevel@tonic-gate 227*0Sstevel@tonic-gate #define EISA_DMA_8 0 /* 8-bit data path */ 228*0Sstevel@tonic-gate #define EISA_DMA_16 1<<2 /* 16-bit data path, word count */ 229*0Sstevel@tonic-gate #define EISA_DMA_32 2<<2 /* 32-bit data path */ 230*0Sstevel@tonic-gate #define EISA_DMA_16B 3<<2 /* 16-bit data path, byte count */ 231*0Sstevel@tonic-gate 232*0Sstevel@tonic-gate #define EISA_ENCM 4 /* enable chaining mode */ 233*0Sstevel@tonic-gate #define EISA_CMOK 8 /* chaining mode completed (OK) */ 234*0Sstevel@tonic-gate 235*0Sstevel@tonic-gate 236*0Sstevel@tonic-gate /* 237*0Sstevel@tonic-gate * Channel Address Array - makes life much easier 238*0Sstevel@tonic-gate */ 239*0Sstevel@tonic-gate struct d37A_chan_reg_addr { 240*0Sstevel@tonic-gate uchar_t addr_reg; /* address register */ 241*0Sstevel@tonic-gate uchar_t cnt_reg; /* count register */ 242*0Sstevel@tonic-gate uchar_t page_reg; /* page register */ 243*0Sstevel@tonic-gate uchar_t ff_reg; /* first-last flipflop */ 244*0Sstevel@tonic-gate uchar_t cmd_reg; /* command register */ 245*0Sstevel@tonic-gate uchar_t mode_reg; /* mode register */ 246*0Sstevel@tonic-gate uchar_t mask_reg; /* mask register */ 247*0Sstevel@tonic-gate uchar_t stat_reg; /* status register */ 248*0Sstevel@tonic-gate uchar_t reqt_reg; /* request register */ 249*0Sstevel@tonic-gate ushort_t hpage_reg; /* high page register */ 250*0Sstevel@tonic-gate ushort_t hcnt_reg; /* high count register */ 251*0Sstevel@tonic-gate ushort_t emode_reg; /* extended mode register */ 252*0Sstevel@tonic-gate ushort_t scm_reg; /* set chaining mode register */ 253*0Sstevel@tonic-gate }; 254*0Sstevel@tonic-gate 255*0Sstevel@tonic-gate /* 256*0Sstevel@tonic-gate * macro to initialize array of d37A_chan_reg_addr structures 257*0Sstevel@tonic-gate */ 258*0Sstevel@tonic-gate #define D37A_BASE_REGS_VALUES \ 259*0Sstevel@tonic-gate {DMA_0ADR, DMA_0WCNT, DMA_0PAGE, DMAC1_CLFF, \ 260*0Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 261*0Sstevel@tonic-gate DMA_0HPG, DMA_0XCNT, DMAC1_EWM, DMAC1_SCM}, \ 262*0Sstevel@tonic-gate {DMA_1ADR, DMA_1WCNT, DMA_1PAGE, DMAC1_CLFF, \ 263*0Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 264*0Sstevel@tonic-gate DMA_1HPG, DMA_1XCNT, DMAC1_EWM, DMAC1_SCM}, \ 265*0Sstevel@tonic-gate {DMA_2ADR, DMA_2WCNT, DMA_2PAGE, DMAC1_CLFF, \ 266*0Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 267*0Sstevel@tonic-gate DMA_2HPG, DMA_2XCNT, DMAC1_EWM, DMAC1_SCM}, \ 268*0Sstevel@tonic-gate {DMA_3ADR, DMA_3WCNT, DMA_3PAGE, DMAC1_CLFF, \ 269*0Sstevel@tonic-gate DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \ 270*0Sstevel@tonic-gate DMA_3HPG, DMA_3XCNT, DMAC1_EWM, DMAC1_SCM}, \ 271*0Sstevel@tonic-gate {DMA_4ADR, DMA_4WCNT, DMA_4PAGE, DMAC2_CLFF, \ 272*0Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 273*0Sstevel@tonic-gate DMA_4HPG, DMA_4XCNT, DMAC2_EWM, DMAC2_SCM}, \ 274*0Sstevel@tonic-gate {DMA_5ADR, DMA_5WCNT, DMA_5PAGE, DMAC2_CLFF, \ 275*0Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 276*0Sstevel@tonic-gate DMA_5HPG, DMA_5XCNT, DMAC2_EWM, DMAC2_SCM}, \ 277*0Sstevel@tonic-gate {DMA_6ADR, DMA_6WCNT, DMA_6PAGE, DMAC2_CLFF, \ 278*0Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 279*0Sstevel@tonic-gate DMA_6HPG, DMA_6XCNT, DMAC2_EWM, DMAC2_SCM}, \ 280*0Sstevel@tonic-gate {DMA_7ADR, DMA_7WCNT, DMA_7PAGE, DMAC2_CLFF, \ 281*0Sstevel@tonic-gate DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \ 282*0Sstevel@tonic-gate DMA_7HPG, DMA_7XCNT, DMAC2_EWM, DMAC2_SCM} 283*0Sstevel@tonic-gate 284*0Sstevel@tonic-gate extern int d37A_init(dev_info_t *); 285*0Sstevel@tonic-gate extern void d37A_dma_disable(int); 286*0Sstevel@tonic-gate extern void d37A_dma_enable(int); 287*0Sstevel@tonic-gate extern void d37A_dma_swstart(int); 288*0Sstevel@tonic-gate extern void d37A_dma_stop(int); 289*0Sstevel@tonic-gate extern void d37A_get_chan_stat(int, ulong_t *, int *); 290*0Sstevel@tonic-gate extern int d37A_dma_valid(int); 291*0Sstevel@tonic-gate extern void d37A_dma_release(int); 292*0Sstevel@tonic-gate 293*0Sstevel@tonic-gate /* The following 3 routines are intel specific : man page ddi_dmae_req(9S) */ 294*0Sstevel@tonic-gate #if defined(__i386) || defined(__amd64) 295*0Sstevel@tonic-gate extern uchar_t d37A_get_best_mode(struct ddi_dmae_req *); 296*0Sstevel@tonic-gate extern int d37A_prog_chan(struct ddi_dmae_req *, ddi_dma_cookie_t *, int); 297*0Sstevel@tonic-gate extern int d37A_dma_swsetup(struct ddi_dmae_req *, ddi_dma_cookie_t *, int); 298*0Sstevel@tonic-gate #endif 299*0Sstevel@tonic-gate 300*0Sstevel@tonic-gate #ifdef __cplusplus 301*0Sstevel@tonic-gate } 302*0Sstevel@tonic-gate #endif 303*0Sstevel@tonic-gate 304*0Sstevel@tonic-gate #endif /* _SYS_DMA_I8237A_H */ 305