xref: /onnv-gate/usr/src/uts/common/sys/ddi_intr_impl.h (revision 1725:01979e41e5c6)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
51542Sjohnny  * Common Development and Distribution License (the "License").
61542Sjohnny  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
221542Sjohnny  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #ifndef	_SYS_DDI_INTR_IMPL_H
270Sstevel@tonic-gate #define	_SYS_DDI_INTR_IMPL_H
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
300Sstevel@tonic-gate 
310Sstevel@tonic-gate /*
320Sstevel@tonic-gate  * Sun DDI interrupt implementation specific definitions
330Sstevel@tonic-gate  */
340Sstevel@tonic-gate 
350Sstevel@tonic-gate #ifdef	__cplusplus
360Sstevel@tonic-gate extern "C" {
370Sstevel@tonic-gate #endif
380Sstevel@tonic-gate 
390Sstevel@tonic-gate #ifdef _KERNEL
400Sstevel@tonic-gate 
410Sstevel@tonic-gate /*
420Sstevel@tonic-gate  * Typedef for interrupt ops
430Sstevel@tonic-gate  */
440Sstevel@tonic-gate typedef enum {
450Sstevel@tonic-gate 	DDI_INTROP_SUPPORTED_TYPES = 1,	/* 1 get supported interrupts types */
460Sstevel@tonic-gate 	DDI_INTROP_NINTRS,		/* 2 get num of interrupts supported */
470Sstevel@tonic-gate 	DDI_INTROP_ALLOC,		/* 3 allocate interrupt handle */
480Sstevel@tonic-gate 	DDI_INTROP_GETPRI,		/* 4 get priority */
490Sstevel@tonic-gate 	DDI_INTROP_SETPRI,		/* 5 set priority */
500Sstevel@tonic-gate 	DDI_INTROP_ADDISR,		/* 6 add interrupt handler */
510Sstevel@tonic-gate 	DDI_INTROP_DUPVEC,		/* 7 duplicate interrupt handler */
520Sstevel@tonic-gate 	DDI_INTROP_ENABLE,		/* 8 enable interrupt */
530Sstevel@tonic-gate 	DDI_INTROP_BLOCKENABLE,		/* 9 block enable interrupts */
540Sstevel@tonic-gate 	DDI_INTROP_BLOCKDISABLE,	/* 10 block disable interrupts */
550Sstevel@tonic-gate 	DDI_INTROP_DISABLE,		/* 11 disable interrupt */
560Sstevel@tonic-gate 	DDI_INTROP_REMISR,		/* 12 remove interrupt handler */
570Sstevel@tonic-gate 	DDI_INTROP_FREE,		/* 13 free interrupt handle */
580Sstevel@tonic-gate 	DDI_INTROP_GETCAP,		/* 14 get capacity */
590Sstevel@tonic-gate 	DDI_INTROP_SETCAP,		/* 15 set capacity */
600Sstevel@tonic-gate 	DDI_INTROP_SETMASK,		/* 16 set mask */
610Sstevel@tonic-gate 	DDI_INTROP_CLRMASK,		/* 17 clear mask */
620Sstevel@tonic-gate 	DDI_INTROP_GETPENDING,		/* 18 get pending interrupt */
630Sstevel@tonic-gate 	DDI_INTROP_NAVAIL		/* 19 get num of available interrupts */
640Sstevel@tonic-gate } ddi_intr_op_t;
650Sstevel@tonic-gate 
660Sstevel@tonic-gate /* Version number used in the handles */
670Sstevel@tonic-gate #define	DDI_INTR_VERSION_1	1
680Sstevel@tonic-gate #define	DDI_INTR_VERSION	DDI_INTR_VERSION_1
690Sstevel@tonic-gate 
700Sstevel@tonic-gate /*
710Sstevel@tonic-gate  * One such data structure is allocated per ddi_intr_handle_t
720Sstevel@tonic-gate  * This is the incore copy of the regular interrupt info.
730Sstevel@tonic-gate  */
740Sstevel@tonic-gate typedef struct ddi_intr_handle_impl {
750Sstevel@tonic-gate 	dev_info_t		*ih_dip;	/* dip associated with handle */
760Sstevel@tonic-gate 	uint16_t		ih_type;	/* interrupt type being used */
770Sstevel@tonic-gate 	ushort_t		ih_inum;	/* interrupt number */
78693Sgovinda 	uint32_t		ih_vector;	/* vector number */
790Sstevel@tonic-gate 	uint16_t		ih_ver;		/* Version */
800Sstevel@tonic-gate 	uint_t			ih_state;	/* interrupt handle state */
810Sstevel@tonic-gate 	uint_t			ih_cap;		/* interrupt capabilities */
820Sstevel@tonic-gate 	uint_t			ih_pri;		/* priority - bus dependent */
830Sstevel@tonic-gate 	krwlock_t		ih_rwlock;	/* read/write lock per handle */
840Sstevel@tonic-gate 
850Sstevel@tonic-gate 	uint_t			(*ih_cb_func)(caddr_t, caddr_t);
860Sstevel@tonic-gate 	void			*ih_cb_arg1;
870Sstevel@tonic-gate 	void			*ih_cb_arg2;
880Sstevel@tonic-gate 
890Sstevel@tonic-gate 	/*
90*1725Segillett 	 * The following 3 members are used to support MSI-X specific features
91*1725Segillett 	 */
92*1725Segillett 	uint_t			ih_flags;	/* Misc flags */
93*1725Segillett 	uint_t			ih_dup_cnt;	/* # of dupped msi-x vectors */
94*1725Segillett 	struct ddi_intr_handle_impl	*ih_main;
95*1725Segillett 						/* pntr to the main vector */
96*1725Segillett 	/*
970Sstevel@tonic-gate 	 * The next set of members are for 'scratch' purpose only.
980Sstevel@tonic-gate 	 * The DDI interrupt framework uses them internally and their
990Sstevel@tonic-gate 	 * interpretation is left to the framework. For now,
1000Sstevel@tonic-gate 	 *	scratch1	- used to send NINTRs information
1010Sstevel@tonic-gate 	 *			  to various nexus drivers.
1020Sstevel@tonic-gate 	 *	scratch2	- used to send 'behavior' flag
1030Sstevel@tonic-gate 	 *			  information to the nexus drivers
1041542Sjohnny 	 *			  from ddi_intr_alloc().  It is also
1051542Sjohnny 	 *			  used to send 'h_array' to the nexus drivers
1061542Sjohnny 	 *			  for ddi_intr_block_enable/disable() on x86.
107916Sschwartz 	 *	private		- On X86 it usually carries a pointer to
108916Sschwartz 	 *			  ihdl_plat_t.  Not used on SPARC platforms.
1090Sstevel@tonic-gate 	 */
1100Sstevel@tonic-gate 	void			*ih_private;	/* Platform specific data */
1110Sstevel@tonic-gate 	uint_t			ih_scratch1;	/* Scratch1: #interrupts */
1121542Sjohnny 	void			*ih_scratch2;	/* Scratch2: flag/h_array */
1130Sstevel@tonic-gate } ddi_intr_handle_impl_t;
1140Sstevel@tonic-gate 
1150Sstevel@tonic-gate /* values for ih_state (strictly for interrupt handle) */
1160Sstevel@tonic-gate #define	DDI_IHDL_STATE_ALLOC	0x01	/* Allocated. ddi_intr_alloc() called */
1170Sstevel@tonic-gate #define	DDI_IHDL_STATE_ADDED	0x02	/* Added interrupt handler */
1180Sstevel@tonic-gate 					/* ddi_intr_add_handler() called */
1190Sstevel@tonic-gate #define	DDI_IHDL_STATE_ENABLE	0x04	/* Enabled. ddi_intr_enable() called */
1200Sstevel@tonic-gate 
1210Sstevel@tonic-gate #define	DDI_INTR_IS_MSI_OR_MSIX(type) \
1220Sstevel@tonic-gate 	((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX)
1230Sstevel@tonic-gate 
124693Sgovinda #define	DDI_INTR_SUP_TYPES	DDI_INTR_TYPE_FIXED|DDI_INTR_TYPE_MSI|\
125693Sgovinda 				DDI_INTR_TYPE_MSIX
126693Sgovinda 
127*1725Segillett /* values for ih_flags */
128*1725Segillett #define	DDI_INTR_MSIX_DUP	0x01	/* MSI-X vector which has been dupped */
129*1725Segillett 
130999Slq150181 struct av_softinfo;
131999Slq150181 
1320Sstevel@tonic-gate /*
1330Sstevel@tonic-gate  * One such data structure is allocated per ddi_soft_intr_handle
1340Sstevel@tonic-gate  * This is the incore copy of the softint info.
1350Sstevel@tonic-gate  */
1360Sstevel@tonic-gate typedef struct ddi_softint_hdl_impl {
1370Sstevel@tonic-gate 	dev_info_t	*ih_dip;		/* dip associated with handle */
1380Sstevel@tonic-gate 	uint_t		ih_pri;			/* priority - bus dependent */
1390Sstevel@tonic-gate 	krwlock_t	ih_rwlock;		/* read/write lock per handle */
140999Slq150181 	struct av_softinfo *ih_pending;		/* whether softint is pending */
1410Sstevel@tonic-gate 
1420Sstevel@tonic-gate 	uint_t		(*ih_cb_func)(caddr_t, caddr_t);
1430Sstevel@tonic-gate 						/* cb function for soft ints */
1440Sstevel@tonic-gate 	void		*ih_cb_arg1;		/* arg1 of callback function */
1450Sstevel@tonic-gate 	void		*ih_cb_arg2;		/* arg2 passed to "trigger" */
1460Sstevel@tonic-gate 
1470Sstevel@tonic-gate 	/*
1480Sstevel@tonic-gate 	 * The next member is for 'scratch' purpose only.
1490Sstevel@tonic-gate 	 * The DDI interrupt framework uses it internally and its
1500Sstevel@tonic-gate 	 * interpretation is left to the framework.
1510Sstevel@tonic-gate 	 *	private		- used by the DDI framework to pass back
1520Sstevel@tonic-gate 	 *			  and forth 'softid' information on SPARC
1530Sstevel@tonic-gate 	 *			  side only. Not used on X86 platform.
1540Sstevel@tonic-gate 	 */
1550Sstevel@tonic-gate 	void		*ih_private;		/* Platform specific data */
1560Sstevel@tonic-gate } ddi_softint_hdl_impl_t;
1570Sstevel@tonic-gate 
1580Sstevel@tonic-gate /* Softint internal implementation defines */
1590Sstevel@tonic-gate #define	DDI_SOFT_INTR_PRI_M	4
1600Sstevel@tonic-gate #define	DDI_SOFT_INTR_PRI_H	6
1610Sstevel@tonic-gate 
1620Sstevel@tonic-gate /*
1630Sstevel@tonic-gate  * One such data structure is allocated for MSI-X enabled
1640Sstevel@tonic-gate  * device. If no MSI-X is enabled then it is NULL
1650Sstevel@tonic-gate  */
1660Sstevel@tonic-gate typedef struct ddi_intr_msix {
1670Sstevel@tonic-gate 	/* MSI-X Table related information */
1680Sstevel@tonic-gate 	ddi_acc_handle_t	msix_tbl_hdl;		/* MSI-X table handle */
169965Sgovinda 	uint32_t		*msix_tbl_addr;		/* MSI-X table addr */
170965Sgovinda 	uint32_t		msix_tbl_offset;	/* MSI-X table offset */
1710Sstevel@tonic-gate 
1720Sstevel@tonic-gate 	/* MSI-X PBA Table related information */
1730Sstevel@tonic-gate 	ddi_acc_handle_t	msix_pba_hdl;		/* MSI-X PBA handle */
174965Sgovinda 	uint32_t		*msix_pba_addr;		/* MSI-X PBA addr */
175965Sgovinda 	uint32_t		msix_pba_offset;	/* MSI-X PBA offset */
1760Sstevel@tonic-gate 
1770Sstevel@tonic-gate 	ddi_device_acc_attr_t	msix_dev_attr;		/* MSI-X device attr */
1780Sstevel@tonic-gate } ddi_intr_msix_t;
1790Sstevel@tonic-gate 
1800Sstevel@tonic-gate 
1810Sstevel@tonic-gate /*
1820Sstevel@tonic-gate  * One such data structure is allocated for each dip.
1830Sstevel@tonic-gate  * It has interrupt related information that can be
1840Sstevel@tonic-gate  * stored/retrieved for convenience.
1850Sstevel@tonic-gate  */
1860Sstevel@tonic-gate typedef struct devinfo_intr {
1870Sstevel@tonic-gate 	/* These three fields show what the device is capable of */
1880Sstevel@tonic-gate 	uint_t		devi_intr_sup_types;	/* Intrs supported by device */
1890Sstevel@tonic-gate 
1900Sstevel@tonic-gate 	ddi_intr_msix_t	*devi_msix_p;		/* MSI-X info, if supported */
1910Sstevel@tonic-gate 
1920Sstevel@tonic-gate 	/* Next three fields show current status for the device */
1930Sstevel@tonic-gate 	uint_t		devi_intr_curr_type;	/* Interrupt type being used */
1940Sstevel@tonic-gate 	uint_t		devi_intr_sup_nintrs;	/* #intr supported */
1950Sstevel@tonic-gate 	uint_t		devi_intr_curr_nintrs;	/* #intr currently being used */
1960Sstevel@tonic-gate 
1970Sstevel@tonic-gate 	ddi_intr_handle_t **devi_intr_handle_p;	/* Hdl for legacy intr APIs */
1980Sstevel@tonic-gate } devinfo_intr_t;
1990Sstevel@tonic-gate 
2000Sstevel@tonic-gate #define	NEXUS_HAS_INTR_OP(dip)	\
2010Sstevel@tonic-gate 	((DEVI(dip)->devi_ops->devo_bus_ops) && \
2020Sstevel@tonic-gate 	(DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \
2030Sstevel@tonic-gate 	(DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op))
2040Sstevel@tonic-gate 
2050Sstevel@tonic-gate int	i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op,
2060Sstevel@tonic-gate 	    ddi_intr_handle_impl_t *hdlp, void *result);
2070Sstevel@tonic-gate 
2080Sstevel@tonic-gate int	i_ddi_add_softint(ddi_softint_hdl_impl_t *);
2090Sstevel@tonic-gate void	i_ddi_remove_softint(ddi_softint_hdl_impl_t *);
210278Sgovinda int	i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *);
2110Sstevel@tonic-gate int	i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t);
2120Sstevel@tonic-gate 
2130Sstevel@tonic-gate void	i_ddi_intr_devi_init(dev_info_t *dip);
2140Sstevel@tonic-gate void	i_ddi_intr_devi_fini(dev_info_t *dip);
2150Sstevel@tonic-gate 
2160Sstevel@tonic-gate uint_t	i_ddi_intr_get_supported_types(dev_info_t *dip);
2170Sstevel@tonic-gate void	i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type);
2180Sstevel@tonic-gate uint_t	i_ddi_intr_get_current_type(dev_info_t *dip);
2190Sstevel@tonic-gate void	i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type);
2200Sstevel@tonic-gate uint_t	i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type);
2210Sstevel@tonic-gate void	i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs);
2220Sstevel@tonic-gate uint_t	i_ddi_intr_get_current_nintrs(dev_info_t *dip);
2230Sstevel@tonic-gate void	i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs);
2240Sstevel@tonic-gate 
225693Sgovinda ddi_intr_handle_t *i_ddi_get_intr_handle(dev_info_t *dip, int inum);
2260Sstevel@tonic-gate void	i_ddi_set_intr_handle(dev_info_t *dip, int inum,
2270Sstevel@tonic-gate 	    ddi_intr_handle_t *hdlp);
2280Sstevel@tonic-gate 
2290Sstevel@tonic-gate ddi_intr_msix_t	*i_ddi_get_msix(dev_info_t *dip);
2300Sstevel@tonic-gate void	i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p);
2310Sstevel@tonic-gate 
2320Sstevel@tonic-gate int32_t i_ddi_get_intr_weight(dev_info_t *);
2330Sstevel@tonic-gate int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t);
2340Sstevel@tonic-gate 
235916Sschwartz void	i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *);
236916Sschwartz void	i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *);
237916Sschwartz 
2380Sstevel@tonic-gate #define	DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \
2390Sstevel@tonic-gate 	hdlp->ih_cb_func = func; \
2400Sstevel@tonic-gate 	hdlp->ih_cb_arg1 = arg1; \
2410Sstevel@tonic-gate 	hdlp->ih_cb_arg2 = arg2;
2420Sstevel@tonic-gate 
243*1725Segillett #ifdef DEBUG
244*1725Segillett #define	I_DDI_VERIFY_MSIX_HANDLE(hdlp)					\
245*1725Segillett 	if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && 			\
246*1725Segillett 	    (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) {			\
247*1725Segillett 		ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip);		\
248*1725Segillett 		ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type);	\
249*1725Segillett 		ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector);	\
250*1725Segillett 		ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver);		\
251*1725Segillett 		ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap);		\
252*1725Segillett 		ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri);		\
253*1725Segillett 	}
254*1725Segillett #else
255*1725Segillett #define	I_DDI_VERIFY_MSIX_HANDLE(hdlp)
256*1725Segillett #endif
257*1725Segillett 
2580Sstevel@tonic-gate #else	/* _KERNEL */
2590Sstevel@tonic-gate 
2600Sstevel@tonic-gate typedef struct devinfo_intr devinfo_intr_t;
2610Sstevel@tonic-gate 
2620Sstevel@tonic-gate #endif	/* _KERNEL */
2630Sstevel@tonic-gate 
2640Sstevel@tonic-gate /*
2650Sstevel@tonic-gate  * Used only by old DDI interrupt interfaces.
2660Sstevel@tonic-gate  */
2670Sstevel@tonic-gate 
2680Sstevel@tonic-gate /*
2690Sstevel@tonic-gate  * This structure represents one interrupt possible from the given
2700Sstevel@tonic-gate  * device. It is used in an array for devices with multiple interrupts.
2710Sstevel@tonic-gate  */
2720Sstevel@tonic-gate struct intrspec {
2730Sstevel@tonic-gate 	uint_t intrspec_pri;		/* interrupt priority */
2740Sstevel@tonic-gate 	uint_t intrspec_vec;		/* vector # (0 if none) */
2750Sstevel@tonic-gate 	uint_t (*intrspec_func)();	/* function to call for interrupt, */
2760Sstevel@tonic-gate 					/* If (uint_t (*)()) 0, none. */
2770Sstevel@tonic-gate 					/* If (uint_t (*)()) 1, then */
2780Sstevel@tonic-gate };
2790Sstevel@tonic-gate 
2800Sstevel@tonic-gate #ifdef _KERNEL
2810Sstevel@tonic-gate 
2820Sstevel@tonic-gate /*
2830Sstevel@tonic-gate  * NOTE:
2840Sstevel@tonic-gate  *	The following 4 busops entry points are obsoleted with version
2850Sstevel@tonic-gate  *	9 or greater. Use i_ddi_intr_op interface in place of these
2860Sstevel@tonic-gate  *	obsolete interfaces.
2870Sstevel@tonic-gate  *
2880Sstevel@tonic-gate  *	Remove these busops entry points and all related data structures
2890Sstevel@tonic-gate  *	in future minor/major solaris release.
2900Sstevel@tonic-gate  */
2910Sstevel@tonic-gate typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t;
2920Sstevel@tonic-gate 
2930Sstevel@tonic-gate /* The following are the obsolete interfaces */
2940Sstevel@tonic-gate ddi_intrspec_t	i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip,
2950Sstevel@tonic-gate 	    uint_t inumber);
2960Sstevel@tonic-gate 
2970Sstevel@tonic-gate int	i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip,
2980Sstevel@tonic-gate 	    ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep,
2990Sstevel@tonic-gate 	    ddi_idevice_cookie_t *idevice_cookiep,
3000Sstevel@tonic-gate 	    uint_t (*int_handler)(caddr_t int_handler_arg),
3010Sstevel@tonic-gate 	    caddr_t int_handler_arg, int kind);
3020Sstevel@tonic-gate 
3030Sstevel@tonic-gate void	i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip,
3040Sstevel@tonic-gate 	    ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie);
3050Sstevel@tonic-gate 
3060Sstevel@tonic-gate int	i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip,
3070Sstevel@tonic-gate 	    ddi_intr_ctlop_t op, void *arg, void *val);
3080Sstevel@tonic-gate 
3090Sstevel@tonic-gate #endif	/* _KERNEL */
3100Sstevel@tonic-gate 
3110Sstevel@tonic-gate #ifdef	__cplusplus
3120Sstevel@tonic-gate }
3130Sstevel@tonic-gate #endif
3140Sstevel@tonic-gate 
3150Sstevel@tonic-gate #endif	/* _SYS_DDI_INTR_IMPL_H */
316