xref: /onnv-gate/usr/src/uts/common/sys/1394/targets/dcam1394/dcam.h (revision 21:9318364fb703)
1*21Sap25164 /*
2*21Sap25164  * CDDL HEADER START
3*21Sap25164  *
4*21Sap25164  * The contents of this file are subject to the terms of the
5*21Sap25164  * Common Development and Distribution License, Version 1.0 only
6*21Sap25164  * (the "License").  You may not use this file except in compliance
7*21Sap25164  * with the License.
8*21Sap25164  *
9*21Sap25164  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*21Sap25164  * or http://www.opensolaris.org/os/licensing.
11*21Sap25164  * See the License for the specific language governing permissions
12*21Sap25164  * and limitations under the License.
13*21Sap25164  *
14*21Sap25164  * When distributing Covered Code, include this CDDL HEADER in each
15*21Sap25164  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*21Sap25164  * If applicable, add the following below this CDDL HEADER, with the
17*21Sap25164  * fields enclosed by brackets "[]" replaced with your own identifying
18*21Sap25164  * information: Portions Copyright [yyyy] [name of copyright owner]
19*21Sap25164  *
20*21Sap25164  * CDDL HEADER END
21*21Sap25164  */
22*21Sap25164 /*
23*21Sap25164  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24*21Sap25164  * Use is subject to license terms.
25*21Sap25164  */
26*21Sap25164 
27*21Sap25164 #ifndef _SYS_1394_TARGETS_DCAM1394_DCAM_H
28*21Sap25164 #define	_SYS_1394_TARGETS_DCAM1394_DCAM_H
29*21Sap25164 
30*21Sap25164 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*21Sap25164 
32*21Sap25164 #include <sys/modctl.h>
33*21Sap25164 #include <sys/ksynch.h>
34*21Sap25164 #include <sys/types.h>
35*21Sap25164 #include <sys/dditypes.h>
36*21Sap25164 #include <sys/1394/t1394.h>
37*21Sap25164 #include <sys/dcam/dcam1394_io.h>
38*21Sap25164 
39*21Sap25164 #ifdef	__cplusplus
40*21Sap25164 extern "C" {
41*21Sap25164 #endif
42*21Sap25164 
43*21Sap25164 #define	ILP32_PTR_SIZE	4	/* caller's data model type	*/
44*21Sap25164 #define	LP64_PTR_SIZE 	8
45*21Sap25164 
46*21Sap25164 #define	DCAM_POWER_OFF	0	/* power management state	*/
47*21Sap25164 #define	DCAM_POWER_ON	1
48*21Sap25164 
49*21Sap25164 #define	DCAM1394_MINOR_CTRL	0x80		/* this is the control device */
50*21Sap25164 
51*21Sap25164 #define	DCAM1394_FLAG_ATTACH_COMPLETE	0x1  /* dcam_attach() is complete */
52*21Sap25164 #define	DCAM1394_FLAG_OPEN		0x2  /* driver is open */
53*21Sap25164 #define	DCAM1394_FLAG_OPEN_CAPTURE	0x4  /* device is open for capture */
54*21Sap25164 #define	DCAM1394_FLAG_OPEN_CONTROL	0x8  /* device is open for control */
55*21Sap25164 #define	DCAM1394_FLAG_FRAME_RCV_INIT	0x10
56*21Sap25164 #define	DCAM1394_FLAG_FRAME_RCVING	0x20
57*21Sap25164 #define	DCAM1394_FLAG_READ_REQ_PROC	0x40
58*21Sap25164 #define	DCAM1394_FLAG_READ_REQ_INVALID	0x80
59*21Sap25164 
60*21Sap25164 #define	IS_VALID	0x1
61*21Sap25164 #define	IS_PRESENT	0x2
62*21Sap25164 #define	CAP_GET		0x4
63*21Sap25164 #define	CAP_SET		0x8
64*21Sap25164 #define	CAP_CTRL_SET	0x10
65*21Sap25164 
66*21Sap25164 #define	MAX_STR_LEN	50
67*21Sap25164 
68*21Sap25164 #define	DEV_TO_INSTANCE(d) (getminor(d) & 0x7f)
69*21Sap25164 
70*21Sap25164 typedef uint_t
71*21Sap25164     dcam1394_param_attr_t[DCAM1394_NUM_PARAM][DCAM1394_NUM_SUBPARAM];
72*21Sap25164 
73*21Sap25164 typedef struct buff_info_s {
74*21Sap25164 	uint_t			vid_mode;
75*21Sap25164 	unsigned int		seq_num;
76*21Sap25164 	hrtime_t		timestamp;
77*21Sap25164 	caddr_t			kaddr_p;		/* kernel data buffer */
78*21Sap25164 	ddi_dma_handle_t	dma_handle;		/* bind handle */
79*21Sap25164 	ddi_acc_handle_t	data_acc_handle;  	/* acc handle */
80*21Sap25164 	ddi_dma_cookie_t	dma_cookie;		/* cookie */
81*21Sap25164 	size_t			real_len;    		/* mem len */
82*21Sap25164 	uint_t			dma_cookie_count;	/* cookie count */
83*21Sap25164 } buff_info_t;
84*21Sap25164 
85*21Sap25164 #define	MAX_NUM_READ_PTRS 1
86*21Sap25164 
87*21Sap25164 typedef struct ring_buff_s {
88*21Sap25164 	size_t		 num_buffs;
89*21Sap25164 	size_t		 buff_num_bytes;
90*21Sap25164 	buff_info_t	*buff_info_array_p;
91*21Sap25164 	int		 num_read_ptrs;
92*21Sap25164 	int		 read_ptr_incr_val;
93*21Sap25164 	size_t		 read_ptr_pos[MAX_NUM_READ_PTRS];
94*21Sap25164 	uint_t		 status[MAX_NUM_READ_PTRS];
95*21Sap25164 	size_t		 write_ptr_pos;
96*21Sap25164 } ring_buff_t;
97*21Sap25164 
98*21Sap25164 typedef struct dcam_state_s {
99*21Sap25164 	dev_info_t			*dip;
100*21Sap25164 	int				instance;
101*21Sap25164 	int				usr_model;
102*21Sap25164 	t1394_handle_t			sl_handle;
103*21Sap25164 	t1394_attachinfo_t		attachinfo;
104*21Sap25164 	t1394_targetinfo_t		targetinfo;
105*21Sap25164 	t1394_isoch_singleinfo_t	sii;
106*21Sap25164 	t1394_isoch_single_out_t	sii_output_args;
107*21Sap25164 	t1394_isoch_single_handle_t	sii_hdl;
108*21Sap25164 	t1394_isoch_dma_handle_t 	isoch_handle;
109*21Sap25164 	kmutex_t			softc_mutex;
110*21Sap25164 	kmutex_t			dcam_frame_is_done_mutex;
111*21Sap25164 	dcam1394_param_attr_t		param_attr;
112*21Sap25164 
113*21Sap25164 	ixl1394_command_t		*ixlp;
114*21Sap25164 
115*21Sap25164 	ring_buff_t			*ring_buff_p;
116*21Sap25164 	unsigned int			seq_count;
117*21Sap25164 	uint_t				reader_flags[MAX_NUM_READ_PTRS];
118*21Sap25164 	uint_t				flags;
119*21Sap25164 	int				cur_vid_mode;
120*21Sap25164 	int				cur_frame_rate;
121*21Sap25164 	int				cur_ring_buff_capacity;
122*21Sap25164 	int				param_status;
123*21Sap25164 	struct pollhead			dcam_pollhead;
124*21Sap25164 	int				camera_online;
125*21Sap25164 	int				pm_open_count;
126*21Sap25164 	int				pm_cable_power;
127*21Sap25164 	int				suspended;
128*21Sap25164 	ddi_callback_id_t		event_id;
129*21Sap25164 } dcam_state_t;
130*21Sap25164 
131*21Sap25164 int _init(void);
132*21Sap25164 int _info(struct modinfo *modinfop);
133*21Sap25164 int _fini(void);
134*21Sap25164 
135*21Sap25164 int dcam_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
136*21Sap25164 int dcam_power(dev_info_t *dip, int component, int level);
137*21Sap25164 int dcam_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result);
138*21Sap25164 int dcam_identify(dev_info_t *dip);
139*21Sap25164 int dcam_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
140*21Sap25164 int dcam_open(dev_t *devp, int flag, int otyp, cred_t *credp);
141*21Sap25164 int dcam_close(dev_t dev, int flags, int otyp, cred_t *credp);
142*21Sap25164 int dcam_read(dev_t dev, struct uio *uio, cred_t *credp);
143*21Sap25164 int dcam_write(dev_t dev, struct uio *uio, cred_t *credp);
144*21Sap25164 int dcam_mmap(dev_t dev, off_t off, int prot);
145*21Sap25164 int dcam_devmap(dev_t dev, devmap_cookie_t dhp, offset_t off, size_t len,
146*21Sap25164     size_t *maplen, uint_t model);
147*21Sap25164 int dcam_ioctl(dev_t dev, int cmd, intptr_t arg, int mode,
148*21Sap25164     cred_t *credp, int *rvalp);
149*21Sap25164 int dcam_chpoll(dev_t dev, short events, int anyyet, short *reventsp,
150*21Sap25164     struct pollhead **phpp);
151*21Sap25164 int dcam_intr(caddr_t dcam_softc_p);
152*21Sap25164 void dcam_bus_reset_notify(dev_info_t *dip, ddi_eventcookie_t ev_cookie,
153*21Sap25164     void *arg, void *impl_data);
154*21Sap25164 
155*21Sap25164 
156*21Sap25164 ring_buff_t *ring_buff_create(dcam_state_t *softc_p, size_t num_buffs,
157*21Sap25164     size_t buff_num_bytes);
158*21Sap25164 void ring_buff_free(dcam_state_t *softc_p, ring_buff_t *ring_buff_p);
159*21Sap25164 int ring_buff_reader_add(ring_buff_t *ring_buff_p);
160*21Sap25164 int ring_buff_reader_remove(ring_buff_t *ring_buff_p, int reader_id);
161*21Sap25164 buff_info_t *ring_buff_read_ptr_buff_get(ring_buff_t *ring_buff_p, int
162*21Sap25164     reader_id);
163*21Sap25164 size_t ring_buff_read_ptr_pos_get(ring_buff_t *ring_buff_p, int read_ptr_id);
164*21Sap25164 void ring_buff_read_ptr_incr(ring_buff_t *ring_buff_p, int read_ptr_id);
165*21Sap25164 size_t ring_buff_write_ptr_pos_get(ring_buff_t *ring_buff_p);
166*21Sap25164 void ring_buff_write_ptr_incr(ring_buff_t *ring_buff_p);
167*21Sap25164 int dcam_frame_rcv_stop(dcam_state_t *softc_p);
168*21Sap25164 int dcam1394_ioctl_frame_rcv_start(dcam_state_t *softc_p);
169*21Sap25164 
170*21Sap25164 #ifdef	__cplusplus
171*21Sap25164 }
172*21Sap25164 #endif
173*21Sap25164 
174*21Sap25164 #endif	/* _SYS_1394_TARGETS_DCAM1394_DCAM_H */
175