1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 1999-2002 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_1394_H1394_H 28*0Sstevel@tonic-gate #define _SYS_1394_H1394_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * h1394.h 34*0Sstevel@tonic-gate * Contains the structure and error codes used to communicate 35*0Sstevel@tonic-gate * between the HAL and the rest of the 1394 Software Framework 36*0Sstevel@tonic-gate */ 37*0Sstevel@tonic-gate 38*0Sstevel@tonic-gate #include <sys/types.h> 39*0Sstevel@tonic-gate #include <sys/modctl.h> 40*0Sstevel@tonic-gate #include <sys/ddi.h> 41*0Sstevel@tonic-gate #include <sys/sunddi.h> 42*0Sstevel@tonic-gate #include <sys/note.h> 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate #include <sys/1394/cmd1394.h> 45*0Sstevel@tonic-gate #include <sys/1394/id1394.h> 46*0Sstevel@tonic-gate 47*0Sstevel@tonic-gate #ifdef __cplusplus 48*0Sstevel@tonic-gate extern "C" { 49*0Sstevel@tonic-gate #endif 50*0Sstevel@tonic-gate 51*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL7 7 52*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL6 6 53*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL5 5 54*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL4 4 55*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL3 3 56*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL2 2 57*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL1 1 58*0Sstevel@tonic-gate #define H1394_CLEANUP_LEVEL0 0 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate /* h1394_phy_t */ 61*0Sstevel@tonic-gate typedef enum { 62*0Sstevel@tonic-gate H1394_PHY_1995 = 0, 63*0Sstevel@tonic-gate H1394_PHY_1394A = 1 64*0Sstevel@tonic-gate } h1394_phy_t; 65*0Sstevel@tonic-gate 66*0Sstevel@tonic-gate /* h1394_error_t */ 67*0Sstevel@tonic-gate typedef enum { 68*0Sstevel@tonic-gate H1394_LOCK_RESP_ERR = 1, 69*0Sstevel@tonic-gate H1394_POSTED_WR_ERR = 2, 70*0Sstevel@tonic-gate H1394_SELF_INITIATED_SHUTDOWN = 3, 71*0Sstevel@tonic-gate H1394_CYCLE_TOO_LONG = 4 72*0Sstevel@tonic-gate } h1394_error_t; 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate /* 75*0Sstevel@tonic-gate * h1394_posted_wr_err_t 76*0Sstevel@tonic-gate * The upper 16 bits contain the source id (bus/node) of the source node, 77*0Sstevel@tonic-gate * the lower 48 bits contain the address that the error occured at. 78*0Sstevel@tonic-gate */ 79*0Sstevel@tonic-gate typedef struct h1394_posted_wr_err_s { 80*0Sstevel@tonic-gate uint64_t addr; 81*0Sstevel@tonic-gate } h1394_posted_wr_err_t; 82*0Sstevel@tonic-gate 83*0Sstevel@tonic-gate /* 84*0Sstevel@tonic-gate * h1394_node_pwr_flags_t 85*0Sstevel@tonic-gate * Node power flags info 86*0Sstevel@tonic-gate */ 87*0Sstevel@tonic-gate typedef enum { 88*0Sstevel@tonic-gate H1394_NODE_PWR_FLAGS_NONE = (1 << 1), 89*0Sstevel@tonic-gate H1394_BUS_PWRD_NODES_ONE_MORE = (1 << 2), 90*0Sstevel@tonic-gate H1394_BUS_PWRD_NODES_ONE_LESS = (1 << 3), 91*0Sstevel@tonic-gate H1394_ACTIVE_NODES_ONE_MORE = (1 << 4), 92*0Sstevel@tonic-gate H1394_ACTIVE_NODES_ONE_LESS = (1 << 5) 93*0Sstevel@tonic-gate } h1394_node_pwr_flags_t; 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate /* 96*0Sstevel@tonic-gate * h1394_addr_type_t 97*0Sstevel@tonic-gate * h1394_addr_map.addr_type 98*0Sstevel@tonic-gate */ 99*0Sstevel@tonic-gate typedef enum { 100*0Sstevel@tonic-gate H1394_ADDR_POSTED_WRITE = 0, 101*0Sstevel@tonic-gate H1394_ADDR_NORMAL = 1, 102*0Sstevel@tonic-gate H1394_ADDR_CSR = 2, 103*0Sstevel@tonic-gate H1394_ADDR_PHYSICAL = 3, 104*0Sstevel@tonic-gate H1394_ADDR_RESERVED = 4 105*0Sstevel@tonic-gate } h1394_addr_type_t; 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate /* h1394_mblk_t */ 108*0Sstevel@tonic-gate typedef struct h1394_mblk_s { 109*0Sstevel@tonic-gate mblk_t *curr_mblk; 110*0Sstevel@tonic-gate unsigned char *curr_offset; 111*0Sstevel@tonic-gate uint_t length; 112*0Sstevel@tonic-gate mblk_t *next_mblk; 113*0Sstevel@tonic-gate unsigned char *next_offset; 114*0Sstevel@tonic-gate } h1394_mblk_t; 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate /* h1394_cmd_priv_t */ 117*0Sstevel@tonic-gate typedef struct h1394_cmd_priv_s { 118*0Sstevel@tonic-gate uint_t speed; 119*0Sstevel@tonic-gate uint_t ack_tstamp; 120*0Sstevel@tonic-gate uint_t recv_tstamp; 121*0Sstevel@tonic-gate uint_t bus_generation; 122*0Sstevel@tonic-gate h1394_mblk_t mblk; 123*0Sstevel@tonic-gate void *hal_overhead; 124*0Sstevel@tonic-gate } h1394_cmd_priv_t; 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Used by a single thread", h1394_cmd_priv_s \ 127*0Sstevel@tonic-gate h1394_mblk_s::next_mblk h1394_mblk_s::next_offset)) 128*0Sstevel@tonic-gate 129*0Sstevel@tonic-gate /* h1394_evts_t */ 130*0Sstevel@tonic-gate typedef struct h1394_evts_s { 131*0Sstevel@tonic-gate uint_t hal_version; 132*0Sstevel@tonic-gate uint_t reserved; 133*0Sstevel@tonic-gate void (*shutdown)(void *hal_private); 134*0Sstevel@tonic-gate int (*send_phy_configuration_packet)(void *hal_private, 135*0Sstevel@tonic-gate cmd1394_cmd_t *phy_pkt, h1394_cmd_priv_t *cmd_private, 136*0Sstevel@tonic-gate int *result); 137*0Sstevel@tonic-gate int (*read)(void *hal_private, cmd1394_cmd_t *req, 138*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 139*0Sstevel@tonic-gate int (*read_response)(void *hal_private, cmd1394_cmd_t *resp, 140*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 141*0Sstevel@tonic-gate int (*write)(void *hal_private, cmd1394_cmd_t *req, 142*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 143*0Sstevel@tonic-gate int (*write_response)(void *hal_private, cmd1394_cmd_t *resp, 144*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 145*0Sstevel@tonic-gate void (*response_complete)(void *hal_private, cmd1394_cmd_t *resp, 146*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private); 147*0Sstevel@tonic-gate int (*lock)(void *hal_private, cmd1394_cmd_t *req, 148*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 149*0Sstevel@tonic-gate int (*lock_response)(void *hal_private, cmd1394_cmd_t *resp, 150*0Sstevel@tonic-gate h1394_cmd_priv_t *cmd_private, int *result); 151*0Sstevel@tonic-gate int (*alloc_isoch_dma)(void *hal_private, 152*0Sstevel@tonic-gate id1394_isoch_dmainfo_t *idi, void **hal_idma_handle, 153*0Sstevel@tonic-gate int *result); 154*0Sstevel@tonic-gate void (*free_isoch_dma)(void *hal_private, 155*0Sstevel@tonic-gate void *hal_isoch_dma_handle); 156*0Sstevel@tonic-gate int (*start_isoch_dma)(void *hal_private, 157*0Sstevel@tonic-gate void *hal_isoch_dma_handle, 158*0Sstevel@tonic-gate id1394_isoch_dma_ctrlinfo_t *idma_ctrlinfo, uint_t flags, 159*0Sstevel@tonic-gate int *result); 160*0Sstevel@tonic-gate void (*stop_isoch_dma)(void *hal_private, void *hal_isoch_dma_handle, 161*0Sstevel@tonic-gate int *result); 162*0Sstevel@tonic-gate int (*update_isoch_dma)(void *hal_private, 163*0Sstevel@tonic-gate void *hal_isoch_dma_handle, 164*0Sstevel@tonic-gate id1394_isoch_dma_updateinfo_t *idma_updateinfo, 165*0Sstevel@tonic-gate uint_t flags, int *result); 166*0Sstevel@tonic-gate int (*update_config_rom)(void *hal_private, void *local_buf, 167*0Sstevel@tonic-gate uint_t quadlet_count); 168*0Sstevel@tonic-gate int (*bus_reset)(void *hal_private); 169*0Sstevel@tonic-gate int (*short_bus_reset)(void *hal_private); 170*0Sstevel@tonic-gate int (*set_contender_bit)(void *hal_private); 171*0Sstevel@tonic-gate int (*set_root_holdoff_bit)(void *hal_private); 172*0Sstevel@tonic-gate int (*set_gap_count)(void *hal_private, uint_t gap_count); 173*0Sstevel@tonic-gate int (*csr_read)(void *hal_private, uint_t offset, uint32_t *data); 174*0Sstevel@tonic-gate int (*csr_write)(void *hal_private, uint_t offset, uint32_t data); 175*0Sstevel@tonic-gate int (*csr_cswap32)(void *hal_private, uint_t generation, 176*0Sstevel@tonic-gate uint_t offset, uint32_t compare, uint32_t swap, 177*0Sstevel@tonic-gate uint32_t *old); 178*0Sstevel@tonic-gate int (*physical_arreq_enable_set)(void *hal_private, uint64_t mask, 179*0Sstevel@tonic-gate uint_t generation); 180*0Sstevel@tonic-gate int (*physical_arreq_enable_clr)(void *hal_private, uint64_t mask, 181*0Sstevel@tonic-gate uint_t generation); 182*0Sstevel@tonic-gate void (*node_power_state_change)(void *hal_private, 183*0Sstevel@tonic-gate h1394_node_pwr_flags_t nodeflags); 184*0Sstevel@tonic-gate } h1394_evts_t; 185*0Sstevel@tonic-gate /* Version value for h1394_evts_t */ 186*0Sstevel@tonic-gate #define H1394_EVTS_V1 1 187*0Sstevel@tonic-gate 188*0Sstevel@tonic-gate #define HAL_CALL(hal) (hal)->halinfo.hal_events 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate /* Result field returned by read/write/lock requests */ 191*0Sstevel@tonic-gate #define H1394_STATUS_NO_ERROR 0 192*0Sstevel@tonic-gate #define H1394_STATUS_INVALID_BUSGEN 1 193*0Sstevel@tonic-gate #define H1394_STATUS_EMPTY_TLABEL 2 194*0Sstevel@tonic-gate #define H1394_STATUS_NOMORE_SPACE 3 195*0Sstevel@tonic-gate #define H1394_STATUS_INTERNAL_ERROR 4 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate /* h1394_addr_map_t */ 198*0Sstevel@tonic-gate typedef struct h1394_addr_map_s { 199*0Sstevel@tonic-gate uint64_t address; 200*0Sstevel@tonic-gate uint64_t length; 201*0Sstevel@tonic-gate h1394_addr_type_t addr_type; 202*0Sstevel@tonic-gate } h1394_addr_map_t; 203*0Sstevel@tonic-gate 204*0Sstevel@tonic-gate /* h1394_halinfo_t */ 205*0Sstevel@tonic-gate typedef struct h1394_halinfo_s { 206*0Sstevel@tonic-gate void *hal_private; 207*0Sstevel@tonic-gate dev_info_t *dip; 208*0Sstevel@tonic-gate h1394_evts_t hal_events; 209*0Sstevel@tonic-gate ddi_iblock_cookie_t hw_interrupt; 210*0Sstevel@tonic-gate 211*0Sstevel@tonic-gate /* Buffer attributes */ 212*0Sstevel@tonic-gate ddi_device_acc_attr_t acc_attr; 213*0Sstevel@tonic-gate ddi_dma_attr_t dma_attr; 214*0Sstevel@tonic-gate 215*0Sstevel@tonic-gate /* Type of PHY on HAL */ 216*0Sstevel@tonic-gate h1394_phy_t phy; 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate uint_t hal_overhead; /* in bytes */ 219*0Sstevel@tonic-gate uint32_t bus_capabilities; 220*0Sstevel@tonic-gate uint64_t guid; 221*0Sstevel@tonic-gate uint32_t node_capabilities; 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate /* 224*0Sstevel@tonic-gate * The maximum value generation can have before 225*0Sstevel@tonic-gate * it rolls over (inclusive) 226*0Sstevel@tonic-gate */ 227*0Sstevel@tonic-gate uint_t max_generation; 228*0Sstevel@tonic-gate 229*0Sstevel@tonic-gate /* Description of the 1394 Address Space */ 230*0Sstevel@tonic-gate h1394_addr_map_t *addr_map; 231*0Sstevel@tonic-gate uint_t addr_map_num_entries; 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate /* Description of the reserved spaces */ 234*0Sstevel@tonic-gate h1394_addr_map_t *resv_map; 235*0Sstevel@tonic-gate uint_t resv_map_num_entries; 236*0Sstevel@tonic-gate } h1394_halinfo_t; 237*0Sstevel@tonic-gate 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate /* Calls to Services layer during HAL driver _init() and _fini() */ 240*0Sstevel@tonic-gate int h1394_init(struct modlinkage *modlp); 241*0Sstevel@tonic-gate void h1394_fini(struct modlinkage *modlp); 242*0Sstevel@tonic-gate 243*0Sstevel@tonic-gate 244*0Sstevel@tonic-gate /* Calls to Services layer during HAL driver attach/detach */ 245*0Sstevel@tonic-gate int h1394_attach(h1394_halinfo_t *halinfo, ddi_attach_cmd_t cmd, 246*0Sstevel@tonic-gate void **sl_private); 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate int h1394_detach(void **sl_private, ddi_detach_cmd_t cmd); 249*0Sstevel@tonic-gate 250*0Sstevel@tonic-gate 251*0Sstevel@tonic-gate /* Calls to Services layer during HW interrupt processing */ 252*0Sstevel@tonic-gate void h1394_cmd_is_complete(void *sl_private, cmd1394_cmd_t *command_id, 253*0Sstevel@tonic-gate uint32_t cmd_type, int status); 254*0Sstevel@tonic-gate /* Command types (passed to h1394_command_is_complete) */ 255*0Sstevel@tonic-gate #define H1394_AT_REQ 0 256*0Sstevel@tonic-gate #define H1394_AT_RESP 1 257*0Sstevel@tonic-gate /* Command statuses (passed to h1394_command_is_complete) */ 258*0Sstevel@tonic-gate #define H1394_CMD_SUCCESS 0x00 /* ack_complete */ 259*0Sstevel@tonic-gate #define H1394_CMD_ETIMEOUT 0x01 /* evt_missing_ack */ 260*0Sstevel@tonic-gate #define H1394_CMD_EBUSRESET 0x02 /* evt_flushed */ 261*0Sstevel@tonic-gate #define H1394_CMD_EDEVICE_BUSY 0x03 /* ack_busy_? */ 262*0Sstevel@tonic-gate #define H1394_CMD_EDATA_ERROR 0x04 /* ack_data_error */ 263*0Sstevel@tonic-gate #define H1394_CMD_ETYPE_ERROR 0x05 /* ack_type_error */ 264*0Sstevel@tonic-gate #define H1394_CMD_EADDR_ERROR 0x06 /* resp_address_error */ 265*0Sstevel@tonic-gate #define H1394_CMD_ERSRC_CONFLICT 0x07 /* resp_conflict_error */ 266*0Sstevel@tonic-gate #define H1394_CMD_EDEVICE_POWERUP 0x08 /* ack_tardy */ 267*0Sstevel@tonic-gate #define H1394_CMD_EDEVICE_ERROR 0x09 /* device error */ 268*0Sstevel@tonic-gate #define H1394_CMD_EUNKNOWN_ERROR 0x0A /* unknown error type */ 269*0Sstevel@tonic-gate 270*0Sstevel@tonic-gate void h1394_bus_reset(void *sl_private, void **selfid_buf_addr); 271*0Sstevel@tonic-gate 272*0Sstevel@tonic-gate void h1394_self_ids(void *sl_private, void *selfid_buf_addr, 273*0Sstevel@tonic-gate uint32_t selfid_size, uint32_t node_id, uint32_t generation_count); 274*0Sstevel@tonic-gate 275*0Sstevel@tonic-gate void h1394_write_request(void *sl_private, cmd1394_cmd_t *req); 276*0Sstevel@tonic-gate 277*0Sstevel@tonic-gate void h1394_read_request(void *sl_private, cmd1394_cmd_t *req); 278*0Sstevel@tonic-gate 279*0Sstevel@tonic-gate void h1394_lock_request(void *sl_private, cmd1394_cmd_t *req); 280*0Sstevel@tonic-gate 281*0Sstevel@tonic-gate int h1394_alloc_cmd(void *sl_private, uint_t flags, cmd1394_cmd_t **cmdp, 282*0Sstevel@tonic-gate h1394_cmd_priv_t **hal_priv_ptr); 283*0Sstevel@tonic-gate /* Flags for h1394_alloc_cmd() */ 284*0Sstevel@tonic-gate #define H1394_ALLOC_CMD_SLEEP 0x00000000 /* can sleep allocating */ 285*0Sstevel@tonic-gate #define H1394_ALLOC_CMD_NOSLEEP 0x00000001 /* don't sleep allocating */ 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate int h1394_free_cmd(void *sl_private, cmd1394_cmd_t **cmdp); 288*0Sstevel@tonic-gate int h1394_ioctl(void *sl_private, int cmd, intptr_t arg, int mode, 289*0Sstevel@tonic-gate cred_t *cred_p, int *rval_p); 290*0Sstevel@tonic-gate 291*0Sstevel@tonic-gate void h1394_phy_packet(void *sl_private, uint32_t *packet_data, 292*0Sstevel@tonic-gate uint_t quadlet_count, uint_t timestamp); 293*0Sstevel@tonic-gate 294*0Sstevel@tonic-gate void h1394_error_detected(void *sl_private, h1394_error_t type, void *arg); 295*0Sstevel@tonic-gate 296*0Sstevel@tonic-gate #ifdef __cplusplus 297*0Sstevel@tonic-gate } 298*0Sstevel@tonic-gate #endif 299*0Sstevel@tonic-gate 300*0Sstevel@tonic-gate #endif /* _SYS_1394_H1394_H */ 301