1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_Q_H 28*0Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_Q_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * hci1394_q.h 34*0Sstevel@tonic-gate * This code decouples some of the OpenHCI async descriptor logic/structures 35*0Sstevel@tonic-gate * from the async processing. The goal was to combine as much of the 36*0Sstevel@tonic-gate * duplicate code as possible for the different type of async transfers 37*0Sstevel@tonic-gate * without going too overboard. 38*0Sstevel@tonic-gate * 39*0Sstevel@tonic-gate * There are two parts to the Q, the descriptor buffer and the data buffer. 40*0Sstevel@tonic-gate * for the most part, data to be transmitted and data which is received go 41*0Sstevel@tonic-gate * in the data buffers. The information of where to get the data and put 42*0Sstevel@tonic-gate * the data reside in the descriptor buffers. There are exceptions to this. 43*0Sstevel@tonic-gate */ 44*0Sstevel@tonic-gate 45*0Sstevel@tonic-gate #ifdef __cplusplus 46*0Sstevel@tonic-gate extern "C" { 47*0Sstevel@tonic-gate #endif 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate #include <sys/ddi.h> 50*0Sstevel@tonic-gate #include <sys/modctl.h> 51*0Sstevel@tonic-gate #include <sys/sunddi.h> 52*0Sstevel@tonic-gate #include <sys/types.h> 53*0Sstevel@tonic-gate #include <sys/note.h> 54*0Sstevel@tonic-gate 55*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_def.h> 56*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_tlist.h> 57*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_buf.h> 58*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_descriptors.h> 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate 61*0Sstevel@tonic-gate /* 62*0Sstevel@tonic-gate * Part of q_info passed in during q_init(). This tells us if this is an async 63*0Sstevel@tonic-gate * transmit or async receive Q. This makes a big difference inside of q. For 64*0Sstevel@tonic-gate * the transmit Q we will just setup an empty Q ready for TX calls into us. For 65*0Sstevel@tonic-gate * receive Q's we have to make sure we get multiple data buffers and then setup 66*0Sstevel@tonic-gate * the buffers so they are ready to receive data (by adding in the IM 67*0Sstevel@tonic-gate * descriptors). 68*0Sstevel@tonic-gate */ 69*0Sstevel@tonic-gate typedef enum { 70*0Sstevel@tonic-gate HCI1394_ARQ, 71*0Sstevel@tonic-gate HCI1394_ATQ 72*0Sstevel@tonic-gate } hci1394_q_mode_t; 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate /* 75*0Sstevel@tonic-gate * Part of q_info passed in during q_init(). These are the callbacks for 76*0Sstevel@tonic-gate * starting and waking up the async Q's. When the first descriptor is placed 77*0Sstevel@tonic-gate * on the Q, the async DMA engine is started with an address of where to find 78*0Sstevel@tonic-gate * the descriptor on the Q. That descriptor will be changed to point to the 79*0Sstevel@tonic-gate * next descriptor when the next descriptor is added (i.e. a chained dma). 80*0Sstevel@tonic-gate * Whenever an additional descriptor is added, wake is called. 81*0Sstevel@tonic-gate */ 82*0Sstevel@tonic-gate typedef void (*hci1394_q_start_t)(void *arg, uint32_t io_addr); 83*0Sstevel@tonic-gate typedef void (*hci1394_q_wake_t)(void *arg); 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate /* 86*0Sstevel@tonic-gate * Passed in during q_init(). This contains the size of the descriptor Q, the 87*0Sstevel@tonic-gate * size of the data Q, what kind of Q it is (AT or AR), the callbacks for start 88*0Sstevel@tonic-gate * and wake, and the argument to pass during start and wake. 89*0Sstevel@tonic-gate */ 90*0Sstevel@tonic-gate typedef struct hci1394_q_info_s { 91*0Sstevel@tonic-gate uint_t qi_desc_size; 92*0Sstevel@tonic-gate uint_t qi_data_size; 93*0Sstevel@tonic-gate hci1394_q_mode_t qi_mode; 94*0Sstevel@tonic-gate hci1394_q_start_t qi_start; 95*0Sstevel@tonic-gate hci1394_q_wake_t qi_wake; 96*0Sstevel@tonic-gate void *qi_callback_arg; 97*0Sstevel@tonic-gate } hci1394_q_info_t; 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate /* 100*0Sstevel@tonic-gate * Per command tracking information for the AT Q's. This is not used on the AR 101*0Sstevel@tonic-gate * side. This structure has two parts to it, the public data and the private 102*0Sstevel@tonic-gate * data. The public data is shared between async.c and q.c. The private data 103*0Sstevel@tonic-gate * is for internal q.c access only. It is only put in this structure so that 104*0Sstevel@tonic-gate * we do not have to dynamically alloc space for each transfer. 105*0Sstevel@tonic-gate */ 106*0Sstevel@tonic-gate typedef struct hci1394_q_cmd_s { 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate /* PUBLIC DATA STRUCTURES */ 109*0Sstevel@tonic-gate /* 110*0Sstevel@tonic-gate * qc_arg is an input paramter to hci1394_q_at() (along with the data 111*0Sstevel@tonic-gate * versions). It is an opaque address pointer which is used by async.c 112*0Sstevel@tonic-gate * to determine the commands address after a call to 113*0Sstevel@tonic-gate * hci1394_q_at_next(). 114*0Sstevel@tonic-gate */ 115*0Sstevel@tonic-gate void *qc_arg; 116*0Sstevel@tonic-gate 117*0Sstevel@tonic-gate /* 118*0Sstevel@tonic-gate * qc_generation is an input parameter to hci1394_q_at() (along with the 119*0Sstevel@tonic-gate * data versions). It is the generation count for which this command is 120*0Sstevel@tonic-gate * valid. If qc_generation does not match the current bus generation, 121*0Sstevel@tonic-gate * hci1394_q_at*() will return failure. 122*0Sstevel@tonic-gate */ 123*0Sstevel@tonic-gate uint_t qc_generation; 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate /* 126*0Sstevel@tonic-gate * qc_timestamp is used when sending an atresp to set the time when the 127*0Sstevel@tonic-gate * response is to have timed out. It is also use on at_next to tell 128*0Sstevel@tonic-gate * when the AT command completed. 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate uint_t qc_timestamp; 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate /* 133*0Sstevel@tonic-gate * qc_status is an output of hci1394_q_at_next(). It contains the 134*0Sstevel@tonic-gate * command status after completion. 135*0Sstevel@tonic-gate */ 136*0Sstevel@tonic-gate uint32_t qc_status; 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate /* PRIVATE DATA STRUCTURES */ 140*0Sstevel@tonic-gate /* 141*0Sstevel@tonic-gate * This is the memory address of where the status of this command 142*0Sstevel@tonic-gate * resides. 143*0Sstevel@tonic-gate */ 144*0Sstevel@tonic-gate uint32_t *qc_status_addr; 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate /* 147*0Sstevel@tonic-gate * qc_descriptor_end and qc_descriptor_buf are used to track where the 148*0Sstevel@tonic-gate * descriptor q pointers should be set to when this command has 149*0Sstevel@tonic-gate * completed (i.e. free up the space used by this command) 150*0Sstevel@tonic-gate */ 151*0Sstevel@tonic-gate caddr_t qc_descriptor_end; 152*0Sstevel@tonic-gate uint_t qc_descriptor_buf; 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate /* 155*0Sstevel@tonic-gate * qc_data_end and qc_data_buf are used to track where the data q 156*0Sstevel@tonic-gate * pointers should be set to when this command has completed (i.e. free 157*0Sstevel@tonic-gate * up the space used by this command). Not all commands use the data 158*0Sstevel@tonic-gate * q so qc_data_used give us state on if this command uses the data q. 159*0Sstevel@tonic-gate */ 160*0Sstevel@tonic-gate boolean_t qc_data_used; 161*0Sstevel@tonic-gate caddr_t qc_data_end; 162*0Sstevel@tonic-gate uint_t qc_data_buf; 163*0Sstevel@tonic-gate 164*0Sstevel@tonic-gate /* 165*0Sstevel@tonic-gate * This is the node for the queued list. Since AT requests finish in 166*0Sstevel@tonic-gate * the order that they were submitted, we queue these up in a linked 167*0Sstevel@tonic-gate * list so that it is easy to figure out which command has finished. 168*0Sstevel@tonic-gate * Just look at the head of the list. 169*0Sstevel@tonic-gate */ 170*0Sstevel@tonic-gate hci1394_tlist_node_t qc_node; 171*0Sstevel@tonic-gate } hci1394_q_cmd_t; 172*0Sstevel@tonic-gate 173*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", \ 174*0Sstevel@tonic-gate hci1394_q_cmd_s::qc_status \ 175*0Sstevel@tonic-gate hci1394_q_cmd_s::qc_timestamp)) 176*0Sstevel@tonic-gate 177*0Sstevel@tonic-gate typedef struct hci1394_q_bufptr_s { 178*0Sstevel@tonic-gate /* 179*0Sstevel@tonic-gate * kernel virtual addresses. The q may be broken down into multiple 180*0Sstevel@tonic-gate * cookies. The q is contiguous relative to the driver, but segmented 181*0Sstevel@tonic-gate * relative to the 1394 HW DMA engines. 182*0Sstevel@tonic-gate * 183*0Sstevel@tonic-gate * qp_top is the top the q. qp_bottom is the bottom of the q. These 184*0Sstevel@tonic-gate * never change after initial setup. qp_bottom is inclusive (i.e. for a 185*0Sstevel@tonic-gate * q size of 16 bytes where top was = to 0, qp_bottom would be = to 15). 186*0Sstevel@tonic-gate * 187*0Sstevel@tonic-gate * qp_current and qp_free are pointers within top and bottom. qp_current 188*0Sstevel@tonic-gate * refers to the next free space to write and free refers to the end of 189*0Sstevel@tonic-gate * free space (i.e. used memory within q). qp_free is inclusive (see 190*0Sstevel@tonic-gate * qp_bottom). 191*0Sstevel@tonic-gate */ 192*0Sstevel@tonic-gate caddr_t qp_top; 193*0Sstevel@tonic-gate caddr_t qp_bottom; 194*0Sstevel@tonic-gate caddr_t qp_current; 195*0Sstevel@tonic-gate caddr_t qp_free; 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate /* 198*0Sstevel@tonic-gate * qp_begin and qp_end are also kernel virtual addresses. They are the 199*0Sstevel@tonic-gate * beginning and ending address of the current_buf (cookie) within the 200*0Sstevel@tonic-gate * q. qp_offset is (qp_current - qp_begin). This is used to determine 201*0Sstevel@tonic-gate * the 32 bit PCI address to put into the OpenHCI descriptor. We know 202*0Sstevel@tonic-gate * the base PCI address from the cookie structure, we add offset to that 203*0Sstevel@tonic-gate * to determine the correct PCI address. 204*0Sstevel@tonic-gate */ 205*0Sstevel@tonic-gate caddr_t qp_begin; 206*0Sstevel@tonic-gate caddr_t qp_end; 207*0Sstevel@tonic-gate uint32_t qp_offset; 208*0Sstevel@tonic-gate 209*0Sstevel@tonic-gate /* 210*0Sstevel@tonic-gate * As stated above, the q may be broken into multiple cookies. 211*0Sstevel@tonic-gate * qp_current_buf is the cookie qp_current is in and qp_free_buf is the 212*0Sstevel@tonic-gate * cookie qp_free is in. NOTE: The cookie's are numbered 0, 1, 2, ..., 213*0Sstevel@tonic-gate * (i.e. if we have 4 cookies, qp_current_buf can be 0, 1, 2, or 3) 214*0Sstevel@tonic-gate */ 215*0Sstevel@tonic-gate uint_t qp_current_buf; 216*0Sstevel@tonic-gate uint_t qp_free_buf; 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate /* 219*0Sstevel@tonic-gate * qp_resv_size is only used for the AT Q's. 220*0Sstevel@tonic-gate * How much space has been reserved. This value is set on the call to 221*0Sstevel@tonic-gate * hci1394_q_reserve() and decremented each time a data is written. It 222*0Sstevel@tonic-gate * is used to check for overrun conditions. This extra check is in there 223*0Sstevel@tonic-gate * as an added sanity check due to the complexity of this code. 224*0Sstevel@tonic-gate */ 225*0Sstevel@tonic-gate uint_t qp_resv_size; 226*0Sstevel@tonic-gate } hci1394_q_bufptr_t; 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate 229*0Sstevel@tonic-gate typedef struct hci1394_q_buf_s { 230*0Sstevel@tonic-gate /* pointers to track used/free space/cookies in the buffer */ 231*0Sstevel@tonic-gate hci1394_q_bufptr_t qb_ptrs; 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate /* 234*0Sstevel@tonic-gate * a backup of qb_ptrs. If we fail while setting up an AT Q, we need to 235*0Sstevel@tonic-gate * cleanup by putting things back the way that they were. 236*0Sstevel@tonic-gate */ 237*0Sstevel@tonic-gate hci1394_q_bufptr_t qb_backup_ptrs; 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate /* copy of all of the cookie's structures for this buffer */ 240*0Sstevel@tonic-gate ddi_dma_cookie_t qb_cookie[OHCI_MAX_COOKIE]; 241*0Sstevel@tonic-gate 242*0Sstevel@tonic-gate /* Buffer handle used for calls into hci1394_buf_* routines */ 243*0Sstevel@tonic-gate hci1394_buf_handle_t qb_buf_handle; 244*0Sstevel@tonic-gate 245*0Sstevel@tonic-gate /* Buffer info (i.e. cookie count, kaddr, ddi handles, etc.) */ 246*0Sstevel@tonic-gate hci1394_buf_info_t qb_buf; 247*0Sstevel@tonic-gate } hci1394_q_buf_t; 248*0Sstevel@tonic-gate 249*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", \ 250*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_begin \ 251*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_bottom \ 252*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_current \ 253*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_current_buf \ 254*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_end \ 255*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_offset \ 256*0Sstevel@tonic-gate hci1394_q_buf_s::qb_ptrs.qp_top)) 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate typedef struct hci1394_q_s { 259*0Sstevel@tonic-gate /* 260*0Sstevel@tonic-gate * q_queued_list is only used in the AT descriptor Qs. AT commands 261*0Sstevel@tonic-gate * complete in the order they were issued. We Q these commands up with 262*0Sstevel@tonic-gate * each new command being added to the end of the list. When a command 263*0Sstevel@tonic-gate * completes, we look at the top of this list to determine which command 264*0Sstevel@tonic-gate * completed. 265*0Sstevel@tonic-gate */ 266*0Sstevel@tonic-gate hci1394_tlist_handle_t q_queued_list; 267*0Sstevel@tonic-gate 268*0Sstevel@tonic-gate /* 269*0Sstevel@tonic-gate * pointer to general driver information (dip, instance, etc) and to 270*0Sstevel@tonic-gate * handle for access to openHCI routines. 271*0Sstevel@tonic-gate */ 272*0Sstevel@tonic-gate hci1394_drvinfo_t *q_drvinfo; 273*0Sstevel@tonic-gate hci1394_ohci_handle_t q_ohci; 274*0Sstevel@tonic-gate 275*0Sstevel@tonic-gate /* 276*0Sstevel@tonic-gate * The OpenHCI DMA engines are basically just chained DMA engines. Each 277*0Sstevel@tonic-gate * "link" in the chain is called a descriptor in OpenHCI. When you want 278*0Sstevel@tonic-gate * to add a new descriptor, you init the descriptor, setup its "next" 279*0Sstevel@tonic-gate * pointer to "NULL", update the previous descriptor to point to the 280*0Sstevel@tonic-gate * new descriptor, and tell the HW you added a new descriptor by setting 281*0Sstevel@tonic-gate * its wake bit. q_previous is a pointer to the previous descriptor. 282*0Sstevel@tonic-gate * When adding a new descriptor, we just de-reference q_previous to 283*0Sstevel@tonic-gate * update its "next" pointer. 284*0Sstevel@tonic-gate */ 285*0Sstevel@tonic-gate hci1394_desc_t *q_previous; 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate /* 288*0Sstevel@tonic-gate * When updating the "next" pointer in the previous descriptor block 289*0Sstevel@tonic-gate * (as described above in q_previous), one of the things you need to 290*0Sstevel@tonic-gate * tell the HW is how many 16 byte blocks the next descriptor block 291*0Sstevel@tonic-gate * uses. This is what q_block_cnt is used for. This is only used in the 292*0Sstevel@tonic-gate * AT descriptor Q's. Since the IM's used in the AR Q's are the only 293*0Sstevel@tonic-gate * descriptor types used in AR, the block count is always the same for 294*0Sstevel@tonic-gate * an AR descriptor Q. 295*0Sstevel@tonic-gate */ 296*0Sstevel@tonic-gate uint_t q_block_cnt; 297*0Sstevel@tonic-gate 298*0Sstevel@tonic-gate /* 299*0Sstevel@tonic-gate * q_head is only used in the AR descriptor Qs. It contains the location 300*0Sstevel@tonic-gate * of the first descriptor on the Q. This is used to look at the 301*0Sstevel@tonic-gate * residual count in the AR data Q. The residual count tells us if we 302*0Sstevel@tonic-gate * have received any new packets to process. When a descriptor's data 303*0Sstevel@tonic-gate * buffer is empty (q_space_left = 0), we move q_head to the next 304*0Sstevel@tonic-gate * descriptor in the descriptor buffer. 305*0Sstevel@tonic-gate */ 306*0Sstevel@tonic-gate caddr_t q_head; 307*0Sstevel@tonic-gate 308*0Sstevel@tonic-gate /* 309*0Sstevel@tonic-gate * q_space_left is only used in the AR descriptor Qs. Each AR 310*0Sstevel@tonic-gate * descriptor has residual count embedded in the descriptor which says 311*0Sstevel@tonic-gate * how much free space is left in the descriptors associated data 312*0Sstevel@tonic-gate * buffer. q_space_left is how much SW thinks is left in the data 313*0Sstevel@tonic-gate * buffer. When they do not match, we have a new packet(s) in the data 314*0Sstevel@tonic-gate * buffer to process. Since the residual count is not updated by the 315*0Sstevel@tonic-gate * HW until the entire packet has been written to memory, we don't have 316*0Sstevel@tonic-gate * to worry about any partial packet RX problems. 317*0Sstevel@tonic-gate */ 318*0Sstevel@tonic-gate uint_t q_space_left; 319*0Sstevel@tonic-gate 320*0Sstevel@tonic-gate /* 321*0Sstevel@tonic-gate * status of the dma controller. This tells us if we should do a start 322*0Sstevel@tonic-gate * or a wake. If the dma engine is not running, we should start it. If 323*0Sstevel@tonic-gate * it is running, we should wake it. When the DMA engine is started, it 324*0Sstevel@tonic-gate * expects to have a valid descriptor to process. Since we don't have 325*0Sstevel@tonic-gate * anything to send in the beginning (AT), we have to wait until the 326*0Sstevel@tonic-gate * first AT packet comes down before we can start the DMA engine. 327*0Sstevel@tonic-gate */ 328*0Sstevel@tonic-gate boolean_t q_dma_running; 329*0Sstevel@tonic-gate 330*0Sstevel@tonic-gate /* The descriptor buffer for this Q */ 331*0Sstevel@tonic-gate hci1394_q_buf_t q_desc; 332*0Sstevel@tonic-gate 333*0Sstevel@tonic-gate /* The data buffer for this Q */ 334*0Sstevel@tonic-gate hci1394_q_buf_t q_data; 335*0Sstevel@tonic-gate 336*0Sstevel@tonic-gate /* copy of qinfo passed in during hci1394_q_init() */ 337*0Sstevel@tonic-gate hci1394_q_info_t q_info; 338*0Sstevel@tonic-gate 339*0Sstevel@tonic-gate kmutex_t q_mutex; 340*0Sstevel@tonic-gate } hci1394_q_t; 341*0Sstevel@tonic-gate 342*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", \ 343*0Sstevel@tonic-gate hci1394_q_s::q_dma_running \ 344*0Sstevel@tonic-gate hci1394_q_s::q_head \ 345*0Sstevel@tonic-gate hci1394_q_s::q_previous \ 346*0Sstevel@tonic-gate hci1394_q_s::q_space_left)) 347*0Sstevel@tonic-gate 348*0Sstevel@tonic-gate /* handle passed back from init() and used for rest of functions */ 349*0Sstevel@tonic-gate typedef struct hci1394_q_s *hci1394_q_handle_t; 350*0Sstevel@tonic-gate 351*0Sstevel@tonic-gate 352*0Sstevel@tonic-gate int hci1394_q_init(hci1394_drvinfo_t *drvinfo, 353*0Sstevel@tonic-gate hci1394_ohci_handle_t ohci_handle, hci1394_q_info_t *qinfo, 354*0Sstevel@tonic-gate hci1394_q_handle_t *q_handle); 355*0Sstevel@tonic-gate void hci1394_q_fini(hci1394_q_handle_t *q_handle); 356*0Sstevel@tonic-gate void hci1394_q_resume(hci1394_q_handle_t q_handle); 357*0Sstevel@tonic-gate void hci1394_q_stop(hci1394_q_handle_t q_handle); 358*0Sstevel@tonic-gate 359*0Sstevel@tonic-gate int hci1394_q_at(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 360*0Sstevel@tonic-gate hci1394_basic_pkt_t *hdr, uint_t hdrsize, int *result); 361*0Sstevel@tonic-gate int hci1394_q_at_with_data(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 362*0Sstevel@tonic-gate hci1394_basic_pkt_t *hdr, uint_t hdrsize, uint8_t *data, uint_t datasize, 363*0Sstevel@tonic-gate int *result); 364*0Sstevel@tonic-gate int hci1394_q_at_with_mblk(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 365*0Sstevel@tonic-gate hci1394_basic_pkt_t *hdr, uint_t hdrsize, h1394_mblk_t *mblk, int *result); 366*0Sstevel@tonic-gate void hci1394_q_at_next(hci1394_q_handle_t q_handle, boolean_t flush_q, 367*0Sstevel@tonic-gate hci1394_q_cmd_t **cmd); 368*0Sstevel@tonic-gate 369*0Sstevel@tonic-gate void hci1394_q_ar_next(hci1394_q_handle_t q_handle, uint32_t **q_addr); 370*0Sstevel@tonic-gate void hci1394_q_ar_free(hci1394_q_handle_t q_handle, uint_t size); 371*0Sstevel@tonic-gate uint32_t hci1394_q_ar_get32(hci1394_q_handle_t q_handle, uint32_t *addr); 372*0Sstevel@tonic-gate void hci1394_q_ar_rep_get8(hci1394_q_handle_t q_handle, uint8_t *dest, 373*0Sstevel@tonic-gate uint8_t *q_addr, uint_t size); 374*0Sstevel@tonic-gate void hci1394_q_ar_copy_to_mblk(hci1394_q_handle_t q_handle, uint8_t *addr, 375*0Sstevel@tonic-gate h1394_mblk_t *mblk); 376*0Sstevel@tonic-gate 377*0Sstevel@tonic-gate 378*0Sstevel@tonic-gate #ifdef __cplusplus 379*0Sstevel@tonic-gate } 380*0Sstevel@tonic-gate #endif 381*0Sstevel@tonic-gate 382*0Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_Q_H */ 383