1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 1999-2002 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_IXL_H 28*0Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_IXL_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * hci1394_ixl.h 34*0Sstevel@tonic-gate * Structures and defines for IXL processing. 35*0Sstevel@tonic-gate * 1. Structures tracking per-command state [created during compilation 36*0Sstevel@tonic-gate * and stored in each command's compiler_privatep]. 37*0Sstevel@tonic-gate * 2. Structures used for state tracking during IXL program compilation. 38*0Sstevel@tonic-gate * 3. Structures used during IXL dynamic update for assessment and the 39*0Sstevel@tonic-gate * performing the update itself. 40*0Sstevel@tonic-gate */ 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate #ifdef __cplusplus 43*0Sstevel@tonic-gate extern "C" { 44*0Sstevel@tonic-gate #endif 45*0Sstevel@tonic-gate 46*0Sstevel@tonic-gate #include <sys/note.h> 47*0Sstevel@tonic-gate 48*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_def.h> 49*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_isoch.h> 50*0Sstevel@tonic-gate 51*0Sstevel@tonic-gate /* 52*0Sstevel@tonic-gate * function return codes from hci1394_ixl_dma_sync() 53*0Sstevel@tonic-gate */ 54*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_NOERROR (0) /* no error */ 55*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_INUPDATE (1) /* update active at intr entry */ 56*0Sstevel@tonic-gate /* (info only, not err) */ 57*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_DMASTOP (2) /* encountered end of dma or stopped */ 58*0Sstevel@tonic-gate /* (might be info only) */ 59*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_DMALOST (-1) /* dma location indeterminate (lost) */ 60*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_NOADV (-2) /* dma non-advance retries exhausted */ 61*0Sstevel@tonic-gate /* (stuck or lost) */ 62*0Sstevel@tonic-gate /* fatal internal errors from hci1394_ixl_dma_sync() */ 63*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_ININTR (-3) /* interrupt active at intrrupt entry */ 64*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_INCALL (-4) /* callback active at entry */ 65*0Sstevel@tonic-gate #define HCI1394_IXL_INTR_STOP (-5) /* context is being stopped */ 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate /* 68*0Sstevel@tonic-gate * maximum number of jump IXL commands permitted between two data transfer 69*0Sstevel@tonic-gate * commands. This allows for several label and jump combinations to exist, but 70*0Sstevel@tonic-gate * also is used to detect when the label/jump complexity probably indicates 71*0Sstevel@tonic-gate * an infinite loop without any transfers. 72*0Sstevel@tonic-gate */ 73*0Sstevel@tonic-gate #define HCI1394_IXL_MAX_SEQ_JUMPS 10 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate /* 76*0Sstevel@tonic-gate * xfer control structures - for execution and update control of compiled 77*0Sstevel@tonic-gate * ixl program. 78*0Sstevel@tonic-gate * 79*0Sstevel@tonic-gate * For pkt, buf and special xfer start ixl commands, address 80*0Sstevel@tonic-gate * of allocated xfer_ctl struct is set into ixl compiler_privatep. 81*0Sstevel@tonic-gate * 82*0Sstevel@tonic-gate * For pkt xfer non-start ixl commands, address of pkt xfer start ixl 83*0Sstevel@tonic-gate * command is set into compiler_privatep and the index [1-n] of 84*0Sstevel@tonic-gate * this non-start pkt xfer ixl command to its related component in the 85*0Sstevel@tonic-gate * generated descriptor block is set into compiler_resv. 86*0Sstevel@tonic-gate * 87*0Sstevel@tonic-gate * The xfer_ctl_dma struct array is needed because allocation of subsequent 88*0Sstevel@tonic-gate * descriptor blocks may be from different memory pages (i.e. not contiguous) 89*0Sstevel@tonic-gate * and thus, during update processing, subsequent descriptor block addrs 90*0Sstevel@tonic-gate * can't be calculated (e.g. change of buf addr or size or modification to 91*0Sstevel@tonic-gate * set tag&sync, setskipmode or jump cmds). 92*0Sstevel@tonic-gate */ 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate #define XCTL_LABELLED 1 /* flag: ixl xfer cmd initiated by ixl label cmd */ 95*0Sstevel@tonic-gate 96*0Sstevel@tonic-gate typedef struct hci1394_xfer_ctl_dma { 97*0Sstevel@tonic-gate /* 98*0Sstevel@tonic-gate * dma descriptor block's bound addr (with "Z" bits set); is used to 99*0Sstevel@tonic-gate * fill jump/skip addrs of previous dma descriptor block (previous on 100*0Sstevel@tonic-gate * exec path, not link path); Note:("Z" bits)*16 is size of this 101*0Sstevel@tonic-gate * descriptor block; individual component's format depends on IXL cmd 102*0Sstevel@tonic-gate * type; 103*0Sstevel@tonic-gate */ 104*0Sstevel@tonic-gate uint32_t dma_bound; 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate /* 107*0Sstevel@tonic-gate * kernel virtual (unbound) addr of last component of allocated 108*0Sstevel@tonic-gate * descriptor block; start addr of descriptor block can be calculated 109*0Sstevel@tonic-gate * by adding size of a descriptor block component(16) and subtracting 110*0Sstevel@tonic-gate * ("Z" bits)*16; Note: if ixl cmd is xmit_hdr_only, must add 2*desc 111*0Sstevel@tonic-gate * block component(32), instead; 112*0Sstevel@tonic-gate * used to determine current location during exec by examining/clearing 113*0Sstevel@tonic-gate * the status/timestamp value; 114*0Sstevel@tonic-gate * used to obtain value for store timestamp cmd; used to set new 115*0Sstevel@tonic-gate * jump/skip addr on update calls; 116*0Sstevel@tonic-gate * used to set new tag and sync on update calls; 117*0Sstevel@tonic-gate */ 118*0Sstevel@tonic-gate caddr_t dma_descp; 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate /* 121*0Sstevel@tonic-gate * pointer to the hci1394_buf_info_t structure corresponding to the 122*0Sstevel@tonic-gate * mapped DMA memory into which this descriptor was written. Contains 123*0Sstevel@tonic-gate * the DMA handles necessary for ddi_dma_sync() and ddi_put32/get32() 124*0Sstevel@tonic-gate * calls. 125*0Sstevel@tonic-gate */ 126*0Sstevel@tonic-gate hci1394_buf_info_t *dma_buf; 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate } hci1394_xfer_ctl_dma_t; 129*0Sstevel@tonic-gate 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate typedef struct hci1394_xfer_ctl { 132*0Sstevel@tonic-gate struct hci1394_xfer_ctl *ctl_nextp; /* next ixl xfer_ctl struct */ 133*0Sstevel@tonic-gate ixl1394_command_t *execp; /* next ixlxfer cmd (along exec path) */ 134*0Sstevel@tonic-gate ixl1394_set_skipmode_t *skipmodep; /* associated skip cmd. if any */ 135*0Sstevel@tonic-gate uint16_t ctl_flags; /* xctl flags defined above */ 136*0Sstevel@tonic-gate uint16_t cnt; /* dma descriptor blocks alloc count */ 137*0Sstevel@tonic-gate /* (for pkt=1) */ 138*0Sstevel@tonic-gate hci1394_xfer_ctl_dma_t dma[1]; /* addrs of descriptor blocks, cnt of */ 139*0Sstevel@tonic-gate /* these are allocated */ 140*0Sstevel@tonic-gate } hci1394_xfer_ctl_t; 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_xfer_ctl)) 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate /* 145*0Sstevel@tonic-gate * IXL Compiler temporary working variables for building IXL context program. 146*0Sstevel@tonic-gate * (i.e. converting IXL program to a list of hci descriptor blocks) 147*0Sstevel@tonic-gate */ 148*0Sstevel@tonic-gate typedef struct hci1394_comp_ixl_vars_s { 149*0Sstevel@tonic-gate /* COMMON RECV/XMIT COMPILE VALUES */ 150*0Sstevel@tonic-gate hci1394_state_t *soft_statep; /* driver state */ 151*0Sstevel@tonic-gate hci1394_iso_ctxt_t *ctxtp; /* current context */ 152*0Sstevel@tonic-gate hci1394_xfer_ctl_t *xcs_firstp; /* 1st alloc xfer_ctl_t struc */ 153*0Sstevel@tonic-gate hci1394_xfer_ctl_t *xcs_currentp; /* last alloc xfer_ctl_t struc */ 154*0Sstevel@tonic-gate 155*0Sstevel@tonic-gate hci1394_idma_desc_mem_t *dma_firstp; /* 1st alloc descriptor mem */ 156*0Sstevel@tonic-gate hci1394_idma_desc_mem_t *dma_currentp; /* cur dma descriptor mem */ 157*0Sstevel@tonic-gate 158*0Sstevel@tonic-gate int dma_bld_error; /* compilation error code */ 159*0Sstevel@tonic-gate uint_t ixl_io_mode; /* I/O mode: 0=recv,1=xmit */ 160*0Sstevel@tonic-gate 161*0Sstevel@tonic-gate ixl1394_command_t *ixl_cur_cmdp; /* processing current ixl cmd */ 162*0Sstevel@tonic-gate ixl1394_command_t *ixl_cur_xfer_stp; /* currently buildng xfer cmd */ 163*0Sstevel@tonic-gate ixl1394_command_t *ixl_cur_labelp; /* set if xfer inited by labl */ 164*0Sstevel@tonic-gate 165*0Sstevel@tonic-gate uint16_t ixl_xfer_st_cnt; /* # of xfer start ixl cmds built */ 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate uint_t xfer_state; /* none, pkt, buf, skip, hdronly */ 168*0Sstevel@tonic-gate uint_t xfer_hci_flush; /* updateable - xfer, jump, set */ 169*0Sstevel@tonic-gate 170*0Sstevel@tonic-gate uint32_t xfer_pktlen; 171*0Sstevel@tonic-gate uint32_t xfer_bufp[HCI1394_DESC_MAX_Z]; 172*0Sstevel@tonic-gate uint16_t xfer_bufcnt; 173*0Sstevel@tonic-gate uint16_t xfer_size[HCI1394_DESC_MAX_Z]; 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate uint16_t descriptors; 176*0Sstevel@tonic-gate uint16_t reserved; 177*0Sstevel@tonic-gate hci1394_desc_t descriptor_block[HCI1394_DESC_MAX_Z]; 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate /* START RECV ONLY SECTION */ 180*0Sstevel@tonic-gate uint16_t ixl_setsyncwait_cnt; 181*0Sstevel@tonic-gate /* END RECV ONLY SECTION */ 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate /* START XMIT ONLY SECTION */ 184*0Sstevel@tonic-gate ixl1394_set_tagsync_t *ixl_settagsync_cmdp; 185*0Sstevel@tonic-gate ixl1394_set_skipmode_t *ixl_setskipmode_cmdp; 186*0Sstevel@tonic-gate 187*0Sstevel@tonic-gate uint16_t default_tag; 188*0Sstevel@tonic-gate uint16_t default_sync; 189*0Sstevel@tonic-gate uint16_t default_skipmode; /* next, self, stop, jump */ 190*0Sstevel@tonic-gate uint16_t skipmode; /* next, self, stop, jump */ 191*0Sstevel@tonic-gate ixl1394_command_t *default_skiplabelp; 192*0Sstevel@tonic-gate ixl1394_command_t *default_skipxferp; 193*0Sstevel@tonic-gate ixl1394_command_t *skiplabelp; 194*0Sstevel@tonic-gate ixl1394_command_t *skipxferp; 195*0Sstevel@tonic-gate 196*0Sstevel@tonic-gate uint32_t xmit_pkthdr1; 197*0Sstevel@tonic-gate uint32_t xmit_pkthdr2; 198*0Sstevel@tonic-gate uint32_t storevalue_bufp; 199*0Sstevel@tonic-gate uint32_t storevalue_data; 200*0Sstevel@tonic-gate /* END XMIT ONLY SECTION */ 201*0Sstevel@tonic-gate } hci1394_comp_ixl_vars_t; 202*0Sstevel@tonic-gate 203*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_comp_ixl_vars_s)) 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate /* 206*0Sstevel@tonic-gate * hci1394_comp_ixl_vars.xfer_hci_flush - xfer descriptor block build hci 207*0Sstevel@tonic-gate * flush evaluation flags 208*0Sstevel@tonic-gate */ 209*0Sstevel@tonic-gate #define UPDATEABLE_XFER 0x01 /* current xfer command is updateable */ 210*0Sstevel@tonic-gate #define UPDATEABLE_JUMP 0x02 /* cur xfer is finalized by updateable jump */ 211*0Sstevel@tonic-gate #define UPDATEABLE_SET 0x04 /* current xfer has associated updateable set */ 212*0Sstevel@tonic-gate #define INITIATING_LBL 0x08 /* current xfer is initiated by a label cmd */ 213*0Sstevel@tonic-gate 214*0Sstevel@tonic-gate /* hci1394_comp_ixl_vars.xfer_state - xfer descriptr block build state values */ 215*0Sstevel@tonic-gate #define XFER_NONE 0 /* build inactive */ 216*0Sstevel@tonic-gate #define XFER_PKT 1 /* building xfer packet descriptor block */ 217*0Sstevel@tonic-gate #define XFER_BUF 2 /* building xfer buffer descriptor blocks */ 218*0Sstevel@tonic-gate #define XMIT_NOPKT 3 /* building skip cycle xmit descriptor block */ 219*0Sstevel@tonic-gate #define XMIT_HDRONLY 4 /* building header only xmit descriptor block */ 220*0Sstevel@tonic-gate 221*0Sstevel@tonic-gate /* 222*0Sstevel@tonic-gate * IXL Dynamic Update temporary working variables. 223*0Sstevel@tonic-gate * (used when assessing feasibility of an update based on where the hardware 224*0Sstevel@tonic-gate * is, and for performing the actual update.) 225*0Sstevel@tonic-gate */ 226*0Sstevel@tonic-gate #define IXL_MAX_LOCN 4 /* extent of location array */ 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate typedef struct hci1394_upd_locn_info { 229*0Sstevel@tonic-gate ixl1394_command_t *ixlp; 230*0Sstevel@tonic-gate uint_t ixldepth; 231*0Sstevel@tonic-gate } hci1394_upd_locn_info_t; 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate typedef struct hci1394_ixl_update_vars { 234*0Sstevel@tonic-gate 235*0Sstevel@tonic-gate hci1394_state_t *soft_statep; /* driver state struct */ 236*0Sstevel@tonic-gate hci1394_iso_ctxt_t *ctxtp; /* current iso context */ 237*0Sstevel@tonic-gate ixl1394_command_t *ixlnewp; /* ixl cmd containing new values */ 238*0Sstevel@tonic-gate ixl1394_command_t *ixloldp; /* cmd to be updated with new vals */ 239*0Sstevel@tonic-gate 240*0Sstevel@tonic-gate ixl1394_command_t *ixlxferp; /* xfer cmd which is real targ of upd */ 241*0Sstevel@tonic-gate ixl1394_command_t *skipxferp; /* xfer cmd if mode is skip to label */ 242*0Sstevel@tonic-gate 243*0Sstevel@tonic-gate /* currently exec xfer and MAX_LOCN-1 xfers following */ 244*0Sstevel@tonic-gate hci1394_upd_locn_info_t locn_info[IXL_MAX_LOCN]; 245*0Sstevel@tonic-gate 246*0Sstevel@tonic-gate uint_t ixldepth; /* xferp depth at which to start upd */ 247*0Sstevel@tonic-gate uint_t skipmode; /* set skip mode mode value */ 248*0Sstevel@tonic-gate uint_t pkthdr1; /* new pkt header 1 if tag or sync update */ 249*0Sstevel@tonic-gate uint_t pkthdr2; /* new pkt hdr 2 if send xfer size change */ 250*0Sstevel@tonic-gate uint32_t skipaddr; /* bound skip destaddr (0=not skip to labl) */ 251*0Sstevel@tonic-gate uint32_t jumpaddr; /* bound jump destaddr if jump update (w/Z) */ 252*0Sstevel@tonic-gate uint32_t bufaddr; /* new buf addr if xfer buffr addr change */ 253*0Sstevel@tonic-gate uint32_t bufsize; /* new buf size if xfer buffr size change */ 254*0Sstevel@tonic-gate uint32_t hcihdr; /* new hci descriptor hdr field (cmd,int,cnt) */ 255*0Sstevel@tonic-gate uint32_t hcistatus; /* new hci descrptr stat field (rescount) */ 256*0Sstevel@tonic-gate int32_t hci_offset; /* offset from xfer_ctl dma_descp to */ 257*0Sstevel@tonic-gate /* hci changing */ 258*0Sstevel@tonic-gate int hdr_offset; /* offset from xfer_ctl dma_descp to */ 259*0Sstevel@tonic-gate /* pkthdrs hci */ 260*0Sstevel@tonic-gate int upd_status; /* update completion return status value */ 261*0Sstevel@tonic-gate 262*0Sstevel@tonic-gate uint_t risklevel; /* caller risk override spec (unimplemented) */ 263*0Sstevel@tonic-gate uint16_t ixl_opcode; /* ixl update command code */ 264*0Sstevel@tonic-gate uint16_t ixlcount; /* ixlxferp # of dma cmds to update */ 265*0Sstevel@tonic-gate } hci1394_ixl_update_vars_t; 266*0Sstevel@tonic-gate 267*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_ixl_update_vars)) 268*0Sstevel@tonic-gate 269*0Sstevel@tonic-gate int hci1394_compile_ixl(hci1394_state_t *soft_statep, hci1394_iso_ctxt_t *ctxtp, 270*0Sstevel@tonic-gate ixl1394_command_t *ixlp, int *resultp); 271*0Sstevel@tonic-gate int hci1394_ixl_update(hci1394_state_t *soft_statep, hci1394_iso_ctxt_t *ctxtp, 272*0Sstevel@tonic-gate ixl1394_command_t *ixlnewp, ixl1394_command_t *ixloldp, uint_t riskoverride, 273*0Sstevel@tonic-gate int *resultp); 274*0Sstevel@tonic-gate void hci1394_ixl_interrupt(hci1394_state_t *soft_statep, 275*0Sstevel@tonic-gate hci1394_iso_ctxt_t *ctxtp, boolean_t in_stop); 276*0Sstevel@tonic-gate int hci1394_ixl_dma_sync(hci1394_state_t *soft_statep, 277*0Sstevel@tonic-gate hci1394_iso_ctxt_t *ctxtp); 278*0Sstevel@tonic-gate int hci1394_ixl_set_start(hci1394_iso_ctxt_t *ctxtp, ixl1394_command_t *ixlstp); 279*0Sstevel@tonic-gate void hci1394_ixl_reset_status(hci1394_iso_ctxt_t *ctxtp); 280*0Sstevel@tonic-gate int hci1394_ixl_check_status(hci1394_xfer_ctl_dma_t *dma, uint16_t ixlopcode, 281*0Sstevel@tonic-gate uint16_t *timestamp, boolean_t do_status_reset); 282*0Sstevel@tonic-gate int hci1394_ixl_find_next_exec_xfer(ixl1394_command_t *ixl_start, 283*0Sstevel@tonic-gate uint_t *callback_cnt, ixl1394_command_t **next_exec_ixlpp); 284*0Sstevel@tonic-gate void hci1394_ixl_cleanup(hci1394_state_t *soft_statep, 285*0Sstevel@tonic-gate hci1394_iso_ctxt_t *ctxtp); 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate #ifdef __cplusplus 288*0Sstevel@tonic-gate } 289*0Sstevel@tonic-gate #endif 290*0Sstevel@tonic-gate 291*0Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_IXL_H */ 292