1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 28*0Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_IOCTL_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * hci1394_ioctl.h 34*0Sstevel@tonic-gate * Test ioctl's to support test/debug of the 1394 HW. hci1394_ioctl_enum_t is 35*0Sstevel@tonic-gate * passed in cmd and a pointer to the appropriate structure (i.e. 36*0Sstevel@tonic-gate * hci1394_ioctl_wrreg_t) is passed in arg. 37*0Sstevel@tonic-gate */ 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate #ifdef __cplusplus 40*0Sstevel@tonic-gate extern "C" { 41*0Sstevel@tonic-gate #endif 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate /* 45*0Sstevel@tonic-gate * write_reg - write OpenHCI register 46*0Sstevel@tonic-gate * read_reg - read OpenHCI register 47*0Sstevel@tonic-gate * write_vreg - write OpenHCI Vendor Specific register 48*0Sstevel@tonic-gate * read_vreg - read OpenHCI Vendor Specific register 49*0Sstevel@tonic-gate * reset_bus - reset the 1394 bus 50*0Sstevel@tonic-gate * selfid_cnt - return the number of times we saw the selfid complete 51*0Sstevel@tonic-gate * interrupt signifying a bus reset has completed. This does not 52*0Sstevel@tonic-gate * have to match the bus generation and probably won't. 53*0Sstevel@tonic-gate * busgen_cnt - return the current bus generation 54*0Sstevel@tonic-gate * read_selfid - read selfid buffer 55*0Sstevel@tonic-gate * write_phy - write PHY register 56*0Sstevel@tonic-gate * read_phy - read PHY register 57*0Sstevel@tonic-gate * hba_info - HBA vendor information 58*0Sstevel@tonic-gate */ 59*0Sstevel@tonic-gate #define HCI11394_IOCTL ('f' << 8) 60*0Sstevel@tonic-gate typedef enum { 61*0Sstevel@tonic-gate HCI1394_IOCTL_WRITE_REG = HCI11394_IOCTL | 0x00, 62*0Sstevel@tonic-gate HCI1394_IOCTL_READ_REG = HCI11394_IOCTL | 0x01, 63*0Sstevel@tonic-gate HCI1394_IOCTL_WRITE_VREG = HCI11394_IOCTL | 0x02, 64*0Sstevel@tonic-gate HCI1394_IOCTL_READ_VREG = HCI11394_IOCTL | 0x03, 65*0Sstevel@tonic-gate HCI1394_IOCTL_RESET_BUS = HCI11394_IOCTL | 0x04, 66*0Sstevel@tonic-gate HCI1394_IOCTL_SELFID_CNT = HCI11394_IOCTL | 0x05, 67*0Sstevel@tonic-gate HCI1394_IOCTL_BUSGEN_CNT = HCI11394_IOCTL | 0x06, 68*0Sstevel@tonic-gate HCI1394_IOCTL_READ_SELFID = HCI11394_IOCTL | 0x07, 69*0Sstevel@tonic-gate HCI1394_IOCTL_WRITE_PHY = HCI11394_IOCTL | 0x08, 70*0Sstevel@tonic-gate HCI1394_IOCTL_READ_PHY = HCI11394_IOCTL | 0x09, 71*0Sstevel@tonic-gate HCI1394_IOCTL_HBA_INFO = HCI11394_IOCTL | 0x0A 72*0Sstevel@tonic-gate } hci1394_ioctl_enum_t; 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate /* 76*0Sstevel@tonic-gate * HCI1394_IOCTL_WRITE_REG 77*0Sstevel@tonic-gate * Write OHCI register. addr is an offset into the OpenHCI register map. 78*0Sstevel@tonic-gate * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 79*0Sstevel@tonic-gate * aligned (i.e. 0, 4, 8, C, 10). data is the 32-bit word to write into the 80*0Sstevel@tonic-gate * OpenHCI register. 81*0Sstevel@tonic-gate * 82*0Sstevel@tonic-gate * NOTE: Writing OpenHCI registers can cause the hardware and/or SW to 83*0Sstevel@tonic-gate * misbehave. Extreme care should be used when using this call. 84*0Sstevel@tonic-gate */ 85*0Sstevel@tonic-gate typedef struct hci1394_ioctl_wrreg_s { 86*0Sstevel@tonic-gate uint_t addr; 87*0Sstevel@tonic-gate uint32_t data; 88*0Sstevel@tonic-gate } hci1394_ioctl_wrreg_t; 89*0Sstevel@tonic-gate 90*0Sstevel@tonic-gate 91*0Sstevel@tonic-gate /* 92*0Sstevel@tonic-gate * HCI1394_IOCTL_READ_REG 93*0Sstevel@tonic-gate * Read OHCI register. addr is an offset into the OpenHCI register map. 94*0Sstevel@tonic-gate * (i.e. addr = 0 would write to the Version Register). addr must be 32-bit 95*0Sstevel@tonic-gate * aligned (i.e. 0, 4, 8, C, 10). When the ioctl returns successfully, data 96*0Sstevel@tonic-gate * will contain the 32-bit word read from the OHCI register. 97*0Sstevel@tonic-gate */ 98*0Sstevel@tonic-gate typedef struct hci1394_ioctl_rdreg_s { 99*0Sstevel@tonic-gate uint_t addr; 100*0Sstevel@tonic-gate uint32_t data; 101*0Sstevel@tonic-gate } hci1394_ioctl_rdreg_t; 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate /* 105*0Sstevel@tonic-gate * HCI1394_IOCTL_WRITE_VREG 106*0Sstevel@tonic-gate * Write Vendor Specific OHCI register. addr is an offset into the Vendor 107*0Sstevel@tonic-gate * Specific OpenHCI register map. (i.e. addr = 0 would write to the first 108*0Sstevel@tonic-gate * Vendor Specific register. addr must be 32-bit aligned (i.e. 0, 4, 8, C, 109*0Sstevel@tonic-gate * 10). data is the 32-bit word to write into the Vendor Specific OpenHCI 110*0Sstevel@tonic-gate * register. regset defines which vendor specific register set to write to. 111*0Sstevel@tonic-gate * There will usually be one vendor specific register set so this will 112*0Sstevel@tonic-gate * usually be set to 0. 113*0Sstevel@tonic-gate * 114*0Sstevel@tonic-gate * NOTE: Writing Vendor Specific OpenHCI registers can cause the hardware 115*0Sstevel@tonic-gate * and/or SW to misbehave. Extreme care should be used when using this 116*0Sstevel@tonic-gate * call. 117*0Sstevel@tonic-gate */ 118*0Sstevel@tonic-gate typedef struct hci1394_ioctl_wrvreg_s { 119*0Sstevel@tonic-gate uint_t regset; 120*0Sstevel@tonic-gate uint_t addr; 121*0Sstevel@tonic-gate uint32_t data; 122*0Sstevel@tonic-gate } hci1394_ioctl_wrvreg_t; 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate /* 126*0Sstevel@tonic-gate * HCI1394_IOCTL_READ_VREG 127*0Sstevel@tonic-gate * Read Vendor specific OHCI register. addr is an offset into the Vendor 128*0Sstevel@tonic-gate * Specific OpenHCI register space. (i.e. addr = 0 is the first Vendor 129*0Sstevel@tonic-gate * Specific register). addr must be 32-bit aligned (i.e. 0, 4, 8, C, 10). 130*0Sstevel@tonic-gate * When the ioctl returns successfully, data will contain the 32-bit word 131*0Sstevel@tonic-gate * read from the Vendor Specific OHCI register. regset defines which vendor 132*0Sstevel@tonic-gate * specific register set to read from. There will usually be one vendor 133*0Sstevel@tonic-gate * specific register set so this will usually be set to 0. 134*0Sstevel@tonic-gate */ 135*0Sstevel@tonic-gate typedef struct hci1394_ioctl_rdvreg_s { 136*0Sstevel@tonic-gate uint_t regset; 137*0Sstevel@tonic-gate uint_t addr; 138*0Sstevel@tonic-gate uint32_t data; 139*0Sstevel@tonic-gate } hci1394_ioctl_rdvreg_t; 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate /* HCI1394_IOCTL_RESET_BUS has no parameters */ 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate 145*0Sstevel@tonic-gate /* 146*0Sstevel@tonic-gate * HCI1394_IOCTL_SELFID_CNT 147*0Sstevel@tonic-gate * When the ioctl returns successfully, count will contain the number of 148*0Sstevel@tonic-gate * times the nexus driver has seen and responded to a selfid_complete 149*0Sstevel@tonic-gate * interrupt. This interrupt signifies that the bus reset has completed 150*0Sstevel@tonic-gate * and the hardware based bus enumeration has completed. This number will 151*0Sstevel@tonic-gate * most likely not be the same as the bus generation. Everytime this 152*0Sstevel@tonic-gate * increments, the bus generation count should increment by at least one. 153*0Sstevel@tonic-gate * 154*0Sstevel@tonic-gate * NOTE: The current implementation of the nexus driver uses a uint_t for 155*0Sstevel@tonic-gate * selfid_cnt. 156*0Sstevel@tonic-gate */ 157*0Sstevel@tonic-gate typedef struct hci1394_ioctl_selfid_cnt_s { 158*0Sstevel@tonic-gate uint_t count; 159*0Sstevel@tonic-gate } hci1394_ioctl_selfid_cnt_t; 160*0Sstevel@tonic-gate 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate /* 163*0Sstevel@tonic-gate * HCI1394_IOCTL_BUSGEN_CNT 164*0Sstevel@tonic-gate * When the ioctl returns successfully, count will contain the current 1394 165*0Sstevel@tonic-gate * bus generation count. 166*0Sstevel@tonic-gate * 167*0Sstevel@tonic-gate * NOTE: The current implementation of the nexus driver uses the OpenHCI 168*0Sstevel@tonic-gate * generation count which is an 8 bit value. Therefore, this count will 169*0Sstevel@tonic-gate * wrap over at 0xFF. 170*0Sstevel@tonic-gate */ 171*0Sstevel@tonic-gate typedef struct hci1394_ioctl_busgen_cnt_s { 172*0Sstevel@tonic-gate uint_t count; 173*0Sstevel@tonic-gate } hci1394_ioctl_busgen_cnt_t; 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate 176*0Sstevel@tonic-gate /* 177*0Sstevel@tonic-gate * HCI1394_IOCTL_READ_SELFID 178*0Sstevel@tonic-gate * Copies the contents of the selfid buffer into a buffer pointed to by buf. 179*0Sstevel@tonic-gate * Count is the number of 32-bit words to copy into buf. The maximum size 180*0Sstevel@tonic-gate * of the selfid buffer is 1024 32-bit words. The very first word is the 181*0Sstevel@tonic-gate * OpenHCI selfid header. 182*0Sstevel@tonic-gate */ 183*0Sstevel@tonic-gate typedef struct hci1394_ioctl_read_selfid_s { 184*0Sstevel@tonic-gate uint32_t *buf; 185*0Sstevel@tonic-gate uint_t count; 186*0Sstevel@tonic-gate } hci1394_ioctl_read_selfid_t; 187*0Sstevel@tonic-gate 188*0Sstevel@tonic-gate 189*0Sstevel@tonic-gate /* 190*0Sstevel@tonic-gate * HCI1394_IOCTL_WRPHY 191*0Sstevel@tonic-gate * Write PHY register. addr is an offset into the phy register space. 192*0Sstevel@tonic-gate * (i.e. addr = 0 is the first phy register). addr is byte aligned 193*0Sstevel@tonic-gate * (i.e. 0, 1, 2, 3, 4). data should contain the 8-bit value to write to the 194*0Sstevel@tonic-gate * PHY register. The data should be stored as follows <0x000000dd> where dd 195*0Sstevel@tonic-gate * is the byte written. 196*0Sstevel@tonic-gate * 197*0Sstevel@tonic-gate * NOTE: Phy register 0 cannot be read or written. 198*0Sstevel@tonic-gate * 199*0Sstevel@tonic-gate * NOTE: Writing PHY registers can cause the hardware and/or SW to misbehave. 200*0Sstevel@tonic-gate * Extreme care should be used when using this call. 201*0Sstevel@tonic-gate */ 202*0Sstevel@tonic-gate typedef struct hci1394_ioctl_wrphy_s { 203*0Sstevel@tonic-gate uint_t addr; 204*0Sstevel@tonic-gate uint_t data; 205*0Sstevel@tonic-gate } hci1394_ioctl_wrphy_t; 206*0Sstevel@tonic-gate 207*0Sstevel@tonic-gate 208*0Sstevel@tonic-gate /* 209*0Sstevel@tonic-gate * HCI1394_IOCTL_RDPHY 210*0Sstevel@tonic-gate * Read PHY register. addr is an offset into the phy register space. 211*0Sstevel@tonic-gate * (i.e. addr = 0 is the first phy register). addr is byte aligned 212*0Sstevel@tonic-gate * (i.e. 0, 1, 2, 3, 4). When the ioctl returns successfully, data will 213*0Sstevel@tonic-gate * contain the 8-bit data read from the PHY register. The data will be stored 214*0Sstevel@tonic-gate * as follows <0x000000dd> where dd is the byte read. 215*0Sstevel@tonic-gate * 216*0Sstevel@tonic-gate * NOTE: Phy register 0 cannot be read or written. 217*0Sstevel@tonic-gate */ 218*0Sstevel@tonic-gate typedef struct hci1394_ioctl_rdphy_s { 219*0Sstevel@tonic-gate uint_t addr; 220*0Sstevel@tonic-gate uint_t data; 221*0Sstevel@tonic-gate } hci1394_ioctl_rdphy_t; 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate 224*0Sstevel@tonic-gate /* 225*0Sstevel@tonic-gate * HCI1394_IOCTL_HBA_INFO 226*0Sstevel@tonic-gate * HBA Vendor Information 227*0Sstevel@tonic-gate * 228*0Sstevel@tonic-gate * Vendor Specific Info 229*0Sstevel@tonic-gate * pci_vendor_id - VendorID from PCI config space (0x0-0x1) 230*0Sstevel@tonic-gate * pci_device_id - DeviceID from PCI config space (0x2-0x3) 231*0Sstevel@tonic-gate * pci_revision_id - RevisionID from PCI config space (0x8) 232*0Sstevel@tonic-gate * ohci_version - 1394 OpenHCI Version Register (0x0) 233*0Sstevel@tonic-gate * ohci_vendor_id - 1394 OpenHCI Vendor ID Register (0x40) 234*0Sstevel@tonic-gate * ohci_vregset_cnt - Number of vendor specific register maps that have been 235*0Sstevel@tonic-gate * mapped by the driver. The driver will only map in 236*0Sstevel@tonic-gate * vendor specific registers for adapters it knows about. 237*0Sstevel@tonic-gate */ 238*0Sstevel@tonic-gate typedef struct hci1394_ioctl_hbainfo_s { 239*0Sstevel@tonic-gate uint_t pci_vendor_id; 240*0Sstevel@tonic-gate uint_t pci_device_id; 241*0Sstevel@tonic-gate uint_t pci_revision_id; 242*0Sstevel@tonic-gate uint32_t ohci_version; 243*0Sstevel@tonic-gate uint32_t ohci_vendor_id; 244*0Sstevel@tonic-gate uint_t ohci_vregset_cnt; 245*0Sstevel@tonic-gate } hci1394_ioctl_hbainfo_t; 246*0Sstevel@tonic-gate 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate #ifdef __cplusplus 249*0Sstevel@tonic-gate } 250*0Sstevel@tonic-gate #endif 251*0Sstevel@tonic-gate 252*0Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_IOCTL_H */ 253