1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_1394_ADAPTERS_HCI1394_CSR_H 28*0Sstevel@tonic-gate #define _SYS_1394_ADAPTERS_HCI1394_CSR_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * hci1394_csr.h 34*0Sstevel@tonic-gate * This file contains the code for the CSR registers handled by the HAL in 35*0Sstevel@tonic-gate * SW. The HW implemented CSR registers are in hci1394_ohci.c 36*0Sstevel@tonic-gate * 37*0Sstevel@tonic-gate * For more information on CSR registers, see 38*0Sstevel@tonic-gate * IEEE 1212 39*0Sstevel@tonic-gate * IEEE 1394-1995 40*0Sstevel@tonic-gate * section 8.3.2 41*0Sstevel@tonic-gate * IEEE P1394A Draft 3.0 42*0Sstevel@tonic-gate * sections 10.32,10.33 43*0Sstevel@tonic-gate * 44*0Sstevel@tonic-gate * NOTE: A read/write to a CSR SW based register will first go to the Services 45*0Sstevel@tonic-gate * Layer which will do some filtering and then come through the s1394if. 46*0Sstevel@tonic-gate */ 47*0Sstevel@tonic-gate 48*0Sstevel@tonic-gate #ifdef __cplusplus 49*0Sstevel@tonic-gate extern "C" { 50*0Sstevel@tonic-gate #endif 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate #include <sys/ddi.h> 53*0Sstevel@tonic-gate #include <sys/modctl.h> 54*0Sstevel@tonic-gate #include <sys/sunddi.h> 55*0Sstevel@tonic-gate 56*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394_def.h> 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate 59*0Sstevel@tonic-gate /* 60*0Sstevel@tonic-gate * The 1394 bus sends out cycle start packets periodically. The time in 61*0Sstevel@tonic-gate * between these packets is commonly referred to as a bus cycle. The 1394 62*0Sstevel@tonic-gate * cycle start packets come every 125uS. split_timeout is represented in 1394 63*0Sstevel@tonic-gate * bus cycles (e.g. to have ATREQ ACK_PENDED timeout after 100mS, you would set 64*0Sstevel@tonic-gate * split_timeout to 800). 65*0Sstevel@tonic-gate * 66*0Sstevel@tonic-gate * The CSR register interface has the split timeout broken into two registers, 67*0Sstevel@tonic-gate * split_timeout_hi and split_timeout_lo. The least significant 3 bits of 68*0Sstevel@tonic-gate * split_timeout_hi contain the # of seconds and the most significant 13 bits 69*0Sstevel@tonic-gate * of split_timeout_lo contain the fraction of a seconds in 125uS increments. 70*0Sstevel@tonic-gate * There is a further constraint that the value in split_timeout_lo must be >= 71*0Sstevel@tonic-gate * 800 && <= 7999 (>=100mS && < 1S). (don't forget that this value is in the 72*0Sstevel@tonic-gate * most significant 13 bits, i.e. 800 << 19) We will threshold the writes into 73*0Sstevel@tonic-gate * these registers to make sure they always have legal values (i.e. if 74*0Sstevel@tonic-gate * [8000 << 19] is written to split_timeout_lo, we will write [7999 << 19]. 75*0Sstevel@tonic-gate * 76*0Sstevel@tonic-gate * The split timeout CSR registers have some inherent problems. There is a race 77*0Sstevel@tonic-gate * condition when updating the split timeout value since you cannot atomically 78*0Sstevel@tonic-gate * write to both the hi and lo registers. This should not be a serious problem 79*0Sstevel@tonic-gate * since we should never get close to having a split timeout of 1S or greater. 80*0Sstevel@tonic-gate */ 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate 83*0Sstevel@tonic-gate /* CSR Register Address Offsets (1394-1995 8.3.2.2) */ 84*0Sstevel@tonic-gate #define CSR_STATE_CLEAR 0x000 85*0Sstevel@tonic-gate #define CSR_STATE_SET 0x004 86*0Sstevel@tonic-gate #define CSR_NODE_IDS 0x008 87*0Sstevel@tonic-gate #define CSR_RESET_START 0x00C 88*0Sstevel@tonic-gate #define CSR_SPLIT_TIMEOUT_HI 0x018 89*0Sstevel@tonic-gate #define CSR_SPLIT_TIMEOUT_LO 0x01C 90*0Sstevel@tonic-gate #define CSR_CYCLE_TIME 0x200 91*0Sstevel@tonic-gate #define CSR_BUS_TIME 0x204 92*0Sstevel@tonic-gate #define CSR_BUSY_TIMEOUT 0x210 93*0Sstevel@tonic-gate #define CSR_BUS_MANAGER_ID 0x21C 94*0Sstevel@tonic-gate #define CSR_BANDWIDTH_AVAILABLE 0x220 95*0Sstevel@tonic-gate #define CSR_CHANNELS_AVAILABLE_HI 0x224 96*0Sstevel@tonic-gate #define CSR_CHANNELS_AVAILABLE_LO 0x228 97*0Sstevel@tonic-gate 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate typedef struct hci1394_csr_s { 100*0Sstevel@tonic-gate /* SW registers */ 101*0Sstevel@tonic-gate uint32_t csr_state; 102*0Sstevel@tonic-gate uint32_t csr_split_timeout_lo; 103*0Sstevel@tonic-gate uint32_t csr_split_timeout_hi; 104*0Sstevel@tonic-gate 105*0Sstevel@tonic-gate /* split timeout that we are observing */ 106*0Sstevel@tonic-gate uint_t csr_split_timeout; 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate /* were we root last bus reset */ 109*0Sstevel@tonic-gate boolean_t csr_was_root; 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate /* our node capabilities */ 112*0Sstevel@tonic-gate uint32_t csr_capabilities; 113*0Sstevel@tonic-gate 114*0Sstevel@tonic-gate /* copies of OpenHCI handle and pointer to general driver info */ 115*0Sstevel@tonic-gate hci1394_ohci_handle_t csr_ohci; 116*0Sstevel@tonic-gate hci1394_drvinfo_t *csr_drvinfo; 117*0Sstevel@tonic-gate 118*0Sstevel@tonic-gate kmutex_t csr_mutex; 119*0Sstevel@tonic-gate } hci1394_csr_t; 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate /* handle passed back from init() and used for rest of functions */ 122*0Sstevel@tonic-gate typedef struct hci1394_csr_s *hci1394_csr_handle_t; 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate void hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci, 126*0Sstevel@tonic-gate hci1394_csr_handle_t *csr_handle); 127*0Sstevel@tonic-gate void hci1394_csr_fini(hci1394_csr_handle_t *csr_handle); 128*0Sstevel@tonic-gate void hci1394_csr_resume(hci1394_csr_handle_t csr_handle); 129*0Sstevel@tonic-gate 130*0Sstevel@tonic-gate void hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle, 131*0Sstevel@tonic-gate uint32_t *capabilities); 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate void hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state); 134*0Sstevel@tonic-gate void hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state); 135*0Sstevel@tonic-gate void hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state); 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate void hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle, 138*0Sstevel@tonic-gate uint32_t *split_timeout_hi); 139*0Sstevel@tonic-gate void hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle, 140*0Sstevel@tonic-gate uint32_t *split_timeout_lo); 141*0Sstevel@tonic-gate void hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle, 142*0Sstevel@tonic-gate uint32_t split_timeout_hi); 143*0Sstevel@tonic-gate void hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle, 144*0Sstevel@tonic-gate uint32_t split_timeout_lo); 145*0Sstevel@tonic-gate uint_t hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle); 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate void hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle); 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate #ifdef __cplusplus 151*0Sstevel@tonic-gate } 152*0Sstevel@tonic-gate #endif 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate #endif /* _SYS_1394_ADAPTERS_HCI1394_CSR_H */ 155