14128Shx147065 /* 24128Shx147065 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 34128Shx147065 * Use is subject to license terms. 44128Shx147065 */ 54128Shx147065 64128Shx147065 /* 74128Shx147065 * Copyright (c) 2006 84128Shx147065 * Damien Bergamini <damien.bergamini@free.fr> 94128Shx147065 * 104128Shx147065 * Permission to use, copy, modify, and distribute this software for any 114128Shx147065 * purpose with or without fee is hereby granted, provided that the above 124128Shx147065 * copyright notice and this permission notice appear in all copies. 134128Shx147065 * 144128Shx147065 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 154128Shx147065 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 164128Shx147065 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 174128Shx147065 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 184128Shx147065 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 194128Shx147065 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 204128Shx147065 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 214128Shx147065 */ 224128Shx147065 234128Shx147065 #pragma ident "%Z%%M% %I% %E% SMI" 244128Shx147065 254128Shx147065 /* 264128Shx147065 * Driver for Intel PRO/Wireless 3945ABG 802.11 network adapters. 274128Shx147065 */ 284128Shx147065 294128Shx147065 #include <sys/types.h> 304128Shx147065 #include <sys/byteorder.h> 314128Shx147065 #include <sys/conf.h> 324128Shx147065 #include <sys/cmn_err.h> 334128Shx147065 #include <sys/stat.h> 344128Shx147065 #include <sys/ddi.h> 354128Shx147065 #include <sys/sunddi.h> 364128Shx147065 #include <sys/strsubr.h> 374128Shx147065 #include <sys/ethernet.h> 384128Shx147065 #include <inet/common.h> 394128Shx147065 #include <inet/nd.h> 404128Shx147065 #include <inet/mi.h> 414128Shx147065 #include <sys/note.h> 424128Shx147065 #include <sys/stream.h> 434128Shx147065 #include <sys/strsun.h> 444128Shx147065 #include <sys/modctl.h> 454128Shx147065 #include <sys/devops.h> 464128Shx147065 #include <sys/dlpi.h> 474128Shx147065 #include <sys/mac.h> 484128Shx147065 #include <sys/mac_wifi.h> 494128Shx147065 #include <sys/net80211.h> 504128Shx147065 #include <sys/net80211_proto.h> 514128Shx147065 #include <sys/varargs.h> 524128Shx147065 #include <sys/policy.h> 534128Shx147065 #include <sys/pci.h> 544128Shx147065 554128Shx147065 #include "wpireg.h" 564128Shx147065 #include "wpivar.h" 574128Shx147065 #include <inet/wifi_ioctl.h> 584128Shx147065 594128Shx147065 #ifdef DEBUG 604128Shx147065 #define WPI_DEBUG_80211 (1 << 0) 614128Shx147065 #define WPI_DEBUG_CMD (1 << 1) 624128Shx147065 #define WPI_DEBUG_DMA (1 << 2) 634128Shx147065 #define WPI_DEBUG_EEPROM (1 << 3) 644128Shx147065 #define WPI_DEBUG_FW (1 << 4) 654128Shx147065 #define WPI_DEBUG_HW (1 << 5) 664128Shx147065 #define WPI_DEBUG_INTR (1 << 6) 674128Shx147065 #define WPI_DEBUG_MRR (1 << 7) 684128Shx147065 #define WPI_DEBUG_PIO (1 << 8) 694128Shx147065 #define WPI_DEBUG_RX (1 << 9) 704128Shx147065 #define WPI_DEBUG_SCAN (1 << 10) 714128Shx147065 #define WPI_DEBUG_TX (1 << 11) 724128Shx147065 #define WPI_DEBUG_RATECTL (1 << 12) 734128Shx147065 #define WPI_DEBUG_RADIO (1 << 13) 744128Shx147065 uint32_t wpi_dbg_flags = 0; 754128Shx147065 #define WPI_DBG(x) \ 764128Shx147065 wpi_dbg x 774128Shx147065 #else 784128Shx147065 #define WPI_DBG(x) 794128Shx147065 #endif 804128Shx147065 814128Shx147065 static void *wpi_soft_state_p = NULL; 824128Shx147065 static uint8_t wpi_fw_bin [] = { 834128Shx147065 #include "fw-wpi/ipw3945.ucode.hex" 844128Shx147065 }; 854128Shx147065 864128Shx147065 /* DMA attributes for a shared page */ 874128Shx147065 static ddi_dma_attr_t sh_dma_attr = { 884128Shx147065 DMA_ATTR_V0, /* version of this structure */ 894128Shx147065 0, /* lowest usable address */ 904128Shx147065 0xffffffffU, /* highest usable address */ 914128Shx147065 0xffffffffU, /* maximum DMAable byte count */ 924128Shx147065 0x1000, /* alignment in bytes */ 934128Shx147065 0x1000, /* burst sizes (any?) */ 944128Shx147065 1, /* minimum transfer */ 954128Shx147065 0xffffffffU, /* maximum transfer */ 964128Shx147065 0xffffffffU, /* maximum segment length */ 974128Shx147065 1, /* maximum number of segments */ 984128Shx147065 1, /* granularity */ 994128Shx147065 0, /* flags (reserved) */ 1004128Shx147065 }; 1014128Shx147065 1024128Shx147065 /* DMA attributes for a ring descriptor */ 1034128Shx147065 static ddi_dma_attr_t ring_desc_dma_attr = { 1044128Shx147065 DMA_ATTR_V0, /* version of this structure */ 1054128Shx147065 0, /* lowest usable address */ 1064128Shx147065 0xffffffffU, /* highest usable address */ 1074128Shx147065 0xffffffffU, /* maximum DMAable byte count */ 1084128Shx147065 0x4000, /* alignment in bytes */ 1094128Shx147065 0x100, /* burst sizes (any?) */ 1104128Shx147065 1, /* minimum transfer */ 1114128Shx147065 0xffffffffU, /* maximum transfer */ 1124128Shx147065 0xffffffffU, /* maximum segment length */ 1134128Shx147065 1, /* maximum number of segments */ 1144128Shx147065 1, /* granularity */ 1154128Shx147065 0, /* flags (reserved) */ 1164128Shx147065 }; 1174128Shx147065 1184128Shx147065 1194128Shx147065 /* DMA attributes for a tx cmd */ 1204128Shx147065 static ddi_dma_attr_t tx_cmd_dma_attr = { 1214128Shx147065 DMA_ATTR_V0, /* version of this structure */ 1224128Shx147065 0, /* lowest usable address */ 1234128Shx147065 0xffffffffU, /* highest usable address */ 1244128Shx147065 0xffffffffU, /* maximum DMAable byte count */ 1254128Shx147065 4, /* alignment in bytes */ 1264128Shx147065 0x100, /* burst sizes (any?) */ 1274128Shx147065 1, /* minimum transfer */ 1284128Shx147065 0xffffffffU, /* maximum transfer */ 1294128Shx147065 0xffffffffU, /* maximum segment length */ 1304128Shx147065 1, /* maximum number of segments */ 1314128Shx147065 1, /* granularity */ 1324128Shx147065 0, /* flags (reserved) */ 1334128Shx147065 }; 1344128Shx147065 1354128Shx147065 /* DMA attributes for a rx buffer */ 1364128Shx147065 static ddi_dma_attr_t rx_buffer_dma_attr = { 1374128Shx147065 DMA_ATTR_V0, /* version of this structure */ 1384128Shx147065 0, /* lowest usable address */ 1394128Shx147065 0xffffffffU, /* highest usable address */ 1404128Shx147065 0xffffffffU, /* maximum DMAable byte count */ 1414128Shx147065 1, /* alignment in bytes */ 1424128Shx147065 0x100, /* burst sizes (any?) */ 1434128Shx147065 1, /* minimum transfer */ 1444128Shx147065 0xffffffffU, /* maximum transfer */ 1454128Shx147065 0xffffffffU, /* maximum segment length */ 1464128Shx147065 1, /* maximum number of segments */ 1474128Shx147065 1, /* granularity */ 1484128Shx147065 0, /* flags (reserved) */ 1494128Shx147065 }; 1504128Shx147065 1514128Shx147065 /* 1524128Shx147065 * DMA attributes for a tx buffer. 1534128Shx147065 * the maximum number of segments is 4 for the hardware. 1544128Shx147065 * now all the wifi drivers put the whole frame in a single 1554128Shx147065 * descriptor, so we define the maximum number of segments 4, 1564128Shx147065 * just the same as the rx_buffer. we consider leverage the HW 1574128Shx147065 * ability in the future, that is why we don't define rx and tx 1584128Shx147065 * buffer_dma_attr as the same. 1594128Shx147065 */ 1604128Shx147065 static ddi_dma_attr_t tx_buffer_dma_attr = { 1614128Shx147065 DMA_ATTR_V0, /* version of this structure */ 1624128Shx147065 0, /* lowest usable address */ 1634128Shx147065 0xffffffffU, /* highest usable address */ 1644128Shx147065 0xffffffffU, /* maximum DMAable byte count */ 1654128Shx147065 1, /* alignment in bytes */ 1664128Shx147065 0x100, /* burst sizes (any?) */ 1674128Shx147065 1, /* minimum transfer */ 1684128Shx147065 0xffffffffU, /* maximum transfer */ 1694128Shx147065 0xffffffffU, /* maximum segment length */ 1704128Shx147065 1, /* maximum number of segments */ 1714128Shx147065 1, /* granularity */ 1724128Shx147065 0, /* flags (reserved) */ 1734128Shx147065 }; 1744128Shx147065 1754128Shx147065 /* DMA attributes for a load firmware */ 1764128Shx147065 static ddi_dma_attr_t fw_buffer_dma_attr = { 1774128Shx147065 DMA_ATTR_V0, /* version of this structure */ 1784128Shx147065 0, /* lowest usable address */ 1794128Shx147065 0xffffffffU, /* highest usable address */ 1804128Shx147065 0x7fffffff, /* maximum DMAable byte count */ 1814128Shx147065 4, /* alignment in bytes */ 1824128Shx147065 0x100, /* burst sizes (any?) */ 1834128Shx147065 1, /* minimum transfer */ 1844128Shx147065 0xffffffffU, /* maximum transfer */ 1854128Shx147065 0xffffffffU, /* maximum segment length */ 1864128Shx147065 4, /* maximum number of segments */ 1874128Shx147065 1, /* granularity */ 1884128Shx147065 0, /* flags (reserved) */ 1894128Shx147065 }; 1904128Shx147065 1914128Shx147065 /* regs access attributes */ 1924128Shx147065 static ddi_device_acc_attr_t wpi_reg_accattr = { 1934128Shx147065 DDI_DEVICE_ATTR_V0, 1944128Shx147065 DDI_STRUCTURE_LE_ACC, 1954128Shx147065 DDI_STRICTORDER_ACC, 1964128Shx147065 DDI_DEFAULT_ACC 1974128Shx147065 }; 1984128Shx147065 1994128Shx147065 /* DMA access attributes */ 2004128Shx147065 static ddi_device_acc_attr_t wpi_dma_accattr = { 2014128Shx147065 DDI_DEVICE_ATTR_V0, 2024128Shx147065 DDI_NEVERSWAP_ACC, 2034128Shx147065 DDI_STRICTORDER_ACC, 2044128Shx147065 DDI_DEFAULT_ACC 2054128Shx147065 }; 2064128Shx147065 2074128Shx147065 static int wpi_ring_init(wpi_sc_t *); 2084128Shx147065 static void wpi_ring_free(wpi_sc_t *); 2094128Shx147065 static int wpi_alloc_shared(wpi_sc_t *); 2104128Shx147065 static void wpi_free_shared(wpi_sc_t *); 2114128Shx147065 static int wpi_alloc_fw_dma(wpi_sc_t *); 2124128Shx147065 static void wpi_free_fw_dma(wpi_sc_t *); 2134128Shx147065 static int wpi_alloc_rx_ring(wpi_sc_t *); 2144128Shx147065 static void wpi_reset_rx_ring(wpi_sc_t *); 2154128Shx147065 static void wpi_free_rx_ring(wpi_sc_t *); 2164128Shx147065 static int wpi_alloc_tx_ring(wpi_sc_t *, wpi_tx_ring_t *, int, int); 2174128Shx147065 static void wpi_reset_tx_ring(wpi_sc_t *, wpi_tx_ring_t *); 2184128Shx147065 static void wpi_free_tx_ring(wpi_sc_t *, wpi_tx_ring_t *); 2194128Shx147065 2204128Shx147065 static ieee80211_node_t *wpi_node_alloc(ieee80211com_t *); 2214128Shx147065 static void wpi_node_free(ieee80211_node_t *); 2224128Shx147065 static int wpi_newstate(ieee80211com_t *, enum ieee80211_state, int); 2234128Shx147065 static void wpi_mem_lock(wpi_sc_t *); 2244128Shx147065 static void wpi_mem_unlock(wpi_sc_t *); 2254128Shx147065 static uint32_t wpi_mem_read(wpi_sc_t *, uint16_t); 2264128Shx147065 static void wpi_mem_write(wpi_sc_t *, uint16_t, uint32_t); 2274128Shx147065 static void wpi_mem_write_region_4(wpi_sc_t *, uint16_t, 2284128Shx147065 const uint32_t *, int); 2294128Shx147065 static uint16_t wpi_read_prom_word(wpi_sc_t *, uint32_t); 2304128Shx147065 static int wpi_load_microcode(wpi_sc_t *); 2314128Shx147065 static int wpi_load_firmware(wpi_sc_t *, uint32_t); 2324128Shx147065 static void wpi_rx_intr(wpi_sc_t *, wpi_rx_desc_t *, 2334128Shx147065 wpi_rx_data_t *); 2344128Shx147065 static void wpi_tx_intr(wpi_sc_t *, wpi_rx_desc_t *, 2354128Shx147065 wpi_rx_data_t *); 2364128Shx147065 static void wpi_cmd_intr(wpi_sc_t *, wpi_rx_desc_t *); 2374128Shx147065 static uint_t wpi_intr(caddr_t); 2384128Shx147065 static uint_t wpi_notif_softintr(caddr_t); 2394128Shx147065 static uint8_t wpi_plcp_signal(int); 2404128Shx147065 static void wpi_read_eeprom(wpi_sc_t *); 2414128Shx147065 static int wpi_cmd(wpi_sc_t *, int, const void *, int, int); 2424128Shx147065 static int wpi_mrr_setup(wpi_sc_t *); 2434128Shx147065 static void wpi_set_led(wpi_sc_t *, uint8_t, uint8_t, uint8_t); 2444128Shx147065 static int wpi_auth(wpi_sc_t *); 2454128Shx147065 static int wpi_scan(wpi_sc_t *); 2464128Shx147065 static int wpi_config(wpi_sc_t *); 2474128Shx147065 static void wpi_stop_master(wpi_sc_t *); 2484128Shx147065 static int wpi_power_up(wpi_sc_t *); 2494128Shx147065 static int wpi_reset(wpi_sc_t *); 2504128Shx147065 static void wpi_hw_config(wpi_sc_t *); 2514128Shx147065 static int wpi_init(wpi_sc_t *); 2524128Shx147065 static void wpi_stop(wpi_sc_t *); 2534128Shx147065 static void wpi_amrr_init(wpi_amrr_t *); 2544128Shx147065 static void wpi_amrr_timeout(wpi_sc_t *); 2554128Shx147065 static void wpi_amrr_ratectl(void *, ieee80211_node_t *); 2564128Shx147065 2574128Shx147065 static int wpi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 2584128Shx147065 static int wpi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 2594128Shx147065 2604128Shx147065 /* 2614128Shx147065 * GLD specific operations 2624128Shx147065 */ 2634128Shx147065 static int wpi_m_stat(void *arg, uint_t stat, uint64_t *val); 2644128Shx147065 static int wpi_m_start(void *arg); 2654128Shx147065 static void wpi_m_stop(void *arg); 2664128Shx147065 static int wpi_m_unicst(void *arg, const uint8_t *macaddr); 2674128Shx147065 static int wpi_m_multicst(void *arg, boolean_t add, const uint8_t *m); 2684128Shx147065 static int wpi_m_promisc(void *arg, boolean_t on); 2694128Shx147065 static mblk_t *wpi_m_tx(void *arg, mblk_t *mp); 2704128Shx147065 static void wpi_m_ioctl(void *arg, queue_t *wq, mblk_t *mp); 2714128Shx147065 2724128Shx147065 static void wpi_destroy_locks(wpi_sc_t *sc); 2734128Shx147065 static int wpi_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type); 2744128Shx147065 static void wpi_thread(wpi_sc_t *sc); 2754128Shx147065 2764128Shx147065 /* 2774128Shx147065 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 2784128Shx147065 */ 2794128Shx147065 static const struct ieee80211_rateset wpi_rateset_11b = 2804128Shx147065 { 4, { 2, 4, 11, 22 } }; 2814128Shx147065 2824128Shx147065 static const struct ieee80211_rateset wpi_rateset_11g = 2834128Shx147065 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 2844128Shx147065 2854128Shx147065 static const uint8_t wpi_ridx_to_signal[] = { 2864128Shx147065 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 2874128Shx147065 /* R1-R4 (ral/ural is R4-R1) */ 2884128Shx147065 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 2894128Shx147065 /* CCK: device-dependent */ 2904128Shx147065 10, 20, 55, 110 2914128Shx147065 }; 2924128Shx147065 2934128Shx147065 /* 2944128Shx147065 * For mfthread only 2954128Shx147065 */ 2964128Shx147065 extern pri_t minclsyspri; 2974128Shx147065 2984128Shx147065 /* 2994128Shx147065 * Module Loading Data & Entry Points 3004128Shx147065 */ 3014128Shx147065 DDI_DEFINE_STREAM_OPS(wpi_devops, nulldev, nulldev, wpi_attach, 3024128Shx147065 wpi_detach, nodev, NULL, D_MP, NULL); 3034128Shx147065 3044128Shx147065 static struct modldrv wpi_modldrv = { 3054128Shx147065 &mod_driverops, 3064128Shx147065 "Intel(R) PRO/Wireless 3945ABG driver", 3074128Shx147065 &wpi_devops 3084128Shx147065 }; 3094128Shx147065 3104128Shx147065 static struct modlinkage wpi_modlinkage = { 3114128Shx147065 MODREV_1, 3124128Shx147065 &wpi_modldrv, 3134128Shx147065 NULL 3144128Shx147065 }; 3154128Shx147065 3164128Shx147065 int 3174128Shx147065 _init(void) 3184128Shx147065 { 3194128Shx147065 int status; 3204128Shx147065 3214128Shx147065 status = ddi_soft_state_init(&wpi_soft_state_p, 3224128Shx147065 sizeof (wpi_sc_t), 1); 3234128Shx147065 if (status != DDI_SUCCESS) 3244128Shx147065 return (status); 3254128Shx147065 3264128Shx147065 mac_init_ops(&wpi_devops, "wpi"); 3274128Shx147065 status = mod_install(&wpi_modlinkage); 3284128Shx147065 if (status != DDI_SUCCESS) { 3294128Shx147065 mac_fini_ops(&wpi_devops); 3304128Shx147065 ddi_soft_state_fini(&wpi_soft_state_p); 3314128Shx147065 } 3324128Shx147065 3334128Shx147065 return (status); 3344128Shx147065 } 3354128Shx147065 3364128Shx147065 int 3374128Shx147065 _fini(void) 3384128Shx147065 { 3394128Shx147065 int status; 3404128Shx147065 3414128Shx147065 status = mod_remove(&wpi_modlinkage); 3424128Shx147065 if (status == DDI_SUCCESS) { 3434128Shx147065 mac_fini_ops(&wpi_devops); 3444128Shx147065 ddi_soft_state_fini(&wpi_soft_state_p); 3454128Shx147065 } 3464128Shx147065 3474128Shx147065 return (status); 3484128Shx147065 } 3494128Shx147065 3504128Shx147065 int 3514128Shx147065 _info(struct modinfo *mip) 3524128Shx147065 { 3534128Shx147065 return (mod_info(&wpi_modlinkage, mip)); 3544128Shx147065 } 3554128Shx147065 3564128Shx147065 /* 3574128Shx147065 * Mac Call Back entries 3584128Shx147065 */ 3594128Shx147065 mac_callbacks_t wpi_m_callbacks = { 3604128Shx147065 MC_IOCTL, 3614128Shx147065 wpi_m_stat, 3624128Shx147065 wpi_m_start, 3634128Shx147065 wpi_m_stop, 3644128Shx147065 wpi_m_promisc, 3654128Shx147065 wpi_m_multicst, 3664128Shx147065 wpi_m_unicst, 3674128Shx147065 wpi_m_tx, 3684128Shx147065 NULL, 3694128Shx147065 wpi_m_ioctl 3704128Shx147065 }; 3714128Shx147065 3724128Shx147065 #ifdef DEBUG 3734128Shx147065 void 3744128Shx147065 wpi_dbg(uint32_t flags, const char *fmt, ...) 3754128Shx147065 { 3764128Shx147065 va_list ap; 3774128Shx147065 3784128Shx147065 if (flags & wpi_dbg_flags) { 3794128Shx147065 va_start(ap, fmt); 3804128Shx147065 vcmn_err(CE_NOTE, fmt, ap); 3814128Shx147065 va_end(ap); 3824128Shx147065 } 3834128Shx147065 } 3844128Shx147065 #endif 3854128Shx147065 /* 3864128Shx147065 * device operations 3874128Shx147065 */ 3884128Shx147065 int 3894128Shx147065 wpi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 3904128Shx147065 { 3914128Shx147065 wpi_sc_t *sc; 3924128Shx147065 ddi_acc_handle_t cfg_handle; 3934128Shx147065 caddr_t cfg_base; 3944128Shx147065 ieee80211com_t *ic; 3954128Shx147065 int instance, err, i; 3964128Shx147065 char strbuf[32]; 3974128Shx147065 wifi_data_t wd = { 0 }; 3984128Shx147065 mac_register_t *macp; 3994128Shx147065 4004128Shx147065 if (cmd != DDI_ATTACH) { 4014128Shx147065 err = DDI_FAILURE; 4024128Shx147065 goto attach_fail1; 4034128Shx147065 } 4044128Shx147065 4054128Shx147065 instance = ddi_get_instance(dip); 4064128Shx147065 err = ddi_soft_state_zalloc(wpi_soft_state_p, instance); 4074128Shx147065 if (err != DDI_SUCCESS) { 4084128Shx147065 cmn_err(CE_WARN, 4094128Shx147065 "wpi_attach(): failed to allocate soft state\n"); 4104128Shx147065 goto attach_fail1; 4114128Shx147065 } 4124128Shx147065 sc = ddi_get_soft_state(wpi_soft_state_p, instance); 4134128Shx147065 sc->sc_dip = dip; 4144128Shx147065 4154128Shx147065 err = ddi_regs_map_setup(dip, 0, &cfg_base, 0, 0, 4164128Shx147065 &wpi_reg_accattr, &cfg_handle); 4174128Shx147065 if (err != DDI_SUCCESS) { 4184128Shx147065 cmn_err(CE_WARN, 4194128Shx147065 "wpi_attach(): failed to map config spaces regs\n"); 4204128Shx147065 goto attach_fail2; 4214128Shx147065 } 4224128Shx147065 sc->sc_rev = ddi_get8(cfg_handle, 4234128Shx147065 (uint8_t *)(cfg_base + PCI_CONF_REVID)); 4244128Shx147065 ddi_put8(cfg_handle, (uint8_t *)(cfg_base + 0x41), 0); 4254128Shx147065 sc->sc_clsz = ddi_get16(cfg_handle, 4264128Shx147065 (uint16_t *)(cfg_base + PCI_CONF_CACHE_LINESZ)); 4274128Shx147065 ddi_regs_map_free(&cfg_handle); 4284128Shx147065 if (!sc->sc_clsz) 4294128Shx147065 sc->sc_clsz = 16; 4304128Shx147065 sc->sc_clsz = (sc->sc_clsz << 2); 4314128Shx147065 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) + 4324128Shx147065 IEEE80211_MTU + IEEE80211_CRC_LEN + 4334128Shx147065 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 4344128Shx147065 IEEE80211_WEP_CRCLEN), sc->sc_clsz); 4354128Shx147065 /* 4364128Shx147065 * Map operating registers 4374128Shx147065 */ 4384128Shx147065 err = ddi_regs_map_setup(dip, 1, &sc->sc_base, 4394128Shx147065 0, 0, &wpi_reg_accattr, &sc->sc_handle); 4404128Shx147065 if (err != DDI_SUCCESS) { 4414128Shx147065 cmn_err(CE_WARN, 4424128Shx147065 "wpi_attach(): failed to map device regs\n"); 4434128Shx147065 goto attach_fail2; 4444128Shx147065 } 4454128Shx147065 4464128Shx147065 /* 4474128Shx147065 * Allocate shared page. 4484128Shx147065 */ 4494128Shx147065 err = wpi_alloc_shared(sc); 4504128Shx147065 if (err != DDI_SUCCESS) { 4514128Shx147065 cmn_err(CE_WARN, "failed to allocate shared page\n"); 4524128Shx147065 goto attach_fail3; 4534128Shx147065 } 4544128Shx147065 4554128Shx147065 /* 4564128Shx147065 * Get the hw conf, including MAC address, then init all rings. 4574128Shx147065 */ 4584128Shx147065 wpi_read_eeprom(sc); 4594128Shx147065 err = wpi_ring_init(sc); 4604128Shx147065 if (err != DDI_SUCCESS) { 4614128Shx147065 cmn_err(CE_WARN, "wpi_attach(): " 4624128Shx147065 "failed to allocate and initialize ring\n"); 4634128Shx147065 goto attach_fail4; 4644128Shx147065 } 4654128Shx147065 4664128Shx147065 sc->sc_hdr = (const wpi_firmware_hdr_t *)wpi_fw_bin; 4674128Shx147065 4684128Shx147065 /* firmware image layout: |HDR|<--TEXT-->|<--DATA-->|<--BOOT-->| */ 4694128Shx147065 sc->sc_text = (const char *)(sc->sc_hdr + 1); 4704128Shx147065 sc->sc_data = sc->sc_text + LE_32(sc->sc_hdr->textsz); 4714128Shx147065 sc->sc_boot = sc->sc_data + LE_32(sc->sc_hdr->datasz); 4724128Shx147065 err = wpi_alloc_fw_dma(sc); 4734128Shx147065 if (err != DDI_SUCCESS) { 4744128Shx147065 cmn_err(CE_WARN, "wpi_attach(): " 4754128Shx147065 "failed to allocate firmware dma\n"); 4764128Shx147065 goto attach_fail5; 4774128Shx147065 } 4784128Shx147065 4794128Shx147065 /* 4804128Shx147065 * Initialize mutexs and condvars 4814128Shx147065 */ 4824128Shx147065 err = ddi_get_iblock_cookie(dip, 0, &sc->sc_iblk); 4834128Shx147065 if (err != DDI_SUCCESS) { 4844128Shx147065 cmn_err(CE_WARN, 4854128Shx147065 "wpi_attach(): failed to do ddi_get_iblock_cookie()\n"); 4864128Shx147065 goto attach_fail6; 4874128Shx147065 } 4884128Shx147065 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, sc->sc_iblk); 4894128Shx147065 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER, sc->sc_iblk); 4904128Shx147065 cv_init(&sc->sc_fw_cv, NULL, CV_DRIVER, NULL); 4914128Shx147065 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL); 4924128Shx147065 cv_init(&sc->sc_tx_cv, "tx-ring", CV_DRIVER, NULL); 4934128Shx147065 /* 4944128Shx147065 * initialize the mfthread 4954128Shx147065 */ 4964128Shx147065 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER, 4974128Shx147065 (void *) sc->sc_iblk); 4984128Shx147065 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL); 4994128Shx147065 sc->sc_mf_thread = NULL; 5004128Shx147065 sc->sc_mf_thread_switch = 0; 5014128Shx147065 /* 5024128Shx147065 * Initialize the wifi part, which will be used by 5034128Shx147065 * generic layer 5044128Shx147065 */ 5054128Shx147065 ic = &sc->sc_ic; 5064128Shx147065 ic->ic_phytype = IEEE80211_T_OFDM; 5074128Shx147065 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 5084128Shx147065 ic->ic_state = IEEE80211_S_INIT; 5094128Shx147065 ic->ic_maxrssi = 70; /* experimental number */ 5104128Shx147065 /* 5114128Shx147065 * use software WEP for the current version. 5124128Shx147065 */ 5134128Shx147065 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 514*4499Shx147065 IEEE80211_C_PMGT | IEEE80211_C_SHSLOT; 5154128Shx147065 5164128Shx147065 /* set supported .11b and .11g rates */ 5174128Shx147065 ic->ic_sup_rates[IEEE80211_MODE_11B] = wpi_rateset_11b; 5184128Shx147065 ic->ic_sup_rates[IEEE80211_MODE_11G] = wpi_rateset_11g; 5194128Shx147065 5204128Shx147065 /* set supported .11b and .11g channels (1 through 14) */ 5214128Shx147065 for (i = 1; i <= 14; i++) { 5224128Shx147065 ic->ic_sup_channels[i].ich_freq = 5234128Shx147065 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 5244128Shx147065 ic->ic_sup_channels[i].ich_flags = 5254128Shx147065 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 5264128Shx147065 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 5274128Shx147065 } 5284128Shx147065 ic->ic_ibss_chan = &ic->ic_sup_channels[0]; 5294128Shx147065 ic->ic_xmit = wpi_send; 5304128Shx147065 /* 5314128Shx147065 * init Wifi layer 5324128Shx147065 */ 5334128Shx147065 ieee80211_attach(ic); 5344128Shx147065 5354128Shx147065 /* 5364128Shx147065 * Override 80211 default routines 5374128Shx147065 */ 5384128Shx147065 sc->sc_newstate = ic->ic_newstate; 5394128Shx147065 ic->ic_newstate = wpi_newstate; 5404128Shx147065 ic->ic_node_alloc = wpi_node_alloc; 5414128Shx147065 ic->ic_node_free = wpi_node_free; 5424128Shx147065 ieee80211_media_init(ic); 5434128Shx147065 /* 5444128Shx147065 * initialize default tx key 5454128Shx147065 */ 5464128Shx147065 ic->ic_def_txkey = 0; 5474128Shx147065 5484128Shx147065 err = ddi_add_softintr(dip, DDI_SOFTINT_LOW, 5494128Shx147065 &sc->sc_notif_softint_id, &sc->sc_iblk, NULL, wpi_notif_softintr, 5504128Shx147065 (caddr_t)sc); 5514128Shx147065 if (err != DDI_SUCCESS) { 5524128Shx147065 cmn_err(CE_WARN, 5534128Shx147065 "wpi_attach(): failed to do ddi_add_softintr()\n"); 5544128Shx147065 goto attach_fail7; 5554128Shx147065 } 5564128Shx147065 5574128Shx147065 /* 5584128Shx147065 * Add the interrupt handler 5594128Shx147065 */ 5604128Shx147065 err = ddi_add_intr(dip, 0, &sc->sc_iblk, NULL, 5614128Shx147065 wpi_intr, (caddr_t)sc); 5624128Shx147065 if (err != DDI_SUCCESS) { 5634128Shx147065 cmn_err(CE_WARN, 5644128Shx147065 "wpi_attach(): failed to do ddi_add_intr()\n"); 5654128Shx147065 goto attach_fail8; 5664128Shx147065 } 5674128Shx147065 5684128Shx147065 /* 5694128Shx147065 * Initialize pointer to device specific functions 5704128Shx147065 */ 5714128Shx147065 wd.wd_secalloc = WIFI_SEC_NONE; 5724128Shx147065 wd.wd_opmode = ic->ic_opmode; 5734128Shx147065 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_macaddr); 5744128Shx147065 5754128Shx147065 macp = mac_alloc(MAC_VERSION); 5764128Shx147065 if (err != DDI_SUCCESS) { 5774128Shx147065 cmn_err(CE_WARN, 5784128Shx147065 "wpi_attach(): failed to do mac_alloc()\n"); 5794128Shx147065 goto attach_fail9; 5804128Shx147065 } 5814128Shx147065 5824128Shx147065 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 5834128Shx147065 macp->m_driver = sc; 5844128Shx147065 macp->m_dip = dip; 5854128Shx147065 macp->m_src_addr = ic->ic_macaddr; 5864128Shx147065 macp->m_callbacks = &wpi_m_callbacks; 5874128Shx147065 macp->m_min_sdu = 0; 5884128Shx147065 macp->m_max_sdu = IEEE80211_MTU; 5894128Shx147065 macp->m_pdata = &wd; 5904128Shx147065 macp->m_pdata_size = sizeof (wd); 5914128Shx147065 5924128Shx147065 /* 5934128Shx147065 * Register the macp to mac 5944128Shx147065 */ 5954128Shx147065 err = mac_register(macp, &ic->ic_mach); 5964128Shx147065 mac_free(macp); 5974128Shx147065 if (err != DDI_SUCCESS) { 5984128Shx147065 cmn_err(CE_WARN, 5994128Shx147065 "wpi_attach(): failed to do mac_register()\n"); 6004128Shx147065 goto attach_fail9; 6014128Shx147065 } 6024128Shx147065 6034128Shx147065 /* 6044128Shx147065 * Create minor node of type DDI_NT_NET_WIFI 6054128Shx147065 */ 6064128Shx147065 (void) snprintf(strbuf, sizeof (strbuf), "wpi%d", instance); 6074128Shx147065 err = ddi_create_minor_node(dip, strbuf, S_IFCHR, 6084128Shx147065 instance + 1, DDI_NT_NET_WIFI, 0); 6094128Shx147065 if (err != DDI_SUCCESS) 6104128Shx147065 cmn_err(CE_WARN, 6114128Shx147065 "wpi_attach(): failed to do ddi_create_minor_node()\n"); 6124128Shx147065 6134128Shx147065 /* 6144128Shx147065 * Notify link is down now 6154128Shx147065 */ 6164128Shx147065 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 6174128Shx147065 6184128Shx147065 /* 6194128Shx147065 * create the mf thread to handle the link status, 6204128Shx147065 * recovery fatal error, etc. 6214128Shx147065 */ 6224128Shx147065 6234128Shx147065 sc->sc_mf_thread_switch = 1; 6244128Shx147065 if (sc->sc_mf_thread == NULL) 6254128Shx147065 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0, 6264128Shx147065 wpi_thread, sc, 0, &p0, TS_RUN, minclsyspri); 6274128Shx147065 6284128Shx147065 sc->sc_flags |= WPI_F_ATTACHED; 6294128Shx147065 6304128Shx147065 return (DDI_SUCCESS); 6314128Shx147065 attach_fail9: 6324128Shx147065 ddi_remove_intr(dip, 0, sc->sc_iblk); 6334128Shx147065 attach_fail8: 6344128Shx147065 ddi_remove_softintr(sc->sc_notif_softint_id); 6354128Shx147065 sc->sc_notif_softint_id = NULL; 6364128Shx147065 attach_fail7: 6374128Shx147065 ieee80211_detach(ic); 6384128Shx147065 wpi_destroy_locks(sc); 6394128Shx147065 attach_fail6: 6404128Shx147065 wpi_free_fw_dma(sc); 6414128Shx147065 attach_fail5: 6424128Shx147065 wpi_ring_free(sc); 6434128Shx147065 attach_fail4: 6444128Shx147065 wpi_free_shared(sc); 6454128Shx147065 attach_fail3: 6464128Shx147065 ddi_regs_map_free(&sc->sc_handle); 6474128Shx147065 attach_fail2: 6484128Shx147065 ddi_soft_state_free(wpi_soft_state_p, instance); 6494128Shx147065 attach_fail1: 6504128Shx147065 return (err); 6514128Shx147065 } 6524128Shx147065 6534128Shx147065 int 6544128Shx147065 wpi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 6554128Shx147065 { 6564128Shx147065 wpi_sc_t *sc; 6574128Shx147065 int err; 6584128Shx147065 6594128Shx147065 sc = ddi_get_soft_state(wpi_soft_state_p, ddi_get_instance(dip)); 6604128Shx147065 ASSERT(sc != NULL); 6614128Shx147065 6624128Shx147065 if (cmd != DDI_DETACH) 6634128Shx147065 return (DDI_FAILURE); 6644128Shx147065 if (!(sc->sc_flags & WPI_F_ATTACHED)) 6654128Shx147065 return (DDI_FAILURE); 6664128Shx147065 6674128Shx147065 /* 6684128Shx147065 * Destroy the mf_thread 6694128Shx147065 */ 6704128Shx147065 mutex_enter(&sc->sc_mt_lock); 6714128Shx147065 sc->sc_mf_thread_switch = 0; 6724128Shx147065 while (sc->sc_mf_thread != NULL) { 6734128Shx147065 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) 6744128Shx147065 break; 6754128Shx147065 } 6764128Shx147065 mutex_exit(&sc->sc_mt_lock); 6774128Shx147065 6784128Shx147065 wpi_stop(sc); 6794128Shx147065 6804128Shx147065 /* 6814128Shx147065 * Unregiste from the MAC layer subsystem 6824128Shx147065 */ 6834128Shx147065 err = mac_unregister(sc->sc_ic.ic_mach); 6844128Shx147065 if (err != DDI_SUCCESS) 6854128Shx147065 return (err); 6864128Shx147065 6874128Shx147065 mutex_enter(&sc->sc_glock); 6884128Shx147065 wpi_free_fw_dma(sc); 6894128Shx147065 wpi_ring_free(sc); 6904128Shx147065 wpi_free_shared(sc); 6914128Shx147065 mutex_exit(&sc->sc_glock); 6924128Shx147065 6934128Shx147065 ddi_remove_intr(dip, 0, sc->sc_iblk); 6944128Shx147065 ddi_remove_softintr(sc->sc_notif_softint_id); 6954128Shx147065 sc->sc_notif_softint_id = NULL; 6964128Shx147065 6974128Shx147065 /* 6984128Shx147065 * detach ieee80211 6994128Shx147065 */ 7004128Shx147065 ieee80211_detach(&sc->sc_ic); 7014128Shx147065 7024128Shx147065 wpi_destroy_locks(sc); 7034128Shx147065 7044128Shx147065 ddi_regs_map_free(&sc->sc_handle); 7054128Shx147065 ddi_remove_minor_node(dip, NULL); 7064128Shx147065 ddi_soft_state_free(wpi_soft_state_p, ddi_get_instance(dip)); 7074128Shx147065 7084128Shx147065 return (DDI_SUCCESS); 7094128Shx147065 } 7104128Shx147065 7114128Shx147065 static void 7124128Shx147065 wpi_destroy_locks(wpi_sc_t *sc) 7134128Shx147065 { 7144128Shx147065 cv_destroy(&sc->sc_mt_cv); 7154128Shx147065 mutex_destroy(&sc->sc_mt_lock); 7164128Shx147065 cv_destroy(&sc->sc_tx_cv); 7174128Shx147065 cv_destroy(&sc->sc_cmd_cv); 7184128Shx147065 cv_destroy(&sc->sc_fw_cv); 7194128Shx147065 mutex_destroy(&sc->sc_tx_lock); 7204128Shx147065 mutex_destroy(&sc->sc_glock); 7214128Shx147065 } 7224128Shx147065 7234128Shx147065 /* 7244128Shx147065 * Allocate an area of memory and a DMA handle for accessing it 7254128Shx147065 */ 7264128Shx147065 static int 7274128Shx147065 wpi_alloc_dma_mem(wpi_sc_t *sc, size_t memsize, ddi_dma_attr_t *dma_attr_p, 7284128Shx147065 ddi_device_acc_attr_t *acc_attr_p, uint_t dma_flags, wpi_dma_t *dma_p) 7294128Shx147065 { 7304128Shx147065 caddr_t vaddr; 7314128Shx147065 int err; 7324128Shx147065 7334128Shx147065 /* 7344128Shx147065 * Allocate handle 7354128Shx147065 */ 7364128Shx147065 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p, 737*4499Shx147065 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 7384128Shx147065 if (err != DDI_SUCCESS) { 7394128Shx147065 dma_p->dma_hdl = NULL; 7404128Shx147065 return (DDI_FAILURE); 7414128Shx147065 } 7424128Shx147065 7434128Shx147065 /* 7444128Shx147065 * Allocate memory 7454128Shx147065 */ 7464128Shx147065 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p, 7474128Shx147065 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 7484128Shx147065 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 7494128Shx147065 if (err != DDI_SUCCESS) { 7504128Shx147065 ddi_dma_free_handle(&dma_p->dma_hdl); 7514128Shx147065 dma_p->dma_hdl = NULL; 7524128Shx147065 dma_p->acc_hdl = NULL; 7534128Shx147065 return (DDI_FAILURE); 7544128Shx147065 } 7554128Shx147065 7564128Shx147065 /* 7574128Shx147065 * Bind the two together 7584128Shx147065 */ 7594128Shx147065 dma_p->mem_va = vaddr; 7604128Shx147065 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 7614128Shx147065 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 7624128Shx147065 &dma_p->cookie, &dma_p->ncookies); 7634128Shx147065 if (err != DDI_DMA_MAPPED) { 7644128Shx147065 ddi_dma_mem_free(&dma_p->acc_hdl); 7654128Shx147065 ddi_dma_free_handle(&dma_p->dma_hdl); 7664128Shx147065 dma_p->acc_hdl = NULL; 7674128Shx147065 dma_p->dma_hdl = NULL; 7684128Shx147065 return (DDI_FAILURE); 7694128Shx147065 } 7704128Shx147065 7714128Shx147065 dma_p->nslots = ~0U; 7724128Shx147065 dma_p->size = ~0U; 7734128Shx147065 dma_p->token = ~0U; 7744128Shx147065 dma_p->offset = 0; 7754128Shx147065 return (DDI_SUCCESS); 7764128Shx147065 } 7774128Shx147065 7784128Shx147065 /* 7794128Shx147065 * Free one allocated area of DMAable memory 7804128Shx147065 */ 7814128Shx147065 static void 7824128Shx147065 wpi_free_dma_mem(wpi_dma_t *dma_p) 7834128Shx147065 { 7844128Shx147065 if (dma_p->dma_hdl != NULL) { 7854128Shx147065 if (dma_p->ncookies) { 7864128Shx147065 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 7874128Shx147065 dma_p->ncookies = 0; 7884128Shx147065 } 7894128Shx147065 ddi_dma_free_handle(&dma_p->dma_hdl); 7904128Shx147065 dma_p->dma_hdl = NULL; 7914128Shx147065 } 7924128Shx147065 7934128Shx147065 if (dma_p->acc_hdl != NULL) { 7944128Shx147065 ddi_dma_mem_free(&dma_p->acc_hdl); 7954128Shx147065 dma_p->acc_hdl = NULL; 7964128Shx147065 } 7974128Shx147065 } 7984128Shx147065 7994128Shx147065 /* 8004128Shx147065 * Allocate an area of dma memory for firmware load. 8014128Shx147065 * Idealy, this allocation should be a one time action, that is, 8024128Shx147065 * the memory will be freed after the firmware is uploaded to the 8034128Shx147065 * card. but since a recovery mechanism for the fatal firmware need 8044128Shx147065 * reload the firmware, and re-allocate dma at run time may be failed, 8054128Shx147065 * so we allocate it at attach and keep it in the whole lifecycle of 8064128Shx147065 * the driver. 8074128Shx147065 */ 8084128Shx147065 static int 8094128Shx147065 wpi_alloc_fw_dma(wpi_sc_t *sc) 8104128Shx147065 { 8114128Shx147065 int i, err = DDI_SUCCESS; 8124128Shx147065 wpi_dma_t *dma_p; 8134128Shx147065 8144128Shx147065 err = wpi_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz), 8154128Shx147065 &fw_buffer_dma_attr, &wpi_dma_accattr, 8164128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 8174128Shx147065 &sc->sc_dma_fw_text); 8184128Shx147065 dma_p = &sc->sc_dma_fw_text; 8194128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "ncookies:%d addr1:%x size1:%x\n", 8204128Shx147065 dma_p->ncookies, dma_p->cookie.dmac_address, 8214128Shx147065 dma_p->cookie.dmac_size)); 8224128Shx147065 if (err != DDI_SUCCESS) { 8234128Shx147065 cmn_err(CE_WARN, "wpi_alloc_fw_dma(): failed to alloc" 8244128Shx147065 "text dma memory"); 8254128Shx147065 goto fail; 8264128Shx147065 } 8274128Shx147065 for (i = 0; i < dma_p->ncookies; i++) { 8284128Shx147065 sc->sc_fw_text_cookie[i] = dma_p->cookie; 8294128Shx147065 ddi_dma_nextcookie(dma_p->dma_hdl, &dma_p->cookie); 8304128Shx147065 } 8314128Shx147065 err = wpi_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), 8324128Shx147065 &fw_buffer_dma_attr, &wpi_dma_accattr, 8334128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 8344128Shx147065 &sc->sc_dma_fw_data); 8354128Shx147065 dma_p = &sc->sc_dma_fw_data; 8364128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "ncookies:%d addr1:%x size1:%x\n", 8374128Shx147065 dma_p->ncookies, dma_p->cookie.dmac_address, 8384128Shx147065 dma_p->cookie.dmac_size)); 8394128Shx147065 if (err != DDI_SUCCESS) { 8404128Shx147065 cmn_err(CE_WARN, "wpi_alloc_fw_dma(): failed to alloc" 8414128Shx147065 "data dma memory"); 8424128Shx147065 goto fail; 8434128Shx147065 } 8444128Shx147065 for (i = 0; i < dma_p->ncookies; i++) { 8454128Shx147065 sc->sc_fw_data_cookie[i] = dma_p->cookie; 8464128Shx147065 ddi_dma_nextcookie(dma_p->dma_hdl, &dma_p->cookie); 8474128Shx147065 } 8484128Shx147065 fail: 8494128Shx147065 return (err); 8504128Shx147065 } 8514128Shx147065 8524128Shx147065 static void 8534128Shx147065 wpi_free_fw_dma(wpi_sc_t *sc) 8544128Shx147065 { 8554128Shx147065 wpi_free_dma_mem(&sc->sc_dma_fw_text); 8564128Shx147065 wpi_free_dma_mem(&sc->sc_dma_fw_data); 8574128Shx147065 } 8584128Shx147065 8594128Shx147065 /* 8604128Shx147065 * Allocate a shared page between host and NIC. 8614128Shx147065 */ 8624128Shx147065 static int 8634128Shx147065 wpi_alloc_shared(wpi_sc_t *sc) 8644128Shx147065 { 8654128Shx147065 int err = DDI_SUCCESS; 8664128Shx147065 8674128Shx147065 /* must be aligned on a 4K-page boundary */ 8684128Shx147065 err = wpi_alloc_dma_mem(sc, sizeof (wpi_shared_t), 8694128Shx147065 &sh_dma_attr, &wpi_dma_accattr, 8704128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 8714128Shx147065 &sc->sc_dma_sh); 8724128Shx147065 if (err != DDI_SUCCESS) 8734128Shx147065 goto fail; 8744128Shx147065 sc->sc_shared = (wpi_shared_t *)sc->sc_dma_sh.mem_va; 8754128Shx147065 return (err); 8764128Shx147065 8774128Shx147065 fail: 8784128Shx147065 wpi_free_shared(sc); 8794128Shx147065 return (err); 8804128Shx147065 } 8814128Shx147065 8824128Shx147065 static void 8834128Shx147065 wpi_free_shared(wpi_sc_t *sc) 8844128Shx147065 { 8854128Shx147065 wpi_free_dma_mem(&sc->sc_dma_sh); 8864128Shx147065 } 8874128Shx147065 8884128Shx147065 static int 8894128Shx147065 wpi_alloc_rx_ring(wpi_sc_t *sc) 8904128Shx147065 { 8914128Shx147065 wpi_rx_ring_t *ring; 8924128Shx147065 wpi_rx_data_t *data; 8934128Shx147065 int i, err = DDI_SUCCESS; 8944128Shx147065 8954128Shx147065 ring = &sc->sc_rxq; 8964128Shx147065 ring->cur = 0; 8974128Shx147065 8984128Shx147065 err = wpi_alloc_dma_mem(sc, WPI_RX_RING_COUNT * sizeof (uint32_t), 8994128Shx147065 &ring_desc_dma_attr, &wpi_dma_accattr, 9004128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 9014128Shx147065 &ring->dma_desc); 9024128Shx147065 if (err != DDI_SUCCESS) { 9034128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "dma alloc rx ring desc failed\n")); 9044128Shx147065 goto fail; 9054128Shx147065 } 9064128Shx147065 ring->desc = (uint32_t *)ring->dma_desc.mem_va; 9074128Shx147065 9084128Shx147065 /* 9094128Shx147065 * Allocate Rx buffers. 9104128Shx147065 */ 9114128Shx147065 for (i = 0; i < WPI_RX_RING_COUNT; i++) { 9124128Shx147065 data = &ring->data[i]; 9134128Shx147065 err = wpi_alloc_dma_mem(sc, sc->sc_dmabuf_sz, 9144128Shx147065 &rx_buffer_dma_attr, &wpi_dma_accattr, 9154128Shx147065 DDI_DMA_READ | DDI_DMA_STREAMING, 9164128Shx147065 &data->dma_data); 9174128Shx147065 if (err != DDI_SUCCESS) { 9184128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "dma alloc rx ring buf[%d] " 9194128Shx147065 "failed\n", i)); 9204128Shx147065 goto fail; 9214128Shx147065 } 9224128Shx147065 9234128Shx147065 ring->desc[i] = LE_32(data->dma_data.cookie.dmac_address); 9244128Shx147065 } 9254128Shx147065 9264128Shx147065 WPI_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); 9274128Shx147065 9284128Shx147065 return (err); 9294128Shx147065 9304128Shx147065 fail: 9314128Shx147065 wpi_free_rx_ring(sc); 9324128Shx147065 return (err); 9334128Shx147065 } 9344128Shx147065 9354128Shx147065 static void 9364128Shx147065 wpi_reset_rx_ring(wpi_sc_t *sc) 9374128Shx147065 { 9384128Shx147065 int ntries; 9394128Shx147065 9404128Shx147065 wpi_mem_lock(sc); 9414128Shx147065 9424128Shx147065 WPI_WRITE(sc, WPI_RX_CONFIG, 0); 9434128Shx147065 for (ntries = 0; ntries < 2000; ntries++) { 9444128Shx147065 if (WPI_READ(sc, WPI_RX_STATUS) & WPI_RX_IDLE) 9454128Shx147065 break; 9464128Shx147065 DELAY(1000); 9474128Shx147065 } 9484128Shx147065 #ifdef DEBUG 9494128Shx147065 if (ntries == 2000) 9504128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "timeout resetting Rx ring\n")); 9514128Shx147065 #endif 9524128Shx147065 wpi_mem_unlock(sc); 9534128Shx147065 9544128Shx147065 sc->sc_rxq.cur = 0; 9554128Shx147065 } 9564128Shx147065 9574128Shx147065 static void 9584128Shx147065 wpi_free_rx_ring(wpi_sc_t *sc) 9594128Shx147065 { 9604128Shx147065 int i; 9614128Shx147065 9624128Shx147065 for (i = 0; i < WPI_RX_RING_COUNT; i++) { 9634128Shx147065 if (sc->sc_rxq.data[i].dma_data.dma_hdl) 9644128Shx147065 WPI_DMA_SYNC(sc->sc_rxq.data[i].dma_data, 9654128Shx147065 DDI_DMA_SYNC_FORCPU); 9664128Shx147065 wpi_free_dma_mem(&sc->sc_rxq.data[i].dma_data); 9674128Shx147065 } 9684128Shx147065 9694128Shx147065 if (sc->sc_rxq.dma_desc.dma_hdl) 9704128Shx147065 WPI_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV); 9714128Shx147065 wpi_free_dma_mem(&sc->sc_rxq.dma_desc); 9724128Shx147065 } 9734128Shx147065 9744128Shx147065 static int 9754128Shx147065 wpi_alloc_tx_ring(wpi_sc_t *sc, wpi_tx_ring_t *ring, int count, int qid) 9764128Shx147065 { 9774128Shx147065 wpi_tx_data_t *data; 9784128Shx147065 wpi_tx_desc_t *desc_h; 9794128Shx147065 uint32_t paddr_desc_h; 9804128Shx147065 wpi_tx_cmd_t *cmd_h; 9814128Shx147065 uint32_t paddr_cmd_h; 9824128Shx147065 int i, err = DDI_SUCCESS; 9834128Shx147065 9844128Shx147065 ring->qid = qid; 9854128Shx147065 ring->count = count; 9864128Shx147065 ring->queued = 0; 9874128Shx147065 ring->cur = 0; 9884128Shx147065 9894128Shx147065 err = wpi_alloc_dma_mem(sc, count * sizeof (wpi_tx_desc_t), 9904128Shx147065 &ring_desc_dma_attr, &wpi_dma_accattr, 9914128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 9924128Shx147065 &ring->dma_desc); 9934128Shx147065 if (err != DDI_SUCCESS) { 9944128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "dma alloc tx ring desc[%d] failed\n", 9954128Shx147065 qid)); 9964128Shx147065 goto fail; 9974128Shx147065 } 9984128Shx147065 9994128Shx147065 /* update shared page with ring's base address */ 10004128Shx147065 sc->sc_shared->txbase[qid] = ring->dma_desc.cookie.dmac_address; 10014128Shx147065 10024128Shx147065 desc_h = (wpi_tx_desc_t *)ring->dma_desc.mem_va; 10034128Shx147065 paddr_desc_h = ring->dma_desc.cookie.dmac_address; 10044128Shx147065 10054128Shx147065 err = wpi_alloc_dma_mem(sc, count * sizeof (wpi_tx_cmd_t), 10064128Shx147065 &tx_cmd_dma_attr, &wpi_dma_accattr, 10074128Shx147065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 10084128Shx147065 &ring->dma_cmd); 10094128Shx147065 if (err != DDI_SUCCESS) { 10104128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "dma alloc tx ring cmd[%d] failed\n", 10114128Shx147065 qid)); 10124128Shx147065 goto fail; 10134128Shx147065 } 10144128Shx147065 10154128Shx147065 cmd_h = (wpi_tx_cmd_t *)ring->dma_cmd.mem_va; 10164128Shx147065 paddr_cmd_h = ring->dma_cmd.cookie.dmac_address; 10174128Shx147065 10184128Shx147065 /* 10194128Shx147065 * Allocate Tx buffers. 10204128Shx147065 */ 10214128Shx147065 ring->data = kmem_zalloc(sizeof (wpi_tx_data_t) * count, KM_NOSLEEP); 10224128Shx147065 if (ring->data == NULL) { 10234128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "could not allocate tx data slots\n")); 10244128Shx147065 goto fail; 10254128Shx147065 } 10264128Shx147065 10274128Shx147065 for (i = 0; i < count; i++) { 10284128Shx147065 data = &ring->data[i]; 10294128Shx147065 err = wpi_alloc_dma_mem(sc, sc->sc_dmabuf_sz, 10304128Shx147065 &tx_buffer_dma_attr, &wpi_dma_accattr, 10314128Shx147065 DDI_DMA_WRITE | DDI_DMA_STREAMING, 10324128Shx147065 &data->dma_data); 10334128Shx147065 if (err != DDI_SUCCESS) { 10344128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "dma alloc tx ring buf[%d] " 10354128Shx147065 "failed\n", i)); 10364128Shx147065 goto fail; 10374128Shx147065 } 10384128Shx147065 10394128Shx147065 data->desc = desc_h + i; 10404128Shx147065 data->paddr_desc = paddr_desc_h + 10414128Shx147065 ((caddr_t)data->desc - (caddr_t)desc_h); 10424128Shx147065 data->cmd = cmd_h + i; 10434128Shx147065 data->paddr_cmd = paddr_cmd_h + 10444128Shx147065 ((caddr_t)data->cmd - (caddr_t)cmd_h); 10454128Shx147065 } 10464128Shx147065 10474128Shx147065 return (err); 10484128Shx147065 10494128Shx147065 fail: 10504128Shx147065 if (ring->data) 10514128Shx147065 kmem_free(ring->data, sizeof (wpi_tx_data_t) * count); 10524128Shx147065 wpi_free_tx_ring(sc, ring); 10534128Shx147065 return (err); 10544128Shx147065 } 10554128Shx147065 10564128Shx147065 static void 10574128Shx147065 wpi_reset_tx_ring(wpi_sc_t *sc, wpi_tx_ring_t *ring) 10584128Shx147065 { 10594128Shx147065 wpi_tx_data_t *data; 10604128Shx147065 int i, ntries; 10614128Shx147065 10624128Shx147065 wpi_mem_lock(sc); 10634128Shx147065 10644128Shx147065 WPI_WRITE(sc, WPI_TX_CONFIG(ring->qid), 0); 10654128Shx147065 for (ntries = 0; ntries < 100; ntries++) { 10664128Shx147065 if (WPI_READ(sc, WPI_TX_STATUS) & WPI_TX_IDLE(ring->qid)) 10674128Shx147065 break; 10684128Shx147065 DELAY(10); 10694128Shx147065 } 10704128Shx147065 #ifdef DEBUG 10714128Shx147065 if (ntries == 100 && wpi_dbg_flags > 0) { 10724128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "timeout resetting Tx ring %d\n", 10734128Shx147065 ring->qid)); 10744128Shx147065 } 10754128Shx147065 #endif 10764128Shx147065 wpi_mem_unlock(sc); 10774128Shx147065 10784128Shx147065 for (i = 0; i < ring->count; i++) { 10794128Shx147065 data = &ring->data[i]; 10804128Shx147065 WPI_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV); 10814128Shx147065 } 10824128Shx147065 10834128Shx147065 ring->queued = 0; 10844128Shx147065 ring->cur = 0; 10854128Shx147065 } 10864128Shx147065 10874128Shx147065 /*ARGSUSED*/ 10884128Shx147065 static void 10894128Shx147065 wpi_free_tx_ring(wpi_sc_t *sc, wpi_tx_ring_t *ring) 10904128Shx147065 { 10914128Shx147065 int i; 10924128Shx147065 10934128Shx147065 if (ring->dma_desc.dma_hdl != NULL) 10944128Shx147065 WPI_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); 10954128Shx147065 wpi_free_dma_mem(&ring->dma_desc); 10964128Shx147065 10974128Shx147065 if (ring->dma_cmd.dma_hdl != NULL) 10984128Shx147065 WPI_DMA_SYNC(ring->dma_cmd, DDI_DMA_SYNC_FORDEV); 10994128Shx147065 wpi_free_dma_mem(&ring->dma_cmd); 11004128Shx147065 11014128Shx147065 if (ring->data != NULL) { 11024128Shx147065 for (i = 0; i < ring->count; i++) { 11034128Shx147065 if (ring->data[i].dma_data.dma_hdl) 11044128Shx147065 WPI_DMA_SYNC(ring->data[i].dma_data, 11054128Shx147065 DDI_DMA_SYNC_FORDEV); 11064128Shx147065 wpi_free_dma_mem(&ring->data[i].dma_data); 11074128Shx147065 } 11084128Shx147065 kmem_free(ring->data, ring->count * sizeof (wpi_tx_data_t)); 11094128Shx147065 } 11104128Shx147065 } 11114128Shx147065 11124128Shx147065 static int 11134128Shx147065 wpi_ring_init(wpi_sc_t *sc) 11144128Shx147065 { 11154128Shx147065 int i, err = DDI_SUCCESS; 11164128Shx147065 11174128Shx147065 for (i = 0; i < 4; i++) { 11184128Shx147065 err = wpi_alloc_tx_ring(sc, &sc->sc_txq[i], WPI_TX_RING_COUNT, 11194128Shx147065 i); 11204128Shx147065 if (err != DDI_SUCCESS) 11214128Shx147065 goto fail; 11224128Shx147065 } 11234128Shx147065 err = wpi_alloc_tx_ring(sc, &sc->sc_cmdq, WPI_CMD_RING_COUNT, 4); 11244128Shx147065 if (err != DDI_SUCCESS) 11254128Shx147065 goto fail; 11264128Shx147065 err = wpi_alloc_tx_ring(sc, &sc->sc_svcq, WPI_SVC_RING_COUNT, 5); 11274128Shx147065 if (err != DDI_SUCCESS) 11284128Shx147065 goto fail; 11294128Shx147065 err = wpi_alloc_rx_ring(sc); 11304128Shx147065 if (err != DDI_SUCCESS) 11314128Shx147065 goto fail; 11324128Shx147065 return (err); 11334128Shx147065 11344128Shx147065 fail: 11354128Shx147065 return (err); 11364128Shx147065 } 11374128Shx147065 11384128Shx147065 static void 11394128Shx147065 wpi_ring_free(wpi_sc_t *sc) 11404128Shx147065 { 11414128Shx147065 int i = 4; 11424128Shx147065 11434128Shx147065 wpi_free_rx_ring(sc); 11444128Shx147065 wpi_free_tx_ring(sc, &sc->sc_svcq); 11454128Shx147065 wpi_free_tx_ring(sc, &sc->sc_cmdq); 11464128Shx147065 while (--i >= 0) { 11474128Shx147065 wpi_free_tx_ring(sc, &sc->sc_txq[i]); 11484128Shx147065 } 11494128Shx147065 } 11504128Shx147065 11514128Shx147065 /* ARGSUSED */ 11524128Shx147065 static ieee80211_node_t * 11534128Shx147065 wpi_node_alloc(ieee80211com_t *ic) 11544128Shx147065 { 11554128Shx147065 wpi_amrr_t *amrr; 11564128Shx147065 11574128Shx147065 amrr = kmem_zalloc(sizeof (wpi_amrr_t), KM_SLEEP); 11584128Shx147065 if (amrr != NULL) 11594128Shx147065 wpi_amrr_init(amrr); 11604128Shx147065 return (&amrr->in); 11614128Shx147065 } 11624128Shx147065 11634128Shx147065 static void 11644128Shx147065 wpi_node_free(ieee80211_node_t *in) 11654128Shx147065 { 11664128Shx147065 ieee80211com_t *ic = in->in_ic; 11674128Shx147065 11684128Shx147065 ic->ic_node_cleanup(in); 11694128Shx147065 kmem_free(in, sizeof (wpi_amrr_t)); 11704128Shx147065 } 11714128Shx147065 11724128Shx147065 /*ARGSUSED*/ 11734128Shx147065 static int 11744128Shx147065 wpi_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) 11754128Shx147065 { 11764128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)ic; 11774128Shx147065 ieee80211_node_t *in = ic->ic_bss; 11784128Shx147065 int i, err = WPI_SUCCESS; 11794128Shx147065 11804128Shx147065 mutex_enter(&sc->sc_glock); 11814128Shx147065 switch (nstate) { 11824128Shx147065 case IEEE80211_S_SCAN: 11834128Shx147065 /* ieee80211_node_table_reset(&ic->ic_scan); */ 11844128Shx147065 ic->ic_flags |= IEEE80211_F_SCAN | IEEE80211_F_ASCAN; 11854128Shx147065 /* make the link LED blink while we're scanning */ 11864128Shx147065 wpi_set_led(sc, WPI_LED_LINK, 20, 2); 11874128Shx147065 11884128Shx147065 if ((err = wpi_scan(sc)) != 0) { 11894128Shx147065 WPI_DBG((WPI_DEBUG_80211, "could not initiate scan\n")); 11904128Shx147065 ic->ic_flags &= ~(IEEE80211_F_SCAN | 11914128Shx147065 IEEE80211_F_ASCAN); 11924128Shx147065 mutex_exit(&sc->sc_glock); 11934128Shx147065 return (err); 11944128Shx147065 } 11954128Shx147065 ic->ic_state = nstate; 11964128Shx147065 sc->sc_clk = 0; 11974128Shx147065 11984128Shx147065 mutex_exit(&sc->sc_glock); 11994128Shx147065 return (WPI_SUCCESS); 12004128Shx147065 12014128Shx147065 case IEEE80211_S_AUTH: 12024128Shx147065 /* reset state to handle reassociations correctly */ 12034128Shx147065 sc->sc_config.state = 0; 12044128Shx147065 sc->sc_config.filter &= ~LE_32(WPI_FILTER_BSS); 12054128Shx147065 12064128Shx147065 if ((err = wpi_auth(sc)) != 0) { 12074128Shx147065 WPI_DBG((WPI_DEBUG_80211, 12084128Shx147065 "could not send authentication request\n")); 12094128Shx147065 mutex_exit(&sc->sc_glock); 12104128Shx147065 return (err); 12114128Shx147065 } 12124128Shx147065 break; 12134128Shx147065 12144128Shx147065 case IEEE80211_S_RUN: 12154128Shx147065 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 12164128Shx147065 /* link LED blinks while monitoring */ 12174128Shx147065 wpi_set_led(sc, WPI_LED_LINK, 5, 5); 12184128Shx147065 break; 12194128Shx147065 } 12204128Shx147065 12214128Shx147065 if (ic->ic_opmode != IEEE80211_M_STA) { 12224128Shx147065 (void) wpi_auth(sc); 12234128Shx147065 /* need setup beacon here */ 12244128Shx147065 } 12254128Shx147065 WPI_DBG((WPI_DEBUG_80211, "wpi: associated.")); 12264128Shx147065 12274128Shx147065 /* update adapter's configuration */ 12284128Shx147065 sc->sc_config.state = LE_16(WPI_CONFIG_ASSOCIATED); 12294128Shx147065 /* short preamble/slot time are negotiated when associating */ 12304128Shx147065 sc->sc_config.flags &= ~LE_32(WPI_CONFIG_SHPREAMBLE | 12314128Shx147065 WPI_CONFIG_SHSLOT); 12324128Shx147065 if (ic->ic_flags & IEEE80211_F_SHSLOT) 12334128Shx147065 sc->sc_config.flags |= LE_32(WPI_CONFIG_SHSLOT); 12344128Shx147065 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 12354128Shx147065 sc->sc_config.flags |= LE_32(WPI_CONFIG_SHPREAMBLE); 12364128Shx147065 sc->sc_config.filter |= LE_32(WPI_FILTER_BSS); 12374128Shx147065 if (ic->ic_opmode != IEEE80211_M_STA) 12384128Shx147065 sc->sc_config.filter |= LE_32(WPI_FILTER_BEACON); 12394128Shx147065 12404128Shx147065 WPI_DBG((WPI_DEBUG_80211, "config chan %d flags %x\n", 12414128Shx147065 sc->sc_config.chan, sc->sc_config.flags)); 12424128Shx147065 err = wpi_cmd(sc, WPI_CMD_CONFIGURE, &sc->sc_config, 12434128Shx147065 sizeof (wpi_config_t), 1); 12444128Shx147065 if (err != WPI_SUCCESS) { 12454128Shx147065 WPI_DBG((WPI_DEBUG_80211, 12464128Shx147065 "could not update configuration\n")); 12474128Shx147065 mutex_exit(&sc->sc_glock); 12484128Shx147065 return (err); 12494128Shx147065 } 12504128Shx147065 12514128Shx147065 /* start automatic rate control */ 12524128Shx147065 mutex_enter(&sc->sc_mt_lock); 12534128Shx147065 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 12544128Shx147065 sc->sc_flags |= WPI_F_RATE_AUTO_CTL; 12554128Shx147065 /* set rate to some reasonable initial value */ 1256*4499Shx147065 i = in->in_rates.ir_nrates - 1; 1257*4499Shx147065 while (i > 0 && IEEE80211_RATE(i) > 72) 1258*4499Shx147065 i--; 12594128Shx147065 in->in_txrate = i; 12604128Shx147065 } else { 12614128Shx147065 sc->sc_flags &= ~WPI_F_RATE_AUTO_CTL; 12624128Shx147065 } 12634128Shx147065 mutex_exit(&sc->sc_mt_lock); 12644128Shx147065 12654128Shx147065 /* link LED always on while associated */ 12664128Shx147065 wpi_set_led(sc, WPI_LED_LINK, 0, 1); 12674128Shx147065 break; 12684128Shx147065 12694128Shx147065 case IEEE80211_S_INIT: 12704128Shx147065 case IEEE80211_S_ASSOC: 12714128Shx147065 break; 12724128Shx147065 } 12734128Shx147065 12744128Shx147065 mutex_exit(&sc->sc_glock); 12754128Shx147065 return (sc->sc_newstate(ic, nstate, arg)); 12764128Shx147065 } 12774128Shx147065 12784128Shx147065 /* 12794128Shx147065 * Grab exclusive access to NIC memory. 12804128Shx147065 */ 12814128Shx147065 static void 12824128Shx147065 wpi_mem_lock(wpi_sc_t *sc) 12834128Shx147065 { 12844128Shx147065 uint32_t tmp; 12854128Shx147065 int ntries; 12864128Shx147065 12874128Shx147065 tmp = WPI_READ(sc, WPI_GPIO_CTL); 12884128Shx147065 WPI_WRITE(sc, WPI_GPIO_CTL, tmp | WPI_GPIO_MAC); 12894128Shx147065 12904128Shx147065 /* spin until we actually get the lock */ 12914128Shx147065 for (ntries = 0; ntries < 1000; ntries++) { 12924128Shx147065 if ((WPI_READ(sc, WPI_GPIO_CTL) & 12934128Shx147065 (WPI_GPIO_CLOCK | WPI_GPIO_SLEEP)) == WPI_GPIO_CLOCK) 12944128Shx147065 break; 12954128Shx147065 DELAY(10); 12964128Shx147065 } 12974128Shx147065 if (ntries == 1000) 12984128Shx147065 WPI_DBG((WPI_DEBUG_PIO, "could not lock memory\n")); 12994128Shx147065 } 13004128Shx147065 13014128Shx147065 /* 13024128Shx147065 * Release lock on NIC memory. 13034128Shx147065 */ 13044128Shx147065 static void 13054128Shx147065 wpi_mem_unlock(wpi_sc_t *sc) 13064128Shx147065 { 13074128Shx147065 uint32_t tmp = WPI_READ(sc, WPI_GPIO_CTL); 13084128Shx147065 WPI_WRITE(sc, WPI_GPIO_CTL, tmp & ~WPI_GPIO_MAC); 13094128Shx147065 } 13104128Shx147065 13114128Shx147065 static uint32_t 13124128Shx147065 wpi_mem_read(wpi_sc_t *sc, uint16_t addr) 13134128Shx147065 { 13144128Shx147065 WPI_WRITE(sc, WPI_READ_MEM_ADDR, WPI_MEM_4 | addr); 13154128Shx147065 return (WPI_READ(sc, WPI_READ_MEM_DATA)); 13164128Shx147065 } 13174128Shx147065 13184128Shx147065 static void 13194128Shx147065 wpi_mem_write(wpi_sc_t *sc, uint16_t addr, uint32_t data) 13204128Shx147065 { 13214128Shx147065 WPI_WRITE(sc, WPI_WRITE_MEM_ADDR, WPI_MEM_4 | addr); 13224128Shx147065 WPI_WRITE(sc, WPI_WRITE_MEM_DATA, data); 13234128Shx147065 } 13244128Shx147065 13254128Shx147065 static void 13264128Shx147065 wpi_mem_write_region_4(wpi_sc_t *sc, uint16_t addr, 13274128Shx147065 const uint32_t *data, int wlen) 13284128Shx147065 { 13294128Shx147065 for (; wlen > 0; wlen--, data++, addr += 4) 13304128Shx147065 wpi_mem_write(sc, addr, *data); 13314128Shx147065 } 13324128Shx147065 13334128Shx147065 /* 13344128Shx147065 * Read 16 bits from the EEPROM. We access EEPROM through the MAC instead of 13354128Shx147065 * using the traditional bit-bang method. 13364128Shx147065 */ 13374128Shx147065 static uint16_t 13384128Shx147065 wpi_read_prom_word(wpi_sc_t *sc, uint32_t addr) 13394128Shx147065 { 13404128Shx147065 uint32_t val; 13414128Shx147065 int ntries; 13424128Shx147065 13434128Shx147065 WPI_WRITE(sc, WPI_EEPROM_CTL, addr << 2); 13444128Shx147065 13454128Shx147065 wpi_mem_lock(sc); 13464128Shx147065 for (ntries = 0; ntries < 10; ntries++) { 13474128Shx147065 if ((val = WPI_READ(sc, WPI_EEPROM_CTL)) & WPI_EEPROM_READY) 13484128Shx147065 break; 13494128Shx147065 DELAY(10); 13504128Shx147065 } 13514128Shx147065 wpi_mem_unlock(sc); 13524128Shx147065 13534128Shx147065 if (ntries == 10) { 13544128Shx147065 WPI_DBG((WPI_DEBUG_PIO, "could not read EEPROM\n")); 13554128Shx147065 return (0xdead); 13564128Shx147065 } 13574128Shx147065 return (val >> 16); 13584128Shx147065 } 13594128Shx147065 13604128Shx147065 /* 13614128Shx147065 * The firmware boot code is small and is intended to be copied directly into 13624128Shx147065 * the NIC internal memory. 13634128Shx147065 */ 13644128Shx147065 static int 13654128Shx147065 wpi_load_microcode(wpi_sc_t *sc) 13664128Shx147065 { 13674128Shx147065 const char *ucode; 13684128Shx147065 int size; 13694128Shx147065 13704128Shx147065 ucode = sc->sc_boot; 13714128Shx147065 size = LE_32(sc->sc_hdr->bootsz); 13724128Shx147065 /* check that microcode size is a multiple of 4 */ 13734128Shx147065 if (size & 3) 13744128Shx147065 return (EINVAL); 13754128Shx147065 13764128Shx147065 size /= sizeof (uint32_t); 13774128Shx147065 13784128Shx147065 wpi_mem_lock(sc); 13794128Shx147065 13804128Shx147065 /* copy microcode image into NIC memory */ 13814128Shx147065 wpi_mem_write_region_4(sc, WPI_MEM_UCODE_BASE, (const uint32_t *)ucode, 13824128Shx147065 size); 13834128Shx147065 13844128Shx147065 wpi_mem_write(sc, WPI_MEM_UCODE_SRC, 0); 13854128Shx147065 wpi_mem_write(sc, WPI_MEM_UCODE_DST, WPI_FW_TEXT); 13864128Shx147065 wpi_mem_write(sc, WPI_MEM_UCODE_SIZE, size); 13874128Shx147065 13884128Shx147065 /* run microcode */ 13894128Shx147065 wpi_mem_write(sc, WPI_MEM_UCODE_CTL, WPI_UC_RUN); 13904128Shx147065 13914128Shx147065 wpi_mem_unlock(sc); 13924128Shx147065 13934128Shx147065 return (WPI_SUCCESS); 13944128Shx147065 } 13954128Shx147065 13964128Shx147065 /* 13974128Shx147065 * The firmware text and data segments are transferred to the NIC using DMA. 13984128Shx147065 * The driver just copies the firmware into DMA-safe memory and tells the NIC 13994128Shx147065 * where to find it. Once the NIC has copied the firmware into its internal 14004128Shx147065 * memory, we can free our local copy in the driver. 14014128Shx147065 */ 14024128Shx147065 static int 14034128Shx147065 wpi_load_firmware(wpi_sc_t *sc, uint32_t target) 14044128Shx147065 { 14054128Shx147065 const char *fw; 14064128Shx147065 int size; 14074128Shx147065 wpi_dma_t *dma_p; 14084128Shx147065 ddi_dma_cookie_t *cookie; 14094128Shx147065 wpi_tx_desc_t desc; 14104128Shx147065 int i, ntries, err = WPI_SUCCESS; 14114128Shx147065 14124128Shx147065 /* only text and data here */ 14134128Shx147065 if (target == WPI_FW_TEXT) { 14144128Shx147065 fw = sc->sc_text; 14154128Shx147065 size = LE_32(sc->sc_hdr->textsz); 14164128Shx147065 dma_p = &sc->sc_dma_fw_text; 14174128Shx147065 cookie = sc->sc_fw_text_cookie; 14184128Shx147065 } else { 14194128Shx147065 fw = sc->sc_data; 14204128Shx147065 size = LE_32(sc->sc_hdr->datasz); 14214128Shx147065 dma_p = &sc->sc_dma_fw_data; 14224128Shx147065 cookie = sc->sc_fw_data_cookie; 14234128Shx147065 } 14244128Shx147065 14254128Shx147065 /* copy firmware image to DMA-safe memory */ 14264128Shx147065 (void) memcpy(dma_p->mem_va, fw, size); 14274128Shx147065 14284128Shx147065 /* make sure the adapter will get up-to-date values */ 14294128Shx147065 (void) ddi_dma_sync(dma_p->dma_hdl, 0, size, DDI_DMA_SYNC_FORDEV); 14304128Shx147065 14314128Shx147065 (void) memset(&desc, 0, sizeof (desc)); 14324128Shx147065 desc.flags = LE_32(WPI_PAD32(size) << 28 | dma_p->ncookies << 24); 14334128Shx147065 for (i = 0; i < dma_p->ncookies; i++) { 14344128Shx147065 WPI_DBG((WPI_DEBUG_DMA, "cookie%d addr:%x size:%x\n", 14354128Shx147065 i, cookie[i].dmac_address, cookie[i].dmac_size)); 14364128Shx147065 desc.segs[i].addr = cookie[i].dmac_address; 14374128Shx147065 desc.segs[i].len = (uint32_t)cookie[i].dmac_size; 14384128Shx147065 } 14394128Shx147065 14404128Shx147065 wpi_mem_lock(sc); 14414128Shx147065 14424128Shx147065 /* tell adapter where to copy image in its internal memory */ 14434128Shx147065 WPI_WRITE(sc, WPI_FW_TARGET, target); 14444128Shx147065 14454128Shx147065 WPI_WRITE(sc, WPI_TX_CONFIG(6), 0); 14464128Shx147065 14474128Shx147065 /* copy firmware descriptor into NIC memory */ 14484128Shx147065 WPI_WRITE_REGION_4(sc, WPI_TX_DESC(6), (uint32_t *)&desc, 14494128Shx147065 sizeof desc / sizeof (uint32_t)); 14504128Shx147065 14514128Shx147065 WPI_WRITE(sc, WPI_TX_CREDIT(6), 0xfffff); 14524128Shx147065 WPI_WRITE(sc, WPI_TX_STATE(6), 0x4001); 14534128Shx147065 WPI_WRITE(sc, WPI_TX_CONFIG(6), 0x80000001); 14544128Shx147065 14554128Shx147065 /* wait while the adapter is busy copying the firmware */ 14564128Shx147065 for (ntries = 0; ntries < 100; ntries++) { 14574128Shx147065 if (WPI_READ(sc, WPI_TX_STATUS) & WPI_TX_IDLE(6)) 14584128Shx147065 break; 14594128Shx147065 DELAY(1000); 14604128Shx147065 } 14614128Shx147065 if (ntries == 100) { 14624128Shx147065 WPI_DBG((WPI_DEBUG_FW, "timeout transferring firmware\n")); 14634128Shx147065 err = ETIMEDOUT; 14644128Shx147065 } 14654128Shx147065 14664128Shx147065 WPI_WRITE(sc, WPI_TX_CREDIT(6), 0); 14674128Shx147065 14684128Shx147065 wpi_mem_unlock(sc); 14694128Shx147065 14704128Shx147065 return (err); 14714128Shx147065 } 14724128Shx147065 14734128Shx147065 /*ARGSUSED*/ 14744128Shx147065 static void 14754128Shx147065 wpi_rx_intr(wpi_sc_t *sc, wpi_rx_desc_t *desc, wpi_rx_data_t *data) 14764128Shx147065 { 14774128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 14784128Shx147065 wpi_rx_ring_t *ring = &sc->sc_rxq; 14794128Shx147065 wpi_rx_stat_t *stat; 14804128Shx147065 wpi_rx_head_t *head; 14814128Shx147065 wpi_rx_tail_t *tail; 14824128Shx147065 ieee80211_node_t *in; 14834128Shx147065 struct ieee80211_frame *wh; 14844128Shx147065 mblk_t *mp; 14854128Shx147065 uint16_t len; 14864128Shx147065 14874128Shx147065 stat = (wpi_rx_stat_t *)(desc + 1); 14884128Shx147065 14894128Shx147065 if (stat->len > WPI_STAT_MAXLEN) { 14904128Shx147065 WPI_DBG((WPI_DEBUG_RX, "invalid rx statistic header\n")); 14914128Shx147065 return; 14924128Shx147065 } 14934128Shx147065 14944128Shx147065 head = (wpi_rx_head_t *)((caddr_t)(stat + 1) + stat->len); 14954128Shx147065 tail = (wpi_rx_tail_t *)((caddr_t)(head + 1) + LE_16(head->len)); 14964128Shx147065 14974128Shx147065 len = LE_16(head->len); 14984128Shx147065 14994128Shx147065 WPI_DBG((WPI_DEBUG_RX, "rx intr: idx=%d len=%d stat len=%d rssi=%d " 15004128Shx147065 "rate=%x chan=%d tstamp=%llu", ring->cur, LE_32(desc->len), 15014128Shx147065 len, (int8_t)stat->rssi, head->rate, head->chan, 15024128Shx147065 LE_64(tail->tstamp))); 15034128Shx147065 15044128Shx147065 if ((len < 20) || (len > sc->sc_dmabuf_sz)) { 15054128Shx147065 sc->sc_rx_err++; 15064128Shx147065 return; 15074128Shx147065 } 15084128Shx147065 15094128Shx147065 /* 15104128Shx147065 * Discard Rx frames with bad CRC early 15114128Shx147065 */ 15124128Shx147065 if ((LE_32(tail->flags) & WPI_RX_NOERROR) != WPI_RX_NOERROR) { 15134128Shx147065 WPI_DBG((WPI_DEBUG_RX, "rx tail flags error %x\n", 15144128Shx147065 LE_32(tail->flags))); 15154128Shx147065 sc->sc_rx_err++; 15164128Shx147065 return; 15174128Shx147065 } 15184128Shx147065 15194128Shx147065 /* update Rx descriptor */ 15204128Shx147065 /* ring->desc[ring->cur] = LE_32(data->dma_data.cookie.dmac_address); */ 15214128Shx147065 15224128Shx147065 #ifdef WPI_BPF 15234128Shx147065 #ifndef WPI_CURRENT 15244128Shx147065 if (sc->sc_drvbpf != NULL) { 15254128Shx147065 #else 15264128Shx147065 if (bpf_peers_present(sc->sc_drvbpf)) { 15274128Shx147065 #endif 15284128Shx147065 struct wpi_rx_radiotap_header *tap = &sc->sc_rxtap; 15294128Shx147065 15304128Shx147065 tap->wr_flags = 0; 15314128Shx147065 tap->wr_rate = head->rate; 15324128Shx147065 tap->wr_chan_freq = 15334128Shx147065 LE_16(ic->ic_channels[head->chan].ic_freq); 15344128Shx147065 tap->wr_chan_flags = 15354128Shx147065 LE_16(ic->ic_channels[head->chan].ic_flags); 15364128Shx147065 tap->wr_dbm_antsignal = (int8_t)(stat->rssi - WPI_RSSI_OFFSET); 15374128Shx147065 tap->wr_dbm_antnoise = (int8_t)LE_16(stat->noise); 15384128Shx147065 tap->wr_tsft = tail->tstamp; 15394128Shx147065 tap->wr_antenna = (LE_16(head->flags) >> 4) & 0xf; 15404128Shx147065 switch (head->rate) { 15414128Shx147065 /* CCK rates */ 15424128Shx147065 case 10: tap->wr_rate = 2; break; 15434128Shx147065 case 20: tap->wr_rate = 4; break; 15444128Shx147065 case 55: tap->wr_rate = 11; break; 15454128Shx147065 case 110: tap->wr_rate = 22; break; 15464128Shx147065 /* OFDM rates */ 15474128Shx147065 case 0xd: tap->wr_rate = 12; break; 15484128Shx147065 case 0xf: tap->wr_rate = 18; break; 15494128Shx147065 case 0x5: tap->wr_rate = 24; break; 15504128Shx147065 case 0x7: tap->wr_rate = 36; break; 15514128Shx147065 case 0x9: tap->wr_rate = 48; break; 15524128Shx147065 case 0xb: tap->wr_rate = 72; break; 15534128Shx147065 case 0x1: tap->wr_rate = 96; break; 15544128Shx147065 case 0x3: tap->wr_rate = 108; break; 15554128Shx147065 /* unknown rate: should not happen */ 15564128Shx147065 default: tap->wr_rate = 0; 15574128Shx147065 } 15584128Shx147065 if (LE_16(head->flags) & 0x4) 15594128Shx147065 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 15604128Shx147065 15614128Shx147065 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 15624128Shx147065 } 15634128Shx147065 #endif 15644128Shx147065 /* grab a reference to the source node */ 15654128Shx147065 wh = (struct ieee80211_frame *)(head + 1); 15664128Shx147065 15674128Shx147065 #ifdef DEBUG 15684128Shx147065 if (wpi_dbg_flags & WPI_DEBUG_RX) 15694128Shx147065 ieee80211_dump_pkt((uint8_t *)wh, len, 0, 0); 15704128Shx147065 #endif 15714128Shx147065 15724128Shx147065 in = ieee80211_find_rxnode(ic, wh); 15734128Shx147065 mp = allocb(len, BPRI_MED); 15744128Shx147065 if (mp) { 15754128Shx147065 (void) memcpy(mp->b_wptr, wh, len); 15764128Shx147065 mp->b_wptr += len; 15774128Shx147065 15784128Shx147065 /* send the frame to the 802.11 layer */ 15794128Shx147065 (void) ieee80211_input(ic, mp, in, stat->rssi, 0); 15804128Shx147065 } else { 15814128Shx147065 sc->sc_rx_nobuf++; 15824128Shx147065 WPI_DBG((WPI_DEBUG_RX, 15834128Shx147065 "wpi_rx_intr(): alloc rx buf failed\n")); 15844128Shx147065 } 15854128Shx147065 /* release node reference */ 15864128Shx147065 ieee80211_free_node(in); 15874128Shx147065 } 15884128Shx147065 15894128Shx147065 /*ARGSUSED*/ 15904128Shx147065 static void 15914128Shx147065 wpi_tx_intr(wpi_sc_t *sc, wpi_rx_desc_t *desc, wpi_rx_data_t *data) 15924128Shx147065 { 15934128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 15944128Shx147065 wpi_tx_ring_t *ring = &sc->sc_txq[desc->qid & 0x3]; 15954128Shx147065 /* wpi_tx_data_t *txdata = &ring->data[desc->idx]; */ 15964128Shx147065 wpi_tx_stat_t *stat = (wpi_tx_stat_t *)(desc + 1); 15974128Shx147065 wpi_amrr_t *amrr = (wpi_amrr_t *)ic->ic_bss; 15984128Shx147065 15994128Shx147065 WPI_DBG((WPI_DEBUG_TX, "tx done: qid=%d idx=%d retries=%d nkill=%d " 16004128Shx147065 "rate=%x duration=%d status=%x\n", 16014128Shx147065 desc->qid, desc->idx, stat->ntries, stat->nkill, stat->rate, 16024128Shx147065 LE_32(stat->duration), LE_32(stat->status))); 16034128Shx147065 16044128Shx147065 amrr->txcnt++; 16054128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, "tx: %d cnt\n", amrr->txcnt)); 16064128Shx147065 if (stat->ntries > 0) { 16074128Shx147065 amrr->retrycnt++; 16084128Shx147065 sc->sc_tx_retries++; 16094128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, "tx: %d retries\n", 16104128Shx147065 amrr->retrycnt)); 16114128Shx147065 } 16124128Shx147065 16134128Shx147065 sc->sc_tx_timer = 0; 16144128Shx147065 16154128Shx147065 mutex_enter(&sc->sc_tx_lock); 16164128Shx147065 ring->queued--; 16174128Shx147065 if (ring->queued < 0) 16184128Shx147065 ring->queued = 0; 16194128Shx147065 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count << 3))) { 16204128Shx147065 sc->sc_need_reschedule = 0; 16214128Shx147065 mutex_exit(&sc->sc_tx_lock); 16224128Shx147065 mac_tx_update(ic->ic_mach); 16234128Shx147065 mutex_enter(&sc->sc_tx_lock); 16244128Shx147065 } 16254128Shx147065 mutex_exit(&sc->sc_tx_lock); 16264128Shx147065 } 16274128Shx147065 16284128Shx147065 static void 16294128Shx147065 wpi_cmd_intr(wpi_sc_t *sc, wpi_rx_desc_t *desc) 16304128Shx147065 { 16314128Shx147065 if ((desc->qid & 7) != 4) { 16324128Shx147065 return; /* not a command ack */ 16334128Shx147065 } 16344128Shx147065 mutex_enter(&sc->sc_glock); 16354128Shx147065 sc->sc_flags |= WPI_F_CMD_DONE; 16364128Shx147065 cv_signal(&sc->sc_cmd_cv); 16374128Shx147065 mutex_exit(&sc->sc_glock); 16384128Shx147065 } 16394128Shx147065 16404128Shx147065 static uint_t 16414128Shx147065 wpi_notif_softintr(caddr_t arg) 16424128Shx147065 { 16434128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 16444128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 16454128Shx147065 wpi_rx_desc_t *desc; 16464128Shx147065 wpi_rx_data_t *data; 16474128Shx147065 uint32_t hw; 16484128Shx147065 16494128Shx147065 mutex_enter(&sc->sc_glock); 16504128Shx147065 if (sc->sc_notif_softint_pending != 1) { 16514128Shx147065 mutex_exit(&sc->sc_glock); 16524128Shx147065 return (DDI_INTR_UNCLAIMED); 16534128Shx147065 } 16544128Shx147065 mutex_exit(&sc->sc_glock); 16554128Shx147065 16564128Shx147065 hw = LE_32(sc->sc_shared->next); 16574128Shx147065 16584128Shx147065 while (sc->sc_rxq.cur != hw) { 16594128Shx147065 data = &sc->sc_rxq.data[sc->sc_rxq.cur]; 16604128Shx147065 desc = (wpi_rx_desc_t *)data->dma_data.mem_va; 16614128Shx147065 16624128Shx147065 WPI_DBG((WPI_DEBUG_INTR, "rx notification hw = %d cur = %d " 16634128Shx147065 "qid=%x idx=%d flags=%x type=%d len=%d\n", 16644128Shx147065 hw, sc->sc_rxq.cur, desc->qid, desc->idx, desc->flags, 16654128Shx147065 desc->type, LE_32(desc->len))); 16664128Shx147065 16674128Shx147065 if (!(desc->qid & 0x80)) /* reply to a command */ 16684128Shx147065 wpi_cmd_intr(sc, desc); 16694128Shx147065 16704128Shx147065 switch (desc->type) { 16714128Shx147065 case WPI_RX_DONE: 16724128Shx147065 /* a 802.11 frame was received */ 16734128Shx147065 wpi_rx_intr(sc, desc, data); 16744128Shx147065 break; 16754128Shx147065 16764128Shx147065 case WPI_TX_DONE: 16774128Shx147065 /* a 802.11 frame has been transmitted */ 16784128Shx147065 wpi_tx_intr(sc, desc, data); 16794128Shx147065 break; 16804128Shx147065 16814128Shx147065 case WPI_UC_READY: 16824128Shx147065 { 16834128Shx147065 wpi_ucode_info_t *uc = 16844128Shx147065 (wpi_ucode_info_t *)(desc + 1); 16854128Shx147065 16864128Shx147065 /* the microcontroller is ready */ 16874128Shx147065 WPI_DBG((WPI_DEBUG_FW, 16884128Shx147065 "microcode alive notification version %x " 16894128Shx147065 "alive %x\n", LE_32(uc->version), 16904128Shx147065 LE_32(uc->valid))); 16914128Shx147065 16924128Shx147065 if (LE_32(uc->valid) != 1) { 16934128Shx147065 WPI_DBG((WPI_DEBUG_FW, 16944128Shx147065 "microcontroller initialization failed\n")); 16954128Shx147065 } 16964128Shx147065 break; 16974128Shx147065 } 16984128Shx147065 case WPI_STATE_CHANGED: 16994128Shx147065 { 17004128Shx147065 uint32_t *status = (uint32_t *)(desc + 1); 17014128Shx147065 17024128Shx147065 /* enabled/disabled notification */ 17034128Shx147065 WPI_DBG((WPI_DEBUG_RADIO, "state changed to %x\n", 17044128Shx147065 LE_32(*status))); 17054128Shx147065 17064128Shx147065 if (LE_32(*status) & 1) { 17074128Shx147065 /* the radio button has to be pushed */ 17084128Shx147065 cmn_err(CE_NOTE, 17094128Shx147065 "wpi: Radio transmitter is off\n"); 17104128Shx147065 } 17114128Shx147065 break; 17124128Shx147065 } 17134128Shx147065 case WPI_START_SCAN: 17144128Shx147065 { 17154128Shx147065 wpi_start_scan_t *scan = 17164128Shx147065 (wpi_start_scan_t *)(desc + 1); 17174128Shx147065 17184128Shx147065 WPI_DBG((WPI_DEBUG_SCAN, 17194128Shx147065 "scanning channel %d status %x\n", 17204128Shx147065 scan->chan, LE_32(scan->status))); 17214128Shx147065 17224128Shx147065 /* fix current channel */ 17234128Shx147065 ic->ic_curchan = &ic->ic_sup_channels[scan->chan]; 17244128Shx147065 break; 17254128Shx147065 } 17264128Shx147065 case WPI_STOP_SCAN: 17274128Shx147065 WPI_DBG((WPI_DEBUG_SCAN, "scan finished\n")); 17284128Shx147065 ieee80211_end_scan(ic); 17294128Shx147065 break; 17304128Shx147065 } 17314128Shx147065 17324128Shx147065 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % WPI_RX_RING_COUNT; 17334128Shx147065 } 17344128Shx147065 17354128Shx147065 /* tell the firmware what we have processed */ 17364128Shx147065 hw = (hw == 0) ? WPI_RX_RING_COUNT - 1 : hw - 1; 17374128Shx147065 WPI_WRITE(sc, WPI_RX_WIDX, hw & (~7)); 17384128Shx147065 mutex_enter(&sc->sc_glock); 17394128Shx147065 sc->sc_notif_softint_pending = 0; 17404128Shx147065 mutex_exit(&sc->sc_glock); 17414128Shx147065 17424128Shx147065 return (DDI_INTR_CLAIMED); 17434128Shx147065 } 17444128Shx147065 17454128Shx147065 static uint_t 17464128Shx147065 wpi_intr(caddr_t arg) 17474128Shx147065 { 17484128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 17494128Shx147065 uint32_t r; 17504128Shx147065 17514128Shx147065 mutex_enter(&sc->sc_glock); 17524128Shx147065 r = WPI_READ(sc, WPI_INTR); 17534128Shx147065 if (r == 0 || r == 0xffffffff) { 17544128Shx147065 mutex_exit(&sc->sc_glock); 17554128Shx147065 return (DDI_INTR_UNCLAIMED); 17564128Shx147065 } 17574128Shx147065 17584128Shx147065 WPI_DBG((WPI_DEBUG_INTR, "interrupt reg %x\n", r)); 17594128Shx147065 17604128Shx147065 /* disable interrupts */ 17614128Shx147065 WPI_WRITE(sc, WPI_MASK, 0); 17624128Shx147065 /* ack interrupts */ 17634128Shx147065 WPI_WRITE(sc, WPI_INTR, r); 17644128Shx147065 17654128Shx147065 if (sc->sc_notif_softint_id == NULL) { 17664128Shx147065 mutex_exit(&sc->sc_glock); 17674128Shx147065 return (DDI_INTR_CLAIMED); 17684128Shx147065 } 17694128Shx147065 17704128Shx147065 if (r & (WPI_SW_ERROR | WPI_HW_ERROR)) { 17714128Shx147065 WPI_DBG((WPI_DEBUG_FW, "fatal firmware error\n")); 17724128Shx147065 mutex_exit(&sc->sc_glock); 17734128Shx147065 wpi_stop(sc); 17744128Shx147065 sc->sc_ostate = sc->sc_ic.ic_state; 17754128Shx147065 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1); 17764128Shx147065 sc->sc_flags |= WPI_F_HW_ERR_RECOVER; 17774128Shx147065 return (DDI_INTR_CLAIMED); 17784128Shx147065 } 17794128Shx147065 17804128Shx147065 if (r & WPI_RX_INTR) { 17814128Shx147065 sc->sc_notif_softint_pending = 1; 17824128Shx147065 ddi_trigger_softintr(sc->sc_notif_softint_id); 17834128Shx147065 } 17844128Shx147065 17854128Shx147065 if (r & WPI_ALIVE_INTR) { /* firmware initialized */ 17864128Shx147065 sc->sc_flags |= WPI_F_FW_INIT; 17874128Shx147065 cv_signal(&sc->sc_fw_cv); 17884128Shx147065 } 17894128Shx147065 17904128Shx147065 /* re-enable interrupts */ 17914128Shx147065 WPI_WRITE(sc, WPI_MASK, WPI_INTR_MASK); 17924128Shx147065 mutex_exit(&sc->sc_glock); 17934128Shx147065 17944128Shx147065 return (DDI_INTR_CLAIMED); 17954128Shx147065 } 17964128Shx147065 17974128Shx147065 static uint8_t 17984128Shx147065 wpi_plcp_signal(int rate) 17994128Shx147065 { 18004128Shx147065 switch (rate) { 18014128Shx147065 /* CCK rates (returned values are device-dependent) */ 18024128Shx147065 case 2: return (10); 18034128Shx147065 case 4: return (20); 18044128Shx147065 case 11: return (55); 18054128Shx147065 case 22: return (110); 18064128Shx147065 18074128Shx147065 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 18084128Shx147065 /* R1-R4 (ral/ural is R4-R1) */ 18094128Shx147065 case 12: return (0xd); 18104128Shx147065 case 18: return (0xf); 18114128Shx147065 case 24: return (0x5); 18124128Shx147065 case 36: return (0x7); 18134128Shx147065 case 48: return (0x9); 18144128Shx147065 case 72: return (0xb); 18154128Shx147065 case 96: return (0x1); 18164128Shx147065 case 108: return (0x3); 18174128Shx147065 18184128Shx147065 /* unsupported rates (should not get there) */ 18194128Shx147065 default: return (0); 18204128Shx147065 } 18214128Shx147065 } 18224128Shx147065 18234128Shx147065 static mblk_t * 18244128Shx147065 wpi_m_tx(void *arg, mblk_t *mp) 18254128Shx147065 { 18264128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 18274128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 18284128Shx147065 mblk_t *next; 18294128Shx147065 18304128Shx147065 if (ic->ic_state != IEEE80211_S_RUN) { 18314128Shx147065 freemsgchain(mp); 18324128Shx147065 return (NULL); 18334128Shx147065 } 18344128Shx147065 18354128Shx147065 while (mp != NULL) { 18364128Shx147065 next = mp->b_next; 18374128Shx147065 mp->b_next = NULL; 18384128Shx147065 if (wpi_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != 0) { 18394128Shx147065 mp->b_next = next; 18404128Shx147065 break; 18414128Shx147065 } 18424128Shx147065 mp = next; 18434128Shx147065 } 18444128Shx147065 return (mp); 18454128Shx147065 } 18464128Shx147065 18474128Shx147065 /* ARGSUSED */ 18484128Shx147065 static int 18494128Shx147065 wpi_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 18504128Shx147065 { 18514128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)ic; 18524128Shx147065 wpi_tx_ring_t *ring; 18534128Shx147065 wpi_tx_desc_t *desc; 18544128Shx147065 wpi_tx_data_t *data; 18554128Shx147065 wpi_tx_cmd_t *cmd; 18564128Shx147065 wpi_cmd_data_t *tx; 18574128Shx147065 ieee80211_node_t *in; 18584128Shx147065 struct ieee80211_frame *wh; 18594128Shx147065 struct ieee80211_key *k; 18604128Shx147065 mblk_t *m, *m0; 18614128Shx147065 int rate, hdrlen, len, mblen, off, err = WPI_SUCCESS; 18624128Shx147065 18634128Shx147065 ring = ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) ? 18644128Shx147065 (&sc->sc_txq[0]) : (&sc->sc_txq[1]); 18654128Shx147065 data = &ring->data[ring->cur]; 18664128Shx147065 desc = data->desc; 18674128Shx147065 cmd = data->cmd; 18684128Shx147065 bzero(desc, sizeof (*desc)); 18694128Shx147065 bzero(cmd, sizeof (*cmd)); 18704128Shx147065 18714128Shx147065 mutex_enter(&sc->sc_tx_lock); 18724128Shx147065 if (ring->queued > ring->count - 64) { 18734128Shx147065 WPI_DBG((WPI_DEBUG_TX, "wpi_send(): no txbuf\n")); 18744128Shx147065 sc->sc_need_reschedule = 1; 18754128Shx147065 mutex_exit(&sc->sc_tx_lock); 18764128Shx147065 if ((type & IEEE80211_FC0_TYPE_MASK) != 18774128Shx147065 IEEE80211_FC0_TYPE_DATA) { 18784128Shx147065 freemsg(mp); 18794128Shx147065 } 18804128Shx147065 sc->sc_tx_nobuf++; 18814128Shx147065 err = WPI_FAIL; 18824128Shx147065 goto exit; 18834128Shx147065 } 18844128Shx147065 mutex_exit(&sc->sc_tx_lock); 18854128Shx147065 18864128Shx147065 hdrlen = sizeof (struct ieee80211_frame); 18874128Shx147065 18884128Shx147065 m = allocb(msgdsize(mp) + 32, BPRI_MED); 18894128Shx147065 if (m == NULL) { /* can not alloc buf, drop this package */ 18904128Shx147065 cmn_err(CE_WARN, 18914128Shx147065 "wpi_send(): failed to allocate msgbuf\n"); 18924128Shx147065 freemsg(mp); 18934128Shx147065 err = WPI_SUCCESS; 18944128Shx147065 goto exit; 18954128Shx147065 } 18964128Shx147065 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 18974128Shx147065 mblen = MBLKL(m0); 18984128Shx147065 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 18994128Shx147065 off += mblen; 19004128Shx147065 } 19014128Shx147065 m->b_wptr += off; 19024128Shx147065 freemsg(mp); 19034128Shx147065 19044128Shx147065 wh = (struct ieee80211_frame *)m->b_rptr; 19054128Shx147065 19064128Shx147065 in = ieee80211_find_txnode(ic, wh->i_addr1); 19074128Shx147065 if (in == NULL) { 19084128Shx147065 cmn_err(CE_WARN, "wpi_send(): failed to find tx node\n"); 19094128Shx147065 freemsg(m); 19104128Shx147065 sc->sc_tx_err++; 19114128Shx147065 err = WPI_SUCCESS; 19124128Shx147065 goto exit; 19134128Shx147065 } 19144128Shx147065 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 19154128Shx147065 k = ieee80211_crypto_encap(ic, m); 19164128Shx147065 if (k == NULL) { 19174128Shx147065 freemsg(m); 19184128Shx147065 sc->sc_tx_err++; 19194128Shx147065 err = WPI_SUCCESS; 19204128Shx147065 goto exit; 19214128Shx147065 } 19224128Shx147065 19234128Shx147065 /* packet header may have moved, reset our local pointer */ 19244128Shx147065 wh = (struct ieee80211_frame *)m->b_rptr; 19254128Shx147065 } 19264128Shx147065 19274128Shx147065 len = msgdsize(m); 19284128Shx147065 19294128Shx147065 #ifdef DEBUG 19304128Shx147065 if (wpi_dbg_flags & WPI_DEBUG_TX) 19314128Shx147065 ieee80211_dump_pkt((uint8_t *)wh, hdrlen, 0, 0); 19324128Shx147065 #endif 19334128Shx147065 19344128Shx147065 /* pickup a rate */ 19354128Shx147065 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 19364128Shx147065 IEEE80211_FC0_TYPE_MGT) { 19374128Shx147065 /* mgmt frames are sent at the lowest available bit-rate */ 1938*4499Shx147065 rate = 2; 19394128Shx147065 } else { 19404128Shx147065 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 19414128Shx147065 rate = ic->ic_fixed_rate; 19424128Shx147065 } else 19434128Shx147065 rate = in->in_rates.ir_rates[in->in_txrate]; 19444128Shx147065 } 19454128Shx147065 rate &= IEEE80211_RATE_VAL; 19464128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, "tx rate[%d of %d] = %x", 19474128Shx147065 in->in_txrate, in->in_rates.ir_nrates, rate)); 19484128Shx147065 #ifdef WPI_BPF 19494128Shx147065 #ifndef WPI_CURRENT 19504128Shx147065 if (sc->sc_drvbpf != NULL) { 19514128Shx147065 #else 19524128Shx147065 if (bpf_peers_present(sc->sc_drvbpf)) { 19534128Shx147065 #endif 19544128Shx147065 struct wpi_tx_radiotap_header *tap = &sc->sc_txtap; 19554128Shx147065 19564128Shx147065 tap->wt_flags = 0; 19574128Shx147065 tap->wt_chan_freq = LE_16(ic->ic_curchan->ic_freq); 19584128Shx147065 tap->wt_chan_flags = LE_16(ic->ic_curchan->ic_flags); 19594128Shx147065 tap->wt_rate = rate; 19604128Shx147065 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 19614128Shx147065 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 19624128Shx147065 19634128Shx147065 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 19644128Shx147065 } 19654128Shx147065 #endif 19664128Shx147065 19674128Shx147065 cmd->code = WPI_CMD_TX_DATA; 19684128Shx147065 cmd->flags = 0; 19694128Shx147065 cmd->qid = ring->qid; 19704128Shx147065 cmd->idx = ring->cur; 19714128Shx147065 19724128Shx147065 tx = (wpi_cmd_data_t *)cmd->data; 19734128Shx147065 tx->flags = 0; 19744128Shx147065 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 19754128Shx147065 tx->flags |= LE_32(WPI_TX_NEED_ACK); 19764128Shx147065 } else { 19774128Shx147065 tx->flags &= ~(LE_32(WPI_TX_NEED_ACK)); 19784128Shx147065 } 19794128Shx147065 19804128Shx147065 tx->flags |= (LE_32(WPI_TX_AUTO_SEQ)); 19814128Shx147065 tx->flags |= LE_32(WPI_TX_BT_DISABLE | WPI_TX_CALIBRATION); 19824128Shx147065 19834128Shx147065 /* retrieve destination node's id */ 19844128Shx147065 tx->id = IEEE80211_IS_MULTICAST(wh->i_addr1) ? WPI_ID_BROADCAST : 19854128Shx147065 WPI_ID_BSS; 19864128Shx147065 19874128Shx147065 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 19884128Shx147065 IEEE80211_FC0_TYPE_MGT) { 19894128Shx147065 /* tell h/w to set timestamp in probe responses */ 19904128Shx147065 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 19914128Shx147065 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 19924128Shx147065 tx->flags |= LE_32(WPI_TX_INSERT_TSTAMP); 19934128Shx147065 19944128Shx147065 if (((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 19954128Shx147065 IEEE80211_FC0_SUBTYPE_ASSOC_REQ) || 19964128Shx147065 ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 19974128Shx147065 IEEE80211_FC0_SUBTYPE_REASSOC_REQ)) 19984128Shx147065 tx->timeout = 3; 19994128Shx147065 else 20004128Shx147065 tx->timeout = 2; 20014128Shx147065 } else 20024128Shx147065 tx->timeout = 0; 20034128Shx147065 20044128Shx147065 tx->rate = wpi_plcp_signal(rate); 20054128Shx147065 20064128Shx147065 /* be very persistant at sending frames out */ 20074128Shx147065 tx->rts_ntries = 7; 20084128Shx147065 tx->data_ntries = 15; 20094128Shx147065 20104128Shx147065 tx->cck_mask = 0x0f; 20114128Shx147065 tx->ofdm_mask = 0xff; 20124128Shx147065 tx->lifetime = LE_32(0xffffffff); 20134128Shx147065 20144128Shx147065 tx->len = LE_16(len); 20154128Shx147065 20164128Shx147065 /* save and trim IEEE802.11 header */ 20174128Shx147065 (void) memcpy(tx + 1, m->b_rptr, hdrlen); 20184128Shx147065 m->b_rptr += hdrlen; 20194128Shx147065 (void) memcpy(data->dma_data.mem_va, m->b_rptr, len - hdrlen); 20204128Shx147065 20214128Shx147065 WPI_DBG((WPI_DEBUG_TX, "sending data: qid=%d idx=%d len=%d", ring->qid, 20224128Shx147065 ring->cur, len)); 20234128Shx147065 20244128Shx147065 /* first scatter/gather segment is used by the tx data command */ 20254128Shx147065 desc->flags = LE_32(WPI_PAD32(len) << 28 | (2) << 24); 20264128Shx147065 desc->segs[0].addr = LE_32(data->paddr_cmd); 20274128Shx147065 desc->segs[0].len = LE_32( 20284128Shx147065 roundup(4 + sizeof (wpi_cmd_data_t) + hdrlen, 4)); 20294128Shx147065 desc->segs[1].addr = LE_32(data->dma_data.cookie.dmac_address); 20304128Shx147065 desc->segs[1].len = LE_32(len - hdrlen); 20314128Shx147065 20324128Shx147065 WPI_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV); 20334128Shx147065 WPI_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); 20344128Shx147065 20354128Shx147065 mutex_enter(&sc->sc_tx_lock); 20364128Shx147065 ring->queued++; 20374128Shx147065 mutex_exit(&sc->sc_tx_lock); 20384128Shx147065 20394128Shx147065 /* kick ring */ 20404128Shx147065 ring->cur = (ring->cur + 1) % WPI_TX_RING_COUNT; 20414128Shx147065 WPI_WRITE(sc, WPI_TX_WIDX, ring->qid << 8 | ring->cur); 20424128Shx147065 freemsg(m); 20434128Shx147065 /* release node reference */ 20444128Shx147065 ieee80211_free_node(in); 20454128Shx147065 20464128Shx147065 ic->ic_stats.is_tx_bytes += len; 20474128Shx147065 ic->ic_stats.is_tx_frags++; 20484128Shx147065 20494128Shx147065 if (sc->sc_tx_timer == 0) 20504128Shx147065 sc->sc_tx_timer = 5; 20514128Shx147065 exit: 20524128Shx147065 return (err); 20534128Shx147065 } 20544128Shx147065 20554128Shx147065 static void 20564128Shx147065 wpi_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) 20574128Shx147065 { 20584128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 20594128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 20604128Shx147065 int err; 20614128Shx147065 20624128Shx147065 err = ieee80211_ioctl(ic, wq, mp); 20634128Shx147065 if (err == ENETRESET) { 20644128Shx147065 (void) ieee80211_new_state(ic, 20654128Shx147065 IEEE80211_S_SCAN, -1); 20664128Shx147065 } 20674128Shx147065 } 20684128Shx147065 20694128Shx147065 /*ARGSUSED*/ 20704128Shx147065 static int 20714128Shx147065 wpi_m_stat(void *arg, uint_t stat, uint64_t *val) 20724128Shx147065 { 20734128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 20744128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 20754128Shx147065 ieee80211_node_t *in = ic->ic_bss; 20764128Shx147065 struct ieee80211_rateset *rs = &in->in_rates; 20774128Shx147065 20784128Shx147065 mutex_enter(&sc->sc_glock); 20794128Shx147065 switch (stat) { 20804128Shx147065 case MAC_STAT_IFSPEED: 20814128Shx147065 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ? 20824128Shx147065 (rs->ir_rates[in->in_txrate] & IEEE80211_RATE_VAL) 20834128Shx147065 : ic->ic_fixed_rate) * 5000000ull; 20844128Shx147065 break; 20854128Shx147065 case MAC_STAT_NOXMTBUF: 20864128Shx147065 *val = sc->sc_tx_nobuf; 20874128Shx147065 break; 20884128Shx147065 case MAC_STAT_NORCVBUF: 20894128Shx147065 *val = sc->sc_rx_nobuf; 20904128Shx147065 break; 20914128Shx147065 case MAC_STAT_IERRORS: 20924128Shx147065 *val = sc->sc_rx_err; 20934128Shx147065 break; 20944128Shx147065 case MAC_STAT_RBYTES: 20954128Shx147065 *val = ic->ic_stats.is_rx_bytes; 20964128Shx147065 break; 20974128Shx147065 case MAC_STAT_IPACKETS: 20984128Shx147065 *val = ic->ic_stats.is_rx_frags; 20994128Shx147065 break; 21004128Shx147065 case MAC_STAT_OBYTES: 21014128Shx147065 *val = ic->ic_stats.is_tx_bytes; 21024128Shx147065 break; 21034128Shx147065 case MAC_STAT_OPACKETS: 21044128Shx147065 *val = ic->ic_stats.is_tx_frags; 21054128Shx147065 break; 21064128Shx147065 case MAC_STAT_OERRORS: 21074128Shx147065 case WIFI_STAT_TX_FAILED: 21084128Shx147065 *val = sc->sc_tx_err; 21094128Shx147065 break; 21104128Shx147065 case WIFI_STAT_TX_RETRANS: 21114128Shx147065 *val = sc->sc_tx_retries; 21124128Shx147065 break; 21134128Shx147065 case WIFI_STAT_FCS_ERRORS: 21144128Shx147065 case WIFI_STAT_WEP_ERRORS: 21154128Shx147065 case WIFI_STAT_TX_FRAGS: 21164128Shx147065 case WIFI_STAT_MCAST_TX: 21174128Shx147065 case WIFI_STAT_RTS_SUCCESS: 21184128Shx147065 case WIFI_STAT_RTS_FAILURE: 21194128Shx147065 case WIFI_STAT_ACK_FAILURE: 21204128Shx147065 case WIFI_STAT_RX_FRAGS: 21214128Shx147065 case WIFI_STAT_MCAST_RX: 21224128Shx147065 case WIFI_STAT_RX_DUPS: 21234128Shx147065 mutex_exit(&sc->sc_glock); 21244128Shx147065 return (ieee80211_stat(ic, stat, val)); 21254128Shx147065 default: 21264128Shx147065 mutex_exit(&sc->sc_glock); 21274128Shx147065 return (ENOTSUP); 21284128Shx147065 } 21294128Shx147065 mutex_exit(&sc->sc_glock); 21304128Shx147065 21314128Shx147065 return (WPI_SUCCESS); 21324128Shx147065 21334128Shx147065 } 21344128Shx147065 21354128Shx147065 static int 21364128Shx147065 wpi_m_start(void *arg) 21374128Shx147065 { 21384128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 21394128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 21404128Shx147065 int err; 21414128Shx147065 21424128Shx147065 err = wpi_init(sc); 21434128Shx147065 if (err != WPI_SUCCESS) { 21444128Shx147065 wpi_stop(sc); 21454128Shx147065 DELAY(1000000); 21464128Shx147065 err = wpi_init(sc); 21474128Shx147065 } 21484128Shx147065 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 21494128Shx147065 21504128Shx147065 return (err); 21514128Shx147065 } 21524128Shx147065 21534128Shx147065 static void 21544128Shx147065 wpi_m_stop(void *arg) 21554128Shx147065 { 21564128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 21574128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 21584128Shx147065 21594128Shx147065 wpi_stop(sc); 21604128Shx147065 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 21614128Shx147065 mutex_enter(&sc->sc_mt_lock); 21624128Shx147065 sc->sc_flags &= ~WPI_F_HW_ERR_RECOVER; 21634128Shx147065 sc->sc_flags &= ~WPI_F_RATE_AUTO_CTL; 21644128Shx147065 mutex_exit(&sc->sc_mt_lock); 21654128Shx147065 } 21664128Shx147065 21674128Shx147065 /*ARGSUSED*/ 21684128Shx147065 static int 21694128Shx147065 wpi_m_unicst(void *arg, const uint8_t *macaddr) 21704128Shx147065 { 21714128Shx147065 wpi_sc_t *sc = (wpi_sc_t *)arg; 21724128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 21734128Shx147065 int err; 21744128Shx147065 21754128Shx147065 if (!IEEE80211_ADDR_EQ(ic->ic_macaddr, macaddr)) { 21764128Shx147065 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); 21774128Shx147065 mutex_enter(&sc->sc_glock); 21784128Shx147065 err = wpi_config(sc); 21794128Shx147065 mutex_exit(&sc->sc_glock); 21804128Shx147065 if (err != WPI_SUCCESS) { 21814128Shx147065 cmn_err(CE_WARN, 21824128Shx147065 "wpi_m_unicst(): " 21834128Shx147065 "failed to configure device\n"); 21844128Shx147065 goto fail; 21854128Shx147065 } 21864128Shx147065 } 21874128Shx147065 return (WPI_SUCCESS); 21884128Shx147065 fail: 21894128Shx147065 return (err); 21904128Shx147065 } 21914128Shx147065 21924128Shx147065 /*ARGSUSED*/ 21934128Shx147065 static int 21944128Shx147065 wpi_m_multicst(void *arg, boolean_t add, const uint8_t *m) 21954128Shx147065 { 21964128Shx147065 return (WPI_SUCCESS); 21974128Shx147065 } 21984128Shx147065 21994128Shx147065 /*ARGSUSED*/ 22004128Shx147065 static int 22014128Shx147065 wpi_m_promisc(void *arg, boolean_t on) 22024128Shx147065 { 22034128Shx147065 return (WPI_SUCCESS); 22044128Shx147065 } 22054128Shx147065 22064128Shx147065 static void 22074128Shx147065 wpi_thread(wpi_sc_t *sc) 22084128Shx147065 { 22094128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 22104128Shx147065 clock_t clk; 22114128Shx147065 int times = 0, err, n = 0, timeout = 0; 22124128Shx147065 22134128Shx147065 mutex_enter(&sc->sc_mt_lock); 22144128Shx147065 while (sc->sc_mf_thread_switch) { 22154128Shx147065 /* 22164128Shx147065 * recovery fatal error 22174128Shx147065 */ 22184128Shx147065 if (ic->ic_mach && 22194128Shx147065 (sc->sc_flags & WPI_F_HW_ERR_RECOVER)) { 22204128Shx147065 22214128Shx147065 WPI_DBG((WPI_DEBUG_FW, 22224128Shx147065 "wpi_thread(): " 22234128Shx147065 "try to recover fatal hw error: %d\n", times++)); 22244128Shx147065 22254128Shx147065 wpi_stop(sc); 22264128Shx147065 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 22274128Shx147065 22284128Shx147065 mutex_exit(&sc->sc_mt_lock); 22294128Shx147065 delay(drv_usectohz(2000000)); 22304128Shx147065 mutex_enter(&sc->sc_mt_lock); 22314128Shx147065 err = wpi_init(sc); 22324128Shx147065 if (err != WPI_SUCCESS) { 22334128Shx147065 n++; 22344128Shx147065 if (n < 3) 22354128Shx147065 continue; 22364128Shx147065 } 22374128Shx147065 n = 0; 22384128Shx147065 sc->sc_flags &= ~WPI_F_HW_ERR_RECOVER; 22394128Shx147065 mutex_exit(&sc->sc_mt_lock); 22404128Shx147065 delay(drv_usectohz(2000000)); 22414128Shx147065 if (sc->sc_ostate != IEEE80211_S_INIT) 22424128Shx147065 ieee80211_begin_scan(ic, 0); 22434128Shx147065 mutex_enter(&sc->sc_mt_lock); 22444128Shx147065 } 22454128Shx147065 22464128Shx147065 /* 22474128Shx147065 * rate ctl 22484128Shx147065 */ 22494128Shx147065 if (ic->ic_mach && 22504128Shx147065 (sc->sc_flags & WPI_F_RATE_AUTO_CTL)) { 22514128Shx147065 clk = ddi_get_lbolt(); 22524128Shx147065 if (clk > sc->sc_clk + drv_usectohz(500000)) { 22534128Shx147065 wpi_amrr_timeout(sc); 22544128Shx147065 } 22554128Shx147065 } 22564128Shx147065 mutex_exit(&sc->sc_mt_lock); 22574128Shx147065 delay(drv_usectohz(100000)); 22584128Shx147065 mutex_enter(&sc->sc_mt_lock); 22594128Shx147065 if (sc->sc_tx_timer) { 22604128Shx147065 timeout++; 22614128Shx147065 if (timeout == 10) { 22624128Shx147065 sc->sc_tx_timer--; 22634128Shx147065 if (sc->sc_tx_timer == 0) { 22644128Shx147065 sc->sc_flags |= WPI_F_HW_ERR_RECOVER; 22654128Shx147065 sc->sc_ostate = IEEE80211_S_RUN; 22664128Shx147065 } 22674128Shx147065 timeout = 0; 22684128Shx147065 } 22694128Shx147065 } 22704128Shx147065 } 22714128Shx147065 sc->sc_mf_thread = NULL; 22724128Shx147065 cv_signal(&sc->sc_mt_cv); 22734128Shx147065 mutex_exit(&sc->sc_mt_lock); 22744128Shx147065 } 22754128Shx147065 22764128Shx147065 /* 22774128Shx147065 * Extract various information from EEPROM. 22784128Shx147065 */ 22794128Shx147065 static void 22804128Shx147065 wpi_read_eeprom(wpi_sc_t *sc) 22814128Shx147065 { 22824128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 22834128Shx147065 uint16_t val; 22844128Shx147065 int i; 22854128Shx147065 22864128Shx147065 /* read MAC address */ 22874128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_MAC + 0); 22884128Shx147065 ic->ic_macaddr[0] = val & 0xff; 22894128Shx147065 ic->ic_macaddr[1] = val >> 8; 22904128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_MAC + 1); 22914128Shx147065 ic->ic_macaddr[2] = val & 0xff; 22924128Shx147065 ic->ic_macaddr[3] = val >> 8; 22934128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_MAC + 2); 22944128Shx147065 ic->ic_macaddr[4] = val & 0xff; 22954128Shx147065 ic->ic_macaddr[5] = val >> 8; 22964128Shx147065 22974128Shx147065 WPI_DBG((WPI_DEBUG_EEPROM, 22984128Shx147065 "mac:%2x:%2x:%2x:%2x:%2x:%2x\n", 22994128Shx147065 ic->ic_macaddr[0], ic->ic_macaddr[1], 23004128Shx147065 ic->ic_macaddr[2], ic->ic_macaddr[3], 23014128Shx147065 ic->ic_macaddr[4], ic->ic_macaddr[5])); 23024128Shx147065 /* read power settings for 2.4GHz channels */ 23034128Shx147065 for (i = 0; i < 14; i++) { 23044128Shx147065 sc->sc_pwr1[i] = wpi_read_prom_word(sc, WPI_EEPROM_PWR1 + i); 23054128Shx147065 sc->sc_pwr2[i] = wpi_read_prom_word(sc, WPI_EEPROM_PWR2 + i); 23064128Shx147065 WPI_DBG((WPI_DEBUG_EEPROM, 23074128Shx147065 "channel %d pwr1 0x%04x pwr2 0x%04x\n", i + 1, 23084128Shx147065 sc->sc_pwr1[i], sc->sc_pwr2[i])); 23094128Shx147065 } 23104128Shx147065 } 23114128Shx147065 23124128Shx147065 /* 23134128Shx147065 * Send a command to the firmware. 23144128Shx147065 */ 23154128Shx147065 static int 23164128Shx147065 wpi_cmd(wpi_sc_t *sc, int code, const void *buf, int size, int async) 23174128Shx147065 { 23184128Shx147065 wpi_tx_ring_t *ring = &sc->sc_cmdq; 23194128Shx147065 wpi_tx_desc_t *desc; 23204128Shx147065 wpi_tx_cmd_t *cmd; 23214128Shx147065 23224128Shx147065 ASSERT(size <= sizeof (cmd->data)); 23234128Shx147065 ASSERT(mutex_owned(&sc->sc_glock)); 23244128Shx147065 23254128Shx147065 WPI_DBG((WPI_DEBUG_CMD, "wpi_cmd() # code[%d]", code)); 23264128Shx147065 desc = ring->data[ring->cur].desc; 23274128Shx147065 cmd = ring->data[ring->cur].cmd; 23284128Shx147065 23294128Shx147065 cmd->code = (uint8_t)code; 23304128Shx147065 cmd->flags = 0; 23314128Shx147065 cmd->qid = ring->qid; 23324128Shx147065 cmd->idx = ring->cur; 23334128Shx147065 (void) memcpy(cmd->data, buf, size); 23344128Shx147065 23354128Shx147065 desc->flags = LE_32(WPI_PAD32(size) << 28 | 1 << 24); 23364128Shx147065 desc->segs[0].addr = ring->data[ring->cur].paddr_cmd; 23374128Shx147065 desc->segs[0].len = 4 + size; 23384128Shx147065 23394128Shx147065 /* kick cmd ring */ 23404128Shx147065 ring->cur = (ring->cur + 1) % WPI_CMD_RING_COUNT; 23414128Shx147065 WPI_WRITE(sc, WPI_TX_WIDX, ring->qid << 8 | ring->cur); 23424128Shx147065 23434128Shx147065 if (async) 23444128Shx147065 return (WPI_SUCCESS); 23454128Shx147065 else { 23464128Shx147065 clock_t clk; 23474128Shx147065 sc->sc_flags &= ~WPI_F_CMD_DONE; 23484128Shx147065 clk = ddi_get_lbolt() + drv_usectohz(2000000); 23494128Shx147065 while (!(sc->sc_flags & WPI_F_CMD_DONE)) { 23504128Shx147065 if (cv_timedwait(&sc->sc_cmd_cv, &sc->sc_glock, clk) 23514128Shx147065 < 0) 23524128Shx147065 break; 23534128Shx147065 } 23544128Shx147065 if (sc->sc_flags & WPI_F_CMD_DONE) 23554128Shx147065 return (WPI_SUCCESS); 23564128Shx147065 else 23574128Shx147065 return (WPI_FAIL); 23584128Shx147065 } 23594128Shx147065 } 23604128Shx147065 23614128Shx147065 /* 23624128Shx147065 * Configure h/w multi-rate retries. 23634128Shx147065 */ 23644128Shx147065 static int 23654128Shx147065 wpi_mrr_setup(wpi_sc_t *sc) 23664128Shx147065 { 23674128Shx147065 wpi_mrr_setup_t mrr; 23684128Shx147065 int i, err; 23694128Shx147065 23704128Shx147065 /* CCK rates (not used with 802.11a) */ 23714128Shx147065 for (i = WPI_CCK1; i <= WPI_CCK11; i++) { 23724128Shx147065 mrr.rates[i].flags = 0; 23734128Shx147065 mrr.rates[i].signal = wpi_ridx_to_signal[i]; 23744128Shx147065 /* fallback to the immediate lower CCK rate (if any) */ 23754128Shx147065 mrr.rates[i].next = (i == WPI_CCK1) ? WPI_CCK1 : i - 1; 23764128Shx147065 /* try one time at this rate before falling back to "next" */ 23774128Shx147065 mrr.rates[i].ntries = 1; 23784128Shx147065 } 23794128Shx147065 23804128Shx147065 /* OFDM rates (not used with 802.11b) */ 23814128Shx147065 for (i = WPI_OFDM6; i <= WPI_OFDM54; i++) { 23824128Shx147065 mrr.rates[i].flags = 0; 23834128Shx147065 mrr.rates[i].signal = wpi_ridx_to_signal[i]; 23844128Shx147065 /* fallback to the immediate lower OFDM rate (if any) */ 23854128Shx147065 mrr.rates[i].next = (i == WPI_OFDM6) ? WPI_OFDM6 : i - 1; 23864128Shx147065 /* try one time at this rate before falling back to "next" */ 23874128Shx147065 mrr.rates[i].ntries = 1; 23884128Shx147065 } 23894128Shx147065 23904128Shx147065 /* setup MRR for control frames */ 23914128Shx147065 mrr.which = LE_32(WPI_MRR_CTL); 23924128Shx147065 err = wpi_cmd(sc, WPI_CMD_MRR_SETUP, &mrr, sizeof (mrr), 1); 23934128Shx147065 if (err != WPI_SUCCESS) { 23944128Shx147065 WPI_DBG((WPI_DEBUG_MRR, 23954128Shx147065 "could not setup MRR for control frames\n")); 23964128Shx147065 return (err); 23974128Shx147065 } 23984128Shx147065 23994128Shx147065 /* setup MRR for data frames */ 24004128Shx147065 mrr.which = LE_32(WPI_MRR_DATA); 24014128Shx147065 err = wpi_cmd(sc, WPI_CMD_MRR_SETUP, &mrr, sizeof (mrr), 1); 24024128Shx147065 if (err != WPI_SUCCESS) { 24034128Shx147065 WPI_DBG((WPI_DEBUG_MRR, 24044128Shx147065 "could not setup MRR for data frames\n")); 24054128Shx147065 return (err); 24064128Shx147065 } 24074128Shx147065 24084128Shx147065 return (WPI_SUCCESS); 24094128Shx147065 } 24104128Shx147065 24114128Shx147065 static void 24124128Shx147065 wpi_set_led(wpi_sc_t *sc, uint8_t which, uint8_t off, uint8_t on) 24134128Shx147065 { 24144128Shx147065 wpi_cmd_led_t led; 24154128Shx147065 24164128Shx147065 led.which = which; 24174128Shx147065 led.unit = LE_32(100000); /* on/off in unit of 100ms */ 24184128Shx147065 led.off = off; 24194128Shx147065 led.on = on; 24204128Shx147065 24214128Shx147065 (void) wpi_cmd(sc, WPI_CMD_SET_LED, &led, sizeof (led), 1); 24224128Shx147065 } 24234128Shx147065 24244128Shx147065 static int 24254128Shx147065 wpi_auth(wpi_sc_t *sc) 24264128Shx147065 { 24274128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 24284128Shx147065 ieee80211_node_t *in = ic->ic_bss; 24294128Shx147065 wpi_node_t node; 24304128Shx147065 int err; 24314128Shx147065 24324128Shx147065 /* update adapter's configuration */ 24334128Shx147065 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid); 24344128Shx147065 sc->sc_config.chan = ieee80211_chan2ieee(ic, in->in_chan); 24354128Shx147065 if (ic->ic_curmode == IEEE80211_MODE_11B) { 24364128Shx147065 sc->sc_config.cck_mask = 0x03; 24374128Shx147065 sc->sc_config.ofdm_mask = 0; 24384128Shx147065 } else if ((in->in_chan != IEEE80211_CHAN_ANYC) && 24394128Shx147065 (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) { 24404128Shx147065 sc->sc_config.cck_mask = 0; 24414128Shx147065 sc->sc_config.ofdm_mask = 0x15; 24424128Shx147065 } else { /* assume 802.11b/g */ 24434128Shx147065 sc->sc_config.cck_mask = 0x0f; 24444128Shx147065 sc->sc_config.ofdm_mask = 0x15; 24454128Shx147065 } 24464128Shx147065 24474128Shx147065 WPI_DBG((WPI_DEBUG_80211, "config chan %d flags %x cck %x ofdm %x" 24484128Shx147065 " bssid:%02x:%02x:%02x:%02x:%02x:%2x\n", 24494128Shx147065 sc->sc_config.chan, sc->sc_config.flags, 24504128Shx147065 sc->sc_config.cck_mask, sc->sc_config.ofdm_mask, 24514128Shx147065 sc->sc_config.bssid[0], sc->sc_config.bssid[1], 24524128Shx147065 sc->sc_config.bssid[2], sc->sc_config.bssid[3], 24534128Shx147065 sc->sc_config.bssid[4], sc->sc_config.bssid[5])); 24544128Shx147065 err = wpi_cmd(sc, WPI_CMD_CONFIGURE, &sc->sc_config, 24554128Shx147065 sizeof (wpi_config_t), 1); 24564128Shx147065 if (err != WPI_SUCCESS) { 24574128Shx147065 cmn_err(CE_WARN, "wpi_auth(): failed to configurate chan%d\n", 24584128Shx147065 sc->sc_config.chan); 24594128Shx147065 return (err); 24604128Shx147065 } 24614128Shx147065 24624128Shx147065 /* add default node */ 24634128Shx147065 (void) memset(&node, 0, sizeof (node)); 24644128Shx147065 IEEE80211_ADDR_COPY(node.bssid, in->in_bssid); 24654128Shx147065 node.id = WPI_ID_BSS; 24664128Shx147065 node.rate = wpi_plcp_signal(2); 24674128Shx147065 err = wpi_cmd(sc, WPI_CMD_ADD_NODE, &node, sizeof (node), 1); 24684128Shx147065 if (err != WPI_SUCCESS) { 24694128Shx147065 cmn_err(CE_WARN, "wpi_auth(): failed to add BSS node\n"); 24704128Shx147065 return (err); 24714128Shx147065 } 24724128Shx147065 24734128Shx147065 err = wpi_mrr_setup(sc); 24744128Shx147065 if (err != WPI_SUCCESS) { 24754128Shx147065 cmn_err(CE_WARN, "wpi_auth(): failed to setup MRR\n"); 24764128Shx147065 return (err); 24774128Shx147065 } 24784128Shx147065 24794128Shx147065 return (WPI_SUCCESS); 24804128Shx147065 } 24814128Shx147065 24824128Shx147065 /* 24834128Shx147065 * Send a scan request to the firmware. 24844128Shx147065 */ 24854128Shx147065 static int 24864128Shx147065 wpi_scan(wpi_sc_t *sc) 24874128Shx147065 { 24884128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 24894128Shx147065 wpi_tx_ring_t *ring = &sc->sc_cmdq; 24904128Shx147065 wpi_tx_desc_t *desc; 24914128Shx147065 wpi_tx_data_t *data; 24924128Shx147065 wpi_tx_cmd_t *cmd; 24934128Shx147065 wpi_scan_hdr_t *hdr; 24944128Shx147065 wpi_scan_chan_t *chan; 24954128Shx147065 struct ieee80211_frame *wh; 24964128Shx147065 ieee80211_node_t *in = ic->ic_bss; 24974128Shx147065 struct ieee80211_rateset *rs; 24984128Shx147065 enum ieee80211_phymode mode; 24994128Shx147065 uint8_t *frm; 25004128Shx147065 int i, pktlen, nrates; 25014128Shx147065 25024128Shx147065 data = &ring->data[ring->cur]; 25034128Shx147065 desc = data->desc; 25044128Shx147065 cmd = (wpi_tx_cmd_t *)data->dma_data.mem_va; 25054128Shx147065 25064128Shx147065 cmd->code = WPI_CMD_SCAN; 25074128Shx147065 cmd->flags = 0; 25084128Shx147065 cmd->qid = ring->qid; 25094128Shx147065 cmd->idx = ring->cur; 25104128Shx147065 25114128Shx147065 hdr = (wpi_scan_hdr_t *)cmd->data; 25124128Shx147065 (void) memset(hdr, 0, sizeof (wpi_scan_hdr_t)); 25134128Shx147065 hdr->first = 1; 25144128Shx147065 hdr->nchan = 14; 25154128Shx147065 hdr->len = hdr->nchan * sizeof (wpi_scan_chan_t); 25164128Shx147065 hdr->quiet = LE_16(5); 25174128Shx147065 hdr->threshold = LE_16(1); 25184128Shx147065 hdr->filter = LE_32(5); 25194128Shx147065 hdr->rate = wpi_plcp_signal(2); 25204128Shx147065 hdr->id = WPI_ID_BROADCAST; 25214128Shx147065 hdr->mask = LE_32(0xffffffff); 25224128Shx147065 hdr->esslen = ic->ic_des_esslen; 25234128Shx147065 if (ic->ic_des_esslen) 25244128Shx147065 bcopy(ic->ic_des_essid, hdr->essid, ic->ic_des_esslen); 25254128Shx147065 else 25264128Shx147065 bzero(hdr->essid, sizeof (hdr->essid)); 25274128Shx147065 /* 25284128Shx147065 * Build a probe request frame. Most of the following code is a 25294128Shx147065 * copy & paste of what is done in net80211. Unfortunately, the 25304128Shx147065 * functions to add IEs are static and thus can't be reused here. 25314128Shx147065 */ 25324128Shx147065 wh = (struct ieee80211_frame *)(hdr + 1); 25334128Shx147065 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 25344128Shx147065 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 25354128Shx147065 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 25364128Shx147065 (void) memset(wh->i_addr1, 0xff, 6); 25374128Shx147065 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_macaddr); 25384128Shx147065 (void) memset(wh->i_addr3, 0xff, 6); 25394128Shx147065 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by h/w */ 25404128Shx147065 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by h/w */ 25414128Shx147065 25424128Shx147065 frm = (uint8_t *)(wh + 1); 25434128Shx147065 25444128Shx147065 /* add essid IE */ 25454128Shx147065 *frm++ = IEEE80211_ELEMID_SSID; 25464128Shx147065 *frm++ = in->in_esslen; 25474128Shx147065 (void) memcpy(frm, in->in_essid, in->in_esslen); 25484128Shx147065 frm += in->in_esslen; 25494128Shx147065 25504128Shx147065 mode = ieee80211_chan2mode(ic, ic->ic_curchan); 25514128Shx147065 rs = &ic->ic_sup_rates[mode]; 25524128Shx147065 25534128Shx147065 /* add supported rates IE */ 25544128Shx147065 *frm++ = IEEE80211_ELEMID_RATES; 25554128Shx147065 nrates = rs->ir_nrates; 25564128Shx147065 if (nrates > IEEE80211_RATE_SIZE) 25574128Shx147065 nrates = IEEE80211_RATE_SIZE; 25584128Shx147065 *frm++ = (uint8_t)nrates; 25594128Shx147065 (void) memcpy(frm, rs->ir_rates, nrates); 25604128Shx147065 frm += nrates; 25614128Shx147065 25624128Shx147065 /* add supported xrates IE */ 25634128Shx147065 if (rs->ir_nrates > IEEE80211_RATE_SIZE) { 25644128Shx147065 nrates = rs->ir_nrates - IEEE80211_RATE_SIZE; 25654128Shx147065 *frm++ = IEEE80211_ELEMID_XRATES; 25664128Shx147065 *frm++ = (uint8_t)nrates; 25674128Shx147065 (void) memcpy(frm, rs->ir_rates + IEEE80211_RATE_SIZE, nrates); 25684128Shx147065 frm += nrates; 25694128Shx147065 } 25704128Shx147065 25714128Shx147065 /* add optionnal IE (usually an RSN IE) */ 25724128Shx147065 if (ic->ic_opt_ie != NULL) { 25734128Shx147065 (void) memcpy(frm, ic->ic_opt_ie, ic->ic_opt_ie_len); 25744128Shx147065 frm += ic->ic_opt_ie_len; 25754128Shx147065 } 25764128Shx147065 25774128Shx147065 /* setup length of probe request */ 25784128Shx147065 hdr->pbrlen = LE_16(frm - (uint8_t *)wh); 25794128Shx147065 25804128Shx147065 /* align on a 4-byte boundary */ 25814128Shx147065 chan = (wpi_scan_chan_t *)frm; 25824128Shx147065 for (i = 1; i <= hdr->nchan; i++, chan++) { 25834128Shx147065 chan->flags = 3; 25844128Shx147065 chan->chan = (uint8_t)i; 25854128Shx147065 chan->magic = LE_16(0x62ab); 25864128Shx147065 chan->active = LE_16(20); 25874128Shx147065 chan->passive = LE_16(120); 25884128Shx147065 25894128Shx147065 frm += sizeof (wpi_scan_chan_t); 25904128Shx147065 } 25914128Shx147065 25924128Shx147065 pktlen = frm - (uint8_t *)cmd; 25934128Shx147065 25944128Shx147065 desc->flags = LE_32(WPI_PAD32(pktlen) << 28 | 1 << 24); 25954128Shx147065 desc->segs[0].addr = LE_32(data->dma_data.cookie.dmac_address); 25964128Shx147065 desc->segs[0].len = LE_32(pktlen); 25974128Shx147065 25984128Shx147065 WPI_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV); 25994128Shx147065 WPI_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV); 26004128Shx147065 26014128Shx147065 /* kick cmd ring */ 26024128Shx147065 ring->cur = (ring->cur + 1) % WPI_CMD_RING_COUNT; 26034128Shx147065 WPI_WRITE(sc, WPI_TX_WIDX, ring->qid << 8 | ring->cur); 26044128Shx147065 26054128Shx147065 return (WPI_SUCCESS); /* will be notified async. of failure/success */ 26064128Shx147065 } 26074128Shx147065 26084128Shx147065 static int 26094128Shx147065 wpi_config(wpi_sc_t *sc) 26104128Shx147065 { 26114128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 26124128Shx147065 wpi_txpower_t txpower; 26134128Shx147065 wpi_power_t power; 26144128Shx147065 #ifdef WPI_BLUE_COEXISTENCE 26154128Shx147065 wpi_bluetooth_t bluetooth; 26164128Shx147065 #endif 26174128Shx147065 wpi_node_t node; 26184128Shx147065 int err; 26194128Shx147065 26204128Shx147065 /* Intel's binary only daemon is a joke.. */ 26214128Shx147065 26224128Shx147065 /* set Tx power for 2.4GHz channels (values read from EEPROM) */ 26234128Shx147065 (void) memset(&txpower, 0, sizeof (txpower)); 26244128Shx147065 (void) memcpy(txpower.pwr1, sc->sc_pwr1, 14 * sizeof (uint16_t)); 26254128Shx147065 (void) memcpy(txpower.pwr2, sc->sc_pwr2, 14 * sizeof (uint16_t)); 26264128Shx147065 err = wpi_cmd(sc, WPI_CMD_TXPOWER, &txpower, sizeof (txpower), 0); 26274128Shx147065 if (err != WPI_SUCCESS) { 26284128Shx147065 cmn_err(CE_WARN, "wpi_config(): failed to set txpower\n"); 26294128Shx147065 return (err); 26304128Shx147065 } 26314128Shx147065 26324128Shx147065 /* set power mode */ 26334128Shx147065 (void) memset(&power, 0, sizeof (power)); 26344128Shx147065 power.flags = LE_32(0x8); 26354128Shx147065 err = wpi_cmd(sc, WPI_CMD_SET_POWER_MODE, &power, sizeof (power), 0); 26364128Shx147065 if (err != WPI_SUCCESS) { 26374128Shx147065 cmn_err(CE_WARN, "wpi_config(): failed to set power mode\n"); 26384128Shx147065 return (err); 26394128Shx147065 } 26404128Shx147065 #ifdef WPI_BLUE_COEXISTENCE 26414128Shx147065 /* configure bluetooth coexistence */ 26424128Shx147065 (void) memset(&bluetooth, 0, sizeof (bluetooth)); 26434128Shx147065 bluetooth.flags = 3; 26444128Shx147065 bluetooth.lead = 0xaa; 26454128Shx147065 bluetooth.kill = 1; 26464128Shx147065 err = wpi_cmd(sc, WPI_CMD_BLUETOOTH, &bluetooth, 26474128Shx147065 sizeof (bluetooth), 0); 26484128Shx147065 if (err != WPI_SUCCESS) { 26494128Shx147065 cmn_err(CE_WARN, 26504128Shx147065 "wpi_config(): " 26514128Shx147065 "failed to configurate bluetooth coexistence\n"); 26524128Shx147065 return (err); 26534128Shx147065 } 26544128Shx147065 #endif 26554128Shx147065 /* configure adapter */ 26564128Shx147065 (void) memset(&sc->sc_config, 0, sizeof (wpi_config_t)); 26574128Shx147065 IEEE80211_ADDR_COPY(sc->sc_config.myaddr, ic->ic_macaddr); 26584128Shx147065 sc->sc_config.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 26594128Shx147065 sc->sc_config.flags = LE_32(WPI_CONFIG_TSF | WPI_CONFIG_AUTO | 26604128Shx147065 WPI_CONFIG_24GHZ); 26614128Shx147065 sc->sc_config.filter = 0; 26624128Shx147065 switch (ic->ic_opmode) { 26634128Shx147065 case IEEE80211_M_STA: 26644128Shx147065 sc->sc_config.mode = WPI_MODE_STA; 26654128Shx147065 sc->sc_config.filter |= LE_32(WPI_FILTER_MULTICAST | 26664128Shx147065 WPI_FILTER_NODECRYPT); 26674128Shx147065 break; 26684128Shx147065 case IEEE80211_M_IBSS: 26694128Shx147065 case IEEE80211_M_AHDEMO: 26704128Shx147065 sc->sc_config.mode = WPI_MODE_IBSS; 26714128Shx147065 break; 26724128Shx147065 case IEEE80211_M_HOSTAP: 26734128Shx147065 sc->sc_config.mode = WPI_MODE_HOSTAP; 26744128Shx147065 break; 26754128Shx147065 case IEEE80211_M_MONITOR: 26764128Shx147065 sc->sc_config.mode = WPI_MODE_MONITOR; 26774128Shx147065 sc->sc_config.filter |= LE_32(WPI_FILTER_MULTICAST | 26784128Shx147065 WPI_FILTER_CTL | WPI_FILTER_PROMISC); 26794128Shx147065 break; 26804128Shx147065 } 26814128Shx147065 sc->sc_config.cck_mask = 0x0f; /* not yet negotiated */ 26824128Shx147065 sc->sc_config.ofdm_mask = 0xff; /* not yet negotiated */ 26834128Shx147065 err = wpi_cmd(sc, WPI_CMD_CONFIGURE, &sc->sc_config, 26844128Shx147065 sizeof (wpi_config_t), 0); 26854128Shx147065 if (err != WPI_SUCCESS) { 26864128Shx147065 cmn_err(CE_WARN, "wpi_config(): " 26874128Shx147065 "failed to set configure command\n"); 26884128Shx147065 return (err); 26894128Shx147065 } 26904128Shx147065 26914128Shx147065 /* add broadcast node */ 26924128Shx147065 (void) memset(&node, 0, sizeof (node)); 26934128Shx147065 (void) memset(node.bssid, 0xff, 6); 26944128Shx147065 node.id = WPI_ID_BROADCAST; 26954128Shx147065 node.rate = wpi_plcp_signal(2); 26964128Shx147065 err = wpi_cmd(sc, WPI_CMD_ADD_NODE, &node, sizeof (node), 0); 26974128Shx147065 if (err != WPI_SUCCESS) { 26984128Shx147065 cmn_err(CE_WARN, "wpi_config(): " 26994128Shx147065 "failed to add broadcast node\n"); 27004128Shx147065 return (err); 27014128Shx147065 } 27024128Shx147065 27034128Shx147065 return (WPI_SUCCESS); 27044128Shx147065 } 27054128Shx147065 27064128Shx147065 static void 27074128Shx147065 wpi_stop_master(wpi_sc_t *sc) 27084128Shx147065 { 27094128Shx147065 uint32_t tmp; 27104128Shx147065 int ntries; 27114128Shx147065 27124128Shx147065 tmp = WPI_READ(sc, WPI_RESET); 27134128Shx147065 WPI_WRITE(sc, WPI_RESET, tmp | WPI_STOP_MASTER); 27144128Shx147065 27154128Shx147065 tmp = WPI_READ(sc, WPI_GPIO_CTL); 27164128Shx147065 if ((tmp & WPI_GPIO_PWR_STATUS) == WPI_GPIO_PWR_SLEEP) 27174128Shx147065 return; /* already asleep */ 27184128Shx147065 27194128Shx147065 for (ntries = 0; ntries < 2000; ntries++) { 27204128Shx147065 if (WPI_READ(sc, WPI_RESET) & WPI_MASTER_DISABLED) 27214128Shx147065 break; 27224128Shx147065 DELAY(1000); 27234128Shx147065 } 27244128Shx147065 if (ntries == 2000) 27254128Shx147065 WPI_DBG((WPI_DEBUG_HW, "timeout waiting for master\n")); 27264128Shx147065 } 27274128Shx147065 27284128Shx147065 static int 27294128Shx147065 wpi_power_up(wpi_sc_t *sc) 27304128Shx147065 { 27314128Shx147065 uint32_t tmp; 27324128Shx147065 int ntries; 27334128Shx147065 27344128Shx147065 wpi_mem_lock(sc); 27354128Shx147065 tmp = wpi_mem_read(sc, WPI_MEM_POWER); 27364128Shx147065 wpi_mem_write(sc, WPI_MEM_POWER, tmp & ~0x03000000); 27374128Shx147065 wpi_mem_unlock(sc); 27384128Shx147065 27394128Shx147065 for (ntries = 0; ntries < 5000; ntries++) { 27404128Shx147065 if (WPI_READ(sc, WPI_GPIO_STATUS) & WPI_POWERED) 27414128Shx147065 break; 27424128Shx147065 DELAY(10); 27434128Shx147065 } 27444128Shx147065 if (ntries == 5000) { 27454128Shx147065 cmn_err(CE_WARN, 27464128Shx147065 "wpi_power_up(): timeout waiting for NIC to power up\n"); 27474128Shx147065 return (ETIMEDOUT); 27484128Shx147065 } 27494128Shx147065 return (WPI_SUCCESS); 27504128Shx147065 } 27514128Shx147065 27524128Shx147065 static int 27534128Shx147065 wpi_reset(wpi_sc_t *sc) 27544128Shx147065 { 27554128Shx147065 uint32_t tmp; 27564128Shx147065 int ntries; 27574128Shx147065 27584128Shx147065 /* clear any pending interrupts */ 27594128Shx147065 WPI_WRITE(sc, WPI_INTR, 0xffffffff); 27604128Shx147065 27614128Shx147065 tmp = WPI_READ(sc, WPI_PLL_CTL); 27624128Shx147065 WPI_WRITE(sc, WPI_PLL_CTL, tmp | WPI_PLL_INIT); 27634128Shx147065 27644128Shx147065 tmp = WPI_READ(sc, WPI_CHICKEN); 27654128Shx147065 WPI_WRITE(sc, WPI_CHICKEN, tmp | WPI_CHICKEN_RXNOLOS); 27664128Shx147065 27674128Shx147065 tmp = WPI_READ(sc, WPI_GPIO_CTL); 27684128Shx147065 WPI_WRITE(sc, WPI_GPIO_CTL, tmp | WPI_GPIO_INIT); 27694128Shx147065 27704128Shx147065 /* wait for clock stabilization */ 27714128Shx147065 for (ntries = 0; ntries < 1000; ntries++) { 27724128Shx147065 if (WPI_READ(sc, WPI_GPIO_CTL) & WPI_GPIO_CLOCK) 27734128Shx147065 break; 27744128Shx147065 DELAY(10); 27754128Shx147065 } 27764128Shx147065 if (ntries == 1000) { 27774128Shx147065 cmn_err(CE_WARN, 27784128Shx147065 "wpi_reset(): timeout waiting for clock stabilization\n"); 27794128Shx147065 return (ETIMEDOUT); 27804128Shx147065 } 27814128Shx147065 27824128Shx147065 /* initialize EEPROM */ 27834128Shx147065 tmp = WPI_READ(sc, WPI_EEPROM_STATUS); 27844128Shx147065 if ((tmp & WPI_EEPROM_VERSION) == 0) { 27854128Shx147065 cmn_err(CE_WARN, "wpi_reset(): EEPROM not found\n"); 27864128Shx147065 return (EIO); 27874128Shx147065 } 27884128Shx147065 WPI_WRITE(sc, WPI_EEPROM_STATUS, tmp & ~WPI_EEPROM_LOCKED); 27894128Shx147065 27904128Shx147065 return (WPI_SUCCESS); 27914128Shx147065 } 27924128Shx147065 27934128Shx147065 static void 27944128Shx147065 wpi_hw_config(wpi_sc_t *sc) 27954128Shx147065 { 27964128Shx147065 uint16_t val; 27974128Shx147065 uint32_t hw; 27984128Shx147065 27994128Shx147065 /* voodoo from the Linux "driver".. */ 28004128Shx147065 hw = WPI_READ(sc, WPI_HWCONFIG); 28014128Shx147065 28024128Shx147065 if ((sc->sc_rev & 0xc0) == 0x40) 28034128Shx147065 hw |= WPI_HW_ALM_MB; 28044128Shx147065 else if (!(sc->sc_rev & 0x80)) 28054128Shx147065 hw |= WPI_HW_ALM_MM; 28064128Shx147065 28074128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_CAPABILITIES); 28084128Shx147065 if ((val & 0xff) == 0x80) 28094128Shx147065 hw |= WPI_HW_SKU_MRC; 28104128Shx147065 28114128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_REVISION); 28124128Shx147065 hw &= ~WPI_HW_REV_D; 28134128Shx147065 if ((val & 0xf0) == 0xd0) 28144128Shx147065 hw |= WPI_HW_REV_D; 28154128Shx147065 28164128Shx147065 val = wpi_read_prom_word(sc, WPI_EEPROM_TYPE); 28174128Shx147065 if ((val & 0xff) > 1) 28184128Shx147065 hw |= WPI_HW_TYPE_B; 28194128Shx147065 28204128Shx147065 WPI_DBG((WPI_DEBUG_HW, "setting h/w config %x\n", hw)); 28214128Shx147065 WPI_WRITE(sc, WPI_HWCONFIG, hw); 28224128Shx147065 } 28234128Shx147065 28244128Shx147065 static int 28254128Shx147065 wpi_init(wpi_sc_t *sc) 28264128Shx147065 { 28274128Shx147065 uint32_t tmp; 28284128Shx147065 int qid, ntries, err; 28294128Shx147065 clock_t clk; 28304128Shx147065 28314128Shx147065 mutex_enter(&sc->sc_glock); 28324128Shx147065 sc->sc_flags &= ~WPI_F_FW_INIT; 28334128Shx147065 28344128Shx147065 (void) wpi_reset(sc); 28354128Shx147065 28364128Shx147065 wpi_mem_lock(sc); 28374128Shx147065 wpi_mem_write(sc, WPI_MEM_CLOCK1, 0xa00); 28384128Shx147065 DELAY(20); 28394128Shx147065 tmp = wpi_mem_read(sc, WPI_MEM_PCIDEV); 28404128Shx147065 wpi_mem_write(sc, WPI_MEM_PCIDEV, tmp | 0x800); 28414128Shx147065 wpi_mem_unlock(sc); 28424128Shx147065 28434128Shx147065 (void) wpi_power_up(sc); 28444128Shx147065 wpi_hw_config(sc); 28454128Shx147065 28464128Shx147065 /* init Rx ring */ 28474128Shx147065 wpi_mem_lock(sc); 28484128Shx147065 WPI_WRITE(sc, WPI_RX_BASE, sc->sc_rxq.dma_desc.cookie.dmac_address); 28494128Shx147065 WPI_WRITE(sc, WPI_RX_RIDX_PTR, 28504128Shx147065 (uint32_t)(sc->sc_dma_sh.cookie.dmac_address + 28514128Shx147065 offsetof(wpi_shared_t, next))); 28524128Shx147065 WPI_WRITE(sc, WPI_RX_WIDX, (WPI_RX_RING_COUNT - 1) & (~7)); 28534128Shx147065 WPI_WRITE(sc, WPI_RX_CONFIG, 0xa9601010); 28544128Shx147065 wpi_mem_unlock(sc); 28554128Shx147065 28564128Shx147065 /* init Tx rings */ 28574128Shx147065 wpi_mem_lock(sc); 28584128Shx147065 wpi_mem_write(sc, WPI_MEM_MODE, 2); /* bypass mode */ 28594128Shx147065 wpi_mem_write(sc, WPI_MEM_RA, 1); /* enable RA0 */ 28604128Shx147065 wpi_mem_write(sc, WPI_MEM_TXCFG, 0x3f); /* enable all 6 Tx rings */ 28614128Shx147065 wpi_mem_write(sc, WPI_MEM_BYPASS1, 0x10000); 28624128Shx147065 wpi_mem_write(sc, WPI_MEM_BYPASS2, 0x30002); 28634128Shx147065 wpi_mem_write(sc, WPI_MEM_MAGIC4, 4); 28644128Shx147065 wpi_mem_write(sc, WPI_MEM_MAGIC5, 5); 28654128Shx147065 28664128Shx147065 WPI_WRITE(sc, WPI_TX_BASE_PTR, sc->sc_dma_sh.cookie.dmac_address); 28674128Shx147065 WPI_WRITE(sc, WPI_MSG_CONFIG, 0xffff05a5); 28684128Shx147065 28694128Shx147065 for (qid = 0; qid < 6; qid++) { 28704128Shx147065 WPI_WRITE(sc, WPI_TX_CTL(qid), 0); 28714128Shx147065 WPI_WRITE(sc, WPI_TX_BASE(qid), 0); 28724128Shx147065 WPI_WRITE(sc, WPI_TX_CONFIG(qid), 0x80200008); 28734128Shx147065 } 28744128Shx147065 wpi_mem_unlock(sc); 28754128Shx147065 28764128Shx147065 /* clear "radio off" and "disable command" bits (reversed logic) */ 28774128Shx147065 WPI_WRITE(sc, WPI_UCODE_CLR, WPI_RADIO_OFF); 28784128Shx147065 WPI_WRITE(sc, WPI_UCODE_CLR, WPI_DISABLE_CMD); 28794128Shx147065 28804128Shx147065 /* clear any pending interrupts */ 28814128Shx147065 WPI_WRITE(sc, WPI_INTR, 0xffffffff); 28824128Shx147065 28834128Shx147065 /* enable interrupts */ 28844128Shx147065 WPI_WRITE(sc, WPI_MASK, WPI_INTR_MASK); 28854128Shx147065 28864128Shx147065 /* load firmware boot code into NIC */ 28874128Shx147065 err = wpi_load_microcode(sc); 28884128Shx147065 if (err != WPI_SUCCESS) { 28894128Shx147065 cmn_err(CE_WARN, "wpi_init(): failed to load microcode\n"); 28904128Shx147065 goto fail1; 28914128Shx147065 } 28924128Shx147065 28934128Shx147065 /* load firmware .text segment into NIC */ 28944128Shx147065 err = wpi_load_firmware(sc, WPI_FW_TEXT); 28954128Shx147065 if (err != WPI_SUCCESS) { 28964128Shx147065 cmn_err(CE_WARN, "wpi_init(): " 28974128Shx147065 "failed to load firmware(text)\n"); 28984128Shx147065 goto fail1; 28994128Shx147065 } 29004128Shx147065 29014128Shx147065 /* load firmware .data segment into NIC */ 29024128Shx147065 err = wpi_load_firmware(sc, WPI_FW_DATA); 29034128Shx147065 if (err != WPI_SUCCESS) { 29044128Shx147065 cmn_err(CE_WARN, "wpi_init(): " 29054128Shx147065 "failed to load firmware(data)\n"); 29064128Shx147065 goto fail1; 29074128Shx147065 } 29084128Shx147065 29094128Shx147065 /* now press "execute" ;-) */ 29104128Shx147065 tmp = WPI_READ(sc, WPI_RESET); 29114128Shx147065 tmp &= ~(WPI_MASTER_DISABLED | WPI_STOP_MASTER | WPI_NEVO_RESET); 29124128Shx147065 WPI_WRITE(sc, WPI_RESET, tmp); 29134128Shx147065 29144128Shx147065 /* ..and wait at most one second for adapter to initialize */ 29154128Shx147065 clk = ddi_get_lbolt() + drv_usectohz(2000000); 29164128Shx147065 while (!(sc->sc_flags & WPI_F_FW_INIT)) { 29174128Shx147065 if (cv_timedwait(&sc->sc_fw_cv, &sc->sc_glock, clk) < 0) 29184128Shx147065 break; 29194128Shx147065 } 29204128Shx147065 if (!(sc->sc_flags & WPI_F_FW_INIT)) { 29214128Shx147065 cmn_err(CE_WARN, 29224128Shx147065 "wpi_init(): timeout waiting for firmware init\n"); 29234128Shx147065 goto fail1; 29244128Shx147065 } 29254128Shx147065 29264128Shx147065 /* wait for thermal sensors to calibrate */ 29274128Shx147065 for (ntries = 0; ntries < 1000; ntries++) { 29284128Shx147065 if (WPI_READ(sc, WPI_TEMPERATURE) != 0) 29294128Shx147065 break; 29304128Shx147065 DELAY(10); 29314128Shx147065 } 29324128Shx147065 29334128Shx147065 if (ntries == 1000) { 29344128Shx147065 WPI_DBG((WPI_DEBUG_HW, 29354128Shx147065 "wpi_init(): timeout waiting for thermal sensors " 29364128Shx147065 "calibration\n")); 29374128Shx147065 } 29384128Shx147065 29394128Shx147065 WPI_DBG((WPI_DEBUG_HW, "temperature %d\n", 29404128Shx147065 (int)WPI_READ(sc, WPI_TEMPERATURE))); 29414128Shx147065 29424128Shx147065 err = wpi_config(sc); 29434128Shx147065 if (err) { 29444128Shx147065 cmn_err(CE_WARN, "wpi_init(): failed to configure device\n"); 29454128Shx147065 goto fail1; 29464128Shx147065 } 29474128Shx147065 29484128Shx147065 mutex_exit(&sc->sc_glock); 29494128Shx147065 return (WPI_SUCCESS); 29504128Shx147065 29514128Shx147065 fail1: 29524128Shx147065 err = WPI_FAIL; 29534128Shx147065 mutex_exit(&sc->sc_glock); 29544128Shx147065 return (err); 29554128Shx147065 } 29564128Shx147065 29574128Shx147065 static void 29584128Shx147065 wpi_stop(wpi_sc_t *sc) 29594128Shx147065 { 29604128Shx147065 uint32_t tmp; 29614128Shx147065 int ac; 29624128Shx147065 29634128Shx147065 29644128Shx147065 mutex_enter(&sc->sc_glock); 29654128Shx147065 /* disable interrupts */ 29664128Shx147065 WPI_WRITE(sc, WPI_MASK, 0); 29674128Shx147065 WPI_WRITE(sc, WPI_INTR, WPI_INTR_MASK); 29684128Shx147065 WPI_WRITE(sc, WPI_INTR_STATUS, 0xff); 29694128Shx147065 WPI_WRITE(sc, WPI_INTR_STATUS, 0x00070000); 29704128Shx147065 29714128Shx147065 wpi_mem_lock(sc); 29724128Shx147065 wpi_mem_write(sc, WPI_MEM_MODE, 0); 29734128Shx147065 wpi_mem_unlock(sc); 29744128Shx147065 29754128Shx147065 /* reset all Tx rings */ 29764128Shx147065 for (ac = 0; ac < 4; ac++) 29774128Shx147065 wpi_reset_tx_ring(sc, &sc->sc_txq[ac]); 29784128Shx147065 wpi_reset_tx_ring(sc, &sc->sc_cmdq); 29794128Shx147065 wpi_reset_tx_ring(sc, &sc->sc_svcq); 29804128Shx147065 29814128Shx147065 /* reset Rx ring */ 29824128Shx147065 wpi_reset_rx_ring(sc); 29834128Shx147065 29844128Shx147065 wpi_mem_lock(sc); 29854128Shx147065 wpi_mem_write(sc, WPI_MEM_CLOCK2, 0x200); 29864128Shx147065 wpi_mem_unlock(sc); 29874128Shx147065 29884128Shx147065 DELAY(5); 29894128Shx147065 29904128Shx147065 wpi_stop_master(sc); 29914128Shx147065 29924128Shx147065 sc->sc_tx_timer = 0; 29934128Shx147065 tmp = WPI_READ(sc, WPI_RESET); 29944128Shx147065 WPI_WRITE(sc, WPI_RESET, tmp | WPI_SW_RESET); 29954128Shx147065 mutex_exit(&sc->sc_glock); 29964128Shx147065 } 29974128Shx147065 29984128Shx147065 /* 29994128Shx147065 * Naive implementation of the Adaptive Multi Rate Retry algorithm: 30004128Shx147065 * "IEEE 802.11 Rate Adaptation: A Practical Approach" 30014128Shx147065 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti 30024128Shx147065 * INRIA Sophia - Projet Planete 30034128Shx147065 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html 30044128Shx147065 */ 30054128Shx147065 #define is_success(amrr) \ 30064128Shx147065 ((amrr)->retrycnt < (amrr)->txcnt / 10) 30074128Shx147065 #define is_failure(amrr) \ 30084128Shx147065 ((amrr)->retrycnt > (amrr)->txcnt / 3) 30094128Shx147065 #define is_enough(amrr) \ 30104128Shx147065 ((amrr)->txcnt > 100) 30114128Shx147065 #define is_min_rate(in) \ 30124128Shx147065 ((in)->in_txrate == 0) 30134128Shx147065 #define is_max_rate(in) \ 30144128Shx147065 ((in)->in_txrate == (in)->in_rates.ir_nrates - 1) 30154128Shx147065 #define increase_rate(in) \ 30164128Shx147065 ((in)->in_txrate++) 30174128Shx147065 #define decrease_rate(in) \ 30184128Shx147065 ((in)->in_txrate--) 30194128Shx147065 #define reset_cnt(amrr) \ 30204128Shx147065 { (amrr)->txcnt = (amrr)->retrycnt = 0; } 30214128Shx147065 30224128Shx147065 #define WPI_AMRR_MIN_SUCCESS_THRESHOLD 1 30234128Shx147065 #define WPI_AMRR_MAX_SUCCESS_THRESHOLD 15 30244128Shx147065 30254128Shx147065 static void 30264128Shx147065 wpi_amrr_init(wpi_amrr_t *amrr) 30274128Shx147065 { 30284128Shx147065 amrr->success = 0; 30294128Shx147065 amrr->recovery = 0; 30304128Shx147065 amrr->txcnt = amrr->retrycnt = 0; 30314128Shx147065 amrr->success_threshold = WPI_AMRR_MIN_SUCCESS_THRESHOLD; 30324128Shx147065 } 30334128Shx147065 30344128Shx147065 static void 30354128Shx147065 wpi_amrr_timeout(wpi_sc_t *sc) 30364128Shx147065 { 30374128Shx147065 ieee80211com_t *ic = &sc->sc_ic; 30384128Shx147065 30394128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, "wpi_amrr_timeout() enter\n")); 30404128Shx147065 if (ic->ic_opmode == IEEE80211_M_STA) 30414128Shx147065 wpi_amrr_ratectl(NULL, ic->ic_bss); 30424128Shx147065 else 30434128Shx147065 ieee80211_iterate_nodes(&ic->ic_sta, wpi_amrr_ratectl, NULL); 30444128Shx147065 sc->sc_clk = ddi_get_lbolt(); 30454128Shx147065 } 30464128Shx147065 30474128Shx147065 /* ARGSUSED */ 30484128Shx147065 static void 30494128Shx147065 wpi_amrr_ratectl(void *arg, ieee80211_node_t *in) 30504128Shx147065 { 30514128Shx147065 wpi_amrr_t *amrr = (wpi_amrr_t *)in; 30524128Shx147065 int need_change = 0; 30534128Shx147065 30544128Shx147065 if (is_success(amrr) && is_enough(amrr)) { 30554128Shx147065 amrr->success++; 30564128Shx147065 if (amrr->success >= amrr->success_threshold && 30574128Shx147065 !is_max_rate(in)) { 30584128Shx147065 amrr->recovery = 1; 30594128Shx147065 amrr->success = 0; 30604128Shx147065 increase_rate(in); 30614128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, 30624128Shx147065 "AMRR increasing rate %d (txcnt=%d retrycnt=%d)\n", 30634128Shx147065 in->in_txrate, amrr->txcnt, amrr->retrycnt)); 30644128Shx147065 need_change = 1; 30654128Shx147065 } else { 30664128Shx147065 amrr->recovery = 0; 30674128Shx147065 } 30684128Shx147065 } else if (is_failure(amrr)) { 30694128Shx147065 amrr->success = 0; 30704128Shx147065 if (!is_min_rate(in)) { 30714128Shx147065 if (amrr->recovery) { 30724128Shx147065 amrr->success_threshold++; 30734128Shx147065 if (amrr->success_threshold > 30744128Shx147065 WPI_AMRR_MAX_SUCCESS_THRESHOLD) 30754128Shx147065 amrr->success_threshold = 30764128Shx147065 WPI_AMRR_MAX_SUCCESS_THRESHOLD; 30774128Shx147065 } else { 30784128Shx147065 amrr->success_threshold = 30794128Shx147065 WPI_AMRR_MIN_SUCCESS_THRESHOLD; 30804128Shx147065 } 30814128Shx147065 decrease_rate(in); 30824128Shx147065 WPI_DBG((WPI_DEBUG_RATECTL, 30834128Shx147065 "AMRR decreasing rate %d (txcnt=%d retrycnt=%d)\n", 30844128Shx147065 in->in_txrate, amrr->txcnt, amrr->retrycnt)); 30854128Shx147065 need_change = 1; 30864128Shx147065 } 30874128Shx147065 amrr->recovery = 0; /* paper is incorrect */ 30884128Shx147065 } 30894128Shx147065 30904128Shx147065 if (is_enough(amrr) || need_change) 30914128Shx147065 reset_cnt(amrr); 30924128Shx147065 } 3093