1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * EHCI Host Controller Driver (EHCI) 31 * 32 * The EHCI driver is a software driver which interfaces to the Universal 33 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 34 * the Host Controller is defined by the EHCI Host Controller Interface. 35 * 36 * This module contains the main EHCI driver code which handles all USB 37 * transfers, bandwidth allocations and other general functionalities. 38 */ 39 40 #include <sys/usb/hcd/ehci/ehcid.h> 41 #include <sys/usb/hcd/ehci/ehci_isoch.h> 42 #include <sys/usb/hcd/ehci/ehci_xfer.h> 43 44 /* Pointer to the state structure */ 45 extern void *ehci_statep; 46 47 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 48 49 extern uint_t ehci_vt62x2_workaround; 50 51 /* Adjustable variables for the size of the pools */ 52 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 53 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 54 55 /* 56 * Initialize the values which the order of 32ms intr qh are executed 57 * by the host controller in the lattice tree. 58 */ 59 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 60 {0x00, 0x10, 0x08, 0x18, 61 0x04, 0x14, 0x0c, 0x1c, 62 0x02, 0x12, 0x0a, 0x1a, 63 0x06, 0x16, 0x0e, 0x1e, 64 0x01, 0x11, 0x09, 0x19, 65 0x05, 0x15, 0x0d, 0x1d, 66 0x03, 0x13, 0x0b, 0x1b, 67 0x07, 0x17, 0x0f, 0x1f}; 68 69 /* 70 * Initialize the values which are used to calculate start split mask 71 * for the low/full/high speed interrupt and isochronous endpoints. 72 */ 73 static uint_t ehci_start_split_mask[15] = { 74 /* 75 * For high/full/low speed usb devices. For high speed 76 * device with polling interval greater than or equal 77 * to 8us (125us). 78 */ 79 0x01, /* 00000001 */ 80 0x02, /* 00000010 */ 81 0x04, /* 00000100 */ 82 0x08, /* 00001000 */ 83 0x10, /* 00010000 */ 84 0x20, /* 00100000 */ 85 0x40, /* 01000000 */ 86 0x80, /* 10000000 */ 87 88 /* Only for high speed devices with polling interval 4us */ 89 0x11, /* 00010001 */ 90 0x22, /* 00100010 */ 91 0x44, /* 01000100 */ 92 0x88, /* 10001000 */ 93 94 /* Only for high speed devices with polling interval 2us */ 95 0x55, /* 01010101 */ 96 0xaa, /* 10101010 */ 97 98 /* Only for high speed devices with polling interval 1us */ 99 0xff /* 11111111 */ 100 }; 101 102 /* 103 * Initialize the values which are used to calculate complete split mask 104 * for the low/full speed interrupt and isochronous endpoints. 105 */ 106 static uint_t ehci_intr_complete_split_mask[7] = { 107 /* Only full/low speed devices */ 108 0x1c, /* 00011100 */ 109 0x38, /* 00111000 */ 110 0x70, /* 01110000 */ 111 0xe0, /* 11100000 */ 112 0x00, /* Need FSTN feature */ 113 0x00, /* Need FSTN feature */ 114 0x00 /* Need FSTN feature */ 115 }; 116 117 118 /* 119 * EHCI Internal Function Prototypes 120 */ 121 122 /* Host Controller Driver (HCD) initialization functions */ 123 void ehci_set_dma_attributes(ehci_state_t *ehcip); 124 int ehci_allocate_pools(ehci_state_t *ehcip); 125 void ehci_decode_ddi_dma_addr_bind_handle_result( 126 ehci_state_t *ehcip, 127 int result); 128 int ehci_map_regs(ehci_state_t *ehcip); 129 int ehci_register_intrs_and_init_mutex( 130 ehci_state_t *ehcip); 131 int ehci_init_ctlr(ehci_state_t *ehcip); 132 static int ehci_take_control(ehci_state_t *ehcip); 133 static int ehci_init_periodic_frame_lst_table( 134 ehci_state_t *ehcip); 135 static void ehci_build_interrupt_lattice( 136 ehci_state_t *ehcip); 137 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 138 139 /* Host Controller Driver (HCD) deinitialization functions */ 140 int ehci_cleanup(ehci_state_t *ehcip); 141 int ehci_cpr_suspend(ehci_state_t *ehcip); 142 int ehci_cpr_resume(ehci_state_t *ehcip); 143 144 /* Bandwidth Allocation functions */ 145 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 146 usba_pipe_handle_data_t *ph, 147 uint_t *pnode, 148 uchar_t *smask, 149 uchar_t *cmask); 150 static int ehci_allocate_high_speed_bandwidth( 151 ehci_state_t *ehcip, 152 usba_pipe_handle_data_t *ph, 153 uint_t *hnode, 154 uchar_t *smask, 155 uchar_t *cmask); 156 static int ehci_allocate_classic_tt_bandwidth( 157 ehci_state_t *ehcip, 158 usba_pipe_handle_data_t *ph, 159 uint_t pnode); 160 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 161 usba_pipe_handle_data_t *ph, 162 uint_t pnode, 163 uchar_t smask, 164 uchar_t cmask); 165 static void ehci_deallocate_high_speed_bandwidth( 166 ehci_state_t *ehcip, 167 usba_pipe_handle_data_t *ph, 168 uint_t hnode, 169 uchar_t smask, 170 uchar_t cmask); 171 static void ehci_deallocate_classic_tt_bandwidth( 172 ehci_state_t *ehcip, 173 usba_pipe_handle_data_t *ph, 174 uint_t pnode); 175 static int ehci_compute_high_speed_bandwidth( 176 ehci_state_t *ehcip, 177 usb_ep_descr_t *endpoint, 178 usb_port_status_t port_status, 179 uint_t *sbandwidth, 180 uint_t *cbandwidth); 181 static int ehci_compute_classic_bandwidth( 182 usb_ep_descr_t *endpoint, 183 usb_port_status_t port_status, 184 uint_t *bandwidth); 185 int ehci_adjust_polling_interval( 186 ehci_state_t *ehcip, 187 usb_ep_descr_t *endpoint, 188 usb_port_status_t port_status); 189 static int ehci_adjust_high_speed_polling_interval( 190 ehci_state_t *ehcip, 191 usb_ep_descr_t *endpoint); 192 static uint_t ehci_lattice_height(uint_t interval); 193 static uint_t ehci_lattice_parent(uint_t node); 194 static uint_t ehci_find_periodic_node( 195 uint_t leaf, 196 int interval); 197 static uint_t ehci_leftmost_leaf(uint_t node, 198 uint_t height); 199 static uint_t ehci_pow_2(uint_t x); 200 static uint_t ehci_log_2(uint_t x); 201 static int ehci_find_bestfit_hs_mask( 202 ehci_state_t *ehcip, 203 uchar_t *smask, 204 uint_t *pnode, 205 usb_ep_descr_t *endpoint, 206 uint_t bandwidth, 207 int interval); 208 static int ehci_find_bestfit_ls_intr_mask( 209 ehci_state_t *ehcip, 210 uchar_t *smask, 211 uchar_t *cmask, 212 uint_t *pnode, 213 uint_t sbandwidth, 214 uint_t cbandwidth, 215 int interval); 216 static int ehci_find_bestfit_sitd_in_mask( 217 ehci_state_t *ehcip, 218 uchar_t *smask, 219 uchar_t *cmask, 220 uint_t *pnode, 221 uint_t sbandwidth, 222 uint_t cbandwidth, 223 int interval); 224 static int ehci_find_bestfit_sitd_out_mask( 225 ehci_state_t *ehcip, 226 uchar_t *smask, 227 uint_t *pnode, 228 uint_t sbandwidth, 229 int interval); 230 static uint_t ehci_calculate_bw_availability_mask( 231 ehci_state_t *ehcip, 232 uint_t bandwidth, 233 int leaf, 234 int leaf_count, 235 uchar_t *bw_mask); 236 static void ehci_update_bw_availability( 237 ehci_state_t *ehcip, 238 int bandwidth, 239 int leftmost_leaf, 240 int leaf_count, 241 uchar_t mask); 242 243 /* Miscellaneous functions */ 244 ehci_state_t *ehci_obtain_state( 245 dev_info_t *dip); 246 int ehci_state_is_operational( 247 ehci_state_t *ehcip); 248 int ehci_do_soft_reset( 249 ehci_state_t *ehcip); 250 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 251 ehci_pipe_private_t *pp, 252 ehci_trans_wrapper_t *tw); 253 usb_frame_number_t ehci_get_current_frame_number( 254 ehci_state_t *ehcip); 255 static void ehci_cpr_cleanup( 256 ehci_state_t *ehcip); 257 int ehci_wait_for_sof( 258 ehci_state_t *ehcip); 259 void ehci_toggle_scheduler( 260 ehci_state_t *ehcip); 261 void ehci_print_caps(ehci_state_t *ehcip); 262 void ehci_print_regs(ehci_state_t *ehcip); 263 void ehci_print_qh(ehci_state_t *ehcip, 264 ehci_qh_t *qh); 265 void ehci_print_qtd(ehci_state_t *ehcip, 266 ehci_qtd_t *qtd); 267 void ehci_create_stats(ehci_state_t *ehcip); 268 void ehci_destroy_stats(ehci_state_t *ehcip); 269 void ehci_do_intrs_stats(ehci_state_t *ehcip, 270 int val); 271 void ehci_do_byte_stats(ehci_state_t *ehcip, 272 size_t len, 273 uint8_t attr, 274 uint8_t addr); 275 276 /* 277 * check if this ehci controller can support PM 278 */ 279 int 280 ehci_hcdi_pm_support(dev_info_t *dip) 281 { 282 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 283 ddi_get_instance(dip)); 284 285 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 286 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 287 288 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 289 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 290 291 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 292 293 return (USB_SUCCESS); 294 } 295 296 return (USB_FAILURE); 297 } 298 299 300 /* 301 * Host Controller Driver (HCD) initialization functions 302 */ 303 304 /* 305 * ehci_set_dma_attributes: 306 * 307 * Set the limits in the DMA attributes structure. Most of the values used 308 * in the DMA limit structures are the default values as specified by the 309 * Writing PCI device drivers document. 310 */ 311 void 312 ehci_set_dma_attributes(ehci_state_t *ehcip) 313 { 314 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 315 "ehci_set_dma_attributes:"); 316 317 /* Initialize the DMA attributes */ 318 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 319 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 320 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 321 322 /* 32 bit addressing */ 323 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 324 325 /* Byte alignment */ 326 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 327 328 /* 329 * Since PCI specification is byte alignment, the 330 * burst size field should be set to 1 for PCI devices. 331 */ 332 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 333 334 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 335 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 336 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 337 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 338 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 339 ehcip->ehci_dma_attr.dma_attr_flags = 0; 340 } 341 342 343 /* 344 * ehci_allocate_pools: 345 * 346 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 347 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 348 * to a 16 byte boundary. 349 */ 350 int 351 ehci_allocate_pools(ehci_state_t *ehcip) 352 { 353 ddi_device_acc_attr_t dev_attr; 354 size_t real_length; 355 int result; 356 uint_t ccount; 357 int i; 358 359 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 360 "ehci_allocate_pools:"); 361 362 /* The host controller will be little endian */ 363 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 364 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 365 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 366 367 /* Byte alignment */ 368 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 369 370 /* Allocate the QTD pool DMA handle */ 371 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 372 DDI_DMA_SLEEP, 0, 373 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 374 375 goto failure; 376 } 377 378 /* Allocate the memory for the QTD pool */ 379 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 380 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 381 &dev_attr, 382 DDI_DMA_CONSISTENT, 383 DDI_DMA_SLEEP, 384 0, 385 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 386 &real_length, 387 &ehcip->ehci_qtd_pool_mem_handle)) { 388 389 goto failure; 390 } 391 392 /* Map the QTD pool into the I/O address space */ 393 result = ddi_dma_addr_bind_handle( 394 ehcip->ehci_qtd_pool_dma_handle, 395 NULL, 396 (caddr_t)ehcip->ehci_qtd_pool_addr, 397 real_length, 398 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 399 DDI_DMA_SLEEP, 400 NULL, 401 &ehcip->ehci_qtd_pool_cookie, 402 &ccount); 403 404 bzero((void *)ehcip->ehci_qtd_pool_addr, 405 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 406 407 /* Process the result */ 408 if (result == DDI_DMA_MAPPED) { 409 /* The cookie count should be 1 */ 410 if (ccount != 1) { 411 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 412 "ehci_allocate_pools: More than 1 cookie"); 413 414 goto failure; 415 } 416 } else { 417 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 418 "ehci_allocate_pools: Result = %d", result); 419 420 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 421 422 goto failure; 423 } 424 425 /* 426 * DMA addresses for QTD pools are bound 427 */ 428 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 429 430 /* Initialize the QTD pool */ 431 for (i = 0; i < ehci_qtd_pool_size; i ++) { 432 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 433 qtd_state, EHCI_QTD_FREE); 434 } 435 436 /* Allocate the QTD pool DMA handle */ 437 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 438 &ehcip->ehci_dma_attr, 439 DDI_DMA_SLEEP, 440 0, 441 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 442 443 goto failure; 444 } 445 446 /* Allocate the memory for the QH pool */ 447 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 448 ehci_qh_pool_size * sizeof (ehci_qh_t), 449 &dev_attr, 450 DDI_DMA_CONSISTENT, 451 DDI_DMA_SLEEP, 452 0, 453 (caddr_t *)&ehcip->ehci_qh_pool_addr, 454 &real_length, 455 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 456 457 goto failure; 458 } 459 460 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 461 NULL, 462 (caddr_t)ehcip->ehci_qh_pool_addr, 463 real_length, 464 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 465 DDI_DMA_SLEEP, 466 NULL, 467 &ehcip->ehci_qh_pool_cookie, 468 &ccount); 469 470 bzero((void *)ehcip->ehci_qh_pool_addr, 471 ehci_qh_pool_size * sizeof (ehci_qh_t)); 472 473 /* Process the result */ 474 if (result == DDI_DMA_MAPPED) { 475 /* The cookie count should be 1 */ 476 if (ccount != 1) { 477 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 478 "ehci_allocate_pools: More than 1 cookie"); 479 480 goto failure; 481 } 482 } else { 483 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 484 485 goto failure; 486 } 487 488 /* 489 * DMA addresses for QH pools are bound 490 */ 491 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 492 493 /* Initialize the QH pool */ 494 for (i = 0; i < ehci_qh_pool_size; i ++) { 495 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 496 } 497 498 /* Byte alignment */ 499 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 500 501 return (DDI_SUCCESS); 502 503 failure: 504 /* Byte alignment */ 505 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 506 507 return (DDI_FAILURE); 508 } 509 510 511 /* 512 * ehci_decode_ddi_dma_addr_bind_handle_result: 513 * 514 * Process the return values of ddi_dma_addr_bind_handle() 515 */ 516 void 517 ehci_decode_ddi_dma_addr_bind_handle_result( 518 ehci_state_t *ehcip, 519 int result) 520 { 521 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 522 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 523 524 switch (result) { 525 case DDI_DMA_PARTIAL_MAP: 526 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 527 "Partial transfers not allowed"); 528 break; 529 case DDI_DMA_INUSE: 530 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 531 "Handle is in use"); 532 break; 533 case DDI_DMA_NORESOURCES: 534 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 535 "No resources"); 536 break; 537 case DDI_DMA_NOMAPPING: 538 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 539 "No mapping"); 540 break; 541 case DDI_DMA_TOOBIG: 542 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 543 "Object is too big"); 544 break; 545 default: 546 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 547 "Unknown dma error"); 548 } 549 } 550 551 552 /* 553 * ehci_map_regs: 554 * 555 * The Host Controller (HC) contains a set of on-chip operational registers 556 * and which should be mapped into a non-cacheable portion of the system 557 * addressable space. 558 */ 559 int 560 ehci_map_regs(ehci_state_t *ehcip) 561 { 562 ddi_device_acc_attr_t attr; 563 uint16_t cmd_reg; 564 uint_t length; 565 566 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 567 568 /* Check to make sure we have memory access */ 569 if (pci_config_setup(ehcip->ehci_dip, 570 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 571 572 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 573 "ehci_map_regs: Config error"); 574 575 return (DDI_FAILURE); 576 } 577 578 /* Make sure Memory Access Enable is set */ 579 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 580 581 if (!(cmd_reg & PCI_COMM_MAE)) { 582 583 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 584 "ehci_map_regs: Memory base address access disabled"); 585 586 return (DDI_FAILURE); 587 } 588 589 /* The host controller will be little endian */ 590 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 591 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 592 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 593 594 /* Map in EHCI Capability registers */ 595 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 596 (caddr_t *)&ehcip->ehci_capsp, 0, 597 sizeof (ehci_caps_t), &attr, 598 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 599 600 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 601 "ehci_map_regs: Map setup error"); 602 603 return (DDI_FAILURE); 604 } 605 606 length = ddi_get8(ehcip->ehci_caps_handle, 607 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 608 609 /* Free the original mapping */ 610 ddi_regs_map_free(&ehcip->ehci_caps_handle); 611 612 /* Re-map in EHCI Capability and Operational registers */ 613 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 614 (caddr_t *)&ehcip->ehci_capsp, 0, 615 length + sizeof (ehci_regs_t), &attr, 616 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 617 618 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 619 "ehci_map_regs: Map setup error"); 620 621 return (DDI_FAILURE); 622 } 623 624 /* Get the pointer to EHCI Operational Register */ 625 ehcip->ehci_regsp = (ehci_regs_t *) 626 ((uintptr_t)ehcip->ehci_capsp + length); 627 628 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 629 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 630 ehcip->ehci_capsp, ehcip->ehci_regsp); 631 632 return (DDI_SUCCESS); 633 } 634 635 636 /* 637 * ehci_register_intrs_and_init_mutex: 638 * 639 * Register interrupts and initialize each mutex and condition variables 640 */ 641 int 642 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 643 { 644 int type, count = 0, actual, ret; 645 646 #if defined(__x86) 647 uint8_t iline; 648 #endif 649 650 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 651 "ehci_register_intrs_and_init_mutex:"); 652 653 #if defined(__x86) 654 /* 655 * Make sure that the interrupt pin is connected to the 656 * interrupt controller on x86. Interrupt line 255 means 657 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 658 * If we would return failure when interrupt line equals 255, then 659 * high speed devices will be routed to companion host controllers. 660 * However, it is not necessary to return failure here, and 661 * o/uhci codes don't check the interrupt line either. 662 * But it's good to log a message here for debug purposes. 663 */ 664 iline = pci_config_get8(ehcip->ehci_config_handle, 665 PCI_CONF_ILINE); 666 667 if (iline == 255) { 668 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 669 "ehci_register_intrs_and_init_mutex: " 670 "interrupt line value out of range (%d)", 671 iline); 672 } 673 #endif /* __x86 */ 674 675 ret = ddi_intr_get_supported_types(ehcip->ehci_dip, &type); 676 677 if ((ret != DDI_SUCCESS) || (!(type & DDI_INTR_TYPE_FIXED))) { 678 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 679 "ehci_register_intrs_and_init_mutex: " 680 "Fixed type interrupt is not supported"); 681 682 return (DDI_FAILURE); 683 } 684 685 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, DDI_INTR_TYPE_FIXED, &count); 686 687 /* 688 * Fixed interrupts can only have one interrupt. Check to make 689 * sure that number of supported interrupts and number of 690 * available interrupts are both equal to 1. 691 */ 692 if ((ret != DDI_SUCCESS) || (count != 1)) { 693 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 694 "ehci_register_intrs_and_init_mutex: " 695 "no fixed interrupts"); 696 697 return (DDI_FAILURE); 698 } 699 700 ehcip->ehci_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP); 701 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 702 DDI_INTR_TYPE_FIXED, 0, count, &actual, 0); 703 704 if ((ret != DDI_SUCCESS) || (actual != 1)) { 705 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 706 "ehci_register_intrs_and_init_mutex: " 707 "ddi_intr_alloc() failed 0x%x", ret); 708 709 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 710 711 return (DDI_FAILURE); 712 } 713 714 /* Sanity check that count and avail are the same. */ 715 ASSERT(count == actual); 716 717 if (ddi_intr_get_pri(ehcip->ehci_htable[0], &ehcip->ehci_intr_pri)) { 718 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 719 "ehci_register_intrs_and_init_mutex: " 720 "ddi_intr_get_pri() failed"); 721 722 (void) ddi_intr_free(ehcip->ehci_htable[0]); 723 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 724 725 return (DDI_FAILURE); 726 } 727 728 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 729 "Supported Interrupt priority = 0x%x", ehcip->ehci_intr_pri); 730 731 /* Test for high level mutex */ 732 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 733 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 734 "ehci_register_intrs_and_init_mutex: " 735 "Hi level interrupt not supported"); 736 737 (void) ddi_intr_free(ehcip->ehci_htable[0]); 738 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 739 740 return (DDI_FAILURE); 741 } 742 743 /* Initialize the mutex */ 744 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 745 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 746 747 if (ddi_intr_add_handler(ehcip->ehci_htable[0], 748 (ddi_intr_handler_t *)ehci_intr, (caddr_t)ehcip, NULL) != 749 DDI_SUCCESS) { 750 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 751 "ehci_register_intrs_and_init_mutex: " 752 "ddi_intr_add_handler() failed"); 753 754 mutex_destroy(&ehcip->ehci_int_mutex); 755 (void) ddi_intr_free(ehcip->ehci_htable[0]); 756 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 757 758 return (DDI_FAILURE); 759 } 760 761 if (ddi_intr_enable(ehcip->ehci_htable[0]) != DDI_SUCCESS) { 762 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 763 "ehci_register_intrs_and_init_mutex: " 764 "ddi_intr_enable() failed"); 765 766 (void) ddi_intr_remove_handler(ehcip->ehci_htable[0]); 767 mutex_destroy(&ehcip->ehci_int_mutex); 768 (void) ddi_intr_free(ehcip->ehci_htable[0]); 769 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 770 771 return (DDI_FAILURE); 772 } 773 774 /* Create prototype for advance on async schedule */ 775 cv_init(&ehcip->ehci_async_schedule_advance_cv, 776 NULL, CV_DRIVER, NULL); 777 778 return (DDI_SUCCESS); 779 } 780 781 782 /* 783 * ehci_init_ctlr: 784 * 785 * Initialize the Host Controller (HC). 786 */ 787 int 788 ehci_init_ctlr(ehci_state_t *ehcip) 789 { 790 int revision; 791 uint16_t cmd_reg; 792 clock_t sof_time_wait; 793 int abort_on_BIOS_take_over_failure; 794 795 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 796 797 /* Take control from the BIOS */ 798 if (ehci_take_control(ehcip) != USB_SUCCESS) { 799 800 /* read .conf file properties */ 801 abort_on_BIOS_take_over_failure = 802 ddi_prop_get_int(DDI_DEV_T_ANY, 803 ehcip->ehci_dip, DDI_PROP_DONTPASS, 804 "abort-on-BIOS-take-over-failure", 0); 805 806 if (abort_on_BIOS_take_over_failure) { 807 808 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "Unable to take control from BIOS."); 810 811 return (DDI_FAILURE); 812 } 813 814 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 815 "Unable to take control from BIOS. Failure is ignored."); 816 } 817 818 /* set Memory Master Enable */ 819 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 820 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 821 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 822 823 /* Reset the EHCI host controller */ 824 Set_OpReg(ehci_command, 825 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 826 827 /* Wait 10ms for reset to complete */ 828 drv_usecwait(EHCI_RESET_TIMEWAIT); 829 830 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 831 832 /* Verify the version number */ 833 revision = Get_16Cap(ehci_version); 834 835 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 836 "ehci_init_ctlr: Revision 0x%x", revision); 837 838 /* 839 * EHCI driver supports EHCI host controllers compliant to 840 * 0.95 and higher revisions of EHCI specifications. 841 */ 842 if (revision < EHCI_REVISION_0_95) { 843 844 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "Revision 0x%x is not supported", revision); 846 847 return (DDI_FAILURE); 848 } 849 850 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 851 852 /* Get the ehci chip vendor and device id */ 853 ehcip->ehci_vendor_id = pci_config_get16( 854 ehcip->ehci_config_handle, PCI_CONF_VENID); 855 ehcip->ehci_device_id = pci_config_get16( 856 ehcip->ehci_config_handle, PCI_CONF_DEVID); 857 ehcip->ehci_rev_id = pci_config_get8( 858 ehcip->ehci_config_handle, PCI_CONF_REVID); 859 860 /* Initialize the Frame list base address area */ 861 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 862 863 return (DDI_FAILURE); 864 } 865 866 /* 867 * For performance reasons, do not insert anything into the 868 * asynchronous list or activate the asynch list schedule until 869 * there is a valid QH. 870 */ 871 ehcip->ehci_head_of_async_sched_list = NULL; 872 873 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 874 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 875 /* 876 * The driver is unable to reliably stop the asynch 877 * list schedule on VIA VT6202 controllers, so we 878 * always keep a dummy QH on the list. 879 */ 880 ehci_qh_t *dummy_async_qh = 881 ehci_alloc_qh(ehcip, NULL, NULL); 882 883 Set_QH(dummy_async_qh->qh_link_ptr, 884 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 885 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 886 887 /* Set this QH to be the "head" of the circular list */ 888 Set_QH(dummy_async_qh->qh_ctrl, 889 Get_QH(dummy_async_qh->qh_ctrl) | 890 EHCI_QH_CTRL_RECLAIM_HEAD); 891 892 Set_QH(dummy_async_qh->qh_next_qtd, 893 EHCI_QH_NEXT_QTD_PTR_VALID); 894 Set_QH(dummy_async_qh->qh_alt_next_qtd, 895 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 896 897 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 898 ehcip->ehci_open_async_count++; 899 } 900 } 901 902 /* 903 * Check for Asynchronous schedule park capability feature. If this 904 * feature is supported, then, program ehci command register with 905 * appropriate values.. 906 */ 907 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 908 909 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 910 "ehci_init_ctlr: Async park mode is supported"); 911 912 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 913 (EHCI_CMD_ASYNC_PARK_ENABLE | 914 EHCI_CMD_ASYNC_PARK_COUNT_3))); 915 } 916 917 /* 918 * Check for programmable periodic frame list feature. If this 919 * feature is supported, then, program ehci command register with 920 * 1024 frame list value. 921 */ 922 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 923 924 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 925 "ehci_init_ctlr: Variable programmable periodic " 926 "frame list is supported"); 927 928 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 929 EHCI_CMD_FRAME_1024_SIZE)); 930 } 931 932 /* 933 * Currently EHCI driver doesn't support 64 bit addressing. 934 * 935 * If we are using 64 bit addressing capability, then, program 936 * ehci_ctrl_segment register with 4 Gigabyte segment where all 937 * of the interface data structures are allocated. 938 */ 939 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 940 941 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 942 "ehci_init_ctlr: EHCI driver doesn't support " 943 "64 bit addressing"); 944 } 945 946 /* 64 bit addressing is not support */ 947 Set_OpReg(ehci_ctrl_segment, 0x00000000); 948 949 /* Turn on/off the schedulers */ 950 ehci_toggle_scheduler(ehcip); 951 952 /* 953 * Set the Periodic Frame List Base Address register with the 954 * starting physical address of the Periodic Frame List. 955 */ 956 Set_OpReg(ehci_periodic_list_base, 957 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 0xFFFFF000)); 958 959 /* 960 * Set ehci_interrupt to enable all interrupts except Root 961 * Hub Status change interrupt. 962 */ 963 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 964 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 965 EHCI_INTR_USB); 966 967 /* 968 * Set the desired interrupt threshold and turn on EHCI host controller. 969 */ 970 Set_OpReg(ehci_command, 971 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 972 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 973 974 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 975 976 /* 977 * Acer Labs Inc. M5273 EHCI controller does not send 978 * interrupts unless the Root hub ports are routed to the EHCI 979 * host controller; so route the ports now, before we test for 980 * the presence of SOFs interrupts. 981 */ 982 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 983 /* Route all Root hub ports to EHCI host controller */ 984 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 985 } 986 987 /* 988 * VIA chips have some issues and may not work reliably. 989 * Revisions >= 0x80 are part of a southbridge and appear 990 * to be reliable with the workaround. 991 * For revisions < 0x80, if we were bound using class 992 * complain, else proceed. This will allow the user to 993 * bind ehci specifically to this chip and not have the 994 * warnings 995 */ 996 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 997 998 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 999 1000 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1001 "ehci_init_ctlr: Applying VIA workarounds for " 1002 "the 6212 chip."); 1003 1004 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1005 "pciclass,0c0320") == 0) { 1006 1007 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1008 "Due to recently discovered incompatibilities"); 1009 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1010 "with this USB controller, USB2.x transfer"); 1011 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1012 "support has been disabled. This device will"); 1013 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1014 "continue to function as a USB1.x controller."); 1015 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1016 "If you are interested in enabling USB2.x"); 1017 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1018 "support please, refer to the ehci(7D) man page."); 1019 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1020 "Please also refer to www.sun.com/io for"); 1021 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1022 "Solaris Ready products and to"); 1023 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1024 "www.sun.com/bigadmin/hcl for additional"); 1025 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1026 "compatible USB products."); 1027 1028 return (DDI_FAILURE); 1029 1030 } else if (ehci_vt62x2_workaround) { 1031 1032 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1033 "Applying VIA workarounds"); 1034 } 1035 } 1036 1037 /* 1038 * Get the number of clock ticks to wait. 1039 * This is based on the maximum time it takes for a frame list rollover 1040 * and maximum time wait for SOFs to begin. 1041 */ 1042 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1043 EHCI_SOF_TIMEWAIT); 1044 1045 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1046 ehcip->ehci_flags |= EHCI_CV_INTR; 1047 1048 /* We need to add a delay to allow the chip time to start running */ 1049 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1050 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1051 1052 /* 1053 * Check EHCI host controller is running, otherwise return failure. 1054 */ 1055 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1056 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1057 1058 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1059 "No SOF interrupts have been received, this USB EHCI host" 1060 "controller is unusable"); 1061 1062 /* 1063 * Route all Root hub ports to Classic host 1064 * controller, in case this is an unusable ALI M5273 1065 * EHCI controller. 1066 */ 1067 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1068 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1069 } 1070 1071 return (DDI_FAILURE); 1072 } 1073 1074 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1075 "ehci_init_ctlr: SOF's have started"); 1076 1077 /* Route all Root hub ports to EHCI host controller */ 1078 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1079 1080 /* Set host controller soft state to operational */ 1081 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1082 1083 return (DDI_SUCCESS); 1084 } 1085 1086 /* 1087 * ehci_take_control: 1088 * 1089 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1090 * x86 machines, because sparc doesn't have a BIOS. 1091 * On x86 machine, the take control process includes 1092 * o get the base address of the extended capability list 1093 * o find out the capability for handoff synchronization in the list. 1094 * o check if BIOS has owned the host controller. 1095 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1096 * o wait for a constant time and check if BIOS has relinquished control. 1097 */ 1098 /* ARGSUSED */ 1099 static int 1100 ehci_take_control(ehci_state_t *ehcip) 1101 { 1102 #if defined(__x86) 1103 uint32_t extended_cap; 1104 uint32_t extended_cap_offset; 1105 uint32_t extended_cap_id; 1106 uint_t retry; 1107 1108 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1109 "ehci_take_control:"); 1110 1111 /* 1112 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1113 * register. 1114 */ 1115 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1116 EHCI_HCC_EECP_SHIFT; 1117 1118 /* 1119 * According EHCI Spec 2.2.4, if the extended capability offset is 1120 * less than 40h then its not valid. This means we don't need to 1121 * worry about BIOS handoff. 1122 */ 1123 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1124 1125 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1126 "ehci_take_control: Hardware doesn't support legacy."); 1127 1128 goto success; 1129 } 1130 1131 /* 1132 * According EHCI Spec 2.1.7, A zero offset indicates the 1133 * end of the extended capability list. 1134 */ 1135 while (extended_cap_offset) { 1136 1137 /* Get the extended capability value. */ 1138 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1139 extended_cap_offset); 1140 1141 /* Get the capability ID */ 1142 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1143 EHCI_EX_CAP_ID_SHIFT; 1144 1145 /* Check if the card support legacy */ 1146 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1147 break; 1148 } 1149 1150 /* Get the offset of the next capability */ 1151 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1152 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1153 } 1154 1155 /* 1156 * Unable to find legacy support in hardware's extended capability list. 1157 * This means we don't need to worry about BIOS handoff. 1158 */ 1159 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1160 1161 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1162 "ehci_take_control: Hardware doesn't support legacy"); 1163 1164 goto success; 1165 } 1166 1167 /* Check if BIOS has owned it. */ 1168 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1169 1170 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1171 "ehci_take_control: BIOS does not own EHCI"); 1172 1173 goto success; 1174 } 1175 1176 /* 1177 * According EHCI Spec 5.1, The OS driver initiates an ownership 1178 * request by setting the OS Owned semaphore to a one. The OS 1179 * waits for the BIOS Owned bit to go to a zero before attempting 1180 * to use the EHCI controller. The time that OS must wait for BIOS 1181 * to respond to the request for ownership is beyond the scope of 1182 * this specification. 1183 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1184 * for BIOS to release the ownership. 1185 */ 1186 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1187 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1188 extended_cap); 1189 1190 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1191 1192 /* wait a special interval */ 1193 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1194 1195 /* Check to see if the BIOS has released the ownership */ 1196 extended_cap = pci_config_get32( 1197 ehcip->ehci_config_handle, extended_cap_offset); 1198 1199 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1200 1201 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1202 ehcip->ehci_log_hdl, 1203 "ehci_take_control: BIOS has released " 1204 "the ownership. retry = %d", retry); 1205 1206 goto success; 1207 } 1208 1209 } 1210 1211 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1212 "ehci_take_control: take control from BIOS failed."); 1213 1214 return (USB_FAILURE); 1215 1216 success: 1217 1218 #endif /* __x86 */ 1219 return (USB_SUCCESS); 1220 } 1221 1222 1223 /* 1224 * ehci_init_periodic_frame_list_table : 1225 * 1226 * Allocate the system memory and initialize Host Controller 1227 * Periodic Frame List table area. The starting of the Periodic 1228 * Frame List Table area must be 4096 byte aligned. 1229 */ 1230 static int 1231 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1232 { 1233 ddi_device_acc_attr_t dev_attr; 1234 size_t real_length; 1235 uint_t ccount; 1236 int result; 1237 1238 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1239 1240 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1241 "ehci_init_periodic_frame_lst_table:"); 1242 1243 /* The host controller will be little endian */ 1244 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1245 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1246 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1247 1248 /* Force the required 4K restrictive alignment */ 1249 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1250 1251 /* Create space for the Periodic Frame List */ 1252 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1253 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1254 1255 goto failure; 1256 } 1257 1258 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1259 sizeof (ehci_periodic_frame_list_t), 1260 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1261 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1262 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1263 1264 goto failure; 1265 } 1266 1267 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1268 "ehci_init_periodic_frame_lst_table: " 1269 "Real length %lu", real_length); 1270 1271 /* Map the whole Periodic Frame List into the I/O address space */ 1272 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1273 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1274 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1275 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1276 1277 if (result == DDI_DMA_MAPPED) { 1278 /* The cookie count should be 1 */ 1279 if (ccount != 1) { 1280 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1281 "ehci_init_periodic_frame_lst_table: " 1282 "More than 1 cookie"); 1283 1284 goto failure; 1285 } 1286 } else { 1287 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1288 1289 goto failure; 1290 } 1291 1292 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1293 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1294 (void *)ehcip->ehci_periodic_frame_list_tablep, 1295 ehcip->ehci_pflt_cookie.dmac_address); 1296 1297 /* 1298 * DMA addresses for Periodic Frame List are bound. 1299 */ 1300 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1301 1302 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1303 1304 /* Initialize the Periodic Frame List */ 1305 ehci_build_interrupt_lattice(ehcip); 1306 1307 /* Reset Byte Alignment to Default */ 1308 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1309 1310 return (DDI_SUCCESS); 1311 failure: 1312 /* Byte alignment */ 1313 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1314 1315 return (DDI_FAILURE); 1316 } 1317 1318 1319 /* 1320 * ehci_build_interrupt_lattice: 1321 * 1322 * Construct the interrupt lattice tree using static Endpoint Descriptors 1323 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1324 * lists and the Host Controller (HC) processes one interrupt QH list in 1325 * every frame. The Host Controller traverses the periodic schedule by 1326 * constructing an array offset reference from the Periodic List Base Address 1327 * register and bits 12 to 3 of Frame Index register. It fetches the element 1328 * and begins traversing the graph of linked schedule data structures. 1329 */ 1330 static void 1331 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1332 { 1333 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1334 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1335 ehci_periodic_frame_list_t *periodic_frame_list = 1336 ehcip->ehci_periodic_frame_list_tablep; 1337 ushort_t *temp, num_of_nodes; 1338 uintptr_t addr; 1339 int i, j, k; 1340 1341 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1342 "ehci_build_interrupt_lattice:"); 1343 1344 /* 1345 * Reserve the first 63 Endpoint Descriptor (QH) structures 1346 * in the pool as static endpoints & these are required for 1347 * constructing interrupt lattice tree. 1348 */ 1349 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1350 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1351 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1352 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1353 Set_QH(list_array[i].qh_alt_next_qtd, 1354 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1355 } 1356 1357 /* 1358 * Make sure that last Endpoint on the periodic frame list terminates 1359 * periodic schedule. 1360 */ 1361 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1362 1363 /* Build the interrupt lattice tree */ 1364 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1365 /* 1366 * The next pointer in the host controller endpoint 1367 * descriptor must contain an iommu address. Calculate 1368 * the offset into the cpu address and add this to the 1369 * starting iommu address. 1370 */ 1371 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1372 1373 Set_QH(list_array[2*i + 1].qh_link_ptr, 1374 addr | EHCI_QH_LINK_REF_QH); 1375 Set_QH(list_array[2*i + 2].qh_link_ptr, 1376 addr | EHCI_QH_LINK_REF_QH); 1377 } 1378 1379 /* Build the tree bottom */ 1380 temp = (unsigned short *) 1381 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1382 1383 num_of_nodes = 1; 1384 1385 /* 1386 * Initialize the values which are used for setting up head pointers 1387 * for the 32ms scheduling lists which starts from the Periodic Frame 1388 * List. 1389 */ 1390 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1391 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1392 ehci_index[j++] = temp[k]; 1393 ehci_index[j] = temp[k] + ehci_pow_2(i); 1394 } 1395 1396 num_of_nodes *= 2; 1397 for (k = 0; k < num_of_nodes; k++) 1398 temp[k] = ehci_index[k]; 1399 } 1400 1401 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1402 1403 /* 1404 * Initialize the interrupt list in the Periodic Frame List Table 1405 * so that it points to the bottom of the tree. 1406 */ 1407 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1408 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1409 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1410 1411 ASSERT(addr); 1412 1413 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1414 Set_PFLT(periodic_frame_list-> 1415 ehci_periodic_frame_list_table[ehci_index[j++]], 1416 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1417 } 1418 } 1419 } 1420 1421 1422 /* 1423 * ehci_alloc_hcdi_ops: 1424 * 1425 * The HCDI interfaces or entry points are the software interfaces used by 1426 * the Universal Serial Bus Driver (USBA) to access the services of the 1427 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1428 * about all available HCDI interfaces or entry points. 1429 */ 1430 usba_hcdi_ops_t * 1431 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1432 { 1433 usba_hcdi_ops_t *usba_hcdi_ops; 1434 1435 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1436 "ehci_alloc_hcdi_ops:"); 1437 1438 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1439 1440 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1441 1442 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1443 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1444 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1445 1446 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1447 1448 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1449 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1450 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1451 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1452 1453 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1454 ehci_hcdi_bulk_transfer_size; 1455 1456 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1457 ehci_hcdi_pipe_stop_intr_polling; 1458 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1459 ehci_hcdi_pipe_stop_isoc_polling; 1460 1461 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1462 ehci_hcdi_get_current_frame_number; 1463 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1464 ehci_hcdi_get_max_isoc_pkts; 1465 1466 usba_hcdi_ops->usba_hcdi_console_input_init = 1467 ehci_hcdi_polled_input_init; 1468 usba_hcdi_ops->usba_hcdi_console_input_enter = 1469 ehci_hcdi_polled_input_enter; 1470 usba_hcdi_ops->usba_hcdi_console_read = 1471 ehci_hcdi_polled_read; 1472 usba_hcdi_ops->usba_hcdi_console_input_exit = 1473 ehci_hcdi_polled_input_exit; 1474 usba_hcdi_ops->usba_hcdi_console_input_fini = 1475 ehci_hcdi_polled_input_fini; 1476 return (usba_hcdi_ops); 1477 } 1478 1479 1480 /* 1481 * Host Controller Driver (HCD) deinitialization functions 1482 */ 1483 1484 /* 1485 * ehci_cleanup: 1486 * 1487 * Cleanup on attach failure or detach 1488 */ 1489 int 1490 ehci_cleanup(ehci_state_t *ehcip) 1491 { 1492 ehci_trans_wrapper_t *tw; 1493 ehci_pipe_private_t *pp; 1494 ehci_qtd_t *qtd; 1495 int i, ctrl, rval; 1496 int flags = ehcip->ehci_flags; 1497 1498 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1499 1500 if (flags & EHCI_RHREG) { 1501 /* Unload the root hub driver */ 1502 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1503 1504 return (DDI_FAILURE); 1505 } 1506 } 1507 1508 if (flags & EHCI_USBAREG) { 1509 /* Unregister this HCD instance with USBA */ 1510 usba_hcdi_unregister(ehcip->ehci_dip); 1511 } 1512 1513 if (flags & EHCI_INTR) { 1514 1515 mutex_enter(&ehcip->ehci_int_mutex); 1516 1517 /* Disable all EHCI QH list processing */ 1518 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1519 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1520 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1521 1522 /* Disable all EHCI interrupts */ 1523 Set_OpReg(ehci_interrupt, 0); 1524 1525 /* wait for the next SOF */ 1526 (void) ehci_wait_for_sof(ehcip); 1527 1528 /* Route all Root hub ports to Classic host controller */ 1529 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1530 1531 /* Stop the EHCI host controller */ 1532 Set_OpReg(ehci_command, 1533 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1534 1535 /* Wait for sometime */ 1536 drv_usecwait(EHCI_TIMEWAIT); 1537 1538 mutex_exit(&ehcip->ehci_int_mutex); 1539 1540 /* disable interrupt */ 1541 (void) ddi_intr_disable(ehcip->ehci_htable[0]); 1542 1543 /* Remove interrupt handler */ 1544 (void) ddi_intr_remove_handler(ehcip->ehci_htable[0]); 1545 1546 /* free interrupt handle */ 1547 (void) ddi_intr_free(ehcip->ehci_htable[0]); 1548 1549 /* free memory */ 1550 kmem_free(ehcip->ehci_htable, sizeof (ddi_intr_handle_t)); 1551 } 1552 1553 /* Unmap the EHCI registers */ 1554 if (ehcip->ehci_caps_handle) { 1555 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1556 } 1557 1558 if (ehcip->ehci_config_handle) { 1559 pci_config_teardown(&ehcip->ehci_config_handle); 1560 } 1561 1562 /* Free all the buffers */ 1563 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1564 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1565 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1566 ctrl = Get_QTD(ehcip-> 1567 ehci_qtd_pool_addr[i].qtd_state); 1568 1569 if ((ctrl != EHCI_QTD_FREE) && 1570 (ctrl != EHCI_QTD_DUMMY) && 1571 (qtd->qtd_trans_wrapper)) { 1572 1573 mutex_enter(&ehcip->ehci_int_mutex); 1574 1575 tw = (ehci_trans_wrapper_t *) 1576 EHCI_LOOKUP_ID((uint32_t) 1577 Get_QTD(qtd->qtd_trans_wrapper)); 1578 1579 /* Obtain the pipe private structure */ 1580 pp = tw->tw_pipe_private; 1581 1582 /* Stop the the transfer timer */ 1583 ehci_stop_xfer_timer(ehcip, tw, 1584 EHCI_REMOVE_XFER_ALWAYS); 1585 1586 ehci_deallocate_tw(ehcip, pp, tw); 1587 1588 mutex_exit(&ehcip->ehci_int_mutex); 1589 } 1590 } 1591 1592 /* 1593 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1594 * the handle for QTD pools. 1595 */ 1596 if ((ehcip->ehci_dma_addr_bind_flag & 1597 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1598 1599 rval = ddi_dma_unbind_handle( 1600 ehcip->ehci_qtd_pool_dma_handle); 1601 1602 ASSERT(rval == DDI_SUCCESS); 1603 } 1604 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1605 } 1606 1607 /* Free the QTD pool */ 1608 if (ehcip->ehci_qtd_pool_dma_handle) { 1609 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1610 } 1611 1612 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1613 /* 1614 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1615 * the handle for QH pools. 1616 */ 1617 if ((ehcip->ehci_dma_addr_bind_flag & 1618 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1619 1620 rval = ddi_dma_unbind_handle( 1621 ehcip->ehci_qh_pool_dma_handle); 1622 1623 ASSERT(rval == DDI_SUCCESS); 1624 } 1625 1626 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1627 } 1628 1629 /* Free the QH pool */ 1630 if (ehcip->ehci_qh_pool_dma_handle) { 1631 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1632 } 1633 1634 /* Free the Periodic frame list table (PFLT) area */ 1635 if (ehcip->ehci_periodic_frame_list_tablep && 1636 ehcip->ehci_pflt_mem_handle) { 1637 /* 1638 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1639 * the handle for PFLT. 1640 */ 1641 if ((ehcip->ehci_dma_addr_bind_flag & 1642 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1643 1644 rval = ddi_dma_unbind_handle( 1645 ehcip->ehci_pflt_dma_handle); 1646 1647 ASSERT(rval == DDI_SUCCESS); 1648 } 1649 1650 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1651 } 1652 1653 (void) ehci_isoc_cleanup(ehcip); 1654 1655 if (ehcip->ehci_pflt_dma_handle) { 1656 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1657 } 1658 1659 if (flags & EHCI_INTR) { 1660 /* Destroy the mutex */ 1661 mutex_destroy(&ehcip->ehci_int_mutex); 1662 1663 /* Destroy the async schedule advance condition variable */ 1664 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1665 } 1666 1667 /* clean up kstat structs */ 1668 ehci_destroy_stats(ehcip); 1669 1670 /* Free ehci hcdi ops */ 1671 if (ehcip->ehci_hcdi_ops) { 1672 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1673 } 1674 1675 if (flags & EHCI_ZALLOC) { 1676 1677 usb_free_log_hdl(ehcip->ehci_log_hdl); 1678 1679 /* Remove all properties that might have been created */ 1680 ddi_prop_remove_all(ehcip->ehci_dip); 1681 1682 /* Free the soft state */ 1683 ddi_soft_state_free(ehci_statep, 1684 ddi_get_instance(ehcip->ehci_dip)); 1685 } 1686 1687 return (DDI_SUCCESS); 1688 } 1689 1690 1691 /* 1692 * ehci_cpr_suspend 1693 */ 1694 int 1695 ehci_cpr_suspend(ehci_state_t *ehcip) 1696 { 1697 int i; 1698 1699 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1700 "ehci_cpr_suspend:"); 1701 1702 /* Call into the root hub and suspend it */ 1703 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1704 1705 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1706 "ehci_cpr_suspend: root hub fails to suspend"); 1707 1708 return (DDI_FAILURE); 1709 } 1710 1711 /* Only root hub's intr pipe should be open at this time */ 1712 mutex_enter(&ehcip->ehci_int_mutex); 1713 1714 ASSERT(ehcip->ehci_open_pipe_count == 0); 1715 1716 /* Just wait till all resources are reclaimed */ 1717 i = 0; 1718 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1719 ehci_handle_endpoint_reclaimation(ehcip); 1720 (void) ehci_wait_for_sof(ehcip); 1721 } 1722 ASSERT(ehcip->ehci_reclaim_list == NULL); 1723 1724 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1725 "ehci_cpr_suspend: Disable HC QH list processing"); 1726 1727 /* Disable all EHCI QH list processing */ 1728 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1729 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1730 1731 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1732 "ehci_cpr_suspend: Disable HC interrupts"); 1733 1734 /* Disable all EHCI interrupts */ 1735 Set_OpReg(ehci_interrupt, 0); 1736 1737 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1738 "ehci_cpr_suspend: Wait for the next SOF"); 1739 1740 /* Wait for the next SOF */ 1741 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1742 1743 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1744 "ehci_cpr_suspend: ehci host controller suspend failed"); 1745 1746 mutex_exit(&ehcip->ehci_int_mutex); 1747 return (DDI_FAILURE); 1748 } 1749 1750 /* 1751 * Stop the ehci host controller 1752 * if usb keyboard is not connected. 1753 */ 1754 if (ehcip->ehci_polled_kbd_count == 0) { 1755 Set_OpReg(ehci_command, 1756 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1757 } 1758 1759 /* Set host controller soft state to suspend */ 1760 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 1761 1762 mutex_exit(&ehcip->ehci_int_mutex); 1763 1764 return (DDI_SUCCESS); 1765 } 1766 1767 1768 /* 1769 * ehci_cpr_resume 1770 */ 1771 int 1772 ehci_cpr_resume(ehci_state_t *ehcip) 1773 { 1774 mutex_enter(&ehcip->ehci_int_mutex); 1775 1776 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1777 "ehci_cpr_resume: Restart the controller"); 1778 1779 /* Cleanup ehci specific information across cpr */ 1780 ehci_cpr_cleanup(ehcip); 1781 1782 /* Restart the controller */ 1783 if (ehci_init_ctlr(ehcip) != DDI_SUCCESS) { 1784 1785 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1786 "ehci_cpr_resume: ehci host controller resume failed "); 1787 1788 mutex_exit(&ehcip->ehci_int_mutex); 1789 1790 return (DDI_FAILURE); 1791 } 1792 1793 mutex_exit(&ehcip->ehci_int_mutex); 1794 1795 /* Now resume the root hub */ 1796 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 1797 1798 return (DDI_FAILURE); 1799 } 1800 1801 return (DDI_SUCCESS); 1802 } 1803 1804 1805 /* 1806 * Bandwidth Allocation functions 1807 */ 1808 1809 /* 1810 * ehci_allocate_bandwidth: 1811 * 1812 * Figure out whether or not this interval may be supported. Return the index 1813 * into the lattice if it can be supported. Return allocation failure if it 1814 * can not be supported. 1815 */ 1816 int 1817 ehci_allocate_bandwidth( 1818 ehci_state_t *ehcip, 1819 usba_pipe_handle_data_t *ph, 1820 uint_t *pnode, 1821 uchar_t *smask, 1822 uchar_t *cmask) 1823 { 1824 int error = USB_SUCCESS; 1825 1826 /* This routine is protected by the ehci_int_mutex */ 1827 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1828 1829 /* Reset the pnode to the last checked pnode */ 1830 *pnode = 0; 1831 1832 /* Allocate high speed bandwidth */ 1833 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 1834 ph, pnode, smask, cmask)) != USB_SUCCESS) { 1835 1836 return (error); 1837 } 1838 1839 /* 1840 * For low/full speed usb devices, allocate classic TT bandwidth 1841 * in additional to high speed bandwidth. 1842 */ 1843 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 1844 1845 /* Allocate classic TT bandwidth */ 1846 if ((error = ehci_allocate_classic_tt_bandwidth( 1847 ehcip, ph, *pnode)) != USB_SUCCESS) { 1848 1849 /* Deallocate high speed bandwidth */ 1850 ehci_deallocate_high_speed_bandwidth( 1851 ehcip, ph, *pnode, *smask, *cmask); 1852 } 1853 } 1854 1855 return (error); 1856 } 1857 1858 1859 /* 1860 * ehci_allocate_high_speed_bandwidth: 1861 * 1862 * Allocate high speed bandwidth for the low/full/high speed interrupt and 1863 * isochronous endpoints. 1864 */ 1865 static int 1866 ehci_allocate_high_speed_bandwidth( 1867 ehci_state_t *ehcip, 1868 usba_pipe_handle_data_t *ph, 1869 uint_t *pnode, 1870 uchar_t *smask, 1871 uchar_t *cmask) 1872 { 1873 uint_t sbandwidth, cbandwidth; 1874 int interval; 1875 usb_ep_descr_t *endpoint = &ph->p_ep; 1876 usba_device_t *child_ud; 1877 usb_port_status_t port_status; 1878 int error; 1879 1880 /* This routine is protected by the ehci_int_mutex */ 1881 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1882 1883 /* Get child's usba device structure */ 1884 child_ud = ph->p_usba_device; 1885 1886 mutex_enter(&child_ud->usb_mutex); 1887 1888 /* Get the current usb device's port status */ 1889 port_status = ph->p_usba_device->usb_port_status; 1890 1891 mutex_exit(&child_ud->usb_mutex); 1892 1893 /* 1894 * Calculate the length in bytes of a transaction on this 1895 * periodic endpoint. Return failure if maximum packet is 1896 * zero. 1897 */ 1898 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 1899 port_status, &sbandwidth, &cbandwidth); 1900 if (error != USB_SUCCESS) { 1901 1902 return (error); 1903 } 1904 1905 /* 1906 * Adjust polling interval to be a power of 2. 1907 * If this interval can't be supported, return 1908 * allocation failure. 1909 */ 1910 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 1911 if (interval == USB_FAILURE) { 1912 1913 return (USB_FAILURE); 1914 } 1915 1916 if (port_status == USBA_HIGH_SPEED_DEV) { 1917 /* Allocate bandwidth for high speed devices, except ITD */ 1918 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 1919 endpoint, sbandwidth, interval); 1920 *cmask = 0x00; 1921 1922 } else { 1923 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 1924 USB_EP_ATTR_INTR) { 1925 1926 /* Allocate bandwidth for low speed interrupt */ 1927 error = ehci_find_bestfit_ls_intr_mask(ehcip, 1928 smask, cmask, pnode, sbandwidth, cbandwidth, 1929 interval); 1930 } else { 1931 if ((endpoint->bEndpointAddress & 1932 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 1933 1934 /* Allocate bandwidth for sitd in */ 1935 error = ehci_find_bestfit_sitd_in_mask(ehcip, 1936 smask, cmask, pnode, sbandwidth, cbandwidth, 1937 interval); 1938 } else { 1939 1940 /* Allocate bandwidth for sitd out */ 1941 error = ehci_find_bestfit_sitd_out_mask(ehcip, 1942 smask, pnode, sbandwidth, interval); 1943 *cmask = 0x00; 1944 } 1945 } 1946 } 1947 1948 if (error != USB_SUCCESS) { 1949 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 1950 "ehci_allocate_high_speed_bandwidth: Reached maximum " 1951 "bandwidth value and cannot allocate bandwidth for a " 1952 "given high-speed periodic endpoint"); 1953 1954 return (USB_NO_BANDWIDTH); 1955 } 1956 1957 return (error); 1958 } 1959 1960 1961 /* 1962 * ehci_allocate_classic_tt_speed_bandwidth: 1963 * 1964 * Allocate classic TT bandwidth for the low/full speed interrupt and 1965 * isochronous endpoints. 1966 */ 1967 static int 1968 ehci_allocate_classic_tt_bandwidth( 1969 ehci_state_t *ehcip, 1970 usba_pipe_handle_data_t *ph, 1971 uint_t pnode) 1972 { 1973 uint_t bandwidth, min; 1974 uint_t height, leftmost, list; 1975 usb_ep_descr_t *endpoint = &ph->p_ep; 1976 usba_device_t *child_ud, *parent_ud; 1977 usb_port_status_t port_status; 1978 int i, interval; 1979 1980 /* This routine is protected by the ehci_int_mutex */ 1981 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1982 1983 /* Get child's usba device structure */ 1984 child_ud = ph->p_usba_device; 1985 1986 mutex_enter(&child_ud->usb_mutex); 1987 1988 /* Get the current usb device's port status */ 1989 port_status = child_ud->usb_port_status; 1990 1991 /* Get the parent high speed hub's usba device structure */ 1992 parent_ud = child_ud->usb_hs_hub_usba_dev; 1993 1994 mutex_exit(&child_ud->usb_mutex); 1995 1996 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 1997 "ehci_allocate_classic_tt_bandwidth: " 1998 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 1999 2000 /* 2001 * Calculate the length in bytes of a transaction on this 2002 * periodic endpoint. Return failure if maximum packet is 2003 * zero. 2004 */ 2005 if (ehci_compute_classic_bandwidth(endpoint, 2006 port_status, &bandwidth) != USB_SUCCESS) { 2007 2008 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2009 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2010 "with zero endpoint maximum packet size is not supported"); 2011 2012 return (USB_NOT_SUPPORTED); 2013 } 2014 2015 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2016 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2017 2018 mutex_enter(&parent_ud->usb_mutex); 2019 2020 /* 2021 * If the length in bytes plus the allocated bandwidth exceeds 2022 * the maximum, return bandwidth allocation failure. 2023 */ 2024 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2025 FS_PERIODIC_BANDWIDTH) { 2026 2027 mutex_exit(&parent_ud->usb_mutex); 2028 2029 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2030 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2031 "bandwidth value and cannot allocate bandwidth for a " 2032 "given low/full speed periodic endpoint"); 2033 2034 return (USB_NO_BANDWIDTH); 2035 } 2036 2037 mutex_exit(&parent_ud->usb_mutex); 2038 2039 /* Adjust polling interval to be a power of 2 */ 2040 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2041 2042 /* Find the height in the tree */ 2043 height = ehci_lattice_height(interval); 2044 2045 /* Find the leftmost leaf in the subtree specified by the node. */ 2046 leftmost = ehci_leftmost_leaf(pnode, height); 2047 2048 mutex_enter(&parent_ud->usb_mutex); 2049 2050 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2051 list = ehci_index[leftmost + i]; 2052 2053 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2054 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2055 2056 mutex_exit(&parent_ud->usb_mutex); 2057 2058 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2059 "ehci_allocate_classic_tt_bandwidth: Reached " 2060 "maximum bandwidth value and cannot allocate " 2061 "bandwidth for low/full periodic endpoint"); 2062 2063 return (USB_NO_BANDWIDTH); 2064 } 2065 } 2066 2067 /* 2068 * All the leaves for this node must be updated with the bandwidth. 2069 */ 2070 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2071 list = ehci_index[leftmost + i]; 2072 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2073 } 2074 2075 /* Find the leaf with the smallest allocated bandwidth */ 2076 min = parent_ud->usb_hs_hub_bandwidth[0]; 2077 2078 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2079 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2080 min = parent_ud->usb_hs_hub_bandwidth[i]; 2081 } 2082 } 2083 2084 /* Save the minimum for later use */ 2085 parent_ud->usb_hs_hub_min_bandwidth = min; 2086 2087 mutex_exit(&parent_ud->usb_mutex); 2088 2089 return (USB_SUCCESS); 2090 } 2091 2092 2093 /* 2094 * ehci_deallocate_bandwidth: 2095 * 2096 * Deallocate bandwidth for the given node in the lattice and the length 2097 * of transfer. 2098 */ 2099 void 2100 ehci_deallocate_bandwidth( 2101 ehci_state_t *ehcip, 2102 usba_pipe_handle_data_t *ph, 2103 uint_t pnode, 2104 uchar_t smask, 2105 uchar_t cmask) 2106 { 2107 /* This routine is protected by the ehci_int_mutex */ 2108 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2109 2110 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2111 2112 /* 2113 * For low/full speed usb devices, deallocate classic TT bandwidth 2114 * in additional to high speed bandwidth. 2115 */ 2116 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2117 2118 /* Deallocate classic TT bandwidth */ 2119 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2120 } 2121 } 2122 2123 2124 /* 2125 * ehci_deallocate_high_speed_bandwidth: 2126 * 2127 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2128 */ 2129 static void 2130 ehci_deallocate_high_speed_bandwidth( 2131 ehci_state_t *ehcip, 2132 usba_pipe_handle_data_t *ph, 2133 uint_t pnode, 2134 uchar_t smask, 2135 uchar_t cmask) 2136 { 2137 uint_t height, leftmost; 2138 uint_t list_count; 2139 uint_t sbandwidth, cbandwidth; 2140 int interval; 2141 usb_ep_descr_t *endpoint = &ph->p_ep; 2142 usba_device_t *child_ud; 2143 usb_port_status_t port_status; 2144 2145 /* This routine is protected by the ehci_int_mutex */ 2146 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2147 2148 /* Get child's usba device structure */ 2149 child_ud = ph->p_usba_device; 2150 2151 mutex_enter(&child_ud->usb_mutex); 2152 2153 /* Get the current usb device's port status */ 2154 port_status = ph->p_usba_device->usb_port_status; 2155 2156 mutex_exit(&child_ud->usb_mutex); 2157 2158 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2159 port_status, &sbandwidth, &cbandwidth); 2160 2161 /* Adjust polling interval to be a power of 2 */ 2162 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2163 2164 /* Find the height in the tree */ 2165 height = ehci_lattice_height(interval); 2166 2167 /* 2168 * Find the leftmost leaf in the subtree specified by the node 2169 */ 2170 leftmost = ehci_leftmost_leaf(pnode, height); 2171 2172 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2173 2174 /* Delete the bandwidth from the appropriate lists */ 2175 if (port_status == USBA_HIGH_SPEED_DEV) { 2176 2177 ehci_update_bw_availability(ehcip, -sbandwidth, 2178 leftmost, list_count, smask); 2179 } else { 2180 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2181 USB_EP_ATTR_INTR) { 2182 2183 ehci_update_bw_availability(ehcip, -sbandwidth, 2184 leftmost, list_count, smask); 2185 ehci_update_bw_availability(ehcip, -cbandwidth, 2186 leftmost, list_count, cmask); 2187 } else { 2188 if ((endpoint->bEndpointAddress & 2189 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2190 2191 ehci_update_bw_availability(ehcip, -sbandwidth, 2192 leftmost, list_count, smask); 2193 ehci_update_bw_availability(ehcip, 2194 -MAX_UFRAME_SITD_XFER, leftmost, 2195 list_count, cmask); 2196 } else { 2197 2198 ehci_update_bw_availability(ehcip, 2199 -MAX_UFRAME_SITD_XFER, leftmost, 2200 list_count, smask); 2201 } 2202 } 2203 } 2204 } 2205 2206 /* 2207 * ehci_deallocate_classic_tt_bandwidth: 2208 * 2209 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2210 */ 2211 static void 2212 ehci_deallocate_classic_tt_bandwidth( 2213 ehci_state_t *ehcip, 2214 usba_pipe_handle_data_t *ph, 2215 uint_t pnode) 2216 { 2217 uint_t bandwidth, height, leftmost, list, min; 2218 int i, interval; 2219 usb_ep_descr_t *endpoint = &ph->p_ep; 2220 usba_device_t *child_ud, *parent_ud; 2221 usb_port_status_t port_status; 2222 2223 /* This routine is protected by the ehci_int_mutex */ 2224 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2225 2226 /* Get child's usba device structure */ 2227 child_ud = ph->p_usba_device; 2228 2229 mutex_enter(&child_ud->usb_mutex); 2230 2231 /* Get the current usb device's port status */ 2232 port_status = child_ud->usb_port_status; 2233 2234 /* Get the parent high speed hub's usba device structure */ 2235 parent_ud = child_ud->usb_hs_hub_usba_dev; 2236 2237 mutex_exit(&child_ud->usb_mutex); 2238 2239 /* Obtain the bandwidth */ 2240 (void) ehci_compute_classic_bandwidth(endpoint, 2241 port_status, &bandwidth); 2242 2243 /* Adjust polling interval to be a power of 2 */ 2244 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2245 2246 /* Find the height in the tree */ 2247 height = ehci_lattice_height(interval); 2248 2249 /* Find the leftmost leaf in the subtree specified by the node */ 2250 leftmost = ehci_leftmost_leaf(pnode, height); 2251 2252 mutex_enter(&parent_ud->usb_mutex); 2253 2254 /* Delete the bandwidth from the appropriate lists */ 2255 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2256 list = ehci_index[leftmost + i]; 2257 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2258 } 2259 2260 /* Find the leaf with the smallest allocated bandwidth */ 2261 min = parent_ud->usb_hs_hub_bandwidth[0]; 2262 2263 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2264 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2265 min = parent_ud->usb_hs_hub_bandwidth[i]; 2266 } 2267 } 2268 2269 /* Save the minimum for later use */ 2270 parent_ud->usb_hs_hub_min_bandwidth = min; 2271 2272 mutex_exit(&parent_ud->usb_mutex); 2273 } 2274 2275 2276 /* 2277 * ehci_compute_high_speed_bandwidth: 2278 * 2279 * Given a periodic endpoint (interrupt or isochronous) determine the total 2280 * bandwidth for one transaction. The EHCI host controller traverses the 2281 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2282 * services an endpoint, only a single transaction attempt is made. The HC 2283 * moves to the next Endpoint Descriptor after the first transaction attempt 2284 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2285 * Transfer Descriptor is inserted into the lattice, we will only count the 2286 * number of bytes for one transaction. 2287 * 2288 * The following are the formulas used for calculating bandwidth in terms 2289 * bytes and it is for the single USB high speed transaction. The protocol 2290 * overheads will be different for each of type of USB transfer & all these 2291 * formulas & protocol overheads are derived from the 5.11.3 section of the 2292 * USB 2.0 Specification. 2293 * 2294 * High-Speed: 2295 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2296 * 2297 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2298 * 2299 * Protocol overhead + Split transaction overhead + 2300 * ((MaxPktSz * 7)/6) + Host_Delay; 2301 */ 2302 /* ARGSUSED */ 2303 static int 2304 ehci_compute_high_speed_bandwidth( 2305 ehci_state_t *ehcip, 2306 usb_ep_descr_t *endpoint, 2307 usb_port_status_t port_status, 2308 uint_t *sbandwidth, 2309 uint_t *cbandwidth) 2310 { 2311 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2312 2313 /* Return failure if endpoint maximum packet is zero */ 2314 if (maxpacketsize == 0) { 2315 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2316 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2317 "with zero endpoint maximum packet size is not supported"); 2318 2319 return (USB_NOT_SUPPORTED); 2320 } 2321 2322 /* Add bit-stuffing overhead */ 2323 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2324 2325 /* Add Host Controller specific delay to required bandwidth */ 2326 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2327 2328 /* Add xfer specific protocol overheads */ 2329 if ((endpoint->bmAttributes & 2330 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2331 /* High speed interrupt transaction */ 2332 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2333 } else { 2334 /* Isochronous transaction */ 2335 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2336 } 2337 2338 /* 2339 * For low/full speed devices, add split transaction specific 2340 * overheads. 2341 */ 2342 if (port_status != USBA_HIGH_SPEED_DEV) { 2343 /* 2344 * Add start and complete split transaction 2345 * tokens overheads. 2346 */ 2347 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2348 *sbandwidth += START_SPLIT_OVERHEAD; 2349 2350 /* Add data overhead depending on data direction */ 2351 if ((endpoint->bEndpointAddress & 2352 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2353 *cbandwidth += maxpacketsize; 2354 } else { 2355 if ((endpoint->bmAttributes & 2356 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2357 /* There is no compete splits for out */ 2358 *cbandwidth = 0; 2359 } 2360 *sbandwidth += maxpacketsize; 2361 } 2362 } else { 2363 uint_t xactions; 2364 2365 /* Get the max transactions per microframe */ 2366 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2367 USB_EP_MAX_XACTS_SHIFT) + 1; 2368 2369 /* High speed transaction */ 2370 *sbandwidth += maxpacketsize; 2371 2372 /* Calculate bandwidth per micro-frame */ 2373 *sbandwidth *= xactions; 2374 2375 *cbandwidth = 0; 2376 } 2377 2378 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2379 "ehci_allocate_high_speed_bandwidth: " 2380 "Start split bandwidth %d Complete split bandwidth %d", 2381 *sbandwidth, *cbandwidth); 2382 2383 return (USB_SUCCESS); 2384 } 2385 2386 2387 /* 2388 * ehci_compute_classic_bandwidth: 2389 * 2390 * Given a periodic endpoint (interrupt or isochronous) determine the total 2391 * bandwidth for one transaction. The EHCI host controller traverses the 2392 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2393 * services an endpoint, only a single transaction attempt is made. The HC 2394 * moves to the next Endpoint Descriptor after the first transaction attempt 2395 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2396 * Transfer Descriptor is inserted into the lattice, we will only count the 2397 * number of bytes for one transaction. 2398 * 2399 * The following are the formulas used for calculating bandwidth in terms 2400 * bytes and it is for the single USB high speed transaction. The protocol 2401 * overheads will be different for each of type of USB transfer & all these 2402 * formulas & protocol overheads are derived from the 5.11.3 section of the 2403 * USB 2.0 Specification. 2404 * 2405 * Low-Speed: 2406 * Protocol overhead + Hub LS overhead + 2407 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2408 * 2409 * Full-Speed: 2410 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2411 */ 2412 /* ARGSUSED */ 2413 static int 2414 ehci_compute_classic_bandwidth( 2415 usb_ep_descr_t *endpoint, 2416 usb_port_status_t port_status, 2417 uint_t *bandwidth) 2418 { 2419 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2420 2421 /* 2422 * If endpoint maximum packet is zero, then return immediately. 2423 */ 2424 if (maxpacketsize == 0) { 2425 2426 return (USB_NOT_SUPPORTED); 2427 } 2428 2429 /* Add TT delay to required bandwidth */ 2430 *bandwidth = TT_DELAY; 2431 2432 /* Add bit-stuffing overhead */ 2433 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2434 2435 switch (port_status) { 2436 case USBA_LOW_SPEED_DEV: 2437 /* Low speed interrupt transaction */ 2438 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2439 HUB_LOW_SPEED_PROTO_OVERHEAD + 2440 (LOW_SPEED_CLOCK * maxpacketsize)); 2441 break; 2442 case USBA_FULL_SPEED_DEV: 2443 /* Full speed transaction */ 2444 *bandwidth += maxpacketsize; 2445 2446 /* Add xfer specific protocol overheads */ 2447 if ((endpoint->bmAttributes & 2448 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2449 /* Full speed interrupt transaction */ 2450 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2451 } else { 2452 /* Isochronous and input transaction */ 2453 if ((endpoint->bEndpointAddress & 2454 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2455 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2456 } else { 2457 /* Isochronous and output transaction */ 2458 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2459 } 2460 } 2461 break; 2462 } 2463 2464 return (USB_SUCCESS); 2465 } 2466 2467 2468 /* 2469 * ehci_adjust_polling_interval: 2470 * 2471 * Adjust bandwidth according usb device speed. 2472 */ 2473 /* ARGSUSED */ 2474 int 2475 ehci_adjust_polling_interval( 2476 ehci_state_t *ehcip, 2477 usb_ep_descr_t *endpoint, 2478 usb_port_status_t port_status) 2479 { 2480 uint_t interval; 2481 int i = 0; 2482 2483 /* Get the polling interval */ 2484 interval = endpoint->bInterval; 2485 2486 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2487 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2488 2489 /* 2490 * According USB 2.0 Specifications, a high-speed endpoint's 2491 * polling intervals are specified interms of 125us or micro 2492 * frame, where as full/low endpoint's polling intervals are 2493 * specified in milliseconds. 2494 * 2495 * A high speed interrupt/isochronous endpoints can specify 2496 * desired polling interval between 1 to 16 micro-frames, 2497 * where as full/low endpoints can specify between 1 to 255 2498 * milliseconds. 2499 */ 2500 switch (port_status) { 2501 case USBA_LOW_SPEED_DEV: 2502 /* 2503 * Low speed endpoints are limited to specifying 2504 * only 8ms to 255ms in this driver. If a device 2505 * reports a polling interval that is less than 8ms, 2506 * it will use 8 ms instead. 2507 */ 2508 if (interval < LS_MIN_POLL_INTERVAL) { 2509 2510 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2511 "Low speed endpoint's poll interval of %d ms " 2512 "is below threshold. Rounding up to %d ms", 2513 interval, LS_MIN_POLL_INTERVAL); 2514 2515 interval = LS_MIN_POLL_INTERVAL; 2516 } 2517 2518 /* 2519 * Return an error if the polling interval is greater 2520 * than 255ms. 2521 */ 2522 if (interval > LS_MAX_POLL_INTERVAL) { 2523 2524 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2525 "Low speed endpoint's poll interval is " 2526 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2527 2528 return (USB_FAILURE); 2529 } 2530 break; 2531 2532 case USBA_FULL_SPEED_DEV: 2533 /* 2534 * Return an error if the polling interval is less 2535 * than 1ms and greater than 255ms. 2536 */ 2537 if ((interval < FS_MIN_POLL_INTERVAL) && 2538 (interval > FS_MAX_POLL_INTERVAL)) { 2539 2540 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2541 "Full speed endpoint's poll interval must " 2542 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2543 FS_MAX_POLL_INTERVAL); 2544 2545 return (USB_FAILURE); 2546 } 2547 break; 2548 case USBA_HIGH_SPEED_DEV: 2549 /* 2550 * Return an error if the polling interval is less 1 2551 * and greater than 16. Convert this value to 125us 2552 * units using 2^(bInterval -1). refer usb 2.0 spec 2553 * page 51 for details. 2554 */ 2555 if ((interval < HS_MIN_POLL_INTERVAL) && 2556 (interval > HS_MAX_POLL_INTERVAL)) { 2557 2558 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2559 "High speed endpoint's poll interval " 2560 "must be between %d and %d units", 2561 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2562 2563 return (USB_FAILURE); 2564 } 2565 2566 /* Adjust high speed device polling interval */ 2567 interval = 2568 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2569 2570 break; 2571 } 2572 2573 /* 2574 * If polling interval is greater than 32ms, 2575 * adjust polling interval equal to 32ms. 2576 */ 2577 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2578 interval = EHCI_NUM_INTR_QH_LISTS; 2579 } 2580 2581 /* 2582 * Find the nearest power of 2 that's less 2583 * than interval. 2584 */ 2585 while ((ehci_pow_2(i)) <= interval) { 2586 i++; 2587 } 2588 2589 return (ehci_pow_2((i - 1))); 2590 } 2591 2592 2593 /* 2594 * ehci_adjust_high_speed_polling_interval: 2595 */ 2596 /* ARGSUSED */ 2597 static int 2598 ehci_adjust_high_speed_polling_interval( 2599 ehci_state_t *ehcip, 2600 usb_ep_descr_t *endpoint) 2601 { 2602 uint_t interval; 2603 2604 /* Get the polling interval */ 2605 interval = ehci_pow_2(endpoint->bInterval - 1); 2606 2607 /* 2608 * Convert polling interval from micro seconds 2609 * to milli seconds. 2610 */ 2611 if (interval <= EHCI_MAX_UFRAMES) { 2612 interval = 1; 2613 } else { 2614 interval = interval/EHCI_MAX_UFRAMES; 2615 } 2616 2617 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2618 "ehci_adjust_high_speed_polling_interval: " 2619 "High speed adjusted interval 0x%x", interval); 2620 2621 return (interval); 2622 } 2623 2624 2625 /* 2626 * ehci_lattice_height: 2627 * 2628 * Given the requested bandwidth, find the height in the tree at which the 2629 * nodes for this bandwidth fall. The height is measured as the number of 2630 * nodes from the leaf to the level specified by bandwidth The root of the 2631 * tree is at height TREE_HEIGHT. 2632 */ 2633 static uint_t 2634 ehci_lattice_height(uint_t interval) 2635 { 2636 return (TREE_HEIGHT - (ehci_log_2(interval))); 2637 } 2638 2639 2640 /* 2641 * ehci_lattice_parent: 2642 * 2643 * Given a node in the lattice, find the index of the parent node 2644 */ 2645 static uint_t 2646 ehci_lattice_parent(uint_t node) 2647 { 2648 if ((node % 2) == 0) { 2649 2650 return ((node/2) - 1); 2651 } else { 2652 2653 return ((node + 1)/2 - 1); 2654 } 2655 } 2656 2657 2658 /* 2659 * ehci_find_periodic_node: 2660 * 2661 * Based on the "real" array leaf node and interval, get the periodic node. 2662 */ 2663 static uint_t 2664 ehci_find_periodic_node(uint_t leaf, int interval) { 2665 uint_t lattice_leaf; 2666 uint_t height = ehci_lattice_height(interval); 2667 uint_t pnode; 2668 int i; 2669 2670 /* Get the leaf number in the lattice */ 2671 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2672 2673 /* Get the node in the lattice based on the height and leaf */ 2674 pnode = lattice_leaf; 2675 for (i = 0; i < height; i++) { 2676 pnode = ehci_lattice_parent(pnode); 2677 } 2678 2679 return (pnode); 2680 } 2681 2682 2683 /* 2684 * ehci_leftmost_leaf: 2685 * 2686 * Find the leftmost leaf in the subtree specified by the node. Height refers 2687 * to number of nodes from the bottom of the tree to the node, including the 2688 * node. 2689 * 2690 * The formula for a zero based tree is: 2691 * 2^H * Node + 2^H - 1 2692 * The leaf of the tree is an array, convert the number for the array. 2693 * Subtract the size of nodes not in the array 2694 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2695 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2696 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2697 * 0 2698 * 1 2 2699 * 0 1 2 3 2700 */ 2701 static uint_t 2702 ehci_leftmost_leaf( 2703 uint_t node, 2704 uint_t height) 2705 { 2706 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2707 } 2708 2709 2710 /* 2711 * ehci_pow_2: 2712 * 2713 * Compute 2 to the power 2714 */ 2715 static uint_t 2716 ehci_pow_2(uint_t x) 2717 { 2718 if (x == 0) { 2719 2720 return (1); 2721 } else { 2722 2723 return (2 << (x - 1)); 2724 } 2725 } 2726 2727 2728 /* 2729 * ehci_log_2: 2730 * 2731 * Compute log base 2 of x 2732 */ 2733 static uint_t 2734 ehci_log_2(uint_t x) 2735 { 2736 int i = 0; 2737 2738 while (x != 1) { 2739 x = x >> 1; 2740 i++; 2741 } 2742 2743 return (i); 2744 } 2745 2746 2747 /* 2748 * ehci_find_bestfit_hs_mask: 2749 * 2750 * Find the smask and cmask in the bandwidth allocation, and update the 2751 * bandwidth allocation. 2752 */ 2753 static int 2754 ehci_find_bestfit_hs_mask( 2755 ehci_state_t *ehcip, 2756 uchar_t *smask, 2757 uint_t *pnode, 2758 usb_ep_descr_t *endpoint, 2759 uint_t bandwidth, 2760 int interval) 2761 { 2762 int i; 2763 uint_t elements, index; 2764 int array_leaf, best_array_leaf; 2765 uint_t node_bandwidth, best_node_bandwidth; 2766 uint_t leaf_count; 2767 uchar_t bw_mask; 2768 uchar_t best_smask; 2769 2770 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2771 "ehci_find_bestfit_hs_mask: "); 2772 2773 /* Get all the valid smasks */ 2774 switch (ehci_pow_2(endpoint->bInterval - 1)) { 2775 case EHCI_INTR_1US_POLL: 2776 index = EHCI_1US_MASK_INDEX; 2777 elements = EHCI_INTR_1US_POLL; 2778 break; 2779 case EHCI_INTR_2US_POLL: 2780 index = EHCI_2US_MASK_INDEX; 2781 elements = EHCI_INTR_2US_POLL; 2782 break; 2783 case EHCI_INTR_4US_POLL: 2784 index = EHCI_4US_MASK_INDEX; 2785 elements = EHCI_INTR_4US_POLL; 2786 break; 2787 case EHCI_INTR_XUS_POLL: 2788 default: 2789 index = EHCI_XUS_MASK_INDEX; 2790 elements = EHCI_INTR_XUS_POLL; 2791 break; 2792 } 2793 2794 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 2795 2796 /* 2797 * Because of the way the leaves are setup, we will automatically 2798 * hit the leftmost leaf of every possible node with this interval. 2799 */ 2800 best_smask = 0x00; 2801 best_node_bandwidth = 0; 2802 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 2803 /* Find the bandwidth mask */ 2804 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 2805 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 2806 2807 /* 2808 * If this node cannot support our requirements skip to the 2809 * next leaf. 2810 */ 2811 if (bw_mask == 0x00) { 2812 continue; 2813 } 2814 2815 /* 2816 * Now make sure our bandwidth requirements can be 2817 * satisfied with one of smasks in this node. 2818 */ 2819 *smask = 0x00; 2820 for (i = index; i < (index + elements); i++) { 2821 /* Check the start split mask value */ 2822 if (ehci_start_split_mask[index] & bw_mask) { 2823 *smask = ehci_start_split_mask[index]; 2824 break; 2825 } 2826 } 2827 2828 /* 2829 * If an appropriate smask is found save the information if: 2830 * o best_smask has not been found yet. 2831 * - or - 2832 * o This is the node with the least amount of bandwidth 2833 */ 2834 if ((*smask != 0x00) && 2835 ((best_smask == 0x00) || 2836 (best_node_bandwidth > node_bandwidth))) { 2837 2838 best_node_bandwidth = node_bandwidth; 2839 best_array_leaf = array_leaf; 2840 best_smask = *smask; 2841 } 2842 } 2843 2844 /* 2845 * If we find node that can handle the bandwidth populate the 2846 * appropriate variables and return success. 2847 */ 2848 if (best_smask) { 2849 *smask = best_smask; 2850 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 2851 interval); 2852 ehci_update_bw_availability(ehcip, bandwidth, 2853 ehci_index[best_array_leaf], leaf_count, best_smask); 2854 2855 return (USB_SUCCESS); 2856 } 2857 2858 return (USB_FAILURE); 2859 } 2860 2861 2862 /* 2863 * ehci_find_bestfit_ls_intr_mask: 2864 * 2865 * Find the smask and cmask in the bandwidth allocation. 2866 */ 2867 static int 2868 ehci_find_bestfit_ls_intr_mask( 2869 ehci_state_t *ehcip, 2870 uchar_t *smask, 2871 uchar_t *cmask, 2872 uint_t *pnode, 2873 uint_t sbandwidth, 2874 uint_t cbandwidth, 2875 int interval) 2876 { 2877 int i; 2878 uint_t elements, index; 2879 int array_leaf, best_array_leaf; 2880 uint_t node_sbandwidth, node_cbandwidth; 2881 uint_t best_node_bandwidth; 2882 uint_t leaf_count; 2883 uchar_t bw_smask, bw_cmask; 2884 uchar_t best_smask, best_cmask; 2885 2886 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2887 "ehci_find_bestfit_ls_intr_mask: "); 2888 2889 /* For low and full speed devices */ 2890 index = EHCI_XUS_MASK_INDEX; 2891 elements = EHCI_INTR_4MS_POLL; 2892 2893 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 2894 2895 /* 2896 * Because of the way the leaves are setup, we will automatically 2897 * hit the leftmost leaf of every possible node with this interval. 2898 */ 2899 best_smask = 0x00; 2900 best_node_bandwidth = 0; 2901 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 2902 /* Find the bandwidth mask */ 2903 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 2904 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 2905 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 2906 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 2907 2908 /* 2909 * If this node cannot support our requirements skip to the 2910 * next leaf. 2911 */ 2912 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 2913 continue; 2914 } 2915 2916 /* 2917 * Now make sure our bandwidth requirements can be 2918 * satisfied with one of smasks in this node. 2919 */ 2920 *smask = 0x00; 2921 *cmask = 0x00; 2922 for (i = index; i < (index + elements); i++) { 2923 /* Check the start split mask value */ 2924 if ((ehci_start_split_mask[index] & bw_smask) && 2925 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 2926 *smask = ehci_start_split_mask[index]; 2927 *cmask = ehci_intr_complete_split_mask[index]; 2928 break; 2929 } 2930 } 2931 2932 /* 2933 * If an appropriate smask is found save the information if: 2934 * o best_smask has not been found yet. 2935 * - or - 2936 * o This is the node with the least amount of bandwidth 2937 */ 2938 if ((*smask != 0x00) && 2939 ((best_smask == 0x00) || 2940 (best_node_bandwidth > 2941 (node_sbandwidth + node_cbandwidth)))) { 2942 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 2943 best_array_leaf = array_leaf; 2944 best_smask = *smask; 2945 best_cmask = *cmask; 2946 } 2947 } 2948 2949 /* 2950 * If we find node that can handle the bandwidth populate the 2951 * appropriate variables and return success. 2952 */ 2953 if (best_smask) { 2954 *smask = best_smask; 2955 *cmask = best_cmask; 2956 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 2957 interval); 2958 ehci_update_bw_availability(ehcip, sbandwidth, 2959 ehci_index[best_array_leaf], leaf_count, best_smask); 2960 ehci_update_bw_availability(ehcip, cbandwidth, 2961 ehci_index[best_array_leaf], leaf_count, best_cmask); 2962 2963 return (USB_SUCCESS); 2964 } 2965 2966 return (USB_FAILURE); 2967 } 2968 2969 2970 /* 2971 * ehci_find_bestfit_sitd_in_mask: 2972 * 2973 * Find the smask and cmask in the bandwidth allocation. 2974 */ 2975 static int 2976 ehci_find_bestfit_sitd_in_mask( 2977 ehci_state_t *ehcip, 2978 uchar_t *smask, 2979 uchar_t *cmask, 2980 uint_t *pnode, 2981 uint_t sbandwidth, 2982 uint_t cbandwidth, 2983 int interval) 2984 { 2985 int i, uFrames, found; 2986 int array_leaf, best_array_leaf; 2987 uint_t node_sbandwidth, node_cbandwidth; 2988 uint_t best_node_bandwidth; 2989 uint_t leaf_count; 2990 uchar_t bw_smask, bw_cmask; 2991 uchar_t best_smask, best_cmask; 2992 2993 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2994 "ehci_find_bestfit_sitd_in_mask: "); 2995 2996 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 2997 2998 /* 2999 * Because of the way the leaves are setup, we will automatically 3000 * hit the leftmost leaf of every possible node with this interval. 3001 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3002 */ 3003 /* 3004 * Need to add an additional 2 uFrames, if the "L"ast 3005 * complete split is before uFrame 6. See section 3006 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3007 * the "Back Ptr" which means we support on IN of 3008 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3009 */ 3010 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3011 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3012 uFrames++; 3013 } 3014 if (uFrames > 6) { 3015 3016 return (USB_FAILURE); 3017 } 3018 *smask = 0x1; 3019 *cmask = 0x00; 3020 for (i = 0; i < uFrames; i++) { 3021 *cmask = *cmask << 1; 3022 *cmask |= 0x1; 3023 } 3024 /* cmask must start 2 frames after the smask */ 3025 *cmask = *cmask << 2; 3026 3027 found = 0; 3028 best_smask = 0x00; 3029 best_node_bandwidth = 0; 3030 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3031 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3032 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3033 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3034 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3035 &bw_cmask); 3036 3037 /* 3038 * If this node cannot support our requirements skip to the 3039 * next leaf. 3040 */ 3041 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3042 continue; 3043 } 3044 3045 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3046 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3047 found = 1; 3048 break; 3049 } 3050 *smask = *smask << 1; 3051 *cmask = *cmask << 1; 3052 } 3053 3054 /* 3055 * If an appropriate smask is found save the information if: 3056 * o best_smask has not been found yet. 3057 * - or - 3058 * o This is the node with the least amount of bandwidth 3059 */ 3060 if (found && 3061 ((best_smask == 0x00) || 3062 (best_node_bandwidth > 3063 (node_sbandwidth + node_cbandwidth)))) { 3064 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3065 best_array_leaf = array_leaf; 3066 best_smask = *smask; 3067 best_cmask = *cmask; 3068 } 3069 } 3070 3071 /* 3072 * If we find node that can handle the bandwidth populate the 3073 * appropriate variables and return success. 3074 */ 3075 if (best_smask) { 3076 *smask = best_smask; 3077 *cmask = best_cmask; 3078 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3079 interval); 3080 ehci_update_bw_availability(ehcip, sbandwidth, 3081 ehci_index[best_array_leaf], leaf_count, best_smask); 3082 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3083 ehci_index[best_array_leaf], leaf_count, best_cmask); 3084 3085 return (USB_SUCCESS); 3086 } 3087 3088 return (USB_FAILURE); 3089 } 3090 3091 3092 /* 3093 * ehci_find_bestfit_sitd_out_mask: 3094 * 3095 * Find the smask in the bandwidth allocation. 3096 */ 3097 static int 3098 ehci_find_bestfit_sitd_out_mask( 3099 ehci_state_t *ehcip, 3100 uchar_t *smask, 3101 uint_t *pnode, 3102 uint_t sbandwidth, 3103 int interval) 3104 { 3105 int i, uFrames, found; 3106 int array_leaf, best_array_leaf; 3107 uint_t node_sbandwidth; 3108 uint_t best_node_bandwidth; 3109 uint_t leaf_count; 3110 uchar_t bw_smask; 3111 uchar_t best_smask; 3112 3113 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3114 "ehci_find_bestfit_sitd_out_mask: "); 3115 3116 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3117 3118 /* 3119 * Because of the way the leaves are setup, we will automatically 3120 * hit the leftmost leaf of every possible node with this interval. 3121 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3122 */ 3123 *smask = 0x00; 3124 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3125 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3126 uFrames++; 3127 } 3128 for (i = 0; i < uFrames; i++) { 3129 *smask = *smask << 1; 3130 *smask |= 0x1; 3131 } 3132 3133 found = 0; 3134 best_smask = 0x00; 3135 best_node_bandwidth = 0; 3136 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3137 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3138 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3139 &bw_smask); 3140 3141 /* 3142 * If this node cannot support our requirements skip to the 3143 * next leaf. 3144 */ 3145 if (bw_smask == 0x00) { 3146 continue; 3147 } 3148 3149 /* You cannot have a start split on the 8th uFrame */ 3150 for (i = 0; (*smask & 0x80) == 0; i++) { 3151 if (*smask & bw_smask) { 3152 found = 1; 3153 break; 3154 } 3155 *smask = *smask << 1; 3156 } 3157 3158 /* 3159 * If an appropriate smask is found save the information if: 3160 * o best_smask has not been found yet. 3161 * - or - 3162 * o This is the node with the least amount of bandwidth 3163 */ 3164 if (found && 3165 ((best_smask == 0x00) || 3166 (best_node_bandwidth > node_sbandwidth))) { 3167 best_node_bandwidth = node_sbandwidth; 3168 best_array_leaf = array_leaf; 3169 best_smask = *smask; 3170 } 3171 } 3172 3173 /* 3174 * If we find node that can handle the bandwidth populate the 3175 * appropriate variables and return success. 3176 */ 3177 if (best_smask) { 3178 *smask = best_smask; 3179 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3180 interval); 3181 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3182 ehci_index[best_array_leaf], leaf_count, best_smask); 3183 3184 return (USB_SUCCESS); 3185 } 3186 3187 return (USB_FAILURE); 3188 } 3189 3190 3191 /* 3192 * ehci_calculate_bw_availability_mask: 3193 * 3194 * Returns the "total bandwidth used" in this node. 3195 * Populates bw_mask with the uFrames that can support the bandwidth. 3196 * 3197 * If all the Frames cannot support this bandwidth, then bw_mask 3198 * will return 0x00 and the "total bandwidth used" will be invalid. 3199 */ 3200 static uint_t 3201 ehci_calculate_bw_availability_mask( 3202 ehci_state_t *ehcip, 3203 uint_t bandwidth, 3204 int leaf, 3205 int leaf_count, 3206 uchar_t *bw_mask) 3207 { 3208 int i, j; 3209 uchar_t bw_uframe; 3210 int uframe_total; 3211 ehci_frame_bandwidth_t *fbp; 3212 uint_t total_bandwidth = 0; 3213 3214 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3215 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3216 leaf, leaf_count); 3217 3218 /* Start by saying all uFrames are available */ 3219 *bw_mask = 0xFF; 3220 3221 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3222 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3223 3224 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3225 3226 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3227 /* 3228 * If the uFrame in bw_mask is available check to see if 3229 * it can support the additional bandwidth. 3230 */ 3231 bw_uframe = (*bw_mask & (0x1 << j)); 3232 uframe_total = 3233 fbp->ehci_micro_frame_bandwidth[j] + 3234 bandwidth; 3235 if ((bw_uframe) && 3236 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3237 *bw_mask = *bw_mask & ~bw_uframe; 3238 } 3239 } 3240 } 3241 3242 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3243 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3244 *bw_mask); 3245 3246 return (total_bandwidth); 3247 } 3248 3249 3250 /* 3251 * ehci_update_bw_availability: 3252 * 3253 * The leftmost leaf needs to be in terms of array position and 3254 * not the actual lattice position. 3255 */ 3256 static void 3257 ehci_update_bw_availability( 3258 ehci_state_t *ehcip, 3259 int bandwidth, 3260 int leftmost_leaf, 3261 int leaf_count, 3262 uchar_t mask) 3263 { 3264 int i, j; 3265 ehci_frame_bandwidth_t *fbp; 3266 int uFrame_bandwidth[8]; 3267 3268 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3269 "ehci_update_bw_availability: " 3270 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3271 leftmost_leaf, leaf_count, bandwidth, mask); 3272 3273 ASSERT(leftmost_leaf < 32); 3274 ASSERT(leftmost_leaf >= 0); 3275 3276 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3277 if (mask & 0x1) { 3278 uFrame_bandwidth[j] = bandwidth; 3279 } else { 3280 uFrame_bandwidth[j] = 0; 3281 } 3282 3283 mask = mask >> 1; 3284 } 3285 3286 /* Updated all the effected leafs with the bandwidth */ 3287 for (i = 0; i < leaf_count; i++) { 3288 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3289 3290 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3291 fbp->ehci_micro_frame_bandwidth[j] += 3292 uFrame_bandwidth[j]; 3293 fbp->ehci_allocated_frame_bandwidth += 3294 uFrame_bandwidth[j]; 3295 } 3296 } 3297 } 3298 3299 /* 3300 * Miscellaneous functions 3301 */ 3302 3303 /* 3304 * ehci_obtain_state: 3305 * 3306 * NOTE: This function is also called from POLLED MODE. 3307 */ 3308 ehci_state_t * 3309 ehci_obtain_state(dev_info_t *dip) 3310 { 3311 int instance = ddi_get_instance(dip); 3312 3313 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3314 3315 ASSERT(state != NULL); 3316 3317 return (state); 3318 } 3319 3320 3321 /* 3322 * ehci_state_is_operational: 3323 * 3324 * Check the Host controller state and return proper values. 3325 */ 3326 int 3327 ehci_state_is_operational(ehci_state_t *ehcip) 3328 { 3329 int val; 3330 3331 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3332 3333 switch (ehcip->ehci_hc_soft_state) { 3334 case EHCI_CTLR_INIT_STATE: 3335 case EHCI_CTLR_SUSPEND_STATE: 3336 val = USB_FAILURE; 3337 break; 3338 case EHCI_CTLR_OPERATIONAL_STATE: 3339 val = USB_SUCCESS; 3340 break; 3341 case EHCI_CTLR_ERROR_STATE: 3342 val = USB_HC_HARDWARE_ERROR; 3343 break; 3344 default: 3345 val = USB_FAILURE; 3346 break; 3347 } 3348 3349 return (val); 3350 } 3351 3352 3353 /* 3354 * ehci_do_soft_reset 3355 * 3356 * Do soft reset of ehci host controller. 3357 */ 3358 int 3359 ehci_do_soft_reset(ehci_state_t *ehcip) 3360 { 3361 usb_frame_number_t before_frame_number, after_frame_number; 3362 ehci_regs_t *ehci_save_regs; 3363 3364 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3365 3366 /* Increment host controller error count */ 3367 ehcip->ehci_hc_error++; 3368 3369 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3370 "ehci_do_soft_reset:" 3371 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3372 3373 /* 3374 * Allocate space for saving current Host Controller 3375 * registers. Don't do any recovery if allocation 3376 * fails. 3377 */ 3378 ehci_save_regs = (ehci_regs_t *) 3379 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3380 3381 if (ehci_save_regs == NULL) { 3382 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3383 "ehci_do_soft_reset: kmem_zalloc failed"); 3384 3385 return (USB_FAILURE); 3386 } 3387 3388 /* Save current ehci registers */ 3389 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3390 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3391 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3392 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3393 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3394 ehci_save_regs->ehci_periodic_list_base = 3395 Get_OpReg(ehci_periodic_list_base); 3396 3397 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3398 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3399 3400 /* Disable all list processing and interrupts */ 3401 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3402 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3403 3404 /* Disable all EHCI interrupts */ 3405 Set_OpReg(ehci_interrupt, 0); 3406 3407 /* Wait for few milliseconds */ 3408 drv_usecwait(EHCI_SOF_TIMEWAIT); 3409 3410 /* Do light soft reset of ehci host controller */ 3411 Set_OpReg(ehci_command, 3412 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3413 3414 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3415 "ehci_do_soft_reset: Reset in progress"); 3416 3417 /* Wait for reset to complete */ 3418 drv_usecwait(EHCI_RESET_TIMEWAIT); 3419 3420 /* 3421 * Restore previous saved EHCI register value 3422 * into the current EHCI registers. 3423 */ 3424 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3425 ehci_save_regs->ehci_ctrl_segment); 3426 3427 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3428 ehci_save_regs->ehci_periodic_list_base); 3429 3430 Set_OpReg(ehci_async_list_addr, (uint32_t) 3431 ehci_save_regs->ehci_async_list_addr); 3432 3433 Set_OpReg(ehci_config_flag, (uint32_t) 3434 ehci_save_regs->ehci_config_flag); 3435 3436 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3437 ehci_toggle_scheduler(ehcip); 3438 3439 /* 3440 * Set ehci_interrupt to enable all interrupts except Root 3441 * Hub Status change and frame list rollover interrupts. 3442 */ 3443 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3444 EHCI_INTR_FRAME_LIST_ROLLOVER | 3445 EHCI_INTR_USB_ERROR | 3446 EHCI_INTR_USB); 3447 3448 /* 3449 * Deallocate the space that allocated for saving 3450 * HC registers. 3451 */ 3452 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3453 3454 /* 3455 * Set the desired interrupt threshold, frame list size (if 3456 * applicable) and turn EHCI host controller. 3457 */ 3458 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3459 ~EHCI_CMD_INTR_THRESHOLD) | 3460 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3461 3462 /* Wait 10ms for EHCI to start sending SOF */ 3463 drv_usecwait(EHCI_RESET_TIMEWAIT); 3464 3465 /* 3466 * Get the current usb frame number before waiting for 3467 * few milliseconds. 3468 */ 3469 before_frame_number = ehci_get_current_frame_number(ehcip); 3470 3471 /* Wait for few milliseconds */ 3472 drv_usecwait(EHCI_SOF_TIMEWAIT); 3473 3474 /* 3475 * Get the current usb frame number after waiting for 3476 * few milliseconds. 3477 */ 3478 after_frame_number = ehci_get_current_frame_number(ehcip); 3479 3480 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3481 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3482 "After Frame Number 0x%llx", 3483 before_frame_number, after_frame_number); 3484 3485 if ((after_frame_number <= before_frame_number) && 3486 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3487 3488 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3489 "ehci_do_soft_reset: Soft reset failed"); 3490 3491 return (USB_FAILURE); 3492 } 3493 3494 return (USB_SUCCESS); 3495 } 3496 3497 3498 /* 3499 * ehci_get_xfer_attrs: 3500 * 3501 * Get the attributes of a particular xfer. 3502 * 3503 * NOTE: This function is also called from POLLED MODE. 3504 */ 3505 usb_req_attrs_t 3506 ehci_get_xfer_attrs( 3507 ehci_state_t *ehcip, 3508 ehci_pipe_private_t *pp, 3509 ehci_trans_wrapper_t *tw) 3510 { 3511 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3512 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3513 3514 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3515 "ehci_get_xfer_attrs:"); 3516 3517 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3518 case USB_EP_ATTR_CONTROL: 3519 attrs = ((usb_ctrl_req_t *) 3520 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3521 break; 3522 case USB_EP_ATTR_BULK: 3523 attrs = ((usb_bulk_req_t *) 3524 tw->tw_curr_xfer_reqp)->bulk_attributes; 3525 break; 3526 case USB_EP_ATTR_INTR: 3527 attrs = ((usb_intr_req_t *) 3528 tw->tw_curr_xfer_reqp)->intr_attributes; 3529 break; 3530 } 3531 3532 return (attrs); 3533 } 3534 3535 3536 /* 3537 * ehci_get_current_frame_number: 3538 * 3539 * Get the current software based usb frame number. 3540 */ 3541 usb_frame_number_t 3542 ehci_get_current_frame_number(ehci_state_t *ehcip) 3543 { 3544 usb_frame_number_t usb_frame_number; 3545 usb_frame_number_t ehci_fno, micro_frame_number; 3546 3547 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3548 3549 ehci_fno = ehcip->ehci_fno; 3550 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3551 3552 /* 3553 * Calculate current software based usb frame number. 3554 * 3555 * This code accounts for the fact that frame number is 3556 * updated by the Host Controller before the ehci driver 3557 * gets an FrameListRollover interrupt that will adjust 3558 * Frame higher part. 3559 * 3560 * Refer ehci specification 1.0, section 2.3.2, page 21. 3561 */ 3562 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3563 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3564 ehci_fno) & 0x2000); 3565 3566 /* 3567 * Micro Frame number is equivalent to 125 usec. Eight 3568 * Micro Frame numbers are equivalent to one millsecond 3569 * or one usb frame number. 3570 */ 3571 usb_frame_number = micro_frame_number >> 3572 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3573 3574 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3575 "ehci_get_current_frame_number: " 3576 "Current usb uframe number = 0x%llx " 3577 "Current usb frame number = 0x%llx", 3578 micro_frame_number, usb_frame_number); 3579 3580 return (usb_frame_number); 3581 } 3582 3583 3584 /* 3585 * ehci_cpr_cleanup: 3586 * 3587 * Cleanup ehci state and other ehci specific informations across 3588 * Check Point Resume (CPR). 3589 */ 3590 static void 3591 ehci_cpr_cleanup(ehci_state_t *ehcip) 3592 { 3593 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3594 3595 /* Reset software part of usb frame number */ 3596 ehcip->ehci_fno = 0; 3597 } 3598 3599 3600 /* 3601 * ehci_wait_for_sof: 3602 * 3603 * Wait for couple of SOF interrupts 3604 */ 3605 int 3606 ehci_wait_for_sof(ehci_state_t *ehcip) 3607 { 3608 usb_frame_number_t before_frame_number, after_frame_number; 3609 int error = USB_SUCCESS; 3610 3611 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3612 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3613 3614 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3615 3616 error = ehci_state_is_operational(ehcip); 3617 3618 if (error != USB_SUCCESS) { 3619 3620 return (error); 3621 } 3622 3623 /* Get the current usb frame number before waiting for two SOFs */ 3624 before_frame_number = ehci_get_current_frame_number(ehcip); 3625 3626 mutex_exit(&ehcip->ehci_int_mutex); 3627 3628 /* Wait for few milliseconds */ 3629 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3630 3631 mutex_enter(&ehcip->ehci_int_mutex); 3632 3633 /* Get the current usb frame number after woken up */ 3634 after_frame_number = ehci_get_current_frame_number(ehcip); 3635 3636 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3637 "ehci_wait_for_sof: framenumber: before 0x%llx " 3638 "after 0x%llx", before_frame_number, after_frame_number); 3639 3640 /* Return failure, if usb frame number has not been changed */ 3641 if (after_frame_number <= before_frame_number) { 3642 3643 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3644 3645 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3646 ehcip->ehci_log_hdl, "No SOF interrupts"); 3647 3648 /* Set host controller soft state to error */ 3649 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3650 3651 return (USB_FAILURE); 3652 } 3653 3654 /* Get new usb frame number */ 3655 after_frame_number = before_frame_number = 3656 ehci_get_current_frame_number(ehcip); 3657 } 3658 3659 ASSERT(after_frame_number > before_frame_number); 3660 3661 return (USB_SUCCESS); 3662 } 3663 3664 3665 /* 3666 * ehci_toggle_scheduler: 3667 * 3668 * Turn scheduler based on pipe open count. 3669 */ 3670 void 3671 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3672 uint_t temp_reg, cmd_reg; 3673 3674 cmd_reg = Get_OpReg(ehci_command); 3675 temp_reg = cmd_reg; 3676 3677 /* 3678 * Enable/Disable asynchronous scheduler, and 3679 * turn on/off async list door bell 3680 */ 3681 if (ehcip->ehci_open_async_count) { 3682 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3683 /* 3684 * For some reason this address might get nulled out by 3685 * the ehci chip. Set it here just in case it is null. 3686 */ 3687 Set_OpReg(ehci_async_list_addr, 3688 ehci_qh_cpu_to_iommu(ehcip, 3689 ehcip->ehci_head_of_async_sched_list)); 3690 } 3691 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 3692 } else { 3693 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 3694 } 3695 3696 if (ehcip->ehci_open_periodic_count) { 3697 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 3698 /* 3699 * For some reason this address get's nulled out by 3700 * the ehci chip. Set it here just in case it is null. 3701 */ 3702 Set_OpReg(ehci_periodic_list_base, 3703 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 3704 0xFFFFF000)); 3705 } 3706 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 3707 } else { 3708 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 3709 } 3710 3711 /* Just an optimization */ 3712 if (temp_reg != cmd_reg) { 3713 Set_OpReg(ehci_command, cmd_reg); 3714 } 3715 } 3716 3717 /* 3718 * ehci print functions 3719 */ 3720 3721 /* 3722 * ehci_print_caps: 3723 */ 3724 void 3725 ehci_print_caps(ehci_state_t *ehcip) 3726 { 3727 uint_t i; 3728 3729 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3730 "\n\tUSB 2.0 Host Controller Characteristics\n"); 3731 3732 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3733 "Caps Length: 0x%x Version: 0x%x\n", 3734 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 3735 3736 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3737 "Structural Parameters\n"); 3738 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3739 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 3740 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 3741 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3742 "No of Classic host controllers: 0x%x", 3743 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 3744 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 3745 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3746 "No of ports per Classic host controller: 0x%x", 3747 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 3748 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 3749 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3750 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 3751 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 3752 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3753 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 3754 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 3755 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3756 "No of root hub ports: 0x%x\n", 3757 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 3758 3759 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3760 "Capability Parameters\n"); 3761 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3762 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 3763 EHCI_HCC_EECP) ? "Yes" : "No"); 3764 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3765 "Isoch schedule threshold: 0x%x", 3766 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 3767 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3768 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 3769 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 3770 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3771 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 3772 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 3773 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3774 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 3775 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 3776 3777 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3778 "Classic Port Route Description"); 3779 3780 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 3781 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3782 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 3783 } 3784 } 3785 3786 3787 /* 3788 * ehci_print_regs: 3789 */ 3790 void 3791 ehci_print_regs(ehci_state_t *ehcip) 3792 { 3793 uint_t i; 3794 3795 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3796 "\n\tEHCI%d Operational Registers\n", 3797 ddi_get_instance(ehcip->ehci_dip)); 3798 3799 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3800 "Command: 0x%x Status: 0x%x", 3801 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 3802 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3803 "Interrupt: 0x%x Frame Index: 0x%x", 3804 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 3805 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3806 "Control Segment: 0x%x Periodic List Base: 0x%x", 3807 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 3808 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3809 "Async List Addr: 0x%x Config Flag: 0x%x", 3810 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 3811 3812 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3813 "Root Hub Port Status"); 3814 3815 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 3816 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3817 "\tPort Status 0x%x: 0x%x ", i, 3818 Get_OpReg(ehci_rh_port_status[i])); 3819 } 3820 } 3821 3822 3823 /* 3824 * ehci_print_qh: 3825 */ 3826 void 3827 ehci_print_qh( 3828 ehci_state_t *ehcip, 3829 ehci_qh_t *qh) 3830 { 3831 uint_t i; 3832 3833 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3834 "ehci_print_qh: qh = 0x%p", (void *)qh); 3835 3836 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3837 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 3838 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3839 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 3840 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3841 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 3842 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3843 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 3844 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3845 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 3846 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3847 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 3848 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3849 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 3850 3851 for (i = 0; i < 5; i++) { 3852 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3853 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 3854 } 3855 3856 for (i = 0; i < 5; i++) { 3857 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3858 "\tqh_buf_high[%d]: 0x%x ", 3859 i, Get_QH(qh->qh_buf_high[i])); 3860 } 3861 3862 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3863 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 3864 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3865 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 3866 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3867 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 3868 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3869 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 3870 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3871 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 3872 } 3873 3874 3875 /* 3876 * ehci_print_qtd: 3877 */ 3878 void 3879 ehci_print_qtd( 3880 ehci_state_t *ehcip, 3881 ehci_qtd_t *qtd) 3882 { 3883 uint_t i; 3884 3885 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3886 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 3887 3888 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3889 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 3890 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3891 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 3892 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3893 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 3894 3895 for (i = 0; i < 5; i++) { 3896 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3897 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 3898 } 3899 3900 for (i = 0; i < 5; i++) { 3901 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3902 "\tqtd_buf_high[%d]: 0x%x ", 3903 i, Get_QTD(qtd->qtd_buf_high[i])); 3904 } 3905 3906 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3907 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 3908 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3909 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 3910 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3911 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 3912 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3913 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 3914 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3915 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 3916 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3917 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 3918 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3919 "\tqtd_xfer_addr: 0x%x ", Get_QTD(qtd->qtd_xfer_addr)); 3920 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3921 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 3922 } 3923 3924 /* 3925 * ehci kstat functions 3926 */ 3927 3928 /* 3929 * ehci_create_stats: 3930 * 3931 * Allocate and initialize the ehci kstat structures 3932 */ 3933 void 3934 ehci_create_stats(ehci_state_t *ehcip) 3935 { 3936 char kstatname[KSTAT_STRLEN]; 3937 const char *dname = ddi_driver_name(ehcip->ehci_dip); 3938 char *usbtypes[USB_N_COUNT_KSTATS] = 3939 {"ctrl", "isoch", "bulk", "intr"}; 3940 uint_t instance = ehcip->ehci_instance; 3941 ehci_intrs_stats_t *isp; 3942 int i; 3943 3944 if (EHCI_INTRS_STATS(ehcip) == NULL) { 3945 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 3946 dname, instance); 3947 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 3948 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 3949 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 3950 KSTAT_FLAG_PERSISTENT); 3951 3952 if (EHCI_INTRS_STATS(ehcip)) { 3953 isp = EHCI_INTRS_STATS_DATA(ehcip); 3954 kstat_named_init(&isp->ehci_sts_total, 3955 "Interrupts Total", KSTAT_DATA_UINT64); 3956 kstat_named_init(&isp->ehci_sts_not_claimed, 3957 "Not Claimed", KSTAT_DATA_UINT64); 3958 kstat_named_init(&isp->ehci_sts_async_sched_status, 3959 "Async schedule status", KSTAT_DATA_UINT64); 3960 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 3961 "Periodic sched status", KSTAT_DATA_UINT64); 3962 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 3963 "Empty async schedule", KSTAT_DATA_UINT64); 3964 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 3965 "Host controller Halted", KSTAT_DATA_UINT64); 3966 kstat_named_init(&isp->ehci_sts_async_advance_intr, 3967 "Intr on async advance", KSTAT_DATA_UINT64); 3968 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 3969 "Host system error", KSTAT_DATA_UINT64); 3970 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 3971 "Frame list rollover", KSTAT_DATA_UINT64); 3972 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 3973 "Port change detect", KSTAT_DATA_UINT64); 3974 kstat_named_init(&isp->ehci_sts_usb_error_intr, 3975 "USB error interrupt", KSTAT_DATA_UINT64); 3976 kstat_named_init(&isp->ehci_sts_usb_intr, 3977 "USB interrupt", KSTAT_DATA_UINT64); 3978 3979 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 3980 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 3981 kstat_install(EHCI_INTRS_STATS(ehcip)); 3982 } 3983 } 3984 3985 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 3986 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 3987 dname, instance); 3988 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 3989 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 3990 KSTAT_FLAG_PERSISTENT); 3991 3992 if (EHCI_TOTAL_STATS(ehcip)) { 3993 kstat_install(EHCI_TOTAL_STATS(ehcip)); 3994 } 3995 } 3996 3997 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 3998 if (ehcip->ehci_count_stats[i] == NULL) { 3999 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4000 dname, instance, usbtypes[i]); 4001 ehcip->ehci_count_stats[i] = kstat_create("usba", 4002 instance, kstatname, "usb_byte_count", 4003 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4004 4005 if (ehcip->ehci_count_stats[i]) { 4006 kstat_install(ehcip->ehci_count_stats[i]); 4007 } 4008 } 4009 } 4010 } 4011 4012 4013 /* 4014 * ehci_destroy_stats: 4015 * 4016 * Clean up ehci kstat structures 4017 */ 4018 void 4019 ehci_destroy_stats(ehci_state_t *ehcip) 4020 { 4021 int i; 4022 4023 if (EHCI_INTRS_STATS(ehcip)) { 4024 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4025 EHCI_INTRS_STATS(ehcip) = NULL; 4026 } 4027 4028 if (EHCI_TOTAL_STATS(ehcip)) { 4029 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4030 EHCI_TOTAL_STATS(ehcip) = NULL; 4031 } 4032 4033 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4034 if (ehcip->ehci_count_stats[i]) { 4035 kstat_delete(ehcip->ehci_count_stats[i]); 4036 ehcip->ehci_count_stats[i] = NULL; 4037 } 4038 } 4039 } 4040 4041 4042 /* 4043 * ehci_do_intrs_stats: 4044 * 4045 * ehci status information 4046 */ 4047 void 4048 ehci_do_intrs_stats( 4049 ehci_state_t *ehcip, 4050 int val) 4051 { 4052 if (EHCI_INTRS_STATS(ehcip)) { 4053 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4054 switch (val) { 4055 case EHCI_STS_ASYNC_SCHED_STATUS: 4056 EHCI_INTRS_STATS_DATA(ehcip)-> 4057 ehci_sts_async_sched_status.value.ui64++; 4058 break; 4059 case EHCI_STS_PERIODIC_SCHED_STATUS: 4060 EHCI_INTRS_STATS_DATA(ehcip)-> 4061 ehci_sts_periodic_sched_status.value.ui64++; 4062 break; 4063 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4064 EHCI_INTRS_STATS_DATA(ehcip)-> 4065 ehci_sts_empty_async_schedule.value.ui64++; 4066 break; 4067 case EHCI_STS_HOST_CTRL_HALTED: 4068 EHCI_INTRS_STATS_DATA(ehcip)-> 4069 ehci_sts_host_ctrl_halted.value.ui64++; 4070 break; 4071 case EHCI_STS_ASYNC_ADVANCE_INTR: 4072 EHCI_INTRS_STATS_DATA(ehcip)-> 4073 ehci_sts_async_advance_intr.value.ui64++; 4074 break; 4075 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4076 EHCI_INTRS_STATS_DATA(ehcip)-> 4077 ehci_sts_host_system_error_intr.value.ui64++; 4078 break; 4079 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4080 EHCI_INTRS_STATS_DATA(ehcip)-> 4081 ehci_sts_frm_list_rollover_intr.value.ui64++; 4082 break; 4083 case EHCI_STS_RH_PORT_CHANGE_INTR: 4084 EHCI_INTRS_STATS_DATA(ehcip)-> 4085 ehci_sts_rh_port_change_intr.value.ui64++; 4086 break; 4087 case EHCI_STS_USB_ERROR_INTR: 4088 EHCI_INTRS_STATS_DATA(ehcip)-> 4089 ehci_sts_usb_error_intr.value.ui64++; 4090 break; 4091 case EHCI_STS_USB_INTR: 4092 EHCI_INTRS_STATS_DATA(ehcip)-> 4093 ehci_sts_usb_intr.value.ui64++; 4094 break; 4095 default: 4096 EHCI_INTRS_STATS_DATA(ehcip)-> 4097 ehci_sts_not_claimed.value.ui64++; 4098 break; 4099 } 4100 } 4101 } 4102 4103 4104 /* 4105 * ehci_do_byte_stats: 4106 * 4107 * ehci data xfer information 4108 */ 4109 void 4110 ehci_do_byte_stats( 4111 ehci_state_t *ehcip, 4112 size_t len, 4113 uint8_t attr, 4114 uint8_t addr) 4115 { 4116 uint8_t type = attr & USB_EP_ATTR_MASK; 4117 uint8_t dir = addr & USB_EP_DIR_MASK; 4118 4119 if (dir == USB_EP_DIR_IN) { 4120 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4121 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4122 switch (type) { 4123 case USB_EP_ATTR_CONTROL: 4124 EHCI_CTRL_STATS(ehcip)->reads++; 4125 EHCI_CTRL_STATS(ehcip)->nread += len; 4126 break; 4127 case USB_EP_ATTR_BULK: 4128 EHCI_BULK_STATS(ehcip)->reads++; 4129 EHCI_BULK_STATS(ehcip)->nread += len; 4130 break; 4131 case USB_EP_ATTR_INTR: 4132 EHCI_INTR_STATS(ehcip)->reads++; 4133 EHCI_INTR_STATS(ehcip)->nread += len; 4134 break; 4135 case USB_EP_ATTR_ISOCH: 4136 EHCI_ISOC_STATS(ehcip)->reads++; 4137 EHCI_ISOC_STATS(ehcip)->nread += len; 4138 break; 4139 } 4140 } else if (dir == USB_EP_DIR_OUT) { 4141 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4142 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4143 switch (type) { 4144 case USB_EP_ATTR_CONTROL: 4145 EHCI_CTRL_STATS(ehcip)->writes++; 4146 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4147 break; 4148 case USB_EP_ATTR_BULK: 4149 EHCI_BULK_STATS(ehcip)->writes++; 4150 EHCI_BULK_STATS(ehcip)->nwritten += len; 4151 break; 4152 case USB_EP_ATTR_INTR: 4153 EHCI_INTR_STATS(ehcip)->writes++; 4154 EHCI_INTR_STATS(ehcip)->nwritten += len; 4155 break; 4156 case USB_EP_ATTR_ISOCH: 4157 EHCI_ISOC_STATS(ehcip)->writes++; 4158 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4159 break; 4160 } 4161 } 4162 } 4163