xref: /onnv-gate/usr/src/uts/common/io/rwn/rt2860_reg.h (revision 9172:e625dee308d1)
1*9172SFei.Feng@Sun.COM /*
2*9172SFei.Feng@Sun.COM  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3*9172SFei.Feng@Sun.COM  * Use is subject to license terms.
4*9172SFei.Feng@Sun.COM  */
5*9172SFei.Feng@Sun.COM 
6*9172SFei.Feng@Sun.COM /*
7*9172SFei.Feng@Sun.COM  * Copyright (c) 2007, 2008
8*9172SFei.Feng@Sun.COM  *	Damien Bergamini <damien.bergamini@free.fr>
9*9172SFei.Feng@Sun.COM  *
10*9172SFei.Feng@Sun.COM  * Permission to use, copy, modify, and distribute this software for any
11*9172SFei.Feng@Sun.COM  * purpose with or without fee is hereby granted, provided that the above
12*9172SFei.Feng@Sun.COM  * copyright notice and this permission notice appear in all copies.
13*9172SFei.Feng@Sun.COM  *
14*9172SFei.Feng@Sun.COM  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15*9172SFei.Feng@Sun.COM  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16*9172SFei.Feng@Sun.COM  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17*9172SFei.Feng@Sun.COM  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18*9172SFei.Feng@Sun.COM  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19*9172SFei.Feng@Sun.COM  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20*9172SFei.Feng@Sun.COM  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21*9172SFei.Feng@Sun.COM  */
22*9172SFei.Feng@Sun.COM 
23*9172SFei.Feng@Sun.COM #ifndef _RT2860_REG_H
24*9172SFei.Feng@Sun.COM #define	_RT2860_REG_H
25*9172SFei.Feng@Sun.COM 
26*9172SFei.Feng@Sun.COM #ifdef __cplusplus
27*9172SFei.Feng@Sun.COM extern "C" {
28*9172SFei.Feng@Sun.COM #endif
29*9172SFei.Feng@Sun.COM 
30*9172SFei.Feng@Sun.COM /* Device ID */
31*9172SFei.Feng@Sun.COM #define	PRODUCT_RALINK_RT2860		0x0601
32*9172SFei.Feng@Sun.COM #define	PRODUCT_RALINK_RT2890		0x0681
33*9172SFei.Feng@Sun.COM #define	PRODUCT_RALINK_RT2760		0x0701
34*9172SFei.Feng@Sun.COM #define	PRODUCT_RALINK_RT2790		0x0781
35*9172SFei.Feng@Sun.COM #define	PRODUCT_AWT_RT2890		0x1059
36*9172SFei.Feng@Sun.COM 
37*9172SFei.Feng@Sun.COM /* PCI registers */
38*9172SFei.Feng@Sun.COM #define	RT2860_PCI_CFG			0x0000
39*9172SFei.Feng@Sun.COM #define	RT2860_PCI_EECTRL		0x0004
40*9172SFei.Feng@Sun.COM #define	RT2860_PCI_MCUCTRL		0x0008
41*9172SFei.Feng@Sun.COM #define	RT2860_PCI_SYSCTRL		0x000c
42*9172SFei.Feng@Sun.COM #define	RT2860_PCIE_JTAG		0x0010
43*9172SFei.Feng@Sun.COM 
44*9172SFei.Feng@Sun.COM /* SCH/DMA registers */
45*9172SFei.Feng@Sun.COM #define	RT2860_INT_STATUS		0x0200
46*9172SFei.Feng@Sun.COM #define	RT2860_INT_MASK			0x0204
47*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_GLO_CFG		0x0208
48*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_RST_IDX		0x020c
49*9172SFei.Feng@Sun.COM #define	RT2860_DELAY_INT_CFG		0x0210
50*9172SFei.Feng@Sun.COM #define	RT2860_WMM_AIFSN_CFG		0x0214
51*9172SFei.Feng@Sun.COM #define	RT2860_WMM_CWMIN_CFG		0x0218
52*9172SFei.Feng@Sun.COM #define	RT2860_WMM_CWMAX_CFG		0x021c
53*9172SFei.Feng@Sun.COM #define	RT2860_WMM_TXOP0_CFG		0x0220
54*9172SFei.Feng@Sun.COM #define	RT2860_WMM_TXOP1_CFG		0x0224
55*9172SFei.Feng@Sun.COM #define	RT2860_GPIO_CTRL		0x0228
56*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_REG		0x022c
57*9172SFei.Feng@Sun.COM #define	RT2860_TX_BASE_PTR(qid)		(0x0230 + (qid) * 16)
58*9172SFei.Feng@Sun.COM #define	RT2860_TX_MAX_CNT(qid)		(0x0234 + (qid) * 16)
59*9172SFei.Feng@Sun.COM #define	RT2860_TX_CTX_IDX(qid)		(0x0238 + (qid) * 16)
60*9172SFei.Feng@Sun.COM #define	RT2860_TX_DTX_IDX(qid)		(0x023c + (qid) * 16)
61*9172SFei.Feng@Sun.COM #define	RT2860_RX_BASE_PTR		0x0290
62*9172SFei.Feng@Sun.COM #define	RT2860_RX_MAX_CNT		0x0294
63*9172SFei.Feng@Sun.COM #define	RT2860_RX_CALC_IDX		0x0298
64*9172SFei.Feng@Sun.COM #define	RT2860_FS_DRX_IDX		0x029c
65*9172SFei.Feng@Sun.COM #define	RT2860_US_CYC_CNT		0x02a4
66*9172SFei.Feng@Sun.COM 
67*9172SFei.Feng@Sun.COM /* PBF registers */
68*9172SFei.Feng@Sun.COM #define	RT2860_SYS_CTRL			0x0400
69*9172SFei.Feng@Sun.COM #define	RT2860_HOST_CMD			0x0404
70*9172SFei.Feng@Sun.COM #define	RT2860_PBF_CFG			0x0408
71*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PCNT			0x040c
72*9172SFei.Feng@Sun.COM #define	RT2860_BUF_CTRL			0x0410
73*9172SFei.Feng@Sun.COM #define	RT2860_MCU_INT_STA		0x0414
74*9172SFei.Feng@Sun.COM #define	RT2860_MCU_INT_ENA		0x0418
75*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_IO(qid)		(0x041c + (qid) * 4)
76*9172SFei.Feng@Sun.COM #define	RT2860_RX0Q_IO			0x0424
77*9172SFei.Feng@Sun.COM #define	RT2860_BCN_OFFSET0		0x042c
78*9172SFei.Feng@Sun.COM #define	RT2860_BCN_OFFSET1		0x0430
79*9172SFei.Feng@Sun.COM #define	RT2860_TXRXQ_STA		0x0434
80*9172SFei.Feng@Sun.COM #define	RT2860_TXRXQ_PCNT		0x0438
81*9172SFei.Feng@Sun.COM #define	RT2860_PBF_DBG			0x043c
82*9172SFei.Feng@Sun.COM #define	RT2860_CAP_CTRL			0x0440
83*9172SFei.Feng@Sun.COM 
84*9172SFei.Feng@Sun.COM /* MAC registers */
85*9172SFei.Feng@Sun.COM #define	RT2860_ASIC_VER_ID		0x1000
86*9172SFei.Feng@Sun.COM #define	RT2860_MAC_SYS_CTRL		0x1004
87*9172SFei.Feng@Sun.COM #define	RT2860_MAC_ADDR_DW0		0x1008
88*9172SFei.Feng@Sun.COM #define	RT2860_MAC_ADDR_DW1		0x100c
89*9172SFei.Feng@Sun.COM #define	RT2860_MAC_BSSID_DW0		0x1010
90*9172SFei.Feng@Sun.COM #define	RT2860_MAC_BSSID_DW1		0x1014
91*9172SFei.Feng@Sun.COM #define	RT2860_MAX_LEN_CFG		0x1018
92*9172SFei.Feng@Sun.COM #define	RT2860_BBP_CSR_CFG		0x101c
93*9172SFei.Feng@Sun.COM #define	RT2860_RF_CSR_CFG0		0x1020
94*9172SFei.Feng@Sun.COM #define	RT2860_RF_CSR_CFG1		0x1024
95*9172SFei.Feng@Sun.COM #define	RT2860_RF_CSR_CFG2		0x1028
96*9172SFei.Feng@Sun.COM #define	RT2860_LED_CFG			0x102c
97*9172SFei.Feng@Sun.COM 
98*9172SFei.Feng@Sun.COM /* undocumented registers */
99*9172SFei.Feng@Sun.COM #define	RT2860_DEBUG			0x10f4
100*9172SFei.Feng@Sun.COM 
101*9172SFei.Feng@Sun.COM /* MAC Timing control registers */
102*9172SFei.Feng@Sun.COM #define	RT2860_XIFS_TIME_CFG		0x1100
103*9172SFei.Feng@Sun.COM #define	RT2860_BKOFF_SLOT_CFG		0x1104
104*9172SFei.Feng@Sun.COM #define	RT2860_NAV_TIME_CFG		0x1108
105*9172SFei.Feng@Sun.COM #define	RT2860_CH_TIME_CFG		0x110c
106*9172SFei.Feng@Sun.COM #define	RT2860_PBF_LIFE_TIMER		0x1110
107*9172SFei.Feng@Sun.COM #define	RT2860_BCN_TIME_CFG		0x1114
108*9172SFei.Feng@Sun.COM #define	RT2860_TBTT_SYNC_CFG		0x1118
109*9172SFei.Feng@Sun.COM #define	RT2860_TSF_TIMER_DW0		0x111c
110*9172SFei.Feng@Sun.COM #define	RT2860_TSF_TIMER_DW1		0x1120
111*9172SFei.Feng@Sun.COM #define	RT2860_TBTT_TIMER		0x1124
112*9172SFei.Feng@Sun.COM #define	RT2860_INT_TIMER_CFG		0x1128
113*9172SFei.Feng@Sun.COM #define	RT2860_INT_TIMER_EN		0x112c
114*9172SFei.Feng@Sun.COM #define	RT2860_CH_IDLE_TIME		0x1130
115*9172SFei.Feng@Sun.COM 
116*9172SFei.Feng@Sun.COM /* MAC Power Save configuration registers */
117*9172SFei.Feng@Sun.COM #define	RT2860_MAC_STATUS_REG		0x1200
118*9172SFei.Feng@Sun.COM #define	RT2860_PWR_PIN_CFG		0x1204
119*9172SFei.Feng@Sun.COM #define	RT2860_AUTO_WAKEUP_CFG		0x1208
120*9172SFei.Feng@Sun.COM 
121*9172SFei.Feng@Sun.COM /* MAC TX configuration registers */
122*9172SFei.Feng@Sun.COM #define	RT2860_EDCA_AC_CFG(aci)		(0x1300 + (aci) * 4)
123*9172SFei.Feng@Sun.COM #define	RT2860_EDCA_TID_AC_MAP		0x1310
124*9172SFei.Feng@Sun.COM #define	RT2860_TX_PWR_CFG(ridx)		(0x1314 + (ridx) * 4)
125*9172SFei.Feng@Sun.COM #define	RT2860_TX_PIN_CFG		0x1328
126*9172SFei.Feng@Sun.COM #define	RT2860_TX_BAND_CFG		0x132c
127*9172SFei.Feng@Sun.COM #define	RT2860_TX_SW_CFG0		0x1330
128*9172SFei.Feng@Sun.COM #define	RT2860_TX_SW_CFG1		0x1334
129*9172SFei.Feng@Sun.COM #define	RT2860_TX_SW_CFG2		0x1338
130*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_THRES_CFG		0x133c
131*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_CTRL_CFG		0x1340
132*9172SFei.Feng@Sun.COM #define	RT2860_TX_RTS_CFG		0x1344
133*9172SFei.Feng@Sun.COM #define	RT2860_TX_TIMEOUT_CFG		0x1348
134*9172SFei.Feng@Sun.COM #define	RT2860_TX_RTY_CFG		0x134c
135*9172SFei.Feng@Sun.COM #define	RT2860_TX_LINK_CFG		0x1350
136*9172SFei.Feng@Sun.COM #define	RT2860_HT_FBK_CFG0		0x1354
137*9172SFei.Feng@Sun.COM #define	RT2860_HT_FBK_CFG1		0x1358
138*9172SFei.Feng@Sun.COM #define	RT2860_LG_FBK_CFG0		0x135c
139*9172SFei.Feng@Sun.COM #define	RT2860_LG_FBK_CFG1		0x1360
140*9172SFei.Feng@Sun.COM #define	RT2860_CCK_PROT_CFG		0x1364
141*9172SFei.Feng@Sun.COM #define	RT2860_OFDM_PROT_CFG		0x1368
142*9172SFei.Feng@Sun.COM #define	RT2860_MM20_PROT_CFG		0x136c
143*9172SFei.Feng@Sun.COM #define	RT2860_MM40_PROT_CFG		0x1370
144*9172SFei.Feng@Sun.COM #define	RT2860_GF20_PROT_CFG		0x1374
145*9172SFei.Feng@Sun.COM #define	RT2860_GF40_PROT_CFG		0x1378
146*9172SFei.Feng@Sun.COM #define	RT2860_EXP_CTS_TIME		0x137c
147*9172SFei.Feng@Sun.COM #define	RT2860_EXP_ACK_TIME		0x1380
148*9172SFei.Feng@Sun.COM 
149*9172SFei.Feng@Sun.COM /* MAC RX configuration registers */
150*9172SFei.Feng@Sun.COM #define	RT2860_RX_FILTR_CFG		0x1400
151*9172SFei.Feng@Sun.COM #define	RT2860_AUTO_RSP_CFG		0x1404
152*9172SFei.Feng@Sun.COM #define	RT2860_LEGACY_BASIC_RATE	0x1408
153*9172SFei.Feng@Sun.COM #define	RT2860_HT_BASIC_RATE		0x140c
154*9172SFei.Feng@Sun.COM #define	RT2860_HT_CTRL_CFG		0x1410
155*9172SFei.Feng@Sun.COM #define	RT2860_SIFS_COST_CFG		0x1414
156*9172SFei.Feng@Sun.COM #define	RT2860_RX_PARSER_CFG		0x1418
157*9172SFei.Feng@Sun.COM 
158*9172SFei.Feng@Sun.COM /* MAC Security configuration registers */
159*9172SFei.Feng@Sun.COM #define	RT2860_TX_SEC_CNT0		0x1500
160*9172SFei.Feng@Sun.COM #define	RT2860_RX_SEC_CNT0		0x1504
161*9172SFei.Feng@Sun.COM #define	RT2860_CCMP_FC_MUTE		0x1508
162*9172SFei.Feng@Sun.COM 
163*9172SFei.Feng@Sun.COM /* MAC HCCA/PSMP configuration registers */
164*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_HLDR_ADDR0		0x1600
165*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_HLDR_ADDR1		0x1604
166*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_HLDR_ET		0x1608
167*9172SFei.Feng@Sun.COM #define	RT2860_QOS_CFPOLL_RA_DW0	0x160c
168*9172SFei.Feng@Sun.COM #define	RT2860_QOS_CFPOLL_A1_DW1	0x1610
169*9172SFei.Feng@Sun.COM #define	RT2860_QOS_CFPOLL_QC		0x1614
170*9172SFei.Feng@Sun.COM 
171*9172SFei.Feng@Sun.COM /* MAC Statistics Counters */
172*9172SFei.Feng@Sun.COM #define	RT2860_RX_STA_CNT0		0x1700
173*9172SFei.Feng@Sun.COM #define	RT2860_RX_STA_CNT1		0x1704
174*9172SFei.Feng@Sun.COM #define	RT2860_RX_STA_CNT2		0x1708
175*9172SFei.Feng@Sun.COM #define	RT2860_TX_STA_CNT0		0x170c
176*9172SFei.Feng@Sun.COM #define	RT2860_TX_STA_CNT1		0x1710
177*9172SFei.Feng@Sun.COM #define	RT2860_TX_STA_CNT2		0x1714
178*9172SFei.Feng@Sun.COM #define	RT2860_TX_STAT_FIFO		0x1718
179*9172SFei.Feng@Sun.COM 
180*9172SFei.Feng@Sun.COM /* RX WCID search table */
181*9172SFei.Feng@Sun.COM #define	RT2860_WCID_ENTRY(wcid)		(0x1800 + (wcid) * 8)
182*9172SFei.Feng@Sun.COM 
183*9172SFei.Feng@Sun.COM #define	RT2860_FW_BASE			0x2000
184*9172SFei.Feng@Sun.COM 
185*9172SFei.Feng@Sun.COM /* Pair-wise key table */
186*9172SFei.Feng@Sun.COM #define	RT2860_PKEY(wcid)		(0x4000 + (wcid) * 32)
187*9172SFei.Feng@Sun.COM 
188*9172SFei.Feng@Sun.COM /* IV/EIV table */
189*9172SFei.Feng@Sun.COM #define	RT2860_IVEIV(wcid)		(0x6000 + (wcid) * 8)
190*9172SFei.Feng@Sun.COM 
191*9172SFei.Feng@Sun.COM /* WCID attribute table */
192*9172SFei.Feng@Sun.COM #define	RT2860_WCID_ATTR(wcid)		(0x6800 + (wcid) * 4)
193*9172SFei.Feng@Sun.COM 
194*9172SFei.Feng@Sun.COM /* Shared Key Table */
195*9172SFei.Feng@Sun.COM #define	RT2860_SKEY(vap, kidx)		(0x6c00 + (vap) * 128 + (kidx) * 32)
196*9172SFei.Feng@Sun.COM 
197*9172SFei.Feng@Sun.COM /* Shared Key Mode */
198*9172SFei.Feng@Sun.COM #define	RT2860_SKEY_MODE_0_7		0x7000
199*9172SFei.Feng@Sun.COM #define	RT2860_SKEY_MODE_8_15		0x7004
200*9172SFei.Feng@Sun.COM #define	RT2860_SKEY_MODE_16_23		0x7008
201*9172SFei.Feng@Sun.COM #define	RT2860_SKEY_MODE_24_31		0x700c
202*9172SFei.Feng@Sun.COM 
203*9172SFei.Feng@Sun.COM /* Shared Memory between MCU and host */
204*9172SFei.Feng@Sun.COM #define	RT2860_H2M_MAILBOX		0x7010
205*9172SFei.Feng@Sun.COM #define	RT2860_H2M_BBPAGENT		0x7028
206*9172SFei.Feng@Sun.COM #define	RT2860_BCN_BASE(vap)		(0x7800 + (vap) * 512)
207*9172SFei.Feng@Sun.COM 
208*9172SFei.Feng@Sun.COM /* possible flags for register RT2860_PCI_EECTRL */
209*9172SFei.Feng@Sun.COM #define	RT2860_C	(1 << 0)
210*9172SFei.Feng@Sun.COM #define	RT2860_S	(1 << 1)
211*9172SFei.Feng@Sun.COM #define	RT2860_D	(1 << 2)
212*9172SFei.Feng@Sun.COM #define	RT2860_SHIFT_D	2
213*9172SFei.Feng@Sun.COM #define	RT2860_Q	(1 << 3)
214*9172SFei.Feng@Sun.COM #define	RT2860_SHIFT_Q	3
215*9172SFei.Feng@Sun.COM 
216*9172SFei.Feng@Sun.COM /* possible flags for registers INT_STATUS/INT_MASK */
217*9172SFei.Feng@Sun.COM #define	RT2860_TX_COHERENT	(1 << 17)
218*9172SFei.Feng@Sun.COM #define	RT2860_RX_COHERENT	(1 << 16)
219*9172SFei.Feng@Sun.COM #define	RT2860_MAC_INT_4	(1 << 15)
220*9172SFei.Feng@Sun.COM #define	RT2860_MAC_INT_3	(1 << 14)
221*9172SFei.Feng@Sun.COM #define	RT2860_MAC_INT_2	(1 << 13)
222*9172SFei.Feng@Sun.COM #define	RT2860_MAC_INT_1	(1 << 12)
223*9172SFei.Feng@Sun.COM #define	RT2860_MAC_INT_0	(1 << 11)
224*9172SFei.Feng@Sun.COM #define	RT2860_TX_RX_COHERENT	(1 << 10)
225*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_INT	(1 <<  9)
226*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT5	(1 <<  8)
227*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT4	(1 <<  7)
228*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT3	(1 <<  6)
229*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT2	(1 <<  5)
230*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT1	(1 <<  4)
231*9172SFei.Feng@Sun.COM #define	RT2860_TX_DONE_INT0	(1 <<  3)
232*9172SFei.Feng@Sun.COM #define	RT2860_RX_DONE_INT	(1 <<  2)
233*9172SFei.Feng@Sun.COM #define	RT2860_TX_DLY_INT	(1 <<  1)
234*9172SFei.Feng@Sun.COM #define	RT2860_RX_DLY_INT	(1 <<  0)
235*9172SFei.Feng@Sun.COM 
236*9172SFei.Feng@Sun.COM /* possible flags for register WPDMA_GLO_CFG */
237*9172SFei.Feng@Sun.COM #define	RT2860_HDR_SEG_LEN_SHIFT	8
238*9172SFei.Feng@Sun.COM #define	RT2860_BIG_ENDIAN		(1 << 7)
239*9172SFei.Feng@Sun.COM #define	RT2860_TX_WB_DDONE		(1 << 6)
240*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_BT_SIZE_SHIFT	4
241*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_BT_SIZE16		0
242*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_BT_SIZE32		1
243*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_BT_SIZE64		2
244*9172SFei.Feng@Sun.COM #define	RT2860_WPDMA_BT_SIZE128		3
245*9172SFei.Feng@Sun.COM #define	RT2860_RX_DMA_BUSY		(1 << 3)
246*9172SFei.Feng@Sun.COM #define	RT2860_RX_DMA_EN		(1 << 2)
247*9172SFei.Feng@Sun.COM #define	RT2860_TX_DMA_BUSY		(1 << 1)
248*9172SFei.Feng@Sun.COM #define	RT2860_TX_DMA_EN		(1 << 0)
249*9172SFei.Feng@Sun.COM 
250*9172SFei.Feng@Sun.COM /* possible flags for register DELAY_INT_CFG */
251*9172SFei.Feng@Sun.COM #define	RT2860_TXDLY_INT_EN		(1 << 31)
252*9172SFei.Feng@Sun.COM #define	RT2860_TXMAX_PINT_SHIFT		24
253*9172SFei.Feng@Sun.COM #define	RT2860_TXMAX_PTIME_SHIFT	16
254*9172SFei.Feng@Sun.COM #define	RT2860_RXDLY_INT_EN		(1 << 15)
255*9172SFei.Feng@Sun.COM #define	RT2860_RXMAX_PINT_SHIFT		8
256*9172SFei.Feng@Sun.COM #define	RT2860_RXMAX_PTIME_SHIFT	0
257*9172SFei.Feng@Sun.COM 
258*9172SFei.Feng@Sun.COM /* possible flags for register GPIO_CTRL */
259*9172SFei.Feng@Sun.COM #define	RT2860_GPIO_D_SHIFT	8
260*9172SFei.Feng@Sun.COM #define	RT2860_GPIO_O_SHIFT	0
261*9172SFei.Feng@Sun.COM 
262*9172SFei.Feng@Sun.COM /* possible flags for register US_CYC_CNT */
263*9172SFei.Feng@Sun.COM #define	RT2860_TEST_EN		(1 << 24)
264*9172SFei.Feng@Sun.COM #define	RT2860_TEST_SEL_SHIFT	16
265*9172SFei.Feng@Sun.COM #define	RT2860_BT_MODE_EN	(1 <<  8)
266*9172SFei.Feng@Sun.COM #define	RT2860_US_CYC_CNT_SHIFT	0
267*9172SFei.Feng@Sun.COM 
268*9172SFei.Feng@Sun.COM /* possible flags for register SYS_CTRL */
269*9172SFei.Feng@Sun.COM #define	RT2860_HST_PM_SEL	(1 << 16)
270*9172SFei.Feng@Sun.COM #define	RT2860_CAP_MODE		(1 << 14)
271*9172SFei.Feng@Sun.COM #define	RT2860_PME_OEN		(1 << 13)
272*9172SFei.Feng@Sun.COM #define	RT2860_CLKSELECT	(1 << 12)
273*9172SFei.Feng@Sun.COM #define	RT2860_PBF_CLK_EN	(1 << 11)
274*9172SFei.Feng@Sun.COM #define	RT2860_MAC_CLK_EN	(1 << 10)
275*9172SFei.Feng@Sun.COM #define	RT2860_DMA_CLK_EN	(1 <<  9)
276*9172SFei.Feng@Sun.COM #define	RT2860_MCU_READY	(1 <<  7)
277*9172SFei.Feng@Sun.COM #define	RT2860_ASY_RESET	(1 <<  4)
278*9172SFei.Feng@Sun.COM #define	RT2860_PBF_RESET	(1 <<  3)
279*9172SFei.Feng@Sun.COM #define	RT2860_MAC_RESET	(1 <<  2)
280*9172SFei.Feng@Sun.COM #define	RT2860_DMA_RESET	(1 <<  1)
281*9172SFei.Feng@Sun.COM #define	RT2860_MCU_RESET	(1 <<  0)
282*9172SFei.Feng@Sun.COM 
283*9172SFei.Feng@Sun.COM /* possible values for register HOST_CMD */
284*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_SLEEP	0x30
285*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_WAKEUP	0x31
286*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_LEDS	0x50
287*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_LED_RSSI	0x51
288*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_LED1	0x52
289*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_LED2	0x53
290*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_LED3	0x54
291*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_BOOT	0x72
292*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_BBP	0x80
293*9172SFei.Feng@Sun.COM #define	RT2860_MCU_CMD_PSLEVEL	0x83
294*9172SFei.Feng@Sun.COM 
295*9172SFei.Feng@Sun.COM /* possible flags for register PBF_CFG */
296*9172SFei.Feng@Sun.COM #define	RT2860_TX1Q_NUM_SHIFT	21
297*9172SFei.Feng@Sun.COM #define	RT2860_TX2Q_NUM_SHIFT	16
298*9172SFei.Feng@Sun.COM #define	RT2860_NULL0_MODE	(1 << 15)
299*9172SFei.Feng@Sun.COM #define	RT2860_NULL1_MODE	(1 << 14)
300*9172SFei.Feng@Sun.COM #define	RT2860_RX_DROP_MODE	(1 << 13)
301*9172SFei.Feng@Sun.COM #define	RT2860_TX0Q_MANUAL	(1 << 12)
302*9172SFei.Feng@Sun.COM #define	RT2860_TX1Q_MANUAL	(1 << 11)
303*9172SFei.Feng@Sun.COM #define	RT2860_TX2Q_MANUAL	(1 << 10)
304*9172SFei.Feng@Sun.COM #define	RT2860_RX0Q_MANUAL	(1 <<  9)
305*9172SFei.Feng@Sun.COM #define	RT2860_HCCA_EN		(1 <<  8)
306*9172SFei.Feng@Sun.COM #define	RT2860_TX0Q_EN		(1 <<  4)
307*9172SFei.Feng@Sun.COM #define	RT2860_TX1Q_EN		(1 <<  3)
308*9172SFei.Feng@Sun.COM #define	RT2860_TX2Q_EN		(1 <<  2)
309*9172SFei.Feng@Sun.COM #define	RT2860_RX0Q_EN		(1 <<  1)
310*9172SFei.Feng@Sun.COM 
311*9172SFei.Feng@Sun.COM /* possible flags for register BUF_CTRL */
312*9172SFei.Feng@Sun.COM #define	RT2860_WRITE_TXQ(qid)	(1 << (11 - (qid)))
313*9172SFei.Feng@Sun.COM #define	RT2860_NULL0_KICK	(1 << 7)
314*9172SFei.Feng@Sun.COM #define	RT2860_NULL1_KICK	(1 << 6)
315*9172SFei.Feng@Sun.COM #define	RT2860_BUF_RESET	(1 << 5)
316*9172SFei.Feng@Sun.COM #define	RT2860_READ_TXQ(qid)	(1 << (3 - (qid))
317*9172SFei.Feng@Sun.COM #define	RT2860_READ_RX0Q	(1 << 0)
318*9172SFei.Feng@Sun.COM 
319*9172SFei.Feng@Sun.COM /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */
320*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_8	(1 << 24)
321*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_7	(1 << 23)
322*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_6	(1 << 22)
323*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_4	(1 << 20)
324*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_3	(1 << 19)
325*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_2	(1 << 18)
326*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_1	(1 << 17)
327*9172SFei.Feng@Sun.COM #define	RT2860_MCU_MAC_INT_0	(1 << 16)
328*9172SFei.Feng@Sun.COM #define	RT2860_DTX0_INT		(1 << 11)
329*9172SFei.Feng@Sun.COM #define	RT2860_DTX1_INT		(1 << 10)
330*9172SFei.Feng@Sun.COM #define	RT2860_DTX2_INT		(1 <<  9)
331*9172SFei.Feng@Sun.COM #define	RT2860_DRX0_INT		(1 <<  8)
332*9172SFei.Feng@Sun.COM #define	RT2860_HCMD_INT		(1 <<  7)
333*9172SFei.Feng@Sun.COM #define	RT2860_N0TX_INT		(1 <<  6)
334*9172SFei.Feng@Sun.COM #define	RT2860_N1TX_INT		(1 <<  5)
335*9172SFei.Feng@Sun.COM #define	RT2860_BCNTX_INT	(1 <<  4)
336*9172SFei.Feng@Sun.COM #define	RT2860_MTX0_INT		(1 <<  3)
337*9172SFei.Feng@Sun.COM #define	RT2860_MTX1_INT		(1 <<  2)
338*9172SFei.Feng@Sun.COM #define	RT2860_MTX2_INT		(1 <<  1)
339*9172SFei.Feng@Sun.COM #define	RT2860_MRX0_INT		(1 <<  0)
340*9172SFei.Feng@Sun.COM 
341*9172SFei.Feng@Sun.COM /* possible flags for register CAP_CTRL */
342*9172SFei.Feng@Sun.COM #define	RT2860_CAP_ADC_FEQ		(1 << 31)
343*9172SFei.Feng@Sun.COM #define	RT2860_CAP_START		(1 << 30)
344*9172SFei.Feng@Sun.COM #define	RT2860_MAN_TRIG			(1 << 29)
345*9172SFei.Feng@Sun.COM #define	RT2860_TRIG_OFFSET_SHIFT	16
346*9172SFei.Feng@Sun.COM #define	RT2860_START_ADDR_SHIFT		0
347*9172SFei.Feng@Sun.COM 
348*9172SFei.Feng@Sun.COM /* possible flags for register MAC_SYS_CTRL */
349*9172SFei.Feng@Sun.COM #define	RT2860_RX_TS_EN		(1 << 7)
350*9172SFei.Feng@Sun.COM #define	RT2860_WLAN_HALT_EN	(1 << 6)
351*9172SFei.Feng@Sun.COM #define	RT2860_PBF_LOOP_EN	(1 << 5)
352*9172SFei.Feng@Sun.COM #define	RT2860_CONT_TX_TEST	(1 << 4)
353*9172SFei.Feng@Sun.COM #define	RT2860_MAC_RX_EN	(1 << 3)
354*9172SFei.Feng@Sun.COM #define	RT2860_MAC_TX_EN	(1 << 2)
355*9172SFei.Feng@Sun.COM #define	RT2860_BBP_HRST		(1 << 1)
356*9172SFei.Feng@Sun.COM #define	RT2860_MAC_SRST		(1 << 0)
357*9172SFei.Feng@Sun.COM 
358*9172SFei.Feng@Sun.COM /* possible flags for register MAC_BSSID_DW1 */
359*9172SFei.Feng@Sun.COM #define	RT2860_MULTI_BCN_NUM_SHIFT	18
360*9172SFei.Feng@Sun.COM #define	RT2860_MULTI_BSSID_MODE_SHIFT	16
361*9172SFei.Feng@Sun.COM 
362*9172SFei.Feng@Sun.COM /* possible flags for register MAX_LEN_CFG */
363*9172SFei.Feng@Sun.COM #define	RT2860_MIN_MPDU_LEN_SHIFT	16
364*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PSDU_LEN_SHIFT	12
365*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PSDU_LEN8K		0
366*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PSDU_LEN16K		1
367*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PSDU_LEN32K		2
368*9172SFei.Feng@Sun.COM #define	RT2860_MAX_PSDU_LEN64K		3
369*9172SFei.Feng@Sun.COM #define	RT2860_MAX_MPDU_LEN_SHIFT	0
370*9172SFei.Feng@Sun.COM 
371*9172SFei.Feng@Sun.COM /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */
372*9172SFei.Feng@Sun.COM #define	RT2860_BBP_RW_PARALLEL		(1 << 19)
373*9172SFei.Feng@Sun.COM #define	RT2860_BBP_PAR_DUR_112_5	(1 << 18)
374*9172SFei.Feng@Sun.COM #define	RT2860_BBP_CSR_KICK		(1 << 17)
375*9172SFei.Feng@Sun.COM #define	RT2860_BBP_CSR_READ		(1 << 16)
376*9172SFei.Feng@Sun.COM #define	RT2860_BBP_ADDR_SHIFT		8
377*9172SFei.Feng@Sun.COM #define	RT2860_BBP_DATA_SHIFT		0
378*9172SFei.Feng@Sun.COM 
379*9172SFei.Feng@Sun.COM /* possible flags for register RF_CSR_CFG0 */
380*9172SFei.Feng@Sun.COM #define	RT2860_RF_REG_CTRL		((uint32_t)1 << 31)
381*9172SFei.Feng@Sun.COM #define	RT2860_RF_LE_SEL1		(1 << 30)
382*9172SFei.Feng@Sun.COM #define	RT2860_RF_LE_STBY		(1 << 29)
383*9172SFei.Feng@Sun.COM #define	RT2860_RF_REG_WIDTH_SHIFT	24
384*9172SFei.Feng@Sun.COM #define	RT2860_RF_REG_0_SHIFT		0
385*9172SFei.Feng@Sun.COM 
386*9172SFei.Feng@Sun.COM /* possible flags for register RF_CSR_CFG1 */
387*9172SFei.Feng@Sun.COM #define	RT2860_RF_DUR_5		(1 << 24)
388*9172SFei.Feng@Sun.COM #define	RT2860_RF_REG_1_SHIFT	0
389*9172SFei.Feng@Sun.COM 
390*9172SFei.Feng@Sun.COM /* possible flags for register LED_CFG */
391*9172SFei.Feng@Sun.COM #define	RT2860_LED_POL			(1 << 30)
392*9172SFei.Feng@Sun.COM #define	RT2860_Y_LED_MODE_SHIFT		28
393*9172SFei.Feng@Sun.COM #define	RT2860_G_LED_MODE_SHIFT		26
394*9172SFei.Feng@Sun.COM #define	RT2860_R_LED_MODE_SHIFT		24
395*9172SFei.Feng@Sun.COM #define	RT2860_LED_MODE_OFF		0
396*9172SFei.Feng@Sun.COM #define	RT2860_LED_MODE_BLINK_TX	1
397*9172SFei.Feng@Sun.COM #define	RT2860_LED_MODE_SLOW_BLINK	2
398*9172SFei.Feng@Sun.COM #define	RT2860_LED_MODE_ON		3
399*9172SFei.Feng@Sun.COM #define	RT2860_SLOW_BLK_TIME_SHIFT	16
400*9172SFei.Feng@Sun.COM #define	RT2860_LED_OFF_TIME_SHIFT	8
401*9172SFei.Feng@Sun.COM #define	RT2860_LED_ON_TIME_SHIFT	0
402*9172SFei.Feng@Sun.COM 
403*9172SFei.Feng@Sun.COM /* possible flags for register XIFS_TIME_CFG */
404*9172SFei.Feng@Sun.COM #define	RT2860_BB_RXEND_EN		(1 << 29)
405*9172SFei.Feng@Sun.COM #define	RT2860_EIFS_TIME_SHIFT		20
406*9172SFei.Feng@Sun.COM #define	RT2860_OFDM_XIFS_TIME_SHIFT	16
407*9172SFei.Feng@Sun.COM #define	RT2860_OFDM_SIFS_TIME_SHIFT	8
408*9172SFei.Feng@Sun.COM #define	RT2860_CCK_SIFS_TIME_SHIFT	0
409*9172SFei.Feng@Sun.COM 
410*9172SFei.Feng@Sun.COM /* possible flags for register BKOFF_SLOT_CFG */
411*9172SFei.Feng@Sun.COM #define	RT2860_CC_DELAY_TIME_SHIFT	8
412*9172SFei.Feng@Sun.COM #define	RT2860_SLOT_TIME		0
413*9172SFei.Feng@Sun.COM 
414*9172SFei.Feng@Sun.COM /* possible flags for register NAV_TIME_CFG */
415*9172SFei.Feng@Sun.COM #define	RT2860_NAV_UPD			(1 << 31)
416*9172SFei.Feng@Sun.COM #define	RT2860_NAV_UPD_VAL_SHIFT	16
417*9172SFei.Feng@Sun.COM #define	RT2860_NAV_CLR_EN		(1 << 15)
418*9172SFei.Feng@Sun.COM #define	RT2860_NAV_TIMER_SHIFT		0
419*9172SFei.Feng@Sun.COM 
420*9172SFei.Feng@Sun.COM /* possible flags for register CH_TIME_CFG */
421*9172SFei.Feng@Sun.COM #define	RT2860_EIFS_AS_CH_BUSY	(1 << 4)
422*9172SFei.Feng@Sun.COM #define	RT2860_NAV_AS_CH_BUSY	(1 << 3)
423*9172SFei.Feng@Sun.COM #define	RT2860_RX_AS_CH_BUSY	(1 << 2)
424*9172SFei.Feng@Sun.COM #define	RT2860_TX_AS_CH_BUSY	(1 << 1)
425*9172SFei.Feng@Sun.COM #define	RT2860_CH_STA_TIMER_EN	(1 << 0)
426*9172SFei.Feng@Sun.COM 
427*9172SFei.Feng@Sun.COM /* possible values for register BCN_TIME_CFG */
428*9172SFei.Feng@Sun.COM #define	RT2860_TSF_INS_COMP_SHIFT	24
429*9172SFei.Feng@Sun.COM #define	RT2860_BCN_TX_EN		(1 << 20)
430*9172SFei.Feng@Sun.COM #define	RT2860_TBTT_TIMER_EN		(1 << 19)
431*9172SFei.Feng@Sun.COM #define	RT2860_TSF_SYNC_MODE_SHIFT	17
432*9172SFei.Feng@Sun.COM #define	RT2860_TSF_SYNC_MODE_DIS	0
433*9172SFei.Feng@Sun.COM #define	RT2860_TSF_SYNC_MODE_STA	1
434*9172SFei.Feng@Sun.COM #define	RT2860_TSF_SYNC_MODE_IBSS	2
435*9172SFei.Feng@Sun.COM #define	RT2860_TSF_SYNC_MODE_HOSTAP	3
436*9172SFei.Feng@Sun.COM #define	RT2860_TSF_TIMER_EN		(1 << 16)
437*9172SFei.Feng@Sun.COM #define	RT2860_BCN_INTVAL_SHIFT		0
438*9172SFei.Feng@Sun.COM 
439*9172SFei.Feng@Sun.COM /* possible flags for register TBTT_SYNC_CFG */
440*9172SFei.Feng@Sun.COM #define	RT2860_BCN_CWMIN_SHIFT		20
441*9172SFei.Feng@Sun.COM #define	RT2860_BCN_AIFSN_SHIFT		16
442*9172SFei.Feng@Sun.COM #define	RT2860_BCN_EXP_WIN_SHIFT	8
443*9172SFei.Feng@Sun.COM #define	RT2860_TBTT_ADJUST_SHIFT	0
444*9172SFei.Feng@Sun.COM 
445*9172SFei.Feng@Sun.COM /* possible flags for register INT_TIMER_CFG */
446*9172SFei.Feng@Sun.COM #define	RT2860_GP_TIMER_SHIFT		16
447*9172SFei.Feng@Sun.COM #define	RT2860_PRE_TBTT_TIMER_SHIFT	0
448*9172SFei.Feng@Sun.COM 
449*9172SFei.Feng@Sun.COM /* possible flags for register INT_TIMER_EN */
450*9172SFei.Feng@Sun.COM #define	RT2860_GP_TIMER_EN	(1 << 1)
451*9172SFei.Feng@Sun.COM #define	RT2860_PRE_TBTT_INT_EN	(1 << 0)
452*9172SFei.Feng@Sun.COM 
453*9172SFei.Feng@Sun.COM /* possible flags for register MAC_STATUS_REG */
454*9172SFei.Feng@Sun.COM #define	RT2860_RX_STATUS_BUSY	(1 << 1)
455*9172SFei.Feng@Sun.COM #define	RT2860_TX_STATUS_BUSY	(1 << 0)
456*9172SFei.Feng@Sun.COM 
457*9172SFei.Feng@Sun.COM /* possible flags for register PWR_PIN_CFG */
458*9172SFei.Feng@Sun.COM #define	RT2860_IO_ADDA_PD	(1 << 3)
459*9172SFei.Feng@Sun.COM #define	RT2860_IO_PLL_PD	(1 << 2)
460*9172SFei.Feng@Sun.COM #define	RT2860_IO_RA_PE		(1 << 1)
461*9172SFei.Feng@Sun.COM #define	RT2860_IO_RF_PE		(1 << 0)
462*9172SFei.Feng@Sun.COM 
463*9172SFei.Feng@Sun.COM /* possible flags for register AUTO_WAKEUP_CFG */
464*9172SFei.Feng@Sun.COM #define	RT2860_AUTO_WAKEUP_EN		(1 << 15)
465*9172SFei.Feng@Sun.COM #define	RT2860_SLEEP_TBTT_NUM_SHIFT	8
466*9172SFei.Feng@Sun.COM #define	RT2860_WAKEUP_LEAD_TIME_SHIFT	0
467*9172SFei.Feng@Sun.COM 
468*9172SFei.Feng@Sun.COM /* possible flags for register TX_PIN_CFG */
469*9172SFei.Feng@Sun.COM #define	RT2860_TRSW_POL		(1 << 19)
470*9172SFei.Feng@Sun.COM #define	RT2860_TRSW_EN		(1 << 18)
471*9172SFei.Feng@Sun.COM #define	RT2860_RFTR_POL		(1 << 17)
472*9172SFei.Feng@Sun.COM #define	RT2860_RFTR_EN		(1 << 16)
473*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_G1_POL	(1 << 15)
474*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_A1_POL	(1 << 14)
475*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_G0_POL	(1 << 13)
476*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_A0_POL	(1 << 12)
477*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_G1_EN	(1 << 11)
478*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_A1_EN	(1 << 10)
479*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_G0_EN	(1 <<  9)
480*9172SFei.Feng@Sun.COM #define	RT2860_LNA_PE_A0_EN	(1 <<  8)
481*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_G1_POL	(1 <<  7)
482*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_A1_POL	(1 <<  6)
483*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_G0_POL	(1 <<  5)
484*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_A0_POL	(1 <<  4)
485*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_G1_EN	(1 <<  3)
486*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_A1_EN	(1 <<  2)
487*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_G0_EN	(1 <<  1)
488*9172SFei.Feng@Sun.COM #define	RT2860_PA_PE_A0_EN	(1 <<  0)
489*9172SFei.Feng@Sun.COM 
490*9172SFei.Feng@Sun.COM /* possible flags for register TX_BAND_CFG */
491*9172SFei.Feng@Sun.COM #define	RT2860_5G_BAND_SEL_N	(1 << 2)
492*9172SFei.Feng@Sun.COM #define	RT2860_5G_BAND_SEL_P	(1 << 1)
493*9172SFei.Feng@Sun.COM #define	RT2860_TX_BAND_SEL	(1 << 0)
494*9172SFei.Feng@Sun.COM 
495*9172SFei.Feng@Sun.COM /* possible flags for register TX_SW_CFG0 */
496*9172SFei.Feng@Sun.COM #define	RT2860_DLY_RFTR_EN_SHIFT	24
497*9172SFei.Feng@Sun.COM #define	RT2860_DLY_TRSW_EN_SHIFT	16
498*9172SFei.Feng@Sun.COM #define	RT2860_DLY_PAPE_EN_SHIFT	8
499*9172SFei.Feng@Sun.COM #define	RT2860_DLY_TXPE_EN_SHIFT	0
500*9172SFei.Feng@Sun.COM 
501*9172SFei.Feng@Sun.COM /* possible flags for register TX_SW_CFG1 */
502*9172SFei.Feng@Sun.COM #define	RT2860_DLY_RFTR_DIS_SHIFT	16
503*9172SFei.Feng@Sun.COM #define	RT2860_DLY_TRSW_DIS_SHIFT	8
504*9172SFei.Feng@Sun.COM #define	RT2860_DLY_PAPE_DIS SHIFT	0
505*9172SFei.Feng@Sun.COM 
506*9172SFei.Feng@Sun.COM /* possible flags for register TX_SW_CFG2 */
507*9172SFei.Feng@Sun.COM #define	RT2860_DLY_LNA_EN_SHIFT		24
508*9172SFei.Feng@Sun.COM #define	RT2860_DLY_LNA_DIS_SHIFT	16
509*9172SFei.Feng@Sun.COM #define	RT2860_DLY_DAC_EN_SHIFT		8
510*9172SFei.Feng@Sun.COM #define	RT2860_DLY_DAC_DIS_SHIFT	0
511*9172SFei.Feng@Sun.COM 
512*9172SFei.Feng@Sun.COM /* possible flags for register TXOP_THRES_CFG */
513*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_REM_THRES_SHIFT	24
514*9172SFei.Feng@Sun.COM #define	RT2860_CF_END_THRES_SHIFT	16
515*9172SFei.Feng@Sun.COM #define	RT2860_RDG_IN_THRES		8
516*9172SFei.Feng@Sun.COM #define	RT2860_RDG_OUT_THRES		0
517*9172SFei.Feng@Sun.COM 
518*9172SFei.Feng@Sun.COM /* possible flags for register TXOP_CTRL_CFG */
519*9172SFei.Feng@Sun.COM #define	RT2860_EXT_CW_MIN_SHIFT		16
520*9172SFei.Feng@Sun.COM #define	RT2860_EXT_CCA_DLY_SHIFT	8
521*9172SFei.Feng@Sun.COM #define	RT2860_EXT_CCA_EN		(1 << 7)
522*9172SFei.Feng@Sun.COM #define	RT2860_LSIG_TXOP_EN		(1 << 6)
523*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TRUN_EN_MIMOPS	(1 << 4)
524*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TRUN_EN_TXOP	(1 << 3)
525*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TRUN_EN_RATE	(1 << 2)
526*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TRUN_EN_AC		(1 << 1)
527*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TRUN_EN_TIMEOUT	(1 << 0)
528*9172SFei.Feng@Sun.COM 
529*9172SFei.Feng@Sun.COM /* possible flags for register TX_RTS_CFG */
530*9172SFei.Feng@Sun.COM #define	RT2860_RTS_FBK_EN		(1 << 24)
531*9172SFei.Feng@Sun.COM #define	RT2860_RTS_THRES_SHIFT		8
532*9172SFei.Feng@Sun.COM #define	RT2860_RTS_RTY_LIMIT_SHIFT	0
533*9172SFei.Feng@Sun.COM 
534*9172SFei.Feng@Sun.COM /* possible flags for register TX_TIMEOUT_CFG */
535*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_TIMEOUT_SHIFT	16
536*9172SFei.Feng@Sun.COM #define	RT2860_RX_ACK_TIMEOUT_SHIFT	8
537*9172SFei.Feng@Sun.COM #define	RT2860_MPDU_LIFE_TIME_SHIFT	4
538*9172SFei.Feng@Sun.COM 
539*9172SFei.Feng@Sun.COM /* possible flags for register TX_RTY_CFG */
540*9172SFei.Feng@Sun.COM #define	RT2860_TX_AUTOFB_EN		(1 << 30)
541*9172SFei.Feng@Sun.COM #define	RT2860_AGG_RTY_MODE_TIMER	(1 << 29)
542*9172SFei.Feng@Sun.COM #define	RT2860_NAG_RTY_MODE_TIMER	(1 << 28)
543*9172SFei.Feng@Sun.COM #define	RT2860_LONG_RTY_THRES_SHIFT	16
544*9172SFei.Feng@Sun.COM #define	RT2860_LONG_RTY_LIMIT_SHIFT	8
545*9172SFei.Feng@Sun.COM #define	RT2860_SHORT_RTY_LIMIT_SHIFT	0
546*9172SFei.Feng@Sun.COM 
547*9172SFei.Feng@Sun.COM /* possible flags for register TX_LINK_CFG */
548*9172SFei.Feng@Sun.COM #define	RT2860_REMOTE_MFS_SHIFT		24
549*9172SFei.Feng@Sun.COM #define	RT2860_REMOTE_MFB_SHIFT		16
550*9172SFei.Feng@Sun.COM #define	RT2860_TX_CFACK_EN		(1 << 12)
551*9172SFei.Feng@Sun.COM #define	RT2860_TX_RDG_EN		(1 << 11)
552*9172SFei.Feng@Sun.COM #define	RT2860_TX_MRQ_EN		(1 << 10)
553*9172SFei.Feng@Sun.COM #define	RT2860_REMOTE_UMFS_EN		(1 <<  9)
554*9172SFei.Feng@Sun.COM #define	RT2860_TX_MFB_EN		(1 <<  8)
555*9172SFei.Feng@Sun.COM #define	RT2860_REMOTE_MFB_LT_SHIFT	0
556*9172SFei.Feng@Sun.COM 
557*9172SFei.Feng@Sun.COM /* possible flags for registers *_PROT_CFG */
558*9172SFei.Feng@Sun.COM #define	RT2860_RTSTH_EN			(1 << 26)
559*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_GF40		(1 << 25)
560*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_GF20		(1 << 24)
561*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_MM40		(1 << 23)
562*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_MM20		(1 << 22)
563*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_OFDM		(1 << 21)
564*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_CCK		(1 << 20)
565*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ALLOW_ALL		(0x3f << 20)
566*9172SFei.Feng@Sun.COM #define	RT2860_PROT_NAV_SHORT		(1 << 18)
567*9172SFei.Feng@Sun.COM #define	RT2860_PROT_NAV_LONG		(2 << 18)
568*9172SFei.Feng@Sun.COM #define	RT2860_PROT_CTRL_RTS_CTS	(1 << 16)
569*9172SFei.Feng@Sun.COM #define	RT2860_PROT_CTRL_CTS		(2 << 16)
570*9172SFei.Feng@Sun.COM 
571*9172SFei.Feng@Sun.COM /* possible flags for registers EXP_{CTS,ACK}_TIME */
572*9172SFei.Feng@Sun.COM #define	RT2860_EXP_OFDM_TIME_SHIFT	16
573*9172SFei.Feng@Sun.COM #define	RT2860_EXP_CCK_TIME_SHIFT	0
574*9172SFei.Feng@Sun.COM 
575*9172SFei.Feng@Sun.COM /* possible flags for register RX_FILTR_CFG */
576*9172SFei.Feng@Sun.COM #define	RT2860_DROP_CTRL_RSV	(1 << 16)
577*9172SFei.Feng@Sun.COM #define	RT2860_DROP_BAR		(1 << 15)
578*9172SFei.Feng@Sun.COM #define	RT2860_DROP_BA		(1 << 14)
579*9172SFei.Feng@Sun.COM #define	RT2860_DROP_PSPOLL	(1 << 13)
580*9172SFei.Feng@Sun.COM #define	RT2860_DROP_RTS		(1 << 12)
581*9172SFei.Feng@Sun.COM #define	RT2860_DROP_CTS		(1 << 11)
582*9172SFei.Feng@Sun.COM #define	RT2860_DROP_ACK		(1 << 10)
583*9172SFei.Feng@Sun.COM #define	RT2860_DROP_CFEND	(1 <<  9)
584*9172SFei.Feng@Sun.COM #define	RT2860_DROP_CFACK	(1 <<  8)
585*9172SFei.Feng@Sun.COM #define	RT2860_DROP_DUPL	(1 <<  7)
586*9172SFei.Feng@Sun.COM #define	RT2860_DROP_BC		(1 <<  6)
587*9172SFei.Feng@Sun.COM #define	RT2860_DROP_MC		(1 <<  5)
588*9172SFei.Feng@Sun.COM #define	RT2860_DROP_VER_ERR	(1 <<  4)
589*9172SFei.Feng@Sun.COM #define	RT2860_DROP_NOT_MYBSS	(1 <<  3)
590*9172SFei.Feng@Sun.COM #define	RT2860_DROP_UC_NOME	(1 <<  2)
591*9172SFei.Feng@Sun.COM #define	RT2860_DROP_PHY_ERR	(1 <<  1)
592*9172SFei.Feng@Sun.COM #define	RT2860_DROP_CRC_ERR	(1 <<  0)
593*9172SFei.Feng@Sun.COM 
594*9172SFei.Feng@Sun.COM /* possible flags for register AUTO_RSP_CFG */
595*9172SFei.Feng@Sun.COM #define	RT2860_CTRL_PWR_BIT	(1 << 7)
596*9172SFei.Feng@Sun.COM #define	RT2860_BAC_ACK_POLICY	(1 << 6)
597*9172SFei.Feng@Sun.COM #define	RT2860_CCK_SHORT_EN	(1 << 4)
598*9172SFei.Feng@Sun.COM #define	RT2860_CTS_40M_REF_EN	(1 << 3)
599*9172SFei.Feng@Sun.COM #define	RT2860_CTS_40M_MODE_EN	(1 << 2)
600*9172SFei.Feng@Sun.COM #define	RT2860_BAC_ACKPOLICY_EN	(1 << 1)
601*9172SFei.Feng@Sun.COM #define	RT2860_AUTO_RSP_EN	(1 << 0)
602*9172SFei.Feng@Sun.COM 
603*9172SFei.Feng@Sun.COM /* possible flags for register SIFS_COST_CFG */
604*9172SFei.Feng@Sun.COM #define	RT2860_OFDM_SIFS_COST_SHIFT	8
605*9172SFei.Feng@Sun.COM #define	RT2860_CCK_SIFS_COST_SHIFT	0
606*9172SFei.Feng@Sun.COM 
607*9172SFei.Feng@Sun.COM /* possible flags for register TXOP_HLDR_ET */
608*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ETM1_EN		(1 << 25)
609*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ETM0_EN		(1 << 24)
610*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ETM_THRES_SHIFT	16
611*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ETO_EN		(1 <<  8)
612*9172SFei.Feng@Sun.COM #define	RT2860_TXOP_ETO_THRES_SHIFT	1
613*9172SFei.Feng@Sun.COM #define	RT2860_PER_RX_RST_EN		(1 <<  0)
614*9172SFei.Feng@Sun.COM 
615*9172SFei.Feng@Sun.COM /* possible flags for register TX_STAT_FIFO */
616*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_MCS_SHIFT	16
617*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_WCID_SHIFT	8
618*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_ACKREQ	(1 << 7)
619*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_AGG		(1 << 6)
620*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_OK		(1 << 5)
621*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_PID_SHIFT	1
622*9172SFei.Feng@Sun.COM #define	RT2860_TXQ_VLD		(1 << 0)
623*9172SFei.Feng@Sun.COM 
624*9172SFei.Feng@Sun.COM /* possible flags for register WCID_ATTR */
625*9172SFei.Feng@Sun.COM #define	RT2860_MODE_NOSEC	0
626*9172SFei.Feng@Sun.COM #define	RT2860_MODE_WEP40	1
627*9172SFei.Feng@Sun.COM #define	RT2860_MODE_WEP104	2
628*9172SFei.Feng@Sun.COM #define	RT2860_MODE_TKIP	3
629*9172SFei.Feng@Sun.COM #define	RT2860_MODE_AES_CCMP	4
630*9172SFei.Feng@Sun.COM #define	RT2860_MODE_CKIP40	5
631*9172SFei.Feng@Sun.COM #define	RT2860_MODE_CKIP104	6
632*9172SFei.Feng@Sun.COM #define	RT2860_MODE_CKIP128	7
633*9172SFei.Feng@Sun.COM #define	RT2860_RX_PKEY_EN	(1 << 0)
634*9172SFei.Feng@Sun.COM 
635*9172SFei.Feng@Sun.COM /* possible flags for register H2M_MAILBOX */
636*9172SFei.Feng@Sun.COM #define	RT2860_H2M_BUSY		(1 << 24)
637*9172SFei.Feng@Sun.COM #define	RT2860_TOKEN_NO_INTR	0xff
638*9172SFei.Feng@Sun.COM 
639*9172SFei.Feng@Sun.COM /* possible flags for MCU command RT2860_MCU_CMD_LEDS */
640*9172SFei.Feng@Sun.COM #define	RT2860_LED_RADIO	(1 << 13)
641*9172SFei.Feng@Sun.COM #define	RT2860_LED_LINK_2GHZ	(1 << 14)
642*9172SFei.Feng@Sun.COM #define	RT2860_LED_LINK_5GHZ	(1 << 15)
643*9172SFei.Feng@Sun.COM 
644*9172SFei.Feng@Sun.COM #pragma pack(1)
645*9172SFei.Feng@Sun.COM /* TX descriptor */
646*9172SFei.Feng@Sun.COM struct rt2860_txd {
647*9172SFei.Feng@Sun.COM 	uint32_t	sdp0;		/* Segment Data Pointer 0 */
648*9172SFei.Feng@Sun.COM 	uint16_t	sdl1;		/* Segment Data Length 1 */
649*9172SFei.Feng@Sun.COM #define	RT2860_TX_BURST	(1 << 15)
650*9172SFei.Feng@Sun.COM #define	RT2860_TX_LS1	(1 << 14)	/* SDP1 is the last segment */
651*9172SFei.Feng@Sun.COM 
652*9172SFei.Feng@Sun.COM 	uint16_t	sdl0;		/* Segment Data Length 0 */
653*9172SFei.Feng@Sun.COM #define	RT2860_TX_DDONE	(1 << 15)
654*9172SFei.Feng@Sun.COM #define	RT2860_TX_LS0	(1 << 14)	/* SDP0 is the last segment */
655*9172SFei.Feng@Sun.COM 
656*9172SFei.Feng@Sun.COM 	uint32_t	sdp1;		/* Segment Data Pointer 1 */
657*9172SFei.Feng@Sun.COM 	uint8_t		reserved[3];
658*9172SFei.Feng@Sun.COM 	uint8_t		flags;
659*9172SFei.Feng@Sun.COM #define	RT2860_TX_QSEL_SHIFT	1
660*9172SFei.Feng@Sun.COM #define	RT2860_TX_QSEL_MGMT	(0 << 1)
661*9172SFei.Feng@Sun.COM #define	RT2860_TX_QSEL_HCCA	(1 << 1)
662*9172SFei.Feng@Sun.COM #define	RT2860_TX_QSEL_EDCA	(2 << 1)
663*9172SFei.Feng@Sun.COM #define	RT2860_TX_WIV		(1 << 0)
664*9172SFei.Feng@Sun.COM };
665*9172SFei.Feng@Sun.COM #pragma pack()
666*9172SFei.Feng@Sun.COM 
667*9172SFei.Feng@Sun.COM #pragma pack(1)
668*9172SFei.Feng@Sun.COM /* TX Wireless Information */
669*9172SFei.Feng@Sun.COM struct rt2860_txwi {
670*9172SFei.Feng@Sun.COM 	uint8_t		flags;
671*9172SFei.Feng@Sun.COM #define	RT2860_TX_MPDU_DSITY_SHIFT	5
672*9172SFei.Feng@Sun.COM #define	RT2860_TX_AMPDU			(1 << 4)
673*9172SFei.Feng@Sun.COM #define	RT2860_TX_TS			(1 << 3)
674*9172SFei.Feng@Sun.COM #define	RT2860_TX_CFACK			(1 << 2)
675*9172SFei.Feng@Sun.COM #define	RT2860_TX_MMPS			(1 << 1)
676*9172SFei.Feng@Sun.COM #define	RT2860_TX_FRAG			(1 << 0)
677*9172SFei.Feng@Sun.COM 
678*9172SFei.Feng@Sun.COM 	uint8_t		txop;
679*9172SFei.Feng@Sun.COM #define	RT2860_TX_TXOP_HT	0
680*9172SFei.Feng@Sun.COM #define	RT2860_TX_TXOP_PIFS	1
681*9172SFei.Feng@Sun.COM #define	RT2860_TX_TXOP_SIFS	2
682*9172SFei.Feng@Sun.COM #define	RT2860_TX_TXOP_BACKOFF	3
683*9172SFei.Feng@Sun.COM 
684*9172SFei.Feng@Sun.COM 	uint16_t	phy;
685*9172SFei.Feng@Sun.COM #define	RT2860_PHY_MODE		0xc000
686*9172SFei.Feng@Sun.COM #define	RT2860_PHY_CCK		(0 << 14)
687*9172SFei.Feng@Sun.COM #define	RT2860_PHY_OFDM		(1 << 14)
688*9172SFei.Feng@Sun.COM #define	RT2860_PHY_HT		(2 << 14)
689*9172SFei.Feng@Sun.COM #define	RT2860_PHY_HT_GF	(3 << 14)
690*9172SFei.Feng@Sun.COM #define	RT2860_PHY_SGI		(1 << 8)
691*9172SFei.Feng@Sun.COM #define	RT2860_PHY_BW40		(1 << 7)
692*9172SFei.Feng@Sun.COM #define	RT2860_PHY_MCS		0x7f
693*9172SFei.Feng@Sun.COM #define	RT2860_PHY_SHPRE	(1 << 3)
694*9172SFei.Feng@Sun.COM 
695*9172SFei.Feng@Sun.COM 	uint8_t		xflags;
696*9172SFei.Feng@Sun.COM #define	RT2860_TX_BAWINSIZE_SHIFT	2
697*9172SFei.Feng@Sun.COM #define	RT2860_TX_NSEQ			(1 << 1)
698*9172SFei.Feng@Sun.COM #define	RT2860_TX_ACK			(1 << 0)
699*9172SFei.Feng@Sun.COM 
700*9172SFei.Feng@Sun.COM 	uint8_t		wcid;	/* Wireless Client ID */
701*9172SFei.Feng@Sun.COM 	uint16_t	len;
702*9172SFei.Feng@Sun.COM #define	RT2860_TX_PID_SHIFT	12
703*9172SFei.Feng@Sun.COM 
704*9172SFei.Feng@Sun.COM 	uint32_t	iv;
705*9172SFei.Feng@Sun.COM 	uint32_t	eiv;
706*9172SFei.Feng@Sun.COM 
707*9172SFei.Feng@Sun.COM 	struct		ieee80211_frame wh;
708*9172SFei.Feng@Sun.COM 	uint16_t	pad;
709*9172SFei.Feng@Sun.COM };
710*9172SFei.Feng@Sun.COM #pragma pack()
711*9172SFei.Feng@Sun.COM 
712*9172SFei.Feng@Sun.COM #pragma pack(1)
713*9172SFei.Feng@Sun.COM /* RX descriptor */
714*9172SFei.Feng@Sun.COM struct rt2860_rxd {
715*9172SFei.Feng@Sun.COM 	uint32_t	sdp0;
716*9172SFei.Feng@Sun.COM 	uint16_t	sdl1;	/* unused */
717*9172SFei.Feng@Sun.COM 	uint16_t	sdl0;
718*9172SFei.Feng@Sun.COM #define	RT2860_RX_DDONE	(1 << 15)
719*9172SFei.Feng@Sun.COM #define	RT2860_RX_LS0	(1 << 14)
720*9172SFei.Feng@Sun.COM 
721*9172SFei.Feng@Sun.COM 	uint32_t	sdp1;	/* unused */
722*9172SFei.Feng@Sun.COM 	uint32_t	flags;
723*9172SFei.Feng@Sun.COM #define	RT2860_RX_DEC		(1 << 16)
724*9172SFei.Feng@Sun.COM #define	RT2860_RX_AMPDU		(1 << 15)
725*9172SFei.Feng@Sun.COM #define	RT2860_RX_L2PAD		(1 << 14)
726*9172SFei.Feng@Sun.COM #define	RT2860_RX_RSSI		(1 << 13)
727*9172SFei.Feng@Sun.COM #define	RT2860_RX_HTC		(1 << 12)
728*9172SFei.Feng@Sun.COM #define	RT2860_RX_AMSDU		(1 << 11)
729*9172SFei.Feng@Sun.COM #define	RT2860_RX_MICERR	(1 << 10)
730*9172SFei.Feng@Sun.COM #define	RT2860_RX_ICVERR	(1 <<  9)
731*9172SFei.Feng@Sun.COM #define	RT2860_RX_CRCERR	(1 <<  8)
732*9172SFei.Feng@Sun.COM #define	RT2860_RX_MYBSS		(1 <<  7)
733*9172SFei.Feng@Sun.COM #define	RT2860_RX_BC		(1 <<  6)
734*9172SFei.Feng@Sun.COM #define	RT2860_RX_MC		(1 <<  5)
735*9172SFei.Feng@Sun.COM #define	RT2860_RX_UC2ME		(1 <<  4)
736*9172SFei.Feng@Sun.COM #define	RT2860_RX_FRAG		(1 <<  3)
737*9172SFei.Feng@Sun.COM #define	RT2860_RX_NULL		(1 <<  2)
738*9172SFei.Feng@Sun.COM #define	RT2860_RX_DATA		(1 <<  1)
739*9172SFei.Feng@Sun.COM #define	RT2860_RX_BA		(1 <<  0)
740*9172SFei.Feng@Sun.COM };
741*9172SFei.Feng@Sun.COM #pragma pack()
742*9172SFei.Feng@Sun.COM 
743*9172SFei.Feng@Sun.COM #pragma pack(1)
744*9172SFei.Feng@Sun.COM /* RX Wireless Information */
745*9172SFei.Feng@Sun.COM struct rt2860_rxwi {
746*9172SFei.Feng@Sun.COM 	uint8_t		wcid;
747*9172SFei.Feng@Sun.COM 	uint8_t		keyidx;
748*9172SFei.Feng@Sun.COM #define	RT2860_RX_UDF_SHIFT	5
749*9172SFei.Feng@Sun.COM #define	RT2860_RX_BSS_IDX_SHIFT	2
750*9172SFei.Feng@Sun.COM 
751*9172SFei.Feng@Sun.COM 	uint16_t	len;
752*9172SFei.Feng@Sun.COM #define	RT2860_RX_TID_SHIFT	12
753*9172SFei.Feng@Sun.COM 
754*9172SFei.Feng@Sun.COM 	uint16_t	seq;
755*9172SFei.Feng@Sun.COM 	uint16_t	phy;
756*9172SFei.Feng@Sun.COM 	uint8_t		rssi[3];
757*9172SFei.Feng@Sun.COM 	uint8_t		reserved1;
758*9172SFei.Feng@Sun.COM 	uint8_t		snr[2];
759*9172SFei.Feng@Sun.COM 	uint16_t	reserved2;
760*9172SFei.Feng@Sun.COM };
761*9172SFei.Feng@Sun.COM #pragma pack()
762*9172SFei.Feng@Sun.COM 
763*9172SFei.Feng@Sun.COM #define	RAL_RF1	0
764*9172SFei.Feng@Sun.COM #define	RAL_RF2	2
765*9172SFei.Feng@Sun.COM #define	RAL_RF3	1
766*9172SFei.Feng@Sun.COM #define	RAL_RF4	3
767*9172SFei.Feng@Sun.COM 
768*9172SFei.Feng@Sun.COM #define	RT2860_RF_2820			1	/* 2T3R */
769*9172SFei.Feng@Sun.COM #define	RT2860_RF_2850			2	/* dual-band 2T3R */
770*9172SFei.Feng@Sun.COM #define	RT2860_RF_2720			3	/* 1T2R */
771*9172SFei.Feng@Sun.COM #define	RT2860_RF_2750			4	/* dual-band 1T2R */
772*9172SFei.Feng@Sun.COM 
773*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_DELAY	1	/* minimum hold time (microsecond) */
774*9172SFei.Feng@Sun.COM 
775*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_VERSION		0x01
776*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_MAC01		0x02
777*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_MAC23		0x03
778*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_MAC45		0x04
779*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_PCIE_PSLEVEL	0x11
780*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_REV		0x12
781*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_ANTENNA		0x1a
782*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_CONFIG		0x1b
783*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_COUNTRY		0x1c
784*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_FREQ_LEDS		0x1d
785*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_LED1		0x1e
786*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_LED2		0x1f
787*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_LED3		0x20
788*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_LNA		0x22
789*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_RSSI1_2GHZ	0x23
790*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_RSSI2_2GHZ	0x24
791*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_RSSI1_5GHZ	0x25
792*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_RSSI2_5GHZ	0x26
793*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_DELTAPWR		0x28
794*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_PWR2GHZ_BASE1	0x29
795*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_PWR2GHZ_BASE2	0x30
796*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI1_2GHZ	0x37
797*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI2_2GHZ	0x38
798*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI3_2GHZ	0x39
799*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI4_2GHZ	0x3a
800*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI5_2GHZ	0x3b
801*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_PWR5GHZ_BASE1	0x3c
802*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_PWR5GHZ_BASE2	0x53
803*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI1_5GHZ	0x6a
804*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI2_5GHZ	0x6b
805*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI3_5GHZ	0x6c
806*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI4_5GHZ	0x6d
807*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_TSSI5_5GHZ	0x6e
808*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_RPWR		0x6f
809*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_BBP_BASE		0x78
810*9172SFei.Feng@Sun.COM 
811*9172SFei.Feng@Sun.COM 
812*9172SFei.Feng@Sun.COM /*
813*9172SFei.Feng@Sun.COM  * control and status registers access macros
814*9172SFei.Feng@Sun.COM  */
815*9172SFei.Feng@Sun.COM #define	RT2860_READ(sc, reg)						\
816*9172SFei.Feng@Sun.COM 	ddi_get32((sc)->sc_io_handle,					\
817*9172SFei.Feng@Sun.COM 	    (uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)))
818*9172SFei.Feng@Sun.COM 
819*9172SFei.Feng@Sun.COM #define	RT2860_WRITE(sc, reg, val)					\
820*9172SFei.Feng@Sun.COM 	ddi_put32((sc)->sc_io_handle,					\
821*9172SFei.Feng@Sun.COM 	    (uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)), (val))
822*9172SFei.Feng@Sun.COM 
823*9172SFei.Feng@Sun.COM #define	rt2860_mem_write1(sc, reg, val)					\
824*9172SFei.Feng@Sun.COM 	ddi_put8((sc)->sc_io_handle,					\
825*9172SFei.Feng@Sun.COM 	    (uint8_t *)((sc)->sc_io_base + (reg)), (val))
826*9172SFei.Feng@Sun.COM 
827*9172SFei.Feng@Sun.COM /*
828*9172SFei.Feng@Sun.COM  * EEPROM access macro
829*9172SFei.Feng@Sun.COM  */
830*9172SFei.Feng@Sun.COM #define	RT2860_EEPROM_CTL(sc, val) {					\
831*9172SFei.Feng@Sun.COM 	RT2860_WRITE((sc), RT2860_PCI_EECTRL, (val));			\
832*9172SFei.Feng@Sun.COM 	DELAY(RT2860_EEPROM_DELAY);					\
833*9172SFei.Feng@Sun.COM }
834*9172SFei.Feng@Sun.COM 
835*9172SFei.Feng@Sun.COM /*
836*9172SFei.Feng@Sun.COM  * Default values for MAC registers; values taken from the reference driver.
837*9172SFei.Feng@Sun.COM  */
838*9172SFei.Feng@Sun.COM #define	RT2860_DEF_MAC					\
839*9172SFei.Feng@Sun.COM 	{ RT2860_BCN_OFFSET0,		0xf8f0e8e0 },	\
840*9172SFei.Feng@Sun.COM 	{ RT2860_LEGACY_BASIC_RATE,	0x0000013f },	\
841*9172SFei.Feng@Sun.COM 	{ RT2860_HT_BASIC_RATE,		0x00008003 },	\
842*9172SFei.Feng@Sun.COM 	{ RT2860_MAC_SYS_CTRL,		0x00000000 },	\
843*9172SFei.Feng@Sun.COM 	{ RT2860_BKOFF_SLOT_CFG,	0x00000209 },	\
844*9172SFei.Feng@Sun.COM 	{ RT2860_TX_SW_CFG0,		0x00040a06 },	\
845*9172SFei.Feng@Sun.COM 	{ RT2860_TX_SW_CFG1,		0x00080606 },	\
846*9172SFei.Feng@Sun.COM 	{ RT2860_TX_LINK_CFG,		0x00001020 },	\
847*9172SFei.Feng@Sun.COM 	{ RT2860_TX_TIMEOUT_CFG,	0x000a2090 },	\
848*9172SFei.Feng@Sun.COM 	{ RT2860_LED_CFG,		0x7f031e46 },	\
849*9172SFei.Feng@Sun.COM 	{ RT2860_WMM_AIFSN_CFG,		0x00002273 },	\
850*9172SFei.Feng@Sun.COM 	{ RT2860_WMM_CWMIN_CFG,		0x00002344 },	\
851*9172SFei.Feng@Sun.COM 	{ RT2860_WMM_CWMAX_CFG,		0x000034aa },	\
852*9172SFei.Feng@Sun.COM 	{ RT2860_MAX_PCNT,		0x1f3fbf9f },	\
853*9172SFei.Feng@Sun.COM 	{ RT2860_TX_RTY_CFG,		0x47d01f0f },	\
854*9172SFei.Feng@Sun.COM 	{ RT2860_AUTO_RSP_CFG,		0x00000013 },	\
855*9172SFei.Feng@Sun.COM 	{ RT2860_CCK_PROT_CFG,		0x05740003 },	\
856*9172SFei.Feng@Sun.COM 	{ RT2860_OFDM_PROT_CFG,		0x05740003 },	\
857*9172SFei.Feng@Sun.COM 	{ RT2860_GF20_PROT_CFG,		0x01744004 },	\
858*9172SFei.Feng@Sun.COM 	{ RT2860_GF40_PROT_CFG,		0x03f44084 },	\
859*9172SFei.Feng@Sun.COM 	{ RT2860_MM20_PROT_CFG,		0x01744004 },	\
860*9172SFei.Feng@Sun.COM 	{ RT2860_MM40_PROT_CFG,		0x03f54084 },	\
861*9172SFei.Feng@Sun.COM 	{ RT2860_TXOP_CTRL_CFG,		0x0000583f },	\
862*9172SFei.Feng@Sun.COM 	{ RT2860_TXOP_HLDR_ET,		0x00000002 },	\
863*9172SFei.Feng@Sun.COM 	{ RT2860_TX_RTS_CFG,		0x00092b20 },	\
864*9172SFei.Feng@Sun.COM 	{ RT2860_EXP_ACK_TIME,		0x002400ca },	\
865*9172SFei.Feng@Sun.COM 	{ RT2860_XIFS_TIME_CFG,		0x33a41010 },	\
866*9172SFei.Feng@Sun.COM 	{ RT2860_PWR_PIN_CFG,		0x00000003 }
867*9172SFei.Feng@Sun.COM 
868*9172SFei.Feng@Sun.COM /*
869*9172SFei.Feng@Sun.COM  * Default values for BBP registers; values taken from the reference driver.
870*9172SFei.Feng@Sun.COM  */
871*9172SFei.Feng@Sun.COM #define	RT2860_DEF_BBP	\
872*9172SFei.Feng@Sun.COM 	{  65, 0x2c },	\
873*9172SFei.Feng@Sun.COM 	{  66, 0x38 },	\
874*9172SFei.Feng@Sun.COM 	{  69, 0x12 },	\
875*9172SFei.Feng@Sun.COM 	{  73, 0x10 },	\
876*9172SFei.Feng@Sun.COM 	{  81, 0x37 },	\
877*9172SFei.Feng@Sun.COM 	{  82, 0x62 },	\
878*9172SFei.Feng@Sun.COM 	{  83, 0x6a },	\
879*9172SFei.Feng@Sun.COM 	{  84, 0x19 },	\
880*9172SFei.Feng@Sun.COM 	{  86, 0x00 },	\
881*9172SFei.Feng@Sun.COM 	{  91, 0x04 },	\
882*9172SFei.Feng@Sun.COM 	{  92, 0x00 },	\
883*9172SFei.Feng@Sun.COM 	{ 105, 0x01 }
884*9172SFei.Feng@Sun.COM 
885*9172SFei.Feng@Sun.COM /*
886*9172SFei.Feng@Sun.COM  * Default settings for RF registers; values derived from the reference driver.
887*9172SFei.Feng@Sun.COM  */
888*9172SFei.Feng@Sun.COM #define	RT2860_RF2850						\
889*9172SFei.Feng@Sun.COM 	{   1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 },	\
890*9172SFei.Feng@Sun.COM 	{   2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 },	\
891*9172SFei.Feng@Sun.COM 	{   3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 },	\
892*9172SFei.Feng@Sun.COM 	{   4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 },	\
893*9172SFei.Feng@Sun.COM 	{   5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 },	\
894*9172SFei.Feng@Sun.COM 	{   6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 },	\
895*9172SFei.Feng@Sun.COM 	{   7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 },	\
896*9172SFei.Feng@Sun.COM 	{   8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 },	\
897*9172SFei.Feng@Sun.COM 	{   9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 },	\
898*9172SFei.Feng@Sun.COM 	{  10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 },	\
899*9172SFei.Feng@Sun.COM 	{  11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },	\
900*9172SFei.Feng@Sun.COM 	{  12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 },	\
901*9172SFei.Feng@Sun.COM 	{  13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 },	\
902*9172SFei.Feng@Sun.COM 	{  14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 },	\
903*9172SFei.Feng@Sun.COM 	{  36, 0x100bb3, 0x130266, 0x056014, 0x001408 },	\
904*9172SFei.Feng@Sun.COM 	{  38, 0x100bb3, 0x130267, 0x056014, 0x001404 },	\
905*9172SFei.Feng@Sun.COM 	{  40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 },	\
906*9172SFei.Feng@Sun.COM 	{  44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 },	\
907*9172SFei.Feng@Sun.COM 	{  46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },	\
908*9172SFei.Feng@Sun.COM 	{  48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 },	\
909*9172SFei.Feng@Sun.COM 	{  52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 },	\
910*9172SFei.Feng@Sun.COM 	{  54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 },	\
911*9172SFei.Feng@Sun.COM 	{  56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },	\
912*9172SFei.Feng@Sun.COM 	{  60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 },	\
913*9172SFei.Feng@Sun.COM 	{  62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 },	\
914*9172SFei.Feng@Sun.COM 	{  64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 },	\
915*9172SFei.Feng@Sun.COM 	{ 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 },	\
916*9172SFei.Feng@Sun.COM 	{ 102, 0x100bb2, 0x1301ac, 0x05e014, 0x001404 },	\
917*9172SFei.Feng@Sun.COM 	{ 104, 0x100bb2, 0x1301ac, 0x05e014, 0x001408 },	\
918*9172SFei.Feng@Sun.COM 	{ 108, 0x100bb3, 0x13028c, 0x05e014, 0x001404 },	\
919*9172SFei.Feng@Sun.COM 	{ 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 },	\
920*9172SFei.Feng@Sun.COM 	{ 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 },	\
921*9172SFei.Feng@Sun.COM 	{ 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 },	\
922*9172SFei.Feng@Sun.COM 	{ 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 },	\
923*9172SFei.Feng@Sun.COM 	{ 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 },	\
924*9172SFei.Feng@Sun.COM 	{ 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 },	\
925*9172SFei.Feng@Sun.COM 	{ 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 },	\
926*9172SFei.Feng@Sun.COM 	{ 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 },	\
927*9172SFei.Feng@Sun.COM 	{ 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 },	\
928*9172SFei.Feng@Sun.COM 	{ 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 },	\
929*9172SFei.Feng@Sun.COM 	{ 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 },	\
930*9172SFei.Feng@Sun.COM 	{ 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 },	\
931*9172SFei.Feng@Sun.COM 	{ 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 },	\
932*9172SFei.Feng@Sun.COM 	{ 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 },	\
933*9172SFei.Feng@Sun.COM 	{ 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 },	\
934*9172SFei.Feng@Sun.COM 	{ 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 },	\
935*9172SFei.Feng@Sun.COM 	{ 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 },	\
936*9172SFei.Feng@Sun.COM 	{ 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 },	\
937*9172SFei.Feng@Sun.COM 	{ 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }
938*9172SFei.Feng@Sun.COM 
939*9172SFei.Feng@Sun.COM 
940*9172SFei.Feng@Sun.COM #ifdef __cplusplus
941*9172SFei.Feng@Sun.COM }
942*9172SFei.Feng@Sun.COM #endif
943*9172SFei.Feng@Sun.COM 
944*9172SFei.Feng@Sun.COM #endif /* _RT2860_REG_H */
945