xref: /onnv-gate/usr/src/uts/common/io/rtw/rtwvar.h (revision 10448:fe6b44e693c2)
14689Sql147931 /*
2*10448SMikore.Li@Sun.COM  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
34689Sql147931  * Use is subject to license terms.
44689Sql147931  */
54689Sql147931 /*
64689Sql147931  * Copyright (c) 2004, 2005 David Young.  All rights reserved.
74689Sql147931  *
84689Sql147931  * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young.
94689Sql147931  *
104689Sql147931  * Redistribution and use in source and binary forms, with or without
114689Sql147931  * modification, are permitted provided that the following conditions
124689Sql147931  * are met:
134689Sql147931  * 1. Redistributions of source code must retain the above copyright
144689Sql147931  *    notice, this list of conditions and the following disclaimer.
154689Sql147931  * 2. Redistributions in binary form must reproduce the above copyright
164689Sql147931  *    notice, this list of conditions and the following disclaimer in the
174689Sql147931  *    documentation and/or other materials provided with the distribution.
184689Sql147931  * 3. The name of David Young may not be used to endorse or promote
194689Sql147931  *    products derived from this software without specific prior
204689Sql147931  *    written permission.
214689Sql147931  *
224689Sql147931  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
234689Sql147931  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
244689Sql147931  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
254689Sql147931  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
264689Sql147931  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
274689Sql147931  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
284689Sql147931  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
294689Sql147931  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
304689Sql147931  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
314689Sql147931  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
324689Sql147931  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
334689Sql147931  * OF SUCH DAMAGE.
344689Sql147931  */
354689Sql147931 #ifndef _RTWVAR_H_
364689Sql147931 #define	_RTWVAR_H_
374689Sql147931 
38*10448SMikore.Li@Sun.COM #ifdef __cplusplus
39*10448SMikore.Li@Sun.COM extern "C" {
40*10448SMikore.Li@Sun.COM #endif
41*10448SMikore.Li@Sun.COM 
424689Sql147931 #include <sys/list.h>
434689Sql147931 #include <sys/net80211.h>
444689Sql147931 
454689Sql147931 #ifndef __func__
464689Sql147931 #define	__func__ ""
474689Sql147931 #endif
484689Sql147931 
494689Sql147931 extern void rtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...);
504689Sql147931 
514689Sql147931 #define	RTW_DEBUG_TUNE		0x000001
524689Sql147931 #define	RTW_DEBUG_PKTFILT	0x000002
534689Sql147931 #define	RTW_DEBUG_XMIT		0x000004
544689Sql147931 #define	RTW_DEBUG_DMA		0x000008
554689Sql147931 #define	RTW_DEBUG_NODE		0x000010
564689Sql147931 #define	RTW_DEBUG_PWR		0x000020
574689Sql147931 #define	RTW_DEBUG_ATTACH	0x000040
584689Sql147931 #define	RTW_DEBUG_REGDUMP	0x000080
594689Sql147931 #define	RTW_DEBUG_ACCESS	0x000100
604689Sql147931 #define	RTW_DEBUG_RESET		0x000200
614689Sql147931 #define	RTW_DEBUG_INIT		0x000400
624689Sql147931 #define	RTW_DEBUG_PKTDUMP	0x000800
634689Sql147931 #define	RTW_DEBUG_RECV		0x001000
644689Sql147931 #define	RTW_DEBUG_RECV_DESC	0x002000
654689Sql147931 #define	RTW_DEBUG_IOSTATE	0x004000
664689Sql147931 #define	RTW_DEBUG_INTR		0x008000
674689Sql147931 #define	RTW_DEBUG_PHY		0x010000
684689Sql147931 #define	RTW_DEBUG_PHYIO		0x020000
694689Sql147931 #define	RTW_DEBUG_PHYBITIO	0x040000
704689Sql147931 #define	RTW_DEBUG_TIMEOUT	0x080000
714689Sql147931 #define	RTW_DEBUG_BUGS		0x100000
724689Sql147931 #define	RTW_DEBUG_BEACON	0x200000
734689Sql147931 #define	RTW_DEBUG_WIFICFG	0x400000
744689Sql147931 #define	RTW_DEBUG_80211		0x800000
754689Sql147931 #define	RTW_DEBUG_MAX		0xffffff
764689Sql147931 
774689Sql147931 #ifdef DEBUG
784689Sql147931 #define	RTW_DPRINTF \
794689Sql147931 	rtw_dbg
804689Sql147931 #else /* DEBUG */
814689Sql147931 #define	RTW_DPRINTF
824689Sql147931 #endif /* DEBUG */
834689Sql147931 
844689Sql147931 enum rtw_locale {
854689Sql147931 	RTW_LOCALE_USA = 0,
864689Sql147931 	RTW_LOCALE_EUROPE,
874689Sql147931 	RTW_LOCALE_JAPAN,
884689Sql147931 	RTW_LOCALE_UNKNOWN
894689Sql147931 };
904689Sql147931 
914689Sql147931 enum rtw_rfchipid {
924689Sql147931 	RTW_RFCHIPID_RESERVED = 0,
934689Sql147931 	RTW_RFCHIPID_INTERSIL = 1,
944689Sql147931 	RTW_RFCHIPID_RFMD = 2,
954689Sql147931 	RTW_RFCHIPID_PHILIPS = 3,
964689Sql147931 	RTW_RFCHIPID_MAXIM = 4,
974689Sql147931 	RTW_RFCHIPID_GCT = 5
984689Sql147931 };
994689Sql147931 
1004689Sql147931 /*
1014689Sql147931  * sc_flags
1024689Sql147931  */
1034689Sql147931 #define	RTW_F_ENABLED		0x00000001	/* chip is enabled */
1044689Sql147931 #define	RTW_F_DIGPHY		0x00000002	/* digital PHY */
1054689Sql147931 #define	RTW_F_DFLANTB		0x00000004	/* B antenna is default */
1064689Sql147931 #define	RTW_F_ANTDIV		0x00000010	/* h/w antenna diversity */
1074689Sql147931 #define	RTW_F_9356SROM		0x00000020	/* 93c56 SROM */
1084689Sql147931 #define	RTW_F_SLEEP		0x00000040	/* chip is asleep */
1094689Sql147931 #define	RTW_F_INVALID		0x00000080	/* chip is absent */
110*10448SMikore.Li@Sun.COM #define	RTW_F_SUSPEND		0x00000100	/* driver is suspended */
111*10448SMikore.Li@Sun.COM #define	RTW_F_PLUMBED		0x00000200	/* driver is plumbed */
1124689Sql147931 #define	RTW_F_ATTACHED		0x01000000	/* driver is attached */
1134689Sql147931 /*
1144689Sql147931  * all PHY flags
1154689Sql147931  */
1164689Sql147931 #define	RTW_F_ALLPHY		(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV)
1174689Sql147931 
1184689Sql147931 enum rtw_access {RTW_ACCESS_NONE = 0,
1194689Sql147931 		RTW_ACCESS_CONFIG = 1,
1204689Sql147931 		RTW_ACCESS_ANAPARM = 2};
1214689Sql147931 
1224689Sql147931 struct rtw_regs {
1234689Sql147931 	ddi_acc_handle_t	r_handle;
1244689Sql147931 	caddr_t			r_base;
1254689Sql147931 	enum rtw_access		r_access;
1264689Sql147931 };
1274689Sql147931 
1284689Sql147931 #define	RTW_SR_GET(sr, ofs) \
1294689Sql147931 	(((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff)
1304689Sql147931 
1314689Sql147931 #define	RTW_SR_GET16(sr, ofs) \
1324689Sql147931 	(RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8))
1334689Sql147931 
1344689Sql147931 struct rtw_srom {
1354689Sql147931 	uint16_t		*sr_content;
1364689Sql147931 	uint16_t		sr_size;
1374689Sql147931 };
1384689Sql147931 
1394689Sql147931 
1404689Sql147931 #define	RTW_NTXPRI	4	/* number of Tx priorities */
1414689Sql147931 #define	RTW_TXPRILO	0
1424689Sql147931 #define	RTW_TXPRIMD	1
1434689Sql147931 #define	RTW_TXPRIHI	2
1444689Sql147931 #define	RTW_TXPRIBCN	3	/* beacon priority */
1454689Sql147931 
1464689Sql147931 #define	RTW_MAXPKTSEGS		64	/* Max 64 segments per Tx packet */
1474689Sql147931 
1484689Sql147931 /*
1494689Sql147931  * Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT
1504689Sql147931  * boundaries.  I allocate them consecutively from one buffer, so
1514689Sql147931  * just round up.
1524689Sql147931  */
1534689Sql147931 #define	RTW_TXQLENLO	64	/* low-priority queue length */
1544689Sql147931 #define	RTW_TXQLENMD	64	/* medium-priority */
1554689Sql147931 #define	RTW_TXQLENHI	64	/* high-priority */
1564689Sql147931 #define	RTW_TXQLENBCN	2	/* beacon */
1574689Sql147931 
1584689Sql147931 #define	RTW_NTXDESCLO	RTW_TXQLENLO
1594689Sql147931 #define	RTW_NTXDESCMD	RTW_TXQLENMD
1604689Sql147931 #define	RTW_NTXDESCHI	RTW_TXQLENHI
1614689Sql147931 #define	RTW_NTXDESCBCN	RTW_TXQLENBCN
1624689Sql147931 
1634689Sql147931 #define	RTW_NTXDESCTOTAL	(RTW_NTXDESCLO + RTW_NTXDESCMD + \
1644689Sql147931 				RTW_NTXDESCHI + RTW_NTXDESCBCN)
1654689Sql147931 
1664689Sql147931 #define	RTW_RXQLEN	64
1674689Sql147931 #define	RTW_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\
1684689Sql147931 	(area).offset, (area).alength, (flag)))
1694689Sql147931 
1704689Sql147931 #define	RTW_DMA_SYNC_DESC(area, offset, len, flag) \
1714689Sql147931 	((void) ddi_dma_sync((area).dma_hdl, offset, len, (flag)))
1724689Sql147931 
1734689Sql147931 #define	RTW_MINC(x, y) (x) = ((x + 1) % y)
1744689Sql147931 #define	list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
1754689Sql147931 
1764689Sql147931 typedef struct dma_area {
1774689Sql147931 	ddi_acc_handle_t	acc_hdl;	/* handle for memory */
1784689Sql147931 	caddr_t			mem_va;		/* CPU VA of memory */
1794689Sql147931 	uint32_t		nslots;		/* number of slots */
1804689Sql147931 	uint32_t		size;		/* size per slot */
1814689Sql147931 	size_t			alength;	/* allocated size */
1824689Sql147931 						/* >= product of above */
1834689Sql147931 
1844689Sql147931 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
1854689Sql147931 	offset_t		offset;		/* relative to handle */
1864689Sql147931 	ddi_dma_cookie_t	cookie;		/* associated cookie */
1874689Sql147931 	uint32_t		ncookies;	/* must be 1 */
1884689Sql147931 	uint32_t		token;		/* arbitrary identifier */
1894689Sql147931 } dma_area_t;						/* 0x50 (80) bytes */
1904689Sql147931 
1914689Sql147931 struct rtw_txbuf {
1924689Sql147931 	struct rtw_txdesc	*txdesc;	/* virtual addr of desc */
1934689Sql147931 	uint32_t		bf_daddr;	/* physical addr of desc */
1944689Sql147931 	uint32_t		next_bf_daddr;	/* physical addr of next desc */
1954689Sql147931 	dma_area_t		bf_dma;		/* dma area for buf */
1964689Sql147931 	struct ieee80211_node	*bf_in;		/* pointer to the node */
1974689Sql147931 	list_node_t		bf_node;
1984689Sql147931 	uint32_t		order;
1994689Sql147931 };
2004689Sql147931 
2014689Sql147931 struct rtw_rxbuf {
2024689Sql147931 	struct rtw_rxdesc	*rxdesc;	/* virtual addr of desc */
2034689Sql147931 	uint32_t		bf_daddr;	/* physical addr of desc */
2044689Sql147931 	dma_area_t		bf_dma;		/* dma area for buf */
2054689Sql147931 };
2064689Sql147931 
2074689Sql147931 struct rtw_txq {
2084689Sql147931 	struct	rtw_txdesc	*txdesc_h;
2094689Sql147931 	struct	rtw_txbuf	*txbuf_h;
2104689Sql147931 	uint32_t		tx_prod;
2114689Sql147931 	uint32_t		tx_cons;
2124689Sql147931 	uint32_t		tx_nfree;
2134689Sql147931 	kmutex_t		txbuf_lock;
2144689Sql147931 	list_t			tx_free_list;
2154689Sql147931 	list_t			tx_dirty_list;
2164689Sql147931 };
2174689Sql147931 
2184689Sql147931 struct rtw_descs {
2194689Sql147931 	struct rtw_txdesc	hd_txlo[RTW_NTXDESCLO];
2204689Sql147931 	struct rtw_txdesc	hd_txmd[RTW_NTXDESCMD];
2214689Sql147931 	struct rtw_txdesc	hd_txhi[RTW_NTXDESCHI];
2224689Sql147931 	struct rtw_rxdesc	hd_rx[RTW_RXQLEN];
2234689Sql147931 	struct rtw_txdesc	hd_bcn[RTW_NTXDESCBCN];
2244689Sql147931 };
2254689Sql147931 #define	RTW_DESC_OFFSET(ring, i)	offsetof(struct rtw_descs, ring[i])
2264689Sql147931 #define	RTW_RING_OFFSET(ring)		RTW_DESC_OFFSET(ring, 0)
2274689Sql147931 #define	RTW_RING_BASE(baseaddr0, ring) \
2284689Sql147931 	(baseaddr0 + RTW_RING_OFFSET(ring))
2294689Sql147931 
2304689Sql147931 /*
2314689Sql147931  * One Time Unit (TU) is 1Kus = 1024 microseconds.
2324689Sql147931  */
2334689Sql147931 #define	IEEE80211_DUR_TU		1024
2344689Sql147931 
2354689Sql147931 /*
2364689Sql147931  * IEEE 802.11b durations for DSSS PHY in microseconds
2374689Sql147931  */
2384689Sql147931 #define	IEEE80211_DUR_DS_LONG_PREAMBLE	144
2394689Sql147931 #define	IEEE80211_DUR_DS_SHORT_PREAMBLE	72
2404689Sql147931 
2414689Sql147931 #define	IEEE80211_DUR_DS_SLOW_PLCPHDR	48
2424689Sql147931 #define	IEEE80211_DUR_DS_FAST_PLCPHDR	24
2434689Sql147931 #define	IEEE80211_DUR_DS_SLOW_ACK	112
2444689Sql147931 #define	IEEE80211_DUR_DS_FAST_ACK	56
2454689Sql147931 #define	IEEE80211_DUR_DS_SLOW_CTS	112
2464689Sql147931 #define	IEEE80211_DUR_DS_FAST_CTS	56
2474689Sql147931 
2484689Sql147931 #define	IEEE80211_DUR_DS_SLOT		20
2494689Sql147931 #define	IEEE80211_DUR_DS_SIFS		10
2504689Sql147931 #define	IEEE80211_DUR_DS_PIFS	(IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT)
2514689Sql147931 #define	IEEE80211_DUR_DS_DIFS	(IEEE80211_DUR_DS_SIFS + \
2524689Sql147931 				2 * IEEE80211_DUR_DS_SLOT)
2534689Sql147931 #define	IEEE80211_DUR_DS_EIFS	(IEEE80211_DUR_DS_SIFS + \
2544689Sql147931 				IEEE80211_DUR_DS_SLOW_ACK + \
2554689Sql147931 				IEEE80211_DUR_DS_LONG_PREAMBLE + \
2564689Sql147931 				IEEE80211_DUR_DS_SLOW_PLCPHDR + \
2574689Sql147931 				IEEE80211_DUR_DIFS)
2584689Sql147931 
2594689Sql147931 /*
2604689Sql147931  * 802.11 frame duration definitions.
2614689Sql147931  */
2624689Sql147931 struct rtw_ieee80211_duration {
2634689Sql147931 	uint16_t	d_rts_dur;
2644689Sql147931 	uint16_t	d_data_dur;
2654689Sql147931 	uint16_t	d_plcp_len;
2664689Sql147931 	uint8_t		d_residue;	/* unused octets in time slot */
2674689Sql147931 	uint8_t		resv;
2684689Sql147931 };
2694689Sql147931 
2704689Sql147931 
2714689Sql147931 #ifdef RTW_RADIOTAP
2724689Sql147931 /*
2734689Sql147931  * Radio capture format for RTL8180.
2744689Sql147931  */
2754689Sql147931 
2764689Sql147931 #define	RTW_RX_RADIOTAP_PRESENT					\
2774689Sql147931 	((1 << IEEE80211_RADIOTAP_TSFT)			|	\
2784689Sql147931 	(1 << IEEE80211_RADIOTAP_FLAGS)		|	\
2794689Sql147931 	(1 << IEEE80211_RADIOTAP_RATE)			|	\
2804689Sql147931 	(1 << IEEE80211_RADIOTAP_CHANNEL)		|	\
2814689Sql147931 	(1 << IEEE80211_RADIOTAP_LOCK_QUALITY)		|	\
2824689Sql147931 	(1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)		|	\
2834689Sql147931 	0)
2844689Sql147931 
2854689Sql147931 struct rtw_rx_radiotap_header {
2864689Sql147931 	struct ieee80211_radiotap_header	rr_ihdr;
2874689Sql147931 	uint64_t				rr_tsft;
2884689Sql147931 	uint8_t				rr_flags;
2894689Sql147931 	uint8_t				rr_rate;
2904689Sql147931 	uint16_t				rr_chan_freq;
2914689Sql147931 	uint16_t				rr_chan_flags;
2924689Sql147931 	uint16_t				rr_barker_lock;
2934689Sql147931 	uint8_t				rr_antsignal;
2944689Sql147931 } __attribute__((__packed__));
2954689Sql147931 
2964689Sql147931 #define	RTW_TX_RADIOTAP_PRESENT				\
2974689Sql147931 	((1 << IEEE80211_RADIOTAP_FLAGS)	|	\
2984689Sql147931 	(1 << IEEE80211_RADIOTAP_RATE)		|	\
2994689Sql147931 	(1 << IEEE80211_RADIOTAP_CHANNEL)	|	\
3004689Sql147931 	0)
3014689Sql147931 
3024689Sql147931 struct rtw_tx_radiotap_header {
3034689Sql147931 	struct ieee80211_radiotap_header	rt_ihdr;
3044689Sql147931 	uint8_t				rt_flags;
3054689Sql147931 	uint8_t				rt_rate;
3064689Sql147931 	uint16_t				rt_chan_freq;
3074689Sql147931 	uint16_t				rt_chan_flags;
3084689Sql147931 } __attribute__((__packed__));
3094689Sql147931 #endif
3104689Sql147931 
3114689Sql147931 enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE,
3124689Sql147931 	FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE,
3134689Sql147931 	FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM,
3144689Sql147931 	FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP,
3154689Sql147931 	FINISH_TXCTLBLK_SETUP, DETACHED};
3164689Sql147931 
3174689Sql147931 struct rtw_hooks {
3184689Sql147931 	void			*rh_shutdown;	/* shutdown hook */
3194689Sql147931 	void			*rh_power;	/* power management hook */
3204689Sql147931 };
3214689Sql147931 
3224689Sql147931 enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON };
3234689Sql147931 
3244689Sql147931 typedef void (*rtw_continuous_tx_cb_t)(void *arg, int);
3254689Sql147931 
3264689Sql147931 struct rtw_phy {
3274689Sql147931 	struct rtw_rf	*p_rf;
3284689Sql147931 	struct rtw_regs	*p_regs;
3294689Sql147931 };
3304689Sql147931 
3314689Sql147931 struct rtw_bbpset {
3324689Sql147931 	uint_t	bb_antatten;
3334689Sql147931 	uint_t	bb_chestlim;
3344689Sql147931 	uint_t	bb_chsqlim;
3354689Sql147931 	uint_t	bb_ifagcdet;
3364689Sql147931 	uint_t	bb_ifagcini;
3374689Sql147931 	uint_t	bb_ifagclimit;
3384689Sql147931 	uint_t	bb_lnadet;
3394689Sql147931 	uint_t	bb_sys1;
3404689Sql147931 	uint_t	bb_sys2;
3414689Sql147931 	uint_t	bb_sys3;
3424689Sql147931 	uint_t	bb_trl;
3434689Sql147931 	uint_t	bb_txagc;
3444689Sql147931 };
3454689Sql147931 
3464689Sql147931 struct rtw_rf {
3474689Sql147931 	void	(*rf_destroy)(struct rtw_rf *);
3484689Sql147931 	/*
3494689Sql147931 	 * args: frequency, txpower, power state
3504689Sql147931 	 */
3514689Sql147931 	int	(*rf_init)(struct rtw_rf *, uint_t, uint8_t, enum rtw_pwrstate);
3524689Sql147931 	/*
3534689Sql147931 	 * arg: power state
3544689Sql147931 	 */
3554689Sql147931 	int	(*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate);
3564689Sql147931 	/*
3574689Sql147931 	 * arg: frequency
3584689Sql147931 	 */
3594689Sql147931 	int	(*rf_tune)(struct rtw_rf *, uint_t);
3604689Sql147931 	/*
3614689Sql147931 	 * arg: txpower
3624689Sql147931 	 */
3634689Sql147931 	int	(*rf_txpower)(struct rtw_rf *, uint8_t);
3644689Sql147931 	rtw_continuous_tx_cb_t	rf_continuous_tx_cb;
3654689Sql147931 	void			*rf_continuous_tx_arg;
3664689Sql147931 	struct rtw_bbpset	rf_bbpset;
3674689Sql147931 };
3684689Sql147931 
3694689Sql147931 typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, uint_t,
3704689Sql147931     uint32_t);
3714689Sql147931 
3724689Sql147931 struct rtw_rfbus {
3734689Sql147931 	struct rtw_regs		*b_regs;
3744689Sql147931 	rtw_rf_write_t		b_write;
3754689Sql147931 };
3764689Sql147931 
3774689Sql147931 struct rtw_max2820 {
3784689Sql147931 	struct rtw_rf		mx_rf;
3794689Sql147931 	struct rtw_rfbus	mx_bus;
3804689Sql147931 	int			mx_is_a;	/* 1: MAX2820A/MAX2821A */
3814689Sql147931 };
3824689Sql147931 
3834689Sql147931 struct rtw_sa2400 {
3844689Sql147931 	struct rtw_rf		sa_rf;
3854689Sql147931 	struct rtw_rfbus	sa_bus;
3864689Sql147931 	int			sa_digphy;	/* 1: digital PHY */
3874689Sql147931 };
3884689Sql147931 
3894689Sql147931 typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int);
3904689Sql147931 
3914689Sql147931 union rtw_keys {
3924689Sql147931 	uint8_t		rk_keys[4][16];
3934689Sql147931 	uint32_t	rk_words[16];
3944689Sql147931 };
3954689Sql147931 
3964689Sql147931 #define	RTW_LED_SLOW_TICKS	MAX(1, hz/2)
3974689Sql147931 #define	RTW_LED_FAST_TICKS	MAX(1, hz/10)
3984689Sql147931 
3994689Sql147931 struct rtw_led_state {
4004689Sql147931 #define	RTW_LED0	0x1
4014689Sql147931 #define	RTW_LED1	0x2
4024689Sql147931 	uint8_t		ls_slowblink:2;
4034689Sql147931 	uint8_t		ls_actblink:2;
4044689Sql147931 	uint8_t		ls_default:2;
4054689Sql147931 	uint8_t		ls_state;
4064689Sql147931 	uint8_t		ls_event;
4074689Sql147931 #define	RTW_LED_S_RX	0x1
4084689Sql147931 #define	RTW_LED_S_TX	0x2
4094689Sql147931 #define	RTW_LED_S_SLOW	0x4
4104689Sql147931 };
4114689Sql147931 
4124689Sql147931 typedef struct rtw_softc {
4134689Sql147931 	ieee80211com_t		sc_ic;	/* IEEE 802.11 common */
4144689Sql147931 	dev_info_t		*sc_dev; /* back pointer to dev_info_t */
4154689Sql147931 	kmutex_t		sc_genlock;
4164689Sql147931 	struct rtw_regs		sc_regs;
4174689Sql147931 	ddi_acc_handle_t	sc_cfg_handle;
4184689Sql147931 	caddr_t			sc_cfg_base;
4194689Sql147931 	enum ieee80211_phymode	sc_curmode;
4204689Sql147931 	uint32_t		sc_flags;
4214689Sql147931 	uint32_t		sc_invalid;
4224689Sql147931 	ddi_iblock_cookie_t	sc_iblock;
4234689Sql147931 	uint32_t		sc_need_reschedule;
4244689Sql147931 	uint16_t		sc_cachelsz;	/* cache line size */
4254689Sql147931 	uchar_t			sc_macaddr[6];
4264689Sql147931 
4274689Sql147931 	enum rtw_rfchipid	sc_rfchipid;
4284689Sql147931 	enum rtw_locale		sc_locale;
4294689Sql147931 	uint8_t			sc_phydelay;
4304689Sql147931 
4314689Sql147931 	uint32_t		sc_dmabuf_size;
4324689Sql147931 	dma_area_t		sc_desc_dma;
4334689Sql147931 
4344689Sql147931 	struct rtw_txq		sc_txq[RTW_NTXPRI];
4354689Sql147931 
4364689Sql147931 	struct	rtw_rxdesc	*rxdesc_h;
4374689Sql147931 	struct  rtw_rxbuf	*rxbuf_h;
4384689Sql147931 	uint32_t		rx_next;
4394689Sql147931 	kmutex_t		rxbuf_lock;
4404689Sql147931 	kmutex_t		sc_txlock;
4414689Sql147931 
4424689Sql147931 	struct rtw_srom		sc_srom;
4434689Sql147931 	enum rtw_pwrstate	sc_pwrstate;
4444689Sql147931 	rtw_pwrstate_t		sc_pwrstate_cb;
4454689Sql147931 	struct rtw_rf		*sc_rf;
4464689Sql147931 
4474689Sql147931 	uint16_t		sc_inten;
4484689Sql147931 
4494689Sql147931 	void (*sc_intr_ack)(struct rtw_regs *);
4504689Sql147931 
4514689Sql147931 	int			(*sc_enable)(struct rtw_softc *);
4524689Sql147931 	void			(*sc_disable)(struct rtw_softc *);
4534689Sql147931 	void			(*sc_power)(struct rtw_softc *, int);
4544689Sql147931 	struct rtw_hooks	sc_hooks;
4554689Sql147931 
4564689Sql147931 	uint_t			sc_cur_chan;
4574689Sql147931 
4584689Sql147931 	uint32_t		sc_tsfth;	/* most significant TSFT bits */
4594689Sql147931 	uint32_t		sc_rcr;		/* RTW_RCR */
4604689Sql147931 	uint8_t			sc_csthr;	/* carrier-sense threshold */
4614689Sql147931 
4624689Sql147931 	uint8_t			sc_rev;		/* PCI/Cardbus revision */
4634689Sql147931 
4644689Sql147931 	uint32_t		sc_anaparm;	/* register RTW_ANAPARM */
4654689Sql147931 #ifdef RTW_RADIOTAP
4664689Sql147931 	union {
4674689Sql147931 		struct rtw_rx_radiotap_header	tap;
4684689Sql147931 		uint8_t			pad[64];
4694689Sql147931 	} sc_rxtapu;
4704689Sql147931 	union {
4714689Sql147931 		struct rtw_tx_radiotap_header	tap;
4724689Sql147931 		uint8_t			pad[64];
4734689Sql147931 	} sc_txtapu;
4744689Sql147931 #endif
4754689Sql147931 	union rtw_keys		sc_keys;
4764689Sql147931 	int			sc_txkey;
4774689Sql147931 	struct rtw_led_state	sc_led_state;
4784689Sql147931 	int			sc_hwverid;
4794689Sql147931 
4804689Sql147931 	int			(*sc_newstate)(ieee80211com_t *,
4814689Sql147931 					enum ieee80211_state, int);
4824689Sql147931 
4834689Sql147931 	timeout_id_t		sc_scan_id;
4844689Sql147931 	timeout_id_t		sc_ratectl_id;
4854689Sql147931 	uint32_t		sc_tx_ok;
4864689Sql147931 	uint32_t		sc_tx_err;
4874689Sql147931 	uint32_t		sc_tx_retr;
4884689Sql147931 	uint32_t		sc_xmtretry;
4894689Sql147931 	uint32_t		sc_noxmtbuf;
4904689Sql147931 	uint32_t		sc_norcvbuf;
4914689Sql147931 	uint32_t		sc_bytexmt64;
4924689Sql147931 	uint32_t		sc_bytercv64;
4934689Sql147931 	uint32_t		sc_pktxmt64;
4944689Sql147931 	uint32_t		sc_pktrcv64;
4954689Sql147931 	uint32_t		sc_intr;
4964689Sql147931 	uint32_t		sc_ioerror;
4974689Sql147931 	uint32_t		hw_start;
4984689Sql147931 	uint32_t		hw_go;
4994689Sql147931 } rtw_softc_t;
5004689Sql147931 
5014689Sql147931 #define	RTW_SC(ic) ((rtw_softc_t *)ic)
502*10448SMikore.Li@Sun.COM #ifdef __cplusplus
503*10448SMikore.Li@Sun.COM }
504*10448SMikore.Li@Sun.COM #endif
5054689Sql147931 
5064689Sql147931 #endif /* _RTWVAR_H_ */
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