1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * Support for MSI, MSIX and INTx 31*0Sstevel@tonic-gate */ 32*0Sstevel@tonic-gate 33*0Sstevel@tonic-gate #include <sys/conf.h> 34*0Sstevel@tonic-gate #include <sys/debug.h> 35*0Sstevel@tonic-gate #include <sys/pci.h> 36*0Sstevel@tonic-gate #include <sys/sunddi.h> 37*0Sstevel@tonic-gate #include <sys/bitmap.h> 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate /* 40*0Sstevel@tonic-gate * Library utility functions 41*0Sstevel@tonic-gate */ 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate /* 45*0Sstevel@tonic-gate * pci_check_pciex: 46*0Sstevel@tonic-gate * 47*0Sstevel@tonic-gate * check whether the device has PCI-E capability 48*0Sstevel@tonic-gate */ 49*0Sstevel@tonic-gate int 50*0Sstevel@tonic-gate pci_check_pciex(dev_info_t *dip) 51*0Sstevel@tonic-gate { 52*0Sstevel@tonic-gate ddi_acc_handle_t cfg_handle; 53*0Sstevel@tonic-gate ushort_t status; 54*0Sstevel@tonic-gate ushort_t cap; 55*0Sstevel@tonic-gate ushort_t capsp; 56*0Sstevel@tonic-gate ushort_t cap_count = PCI_CAP_MAX_PTR; 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_check_pciex: dip: 0x%p, driver: %s, " 59*0Sstevel@tonic-gate "binding: %s, nodename: %s\n", (void *)dip, ddi_driver_name(dip), 60*0Sstevel@tonic-gate ddi_binding_name(dip), ddi_node_name(dip))); 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) { 63*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_check_pciex: " 64*0Sstevel@tonic-gate "pci_config_setup() failed\n")); 65*0Sstevel@tonic-gate return (DDI_FAILURE); 66*0Sstevel@tonic-gate } 67*0Sstevel@tonic-gate status = pci_config_get16(cfg_handle, PCI_CONF_STAT); 68*0Sstevel@tonic-gate if (!(status & PCI_STAT_CAP)) 69*0Sstevel@tonic-gate goto notpciex; 70*0Sstevel@tonic-gate 71*0Sstevel@tonic-gate capsp = pci_config_get8(cfg_handle, PCI_CONF_CAP_PTR); 72*0Sstevel@tonic-gate while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { 73*0Sstevel@tonic-gate capsp &= PCI_CAP_PTR_MASK; 74*0Sstevel@tonic-gate cap = pci_config_get8(cfg_handle, capsp); 75*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_check_pciex: capid=0x%x\n", 76*0Sstevel@tonic-gate cap)); 77*0Sstevel@tonic-gate if (cap == PCI_CAP_ID_PCI_E) { 78*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_check_pciex: " 79*0Sstevel@tonic-gate "PCI-Express capability found\n")); 80*0Sstevel@tonic-gate pci_config_teardown(&cfg_handle); 81*0Sstevel@tonic-gate return (DDI_SUCCESS); 82*0Sstevel@tonic-gate } 83*0Sstevel@tonic-gate capsp = pci_config_get8(cfg_handle, capsp + PCI_CAP_NEXT_PTR); 84*0Sstevel@tonic-gate } 85*0Sstevel@tonic-gate notpciex: 86*0Sstevel@tonic-gate pci_config_teardown(&cfg_handle); 87*0Sstevel@tonic-gate return (DDI_FAILURE); 88*0Sstevel@tonic-gate } 89*0Sstevel@tonic-gate 90*0Sstevel@tonic-gate 91*0Sstevel@tonic-gate /* 92*0Sstevel@tonic-gate * pci_get_msi_ctrl: 93*0Sstevel@tonic-gate * 94*0Sstevel@tonic-gate * Helper function that returns with 'cfg_hdl', MSI/X ctrl pointer, 95*0Sstevel@tonic-gate * and caps_ptr for MSI/X if these are found. 96*0Sstevel@tonic-gate */ 97*0Sstevel@tonic-gate static int 98*0Sstevel@tonic-gate pci_get_msi_ctrl(dev_info_t *dip, int type, ushort_t *msi_ctrl, 99*0Sstevel@tonic-gate ushort_t *caps_ptr, ddi_acc_handle_t *cfg_hdle) 100*0Sstevel@tonic-gate { 101*0Sstevel@tonic-gate ushort_t cap, cap_count; 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate *msi_ctrl = *caps_ptr = 0; 104*0Sstevel@tonic-gate 105*0Sstevel@tonic-gate if (pci_config_setup(dip, cfg_hdle) != DDI_SUCCESS) { 106*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: " 107*0Sstevel@tonic-gate "%s%d can't get config handle", 108*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 109*0Sstevel@tonic-gate 110*0Sstevel@tonic-gate return (DDI_FAILURE); 111*0Sstevel@tonic-gate } 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate /* Are capabilities supported? */ 114*0Sstevel@tonic-gate if (!(pci_config_get16(*cfg_hdle, PCI_CONF_STAT) & PCI_STAT_CAP)) { 115*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: " 116*0Sstevel@tonic-gate "%p doesn't support capabilities\n", (void *)dip)); 117*0Sstevel@tonic-gate 118*0Sstevel@tonic-gate pci_config_teardown(cfg_hdle); 119*0Sstevel@tonic-gate return (DDI_FAILURE); 120*0Sstevel@tonic-gate } 121*0Sstevel@tonic-gate 122*0Sstevel@tonic-gate *caps_ptr = pci_config_get8(*cfg_hdle, PCI_CONF_CAP_PTR); 123*0Sstevel@tonic-gate cap_count = PCI_CAP_MAX_PTR; 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate while ((cap_count--) && (*caps_ptr >= PCI_CAP_PTR_OFF)) { 126*0Sstevel@tonic-gate *caps_ptr &= PCI_CAP_PTR_MASK; 127*0Sstevel@tonic-gate cap = pci_config_get8(*cfg_hdle, *caps_ptr); 128*0Sstevel@tonic-gate 129*0Sstevel@tonic-gate if ((cap == PCI_CAP_ID_MSI) && (type == DDI_INTR_TYPE_MSI)) { 130*0Sstevel@tonic-gate *msi_ctrl = pci_config_get16(*cfg_hdle, 131*0Sstevel@tonic-gate *caps_ptr + PCI_MSI_CTRL); 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI " 134*0Sstevel@tonic-gate "caps_ptr=%x msi_ctrl=%x\n", *caps_ptr, *msi_ctrl)); 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate return (DDI_SUCCESS); 137*0Sstevel@tonic-gate } 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate if ((cap == PCI_CAP_ID_MSI_X) && (type == DDI_INTR_TYPE_MSIX)) { 140*0Sstevel@tonic-gate *msi_ctrl = pci_config_get16(*cfg_hdle, 141*0Sstevel@tonic-gate *caps_ptr + PCI_MSIX_CTRL); 142*0Sstevel@tonic-gate 143*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI-X " 144*0Sstevel@tonic-gate "caps_ptr=%x msi_ctrl=%x\n", *caps_ptr, *msi_ctrl)); 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate return (DDI_SUCCESS); 147*0Sstevel@tonic-gate } 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate *caps_ptr = pci_config_get8(*cfg_hdle, 150*0Sstevel@tonic-gate *caps_ptr + PCI_CAP_NEXT_PTR); 151*0Sstevel@tonic-gate } 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate pci_config_teardown(cfg_hdle); 154*0Sstevel@tonic-gate 155*0Sstevel@tonic-gate return (DDI_FAILURE); 156*0Sstevel@tonic-gate } 157*0Sstevel@tonic-gate 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate /* 160*0Sstevel@tonic-gate * pci_msi_get_cap: 161*0Sstevel@tonic-gate * 162*0Sstevel@tonic-gate * Get the capabilities of the MSI/X interrupt 163*0Sstevel@tonic-gate */ 164*0Sstevel@tonic-gate int 165*0Sstevel@tonic-gate pci_msi_get_cap(dev_info_t *rdip, int type, int *flagsp) 166*0Sstevel@tonic-gate { 167*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 168*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 169*0Sstevel@tonic-gate 170*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_cap: rdip = 0x%p\n", 171*0Sstevel@tonic-gate (void *)rdip)); 172*0Sstevel@tonic-gate 173*0Sstevel@tonic-gate *flagsp = 0; 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 176*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 177*0Sstevel@tonic-gate return (DDI_FAILURE); 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 180*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_64BIT_MASK) 181*0Sstevel@tonic-gate *flagsp |= DDI_INTR_FLAG_MSI64; 182*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_PVM_MASK) 183*0Sstevel@tonic-gate *flagsp |= (DDI_INTR_FLAG_MASKABLE | 184*0Sstevel@tonic-gate DDI_INTR_FLAG_PENDING); 185*0Sstevel@tonic-gate else 186*0Sstevel@tonic-gate *flagsp |= DDI_INTR_FLAG_BLOCK; 187*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 188*0Sstevel@tonic-gate /* MSI-X supports PVM, 64bit by default */ 189*0Sstevel@tonic-gate *flagsp |= (DDI_INTR_FLAG_MASKABLE | DDI_INTR_FLAG_MSI64 | 190*0Sstevel@tonic-gate DDI_INTR_FLAG_PENDING); 191*0Sstevel@tonic-gate } 192*0Sstevel@tonic-gate 193*0Sstevel@tonic-gate *flagsp |= DDI_INTR_FLAG_EDGE; 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_cap: flags = 0x%x\n", *flagsp)); 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 198*0Sstevel@tonic-gate return (DDI_SUCCESS); 199*0Sstevel@tonic-gate } 200*0Sstevel@tonic-gate 201*0Sstevel@tonic-gate 202*0Sstevel@tonic-gate /* 203*0Sstevel@tonic-gate * pci_msi_configure: 204*0Sstevel@tonic-gate * 205*0Sstevel@tonic-gate * Configure address/data and number MSI/Xs fields in the MSI/X 206*0Sstevel@tonic-gate * capability structure. 207*0Sstevel@tonic-gate */ 208*0Sstevel@tonic-gate /* ARGSUSED */ 209*0Sstevel@tonic-gate int 210*0Sstevel@tonic-gate pci_msi_configure(dev_info_t *rdip, int type, int count, int inum, 211*0Sstevel@tonic-gate uint64_t addr, uint64_t data) 212*0Sstevel@tonic-gate { 213*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 214*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 215*0Sstevel@tonic-gate 216*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_configure: rdip = 0x%p\n", 217*0Sstevel@tonic-gate (void *)rdip)); 218*0Sstevel@tonic-gate 219*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 220*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 221*0Sstevel@tonic-gate return (DDI_FAILURE); 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 224*0Sstevel@tonic-gate /* Set the bits to inform how many MSIs are enabled */ 225*0Sstevel@tonic-gate msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT); 226*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 227*0Sstevel@tonic-gate caps_ptr + PCI_MSI_CTRL, msi_ctrl); 228*0Sstevel@tonic-gate 229*0Sstevel@tonic-gate /* Set the "data" and "addr" bits */ 230*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 231*0Sstevel@tonic-gate caps_ptr + PCI_MSI_ADDR_OFFSET, addr); 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_64BIT_MASK) { 234*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 235*0Sstevel@tonic-gate caps_ptr + PCI_MSI_ADDR_OFFSET + 4, 0); 236*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 237*0Sstevel@tonic-gate caps_ptr + PCI_MSI_64BIT_DATA, data); 238*0Sstevel@tonic-gate } else { 239*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 240*0Sstevel@tonic-gate caps_ptr + PCI_MSI_32BIT_DATA, data); 241*0Sstevel@tonic-gate } 242*0Sstevel@tonic-gate 243*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_configure: msi_ctrl = %x\n", 244*0Sstevel@tonic-gate pci_config_get16(cfg_hdle, caps_ptr + PCI_MSI_CTRL))); 245*0Sstevel@tonic-gate 246*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 247*0Sstevel@tonic-gate uint64_t off; 248*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p = i_ddi_get_msix(rdip); 249*0Sstevel@tonic-gate 250*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 251*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + 252*0Sstevel@tonic-gate ((inum - 1) * PCI_MSIX_VECTOR_SIZE); 253*0Sstevel@tonic-gate 254*0Sstevel@tonic-gate /* Set the "data" and "addr" bits */ 255*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 256*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off + PCI_MSIX_DATA_OFFSET), data); 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)off, addr); 259*0Sstevel@tonic-gate } 260*0Sstevel@tonic-gate 261*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 262*0Sstevel@tonic-gate return (DDI_SUCCESS); 263*0Sstevel@tonic-gate } 264*0Sstevel@tonic-gate 265*0Sstevel@tonic-gate 266*0Sstevel@tonic-gate /* 267*0Sstevel@tonic-gate * pci_msi_unconfigure: 268*0Sstevel@tonic-gate * 269*0Sstevel@tonic-gate * Unconfigure address/data and number MSI/Xs fields in the MSI/X 270*0Sstevel@tonic-gate * capability structure. 271*0Sstevel@tonic-gate */ 272*0Sstevel@tonic-gate /* ARGSUSED */ 273*0Sstevel@tonic-gate int 274*0Sstevel@tonic-gate pci_msi_unconfigure(dev_info_t *rdip, int type, int inum) 275*0Sstevel@tonic-gate { 276*0Sstevel@tonic-gate ushort_t msi_ctrl, caps_ptr; 277*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 278*0Sstevel@tonic-gate 279*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_unconfigure: rdip = 0x%p\n", 280*0Sstevel@tonic-gate (void *)rdip)); 281*0Sstevel@tonic-gate 282*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 283*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 284*0Sstevel@tonic-gate return (DDI_FAILURE); 285*0Sstevel@tonic-gate 286*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 287*0Sstevel@tonic-gate msi_ctrl &= (~PCI_MSI_MME_MASK); 288*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, caps_ptr + PCI_MSI_CTRL, msi_ctrl); 289*0Sstevel@tonic-gate 290*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 291*0Sstevel@tonic-gate caps_ptr + PCI_MSI_ADDR_OFFSET, 0); 292*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_64BIT_MASK) { 293*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 294*0Sstevel@tonic-gate caps_ptr + PCI_MSI_64BIT_DATA, 0); 295*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 296*0Sstevel@tonic-gate caps_ptr + PCI_MSI_ADDR_OFFSET + 4, 0); 297*0Sstevel@tonic-gate } else { 298*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 299*0Sstevel@tonic-gate caps_ptr + PCI_MSI_32BIT_DATA, 0); 300*0Sstevel@tonic-gate } 301*0Sstevel@tonic-gate 302*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_unconfigure: " 303*0Sstevel@tonic-gate "msi_ctrl = %x\n", 304*0Sstevel@tonic-gate pci_config_get16(cfg_hdle, caps_ptr + PCI_MSI_CTRL))); 305*0Sstevel@tonic-gate 306*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 307*0Sstevel@tonic-gate uint64_t off; 308*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p = i_ddi_get_msix(rdip); 309*0Sstevel@tonic-gate 310*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 311*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + 312*0Sstevel@tonic-gate ((inum - 1) * PCI_MSIX_VECTOR_SIZE); 313*0Sstevel@tonic-gate 314*0Sstevel@tonic-gate /* Reset the "data" and "addr" bits */ 315*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 316*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off + PCI_MSIX_DATA_OFFSET), 0); 317*0Sstevel@tonic-gate 318*0Sstevel@tonic-gate ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)off, 0); 319*0Sstevel@tonic-gate } 320*0Sstevel@tonic-gate 321*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 322*0Sstevel@tonic-gate return (DDI_SUCCESS); 323*0Sstevel@tonic-gate } 324*0Sstevel@tonic-gate 325*0Sstevel@tonic-gate 326*0Sstevel@tonic-gate /* 327*0Sstevel@tonic-gate * pci_is_msi_enabled: 328*0Sstevel@tonic-gate * 329*0Sstevel@tonic-gate * This function returns DDI_SUCCESS if MSI/X is already enabled, otherwise 330*0Sstevel@tonic-gate * it returns DDI_FAILURE. 331*0Sstevel@tonic-gate */ 332*0Sstevel@tonic-gate int 333*0Sstevel@tonic-gate pci_is_msi_enabled(dev_info_t *rdip, int type) 334*0Sstevel@tonic-gate { 335*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 336*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 337*0Sstevel@tonic-gate int ret = DDI_FAILURE; 338*0Sstevel@tonic-gate 339*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_is_msi_enabled: rdip = 0x%p, " 340*0Sstevel@tonic-gate "type = 0x%x\n", (void *)rdip, type)); 341*0Sstevel@tonic-gate 342*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 343*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 344*0Sstevel@tonic-gate return (DDI_FAILURE); 345*0Sstevel@tonic-gate 346*0Sstevel@tonic-gate if ((type == DDI_INTR_TYPE_MSI) && (msi_ctrl & PCI_MSI_ENABLE_BIT)) 347*0Sstevel@tonic-gate ret = DDI_SUCCESS; 348*0Sstevel@tonic-gate 349*0Sstevel@tonic-gate if ((type == DDI_INTR_TYPE_MSIX) && (msi_ctrl & PCI_MSIX_ENABLE_BIT)) 350*0Sstevel@tonic-gate ret = DDI_SUCCESS; 351*0Sstevel@tonic-gate 352*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 353*0Sstevel@tonic-gate return (ret); 354*0Sstevel@tonic-gate } 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate 357*0Sstevel@tonic-gate /* 358*0Sstevel@tonic-gate * pci_msi_enable_mode: 359*0Sstevel@tonic-gate * 360*0Sstevel@tonic-gate * This function sets the MSI_ENABLE bit in the capability structure 361*0Sstevel@tonic-gate * (for MSI) and MSIX_ENABLE bit in the MSI-X capability structure. 362*0Sstevel@tonic-gate */ 363*0Sstevel@tonic-gate int 364*0Sstevel@tonic-gate pci_msi_enable_mode(dev_info_t *rdip, int type, int inum) 365*0Sstevel@tonic-gate { 366*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 367*0Sstevel@tonic-gate uint16_t cmd_reg; 368*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 369*0Sstevel@tonic-gate 370*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: rdip = 0x%p, " 371*0Sstevel@tonic-gate "inum = 0x%x\n", (void *)rdip, inum)); 372*0Sstevel@tonic-gate 373*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 374*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 375*0Sstevel@tonic-gate return (DDI_FAILURE); 376*0Sstevel@tonic-gate 377*0Sstevel@tonic-gate /* Disable INTx simulation, if applicable */ 378*0Sstevel@tonic-gate cmd_reg = pci_config_get16(cfg_hdle, PCI_CONF_COMM); 379*0Sstevel@tonic-gate 380*0Sstevel@tonic-gate /* This write succeeds only for devices > PCI2.3 */ 381*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, PCI_CONF_COMM, 382*0Sstevel@tonic-gate cmd_reg | PCI_COMM_INTX_DISABLE); 383*0Sstevel@tonic-gate 384*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: " 385*0Sstevel@tonic-gate "Before CmdReg = 0x%x, After CmdReg = 0x%x\n", 386*0Sstevel@tonic-gate cmd_reg, pci_config_get16(cfg_hdle, PCI_CONF_COMM))); 387*0Sstevel@tonic-gate 388*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 389*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSI_ENABLE_BIT) 390*0Sstevel@tonic-gate goto finished; 391*0Sstevel@tonic-gate 392*0Sstevel@tonic-gate msi_ctrl |= PCI_MSI_ENABLE_BIT; 393*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 394*0Sstevel@tonic-gate caps_ptr + PCI_MSI_CTRL, msi_ctrl); 395*0Sstevel@tonic-gate 396*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 397*0Sstevel@tonic-gate uint64_t off; 398*0Sstevel@tonic-gate uint32_t mask_bits; 399*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p; 400*0Sstevel@tonic-gate 401*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSIX_ENABLE_BIT) 402*0Sstevel@tonic-gate goto finished; 403*0Sstevel@tonic-gate 404*0Sstevel@tonic-gate msi_ctrl |= PCI_MSIX_ENABLE_BIT; 405*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 406*0Sstevel@tonic-gate caps_ptr + PCI_MSIX_CTRL, msi_ctrl); 407*0Sstevel@tonic-gate 408*0Sstevel@tonic-gate msix_p = i_ddi_get_msix(rdip); 409*0Sstevel@tonic-gate 410*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 411*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + ((inum - 1) * 412*0Sstevel@tonic-gate PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; 413*0Sstevel@tonic-gate 414*0Sstevel@tonic-gate /* Clear the Mask bit */ 415*0Sstevel@tonic-gate mask_bits = ddi_get32(msix_p->msix_tbl_hdl, 416*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off)); 417*0Sstevel@tonic-gate 418*0Sstevel@tonic-gate mask_bits &= ~0; 419*0Sstevel@tonic-gate 420*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 421*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off), mask_bits); 422*0Sstevel@tonic-gate } 423*0Sstevel@tonic-gate 424*0Sstevel@tonic-gate finished: 425*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: msi_ctrl = %x\n", 426*0Sstevel@tonic-gate msi_ctrl)); 427*0Sstevel@tonic-gate 428*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 429*0Sstevel@tonic-gate return (DDI_SUCCESS); 430*0Sstevel@tonic-gate } 431*0Sstevel@tonic-gate 432*0Sstevel@tonic-gate 433*0Sstevel@tonic-gate /* 434*0Sstevel@tonic-gate * pci_msi_disable_mode: 435*0Sstevel@tonic-gate * 436*0Sstevel@tonic-gate * This function resets the MSI_ENABLE bit in the capability structure 437*0Sstevel@tonic-gate * (for MSI) and MSIX_ENABLE bit in the MSI-X capability structure. 438*0Sstevel@tonic-gate */ 439*0Sstevel@tonic-gate int 440*0Sstevel@tonic-gate pci_msi_disable_mode(dev_info_t *rdip, int type, int inum) 441*0Sstevel@tonic-gate { 442*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 443*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 444*0Sstevel@tonic-gate 445*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_disable_mode: rdip = 0x%p " 446*0Sstevel@tonic-gate "inum = 0x%x\n", (void *)rdip, inum)); 447*0Sstevel@tonic-gate 448*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 449*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 450*0Sstevel@tonic-gate return (DDI_FAILURE); 451*0Sstevel@tonic-gate 452*0Sstevel@tonic-gate /* Reset the "enable" bit */ 453*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 454*0Sstevel@tonic-gate if (!(msi_ctrl & PCI_MSI_ENABLE_BIT)) 455*0Sstevel@tonic-gate goto finished; 456*0Sstevel@tonic-gate msi_ctrl &= ~PCI_MSI_ENABLE_BIT; 457*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, 458*0Sstevel@tonic-gate caps_ptr + PCI_MSI_CTRL, msi_ctrl); 459*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 460*0Sstevel@tonic-gate offset_t off; 461*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p; 462*0Sstevel@tonic-gate 463*0Sstevel@tonic-gate if (!(msi_ctrl & PCI_MSIX_ENABLE_BIT)) 464*0Sstevel@tonic-gate goto finished; 465*0Sstevel@tonic-gate 466*0Sstevel@tonic-gate msix_p = i_ddi_get_msix(rdip); 467*0Sstevel@tonic-gate 468*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 469*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + ((inum - 1) * 470*0Sstevel@tonic-gate PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; 471*0Sstevel@tonic-gate 472*0Sstevel@tonic-gate /* Set the Mask bit */ 473*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 474*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off), 0x1); 475*0Sstevel@tonic-gate } 476*0Sstevel@tonic-gate 477*0Sstevel@tonic-gate finished: 478*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_disable_mode: msi_ctrl = %x\n", 479*0Sstevel@tonic-gate msi_ctrl)); 480*0Sstevel@tonic-gate 481*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 482*0Sstevel@tonic-gate return (DDI_SUCCESS); 483*0Sstevel@tonic-gate } 484*0Sstevel@tonic-gate 485*0Sstevel@tonic-gate 486*0Sstevel@tonic-gate /* 487*0Sstevel@tonic-gate * pci_msi_set_mask: 488*0Sstevel@tonic-gate * 489*0Sstevel@tonic-gate * Set the mask bit in the MSI/X capability structure 490*0Sstevel@tonic-gate */ 491*0Sstevel@tonic-gate /* ARGSUSED */ 492*0Sstevel@tonic-gate int 493*0Sstevel@tonic-gate pci_msi_set_mask(dev_info_t *rdip, int type, int inum) 494*0Sstevel@tonic-gate { 495*0Sstevel@tonic-gate int offset; 496*0Sstevel@tonic-gate int ret = DDI_FAILURE; 497*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 498*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 499*0Sstevel@tonic-gate uint_t mask_bits; 500*0Sstevel@tonic-gate 501*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_set_mask: rdip = 0x%p, " 502*0Sstevel@tonic-gate "type = 0x%x\n", (void *)rdip, type)); 503*0Sstevel@tonic-gate 504*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 505*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 506*0Sstevel@tonic-gate return (DDI_FAILURE); 507*0Sstevel@tonic-gate 508*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 509*0Sstevel@tonic-gate if (!(msi_ctrl & PCI_MSI_PVM_MASK)) 510*0Sstevel@tonic-gate goto done; 511*0Sstevel@tonic-gate 512*0Sstevel@tonic-gate offset = (msi_ctrl & PCI_MSI_64BIT_MASK) ? 513*0Sstevel@tonic-gate PCI_MSI_64BIT_MASKBITS : PCI_MSI_32BIT_MASK; 514*0Sstevel@tonic-gate 515*0Sstevel@tonic-gate mask_bits = pci_config_get32(cfg_hdle, 516*0Sstevel@tonic-gate caps_ptr + offset); 517*0Sstevel@tonic-gate 518*0Sstevel@tonic-gate mask_bits |= (1 << inum); 519*0Sstevel@tonic-gate 520*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 521*0Sstevel@tonic-gate caps_ptr + offset, mask_bits); 522*0Sstevel@tonic-gate 523*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 524*0Sstevel@tonic-gate uint64_t off; 525*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p; 526*0Sstevel@tonic-gate 527*0Sstevel@tonic-gate /* Set function mask */ 528*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSIX_FUNCTION_MASK) { 529*0Sstevel@tonic-gate ret = DDI_SUCCESS; 530*0Sstevel@tonic-gate goto done; 531*0Sstevel@tonic-gate } 532*0Sstevel@tonic-gate 533*0Sstevel@tonic-gate msix_p = i_ddi_get_msix(rdip); 534*0Sstevel@tonic-gate 535*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 536*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + ((inum - 1) * 537*0Sstevel@tonic-gate PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; 538*0Sstevel@tonic-gate 539*0Sstevel@tonic-gate /* Set the Mask bit */ 540*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 541*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off), 0x1); 542*0Sstevel@tonic-gate } 543*0Sstevel@tonic-gate 544*0Sstevel@tonic-gate ret = DDI_SUCCESS; 545*0Sstevel@tonic-gate done: 546*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 547*0Sstevel@tonic-gate return (ret); 548*0Sstevel@tonic-gate } 549*0Sstevel@tonic-gate 550*0Sstevel@tonic-gate 551*0Sstevel@tonic-gate /* 552*0Sstevel@tonic-gate * pci_msi_clr_mask: 553*0Sstevel@tonic-gate * 554*0Sstevel@tonic-gate * Clear the mask bit in the MSI/X capability structure 555*0Sstevel@tonic-gate */ 556*0Sstevel@tonic-gate /* ARGSUSED */ 557*0Sstevel@tonic-gate int 558*0Sstevel@tonic-gate pci_msi_clr_mask(dev_info_t *rdip, int type, int inum) 559*0Sstevel@tonic-gate { 560*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 561*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 562*0Sstevel@tonic-gate int offset; 563*0Sstevel@tonic-gate int ret = DDI_FAILURE; 564*0Sstevel@tonic-gate uint_t mask_bits; 565*0Sstevel@tonic-gate 566*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_clr_mask: rdip = 0x%p, " 567*0Sstevel@tonic-gate "type = 0x%x\n", (void *)rdip, type)); 568*0Sstevel@tonic-gate 569*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 570*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 571*0Sstevel@tonic-gate return (DDI_FAILURE); 572*0Sstevel@tonic-gate 573*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 574*0Sstevel@tonic-gate if (!(msi_ctrl & PCI_MSI_PVM_MASK)) 575*0Sstevel@tonic-gate goto done; 576*0Sstevel@tonic-gate 577*0Sstevel@tonic-gate offset = (msi_ctrl & PCI_MSI_64BIT_MASK) ? 578*0Sstevel@tonic-gate PCI_MSI_64BIT_MASKBITS : PCI_MSI_32BIT_MASK; 579*0Sstevel@tonic-gate mask_bits = pci_config_get32(cfg_hdle, 580*0Sstevel@tonic-gate caps_ptr + offset); 581*0Sstevel@tonic-gate 582*0Sstevel@tonic-gate mask_bits &= ~(1 << inum); 583*0Sstevel@tonic-gate 584*0Sstevel@tonic-gate pci_config_put32(cfg_hdle, 585*0Sstevel@tonic-gate caps_ptr + offset, mask_bits); 586*0Sstevel@tonic-gate 587*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 588*0Sstevel@tonic-gate uint64_t off; 589*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p; 590*0Sstevel@tonic-gate 591*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSIX_FUNCTION_MASK) { 592*0Sstevel@tonic-gate ret = DDI_SUCCESS; 593*0Sstevel@tonic-gate goto done; 594*0Sstevel@tonic-gate } 595*0Sstevel@tonic-gate 596*0Sstevel@tonic-gate msix_p = i_ddi_get_msix(rdip); 597*0Sstevel@tonic-gate 598*0Sstevel@tonic-gate /* Offset into the "inum"th entry in the MSI-X table */ 599*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_tbl_addr + ((inum - 1) * 600*0Sstevel@tonic-gate PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; 601*0Sstevel@tonic-gate 602*0Sstevel@tonic-gate /* Clear the Mask bit */ 603*0Sstevel@tonic-gate mask_bits = ddi_get32(msix_p->msix_tbl_hdl, 604*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off)); 605*0Sstevel@tonic-gate 606*0Sstevel@tonic-gate mask_bits &= ~0; 607*0Sstevel@tonic-gate 608*0Sstevel@tonic-gate ddi_put32(msix_p->msix_tbl_hdl, 609*0Sstevel@tonic-gate (uint32_t *)((uchar_t *)off), mask_bits); 610*0Sstevel@tonic-gate } 611*0Sstevel@tonic-gate 612*0Sstevel@tonic-gate ret = DDI_SUCCESS; 613*0Sstevel@tonic-gate done: 614*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 615*0Sstevel@tonic-gate return (ret); 616*0Sstevel@tonic-gate } 617*0Sstevel@tonic-gate 618*0Sstevel@tonic-gate 619*0Sstevel@tonic-gate /* 620*0Sstevel@tonic-gate * pci_msi_get_pending: 621*0Sstevel@tonic-gate * 622*0Sstevel@tonic-gate * Get the pending bit from the MSI/X capability structure 623*0Sstevel@tonic-gate */ 624*0Sstevel@tonic-gate /* ARGSUSED */ 625*0Sstevel@tonic-gate int 626*0Sstevel@tonic-gate pci_msi_get_pending(dev_info_t *rdip, int type, int inum, int *pendingp) 627*0Sstevel@tonic-gate { 628*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 629*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 630*0Sstevel@tonic-gate int offset; 631*0Sstevel@tonic-gate int ret = DDI_FAILURE; 632*0Sstevel@tonic-gate 633*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_pending: rdip = 0x%p\n", 634*0Sstevel@tonic-gate (void *)rdip)); 635*0Sstevel@tonic-gate 636*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 637*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 638*0Sstevel@tonic-gate return (DDI_FAILURE); 639*0Sstevel@tonic-gate 640*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 641*0Sstevel@tonic-gate uint32_t pending_bits; 642*0Sstevel@tonic-gate 643*0Sstevel@tonic-gate if (!(msi_ctrl & PCI_MSI_PVM_MASK)) { 644*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_pending: " 645*0Sstevel@tonic-gate "PVM is not supported\n")); 646*0Sstevel@tonic-gate goto done; 647*0Sstevel@tonic-gate } 648*0Sstevel@tonic-gate 649*0Sstevel@tonic-gate offset = (msi_ctrl & PCI_MSI_64BIT_MASK) ? 650*0Sstevel@tonic-gate PCI_MSI_64BIT_PENDING : PCI_MSI_32BIT_PENDING; 651*0Sstevel@tonic-gate 652*0Sstevel@tonic-gate pending_bits = pci_config_get32(cfg_hdle, 653*0Sstevel@tonic-gate caps_ptr + offset); 654*0Sstevel@tonic-gate 655*0Sstevel@tonic-gate *pendingp = pending_bits & ~(1 >> inum); 656*0Sstevel@tonic-gate 657*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 658*0Sstevel@tonic-gate uint64_t off; 659*0Sstevel@tonic-gate uint64_t pending_bits; 660*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p = i_ddi_get_msix(rdip); 661*0Sstevel@tonic-gate 662*0Sstevel@tonic-gate /* Offset into the PBA array which has entry for "inum" */ 663*0Sstevel@tonic-gate off = (uint64_t)msix_p->msix_pba_addr + ((inum - 1) / 64); 664*0Sstevel@tonic-gate 665*0Sstevel@tonic-gate /* Read the PBA array */ 666*0Sstevel@tonic-gate pending_bits = ddi_get64(msix_p->msix_pba_hdl, 667*0Sstevel@tonic-gate (uint64_t *)((uchar_t *)off)); 668*0Sstevel@tonic-gate 669*0Sstevel@tonic-gate *pendingp = pending_bits & ~(1 >> inum); 670*0Sstevel@tonic-gate } 671*0Sstevel@tonic-gate 672*0Sstevel@tonic-gate ret = DDI_SUCCESS; 673*0Sstevel@tonic-gate done: 674*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 675*0Sstevel@tonic-gate return (ret); 676*0Sstevel@tonic-gate } 677*0Sstevel@tonic-gate 678*0Sstevel@tonic-gate 679*0Sstevel@tonic-gate /* 680*0Sstevel@tonic-gate * pci_msi_get_nintrs: 681*0Sstevel@tonic-gate * 682*0Sstevel@tonic-gate * For a given type (MSI/X) returns the number of interrupts supported 683*0Sstevel@tonic-gate */ 684*0Sstevel@tonic-gate int 685*0Sstevel@tonic-gate pci_msi_get_nintrs(dev_info_t *rdip, int type, int *nintrs) 686*0Sstevel@tonic-gate { 687*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 688*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 689*0Sstevel@tonic-gate 690*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_nintrs: rdip = 0x%p\n", 691*0Sstevel@tonic-gate (void *)rdip)); 692*0Sstevel@tonic-gate 693*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 694*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 695*0Sstevel@tonic-gate return (DDI_FAILURE); 696*0Sstevel@tonic-gate 697*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 698*0Sstevel@tonic-gate *nintrs = 1 << ((msi_ctrl & PCI_MSI_MMC_MASK) >> 699*0Sstevel@tonic-gate PCI_MSI_MMC_SHIFT); 700*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 701*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK) 702*0Sstevel@tonic-gate *nintrs = (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK) + 1; 703*0Sstevel@tonic-gate } 704*0Sstevel@tonic-gate 705*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_nintrs: " 706*0Sstevel@tonic-gate "nintr = 0x%x\n", *nintrs)); 707*0Sstevel@tonic-gate 708*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 709*0Sstevel@tonic-gate return (DDI_SUCCESS); 710*0Sstevel@tonic-gate } 711*0Sstevel@tonic-gate 712*0Sstevel@tonic-gate 713*0Sstevel@tonic-gate /* 714*0Sstevel@tonic-gate * pci_msi_set_nintrs: 715*0Sstevel@tonic-gate * 716*0Sstevel@tonic-gate * For a given type (MSI/X) sets the number of interrupts supported 717*0Sstevel@tonic-gate * by the system. 718*0Sstevel@tonic-gate * For MSI: Return an error if this func is called for navail > 32 719*0Sstevel@tonic-gate * For MSI-X: Return an error if this func is called for navail > 2048 720*0Sstevel@tonic-gate */ 721*0Sstevel@tonic-gate int 722*0Sstevel@tonic-gate pci_msi_set_nintrs(dev_info_t *rdip, int type, int navail) 723*0Sstevel@tonic-gate { 724*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 725*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 726*0Sstevel@tonic-gate 727*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_set_nintrs: rdip = 0x%p, " 728*0Sstevel@tonic-gate "navail = 0x%x\n", (void *)rdip, navail)); 729*0Sstevel@tonic-gate 730*0Sstevel@tonic-gate /* Check for valid input argument */ 731*0Sstevel@tonic-gate if (((type == DDI_INTR_TYPE_MSI) && (navail > PCI_MSI_MAX_INTRS)) || 732*0Sstevel@tonic-gate ((type == DDI_INTR_TYPE_MSIX) && (navail > PCI_MSIX_MAX_INTRS))) 733*0Sstevel@tonic-gate return (DDI_EINVAL); 734*0Sstevel@tonic-gate 735*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, type, &msi_ctrl, 736*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 737*0Sstevel@tonic-gate return (DDI_FAILURE); 738*0Sstevel@tonic-gate 739*0Sstevel@tonic-gate if (type == DDI_INTR_TYPE_MSI) { 740*0Sstevel@tonic-gate msi_ctrl |= ((highbit(navail) -1) << PCI_MSI_MME_SHIFT); 741*0Sstevel@tonic-gate 742*0Sstevel@tonic-gate pci_config_put16(cfg_hdle, caps_ptr + PCI_MSI_CTRL, msi_ctrl); 743*0Sstevel@tonic-gate } else if (type == DDI_INTR_TYPE_MSIX) { 744*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_set_nintrs: unsupported\n")); 745*0Sstevel@tonic-gate } 746*0Sstevel@tonic-gate 747*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 748*0Sstevel@tonic-gate return (DDI_SUCCESS); 749*0Sstevel@tonic-gate } 750*0Sstevel@tonic-gate 751*0Sstevel@tonic-gate 752*0Sstevel@tonic-gate /* 753*0Sstevel@tonic-gate * pci_msi_get_supported_type: 754*0Sstevel@tonic-gate * 755*0Sstevel@tonic-gate * Returns DDI_INTR_TYPE_MSI and/or DDI_INTR_TYPE_MSIX as supported 756*0Sstevel@tonic-gate * types if device supports them. A DDI_FAILURE is returned otherwise. 757*0Sstevel@tonic-gate */ 758*0Sstevel@tonic-gate int 759*0Sstevel@tonic-gate pci_msi_get_supported_type(dev_info_t *rdip, int *typesp) 760*0Sstevel@tonic-gate { 761*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 762*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 763*0Sstevel@tonic-gate 764*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_supported_type: " 765*0Sstevel@tonic-gate "rdip = 0x%p\n", (void *)rdip)); 766*0Sstevel@tonic-gate 767*0Sstevel@tonic-gate *typesp = 0; 768*0Sstevel@tonic-gate 769*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, DDI_INTR_TYPE_MSI, &msi_ctrl, 770*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) == DDI_SUCCESS) { 771*0Sstevel@tonic-gate *typesp |= DDI_INTR_TYPE_MSI; 772*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 773*0Sstevel@tonic-gate } 774*0Sstevel@tonic-gate 775*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, DDI_INTR_TYPE_MSIX, &msi_ctrl, 776*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) == DDI_SUCCESS) { 777*0Sstevel@tonic-gate *typesp |= DDI_INTR_TYPE_MSIX; 778*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 779*0Sstevel@tonic-gate } 780*0Sstevel@tonic-gate 781*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msi_get_supported_type: " 782*0Sstevel@tonic-gate "rdip = 0x%p types 0x%x\n", (void *)rdip, *typesp)); 783*0Sstevel@tonic-gate 784*0Sstevel@tonic-gate return (*typesp == 0 ? DDI_FAILURE : DDI_SUCCESS); 785*0Sstevel@tonic-gate } 786*0Sstevel@tonic-gate 787*0Sstevel@tonic-gate 788*0Sstevel@tonic-gate /* 789*0Sstevel@tonic-gate * pci_msix_init: 790*0Sstevel@tonic-gate * This function initializes the various handles/addrs etc. 791*0Sstevel@tonic-gate * needed for MSI-X support. It also allocates a private 792*0Sstevel@tonic-gate * structure to keep track of these. 793*0Sstevel@tonic-gate */ 794*0Sstevel@tonic-gate ddi_intr_msix_t * 795*0Sstevel@tonic-gate pci_msix_init(dev_info_t *rdip) 796*0Sstevel@tonic-gate { 797*0Sstevel@tonic-gate uint_t rnumber; 798*0Sstevel@tonic-gate size_t msix_tbl_size; 799*0Sstevel@tonic-gate size_t pba_tbl_size; 800*0Sstevel@tonic-gate ushort_t caps_ptr, msi_ctrl; 801*0Sstevel@tonic-gate ddi_intr_msix_t *msix_p; 802*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdle; 803*0Sstevel@tonic-gate 804*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msix_init: rdip = %p\n", (void *)rdip)); 805*0Sstevel@tonic-gate 806*0Sstevel@tonic-gate if (pci_get_msi_ctrl(rdip, DDI_INTR_TYPE_MSI, &msi_ctrl, 807*0Sstevel@tonic-gate &caps_ptr, &cfg_hdle) != DDI_SUCCESS) 808*0Sstevel@tonic-gate return (NULL); 809*0Sstevel@tonic-gate 810*0Sstevel@tonic-gate msix_p = kmem_zalloc(sizeof (ddi_intr_msix_t), KM_SLEEP); 811*0Sstevel@tonic-gate 812*0Sstevel@tonic-gate /* 813*0Sstevel@tonic-gate * Initialize the devacc structure 814*0Sstevel@tonic-gate */ 815*0Sstevel@tonic-gate msix_p->msix_dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 816*0Sstevel@tonic-gate msix_p->msix_dev_attr.devacc_attr_endian_flags = 817*0Sstevel@tonic-gate DDI_STRUCTURE_LE_ACC; 818*0Sstevel@tonic-gate msix_p->msix_dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 819*0Sstevel@tonic-gate 820*0Sstevel@tonic-gate /* 821*0Sstevel@tonic-gate * Map the entire MSI-X vector table 822*0Sstevel@tonic-gate */ 823*0Sstevel@tonic-gate msix_p->msix_tbl_offset = pci_config_get32(cfg_hdle, 824*0Sstevel@tonic-gate caps_ptr + PCI_MSIX_TBL_OFFSET); 825*0Sstevel@tonic-gate rnumber = msix_p->msix_tbl_offset & PCI_MSIX_TBL_BIR_MASK; 826*0Sstevel@tonic-gate msix_p->msix_tbl_offset &= ~rnumber; /* Clear BIR from the offset */ 827*0Sstevel@tonic-gate 828*0Sstevel@tonic-gate msix_tbl_size = (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK) + 1; 829*0Sstevel@tonic-gate 830*0Sstevel@tonic-gate if (ddi_regs_map_setup(rdip, 831*0Sstevel@tonic-gate rnumber, 832*0Sstevel@tonic-gate &msix_p->msix_tbl_addr, 833*0Sstevel@tonic-gate msix_p->msix_tbl_offset, 834*0Sstevel@tonic-gate msix_tbl_size, 835*0Sstevel@tonic-gate &msix_p->msix_dev_attr, 836*0Sstevel@tonic-gate &msix_p->msix_tbl_hdl) != 837*0Sstevel@tonic-gate DDI_SUCCESS) { 838*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msix_initialize: MSI-X Table " 839*0Sstevel@tonic-gate "ddi_regs_map_setup failed\n")); 840*0Sstevel@tonic-gate kmem_free(msix_p, sizeof (ddi_intr_msix_t)); 841*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 842*0Sstevel@tonic-gate return (NULL); 843*0Sstevel@tonic-gate } 844*0Sstevel@tonic-gate 845*0Sstevel@tonic-gate /* 846*0Sstevel@tonic-gate * Map in the MSI-X Pending Bit Array 847*0Sstevel@tonic-gate */ 848*0Sstevel@tonic-gate if (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK) 849*0Sstevel@tonic-gate pba_tbl_size = ((msi_ctrl & PCI_MSIX_TBL_SIZE_MASK) + 1)/64; 850*0Sstevel@tonic-gate 851*0Sstevel@tonic-gate msix_p->msix_pba_offset = pci_config_get32(cfg_hdle, 852*0Sstevel@tonic-gate caps_ptr + PCI_MSIX_PBA_OFFSET); 853*0Sstevel@tonic-gate rnumber = msix_p->msix_pba_offset & PCI_MSIX_PBA_BIR_MASK; 854*0Sstevel@tonic-gate msix_p->msix_pba_offset &= ~rnumber; /* Clear offset from BIR */ 855*0Sstevel@tonic-gate 856*0Sstevel@tonic-gate if (ddi_regs_map_setup(rdip, 857*0Sstevel@tonic-gate rnumber, 858*0Sstevel@tonic-gate &msix_p->msix_pba_addr, 859*0Sstevel@tonic-gate msix_p->msix_pba_offset, 860*0Sstevel@tonic-gate pba_tbl_size, 861*0Sstevel@tonic-gate &msix_p->msix_dev_attr, 862*0Sstevel@tonic-gate &msix_p->msix_pba_hdl) != DDI_SUCCESS) { 863*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msix_initialize: PBA " 864*0Sstevel@tonic-gate "ddi_regs_map_setup failed\n")); 865*0Sstevel@tonic-gate ddi_regs_map_free(&msix_p->msix_tbl_hdl); 866*0Sstevel@tonic-gate kmem_free(msix_p, sizeof (ddi_intr_msix_t)); 867*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 868*0Sstevel@tonic-gate return (NULL); 869*0Sstevel@tonic-gate } 870*0Sstevel@tonic-gate 871*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msix_init: msix_p = 0x%p DONE!!\n", 872*0Sstevel@tonic-gate (void *)msix_p)); 873*0Sstevel@tonic-gate 874*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdle); 875*0Sstevel@tonic-gate return (msix_p); 876*0Sstevel@tonic-gate } 877*0Sstevel@tonic-gate 878*0Sstevel@tonic-gate 879*0Sstevel@tonic-gate /* 880*0Sstevel@tonic-gate * pci_msix_fini: 881*0Sstevel@tonic-gate * This function cleans up previously allocated handles/addrs etc. 882*0Sstevel@tonic-gate * It is only called if no more MSI-X interrupts are being used. 883*0Sstevel@tonic-gate */ 884*0Sstevel@tonic-gate void 885*0Sstevel@tonic-gate pci_msix_fini(ddi_intr_msix_t *msix_p) 886*0Sstevel@tonic-gate { 887*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_msix_fini: msix_p = 0x%p\n", 888*0Sstevel@tonic-gate (void *)msix_p)); 889*0Sstevel@tonic-gate 890*0Sstevel@tonic-gate ddi_regs_map_free(&msix_p->msix_pba_hdl); 891*0Sstevel@tonic-gate ddi_regs_map_free(&msix_p->msix_tbl_hdl); 892*0Sstevel@tonic-gate kmem_free(msix_p, sizeof (ddi_intr_msix_t)); 893*0Sstevel@tonic-gate } 894*0Sstevel@tonic-gate 895*0Sstevel@tonic-gate 896*0Sstevel@tonic-gate 897*0Sstevel@tonic-gate /* 898*0Sstevel@tonic-gate * Next set of routines are for INTx (legacy) PCI interrupt 899*0Sstevel@tonic-gate * support only. 900*0Sstevel@tonic-gate */ 901*0Sstevel@tonic-gate 902*0Sstevel@tonic-gate /* 903*0Sstevel@tonic-gate * pci_intx_get_cap: 904*0Sstevel@tonic-gate * For non-MSI devices that comply to PCI v2.3 or greater; 905*0Sstevel@tonic-gate * read the command register. Bit 10 implies interrupt disable. 906*0Sstevel@tonic-gate * Set this bit and then read the status register bit 3. 907*0Sstevel@tonic-gate * Bit 3 of status register is Interrupt state. 908*0Sstevel@tonic-gate * If it is set; then the device supports 'Masking' 909*0Sstevel@tonic-gate * 910*0Sstevel@tonic-gate * Reset the device back to the original state. 911*0Sstevel@tonic-gate */ 912*0Sstevel@tonic-gate int 913*0Sstevel@tonic-gate pci_intx_get_cap(dev_info_t *dip, int *flagsp) 914*0Sstevel@tonic-gate { 915*0Sstevel@tonic-gate uint16_t cmdreg, savereg; 916*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl; 917*0Sstevel@tonic-gate #ifdef DEBUG 918*0Sstevel@tonic-gate uint16_t statreg; 919*0Sstevel@tonic-gate #endif /* DEBUG */ 920*0Sstevel@tonic-gate 921*0Sstevel@tonic-gate *flagsp = 0; 922*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: %s%d: called\n", 923*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 924*0Sstevel@tonic-gate 925*0Sstevel@tonic-gate if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { 926*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: can't get " 927*0Sstevel@tonic-gate "config handle\n")); 928*0Sstevel@tonic-gate return (DDI_FAILURE); 929*0Sstevel@tonic-gate } 930*0Sstevel@tonic-gate 931*0Sstevel@tonic-gate savereg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); 932*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: " 933*0Sstevel@tonic-gate "command register was 0x%x\n", savereg)); 934*0Sstevel@tonic-gate 935*0Sstevel@tonic-gate /* Disable the interrupts */ 936*0Sstevel@tonic-gate cmdreg = savereg | PCI_COMM_INTX_DISABLE; 937*0Sstevel@tonic-gate pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); 938*0Sstevel@tonic-gate 939*0Sstevel@tonic-gate #ifdef DEBUG 940*0Sstevel@tonic-gate statreg = pci_config_get16(cfg_hdl, PCI_CONF_STAT); 941*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: " 942*0Sstevel@tonic-gate "status register is 0x%x\n", statreg)); 943*0Sstevel@tonic-gate #endif /* DEBUG */ 944*0Sstevel@tonic-gate 945*0Sstevel@tonic-gate /* Read the bit back */ 946*0Sstevel@tonic-gate cmdreg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); 947*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: " 948*0Sstevel@tonic-gate "command register is now 0x%x\n", cmdreg)); 949*0Sstevel@tonic-gate 950*0Sstevel@tonic-gate if (cmdreg & PCI_COMM_INTX_DISABLE) { 951*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_cap: " 952*0Sstevel@tonic-gate "masking supported\n")); 953*0Sstevel@tonic-gate *flagsp = (DDI_INTR_FLAG_MASKABLE | 954*0Sstevel@tonic-gate DDI_INTR_FLAG_PENDING | DDI_INTR_FLAG_LEVEL); 955*0Sstevel@tonic-gate } 956*0Sstevel@tonic-gate 957*0Sstevel@tonic-gate /* Restore the device back to the original state and return */ 958*0Sstevel@tonic-gate pci_config_put16(cfg_hdl, PCI_CONF_COMM, savereg); 959*0Sstevel@tonic-gate 960*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdl); 961*0Sstevel@tonic-gate return (DDI_SUCCESS); 962*0Sstevel@tonic-gate } 963*0Sstevel@tonic-gate 964*0Sstevel@tonic-gate 965*0Sstevel@tonic-gate /* 966*0Sstevel@tonic-gate * pci_intx_clr_mask: 967*0Sstevel@tonic-gate * For non-MSI devices that comply to PCI v2.3 or greater; 968*0Sstevel@tonic-gate * clear the bit10 in the command register. 969*0Sstevel@tonic-gate */ 970*0Sstevel@tonic-gate int 971*0Sstevel@tonic-gate pci_intx_clr_mask(dev_info_t *dip) 972*0Sstevel@tonic-gate { 973*0Sstevel@tonic-gate uint16_t cmdreg; 974*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl; 975*0Sstevel@tonic-gate 976*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_clr_mask: %s%d: called\n", 977*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 978*0Sstevel@tonic-gate 979*0Sstevel@tonic-gate if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { 980*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_clr_mask: can't get " 981*0Sstevel@tonic-gate "config handle\n")); 982*0Sstevel@tonic-gate return (DDI_FAILURE); 983*0Sstevel@tonic-gate } 984*0Sstevel@tonic-gate 985*0Sstevel@tonic-gate cmdreg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); 986*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_clr_mask: " 987*0Sstevel@tonic-gate "command register was 0x%x\n", cmdreg)); 988*0Sstevel@tonic-gate 989*0Sstevel@tonic-gate /* Enable the interrupts */ 990*0Sstevel@tonic-gate cmdreg &= ~PCI_COMM_INTX_DISABLE; 991*0Sstevel@tonic-gate pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); 992*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdl); 993*0Sstevel@tonic-gate return (DDI_SUCCESS); 994*0Sstevel@tonic-gate } 995*0Sstevel@tonic-gate 996*0Sstevel@tonic-gate 997*0Sstevel@tonic-gate /* 998*0Sstevel@tonic-gate * pci_intx_set_mask: 999*0Sstevel@tonic-gate * For non-MSI devices that comply to PCI v2.3 or greater; 1000*0Sstevel@tonic-gate * set the bit10 in the command register. 1001*0Sstevel@tonic-gate */ 1002*0Sstevel@tonic-gate int 1003*0Sstevel@tonic-gate pci_intx_set_mask(dev_info_t *dip) 1004*0Sstevel@tonic-gate { 1005*0Sstevel@tonic-gate uint16_t cmdreg; 1006*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl; 1007*0Sstevel@tonic-gate 1008*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_set_mask: %s%d: called\n", 1009*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 1010*0Sstevel@tonic-gate 1011*0Sstevel@tonic-gate if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { 1012*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_set_mask: can't get " 1013*0Sstevel@tonic-gate "config handle\n")); 1014*0Sstevel@tonic-gate return (DDI_FAILURE); 1015*0Sstevel@tonic-gate } 1016*0Sstevel@tonic-gate 1017*0Sstevel@tonic-gate cmdreg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); 1018*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_set_mask: " 1019*0Sstevel@tonic-gate "command register was 0x%x\n", cmdreg)); 1020*0Sstevel@tonic-gate 1021*0Sstevel@tonic-gate /* Disable the interrupts */ 1022*0Sstevel@tonic-gate cmdreg |= PCI_COMM_INTX_DISABLE; 1023*0Sstevel@tonic-gate pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); 1024*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdl); 1025*0Sstevel@tonic-gate return (DDI_SUCCESS); 1026*0Sstevel@tonic-gate } 1027*0Sstevel@tonic-gate 1028*0Sstevel@tonic-gate /* 1029*0Sstevel@tonic-gate * pci_intx_get_pending: 1030*0Sstevel@tonic-gate * For non-MSI devices that comply to PCI v2.3 or greater; 1031*0Sstevel@tonic-gate * read the status register. Bit 3 of status register is 1032*0Sstevel@tonic-gate * Interrupt state. If it is set; then the interrupt is 1033*0Sstevel@tonic-gate * 'Pending'. 1034*0Sstevel@tonic-gate */ 1035*0Sstevel@tonic-gate int 1036*0Sstevel@tonic-gate pci_intx_get_pending(dev_info_t *dip, int *pendingp) 1037*0Sstevel@tonic-gate { 1038*0Sstevel@tonic-gate uint16_t statreg; 1039*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl; 1040*0Sstevel@tonic-gate 1041*0Sstevel@tonic-gate *pendingp = 0; 1042*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_pending: %s%d: called\n", 1043*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 1044*0Sstevel@tonic-gate 1045*0Sstevel@tonic-gate if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { 1046*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_pending: can't get " 1047*0Sstevel@tonic-gate "config handle\n")); 1048*0Sstevel@tonic-gate return (DDI_FAILURE); 1049*0Sstevel@tonic-gate } 1050*0Sstevel@tonic-gate 1051*0Sstevel@tonic-gate statreg = pci_config_get16(cfg_hdl, PCI_CONF_STAT); 1052*0Sstevel@tonic-gate 1053*0Sstevel@tonic-gate if (statreg & PCI_STAT_INTR) { 1054*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_pending: " 1055*0Sstevel@tonic-gate "interrupt is pending\n")); 1056*0Sstevel@tonic-gate *pendingp = 1; 1057*0Sstevel@tonic-gate } 1058*0Sstevel@tonic-gate 1059*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdl); 1060*0Sstevel@tonic-gate return (DDI_SUCCESS); 1061*0Sstevel@tonic-gate } 1062*0Sstevel@tonic-gate 1063*0Sstevel@tonic-gate 1064*0Sstevel@tonic-gate /* 1065*0Sstevel@tonic-gate * pci_devclass_to_ipl: 1066*0Sstevel@tonic-gate * translate from device class to ipl 1067*0Sstevel@tonic-gate * NOTE: This function is added here as pci_intx_get_ispec() 1068*0Sstevel@tonic-gate * calls this to figure out the priority. 1069*0Sstevel@tonic-gate * It is moved over from x86 pci.c 1070*0Sstevel@tonic-gate */ 1071*0Sstevel@tonic-gate int 1072*0Sstevel@tonic-gate pci_devclass_to_ipl(int class) 1073*0Sstevel@tonic-gate { 1074*0Sstevel@tonic-gate int base_cl; 1075*0Sstevel@tonic-gate int ipl; 1076*0Sstevel@tonic-gate 1077*0Sstevel@tonic-gate base_cl = (class & 0xff0000) >> 16; 1078*0Sstevel@tonic-gate 1079*0Sstevel@tonic-gate /* 1080*0Sstevel@tonic-gate * Use the class code values to construct an ipl for the device. 1081*0Sstevel@tonic-gate */ 1082*0Sstevel@tonic-gate switch (base_cl) { 1083*0Sstevel@tonic-gate default: 1084*0Sstevel@tonic-gate case PCI_CLASS_NONE: 1085*0Sstevel@tonic-gate ipl = 1; 1086*0Sstevel@tonic-gate break; 1087*0Sstevel@tonic-gate case PCI_CLASS_MASS: 1088*0Sstevel@tonic-gate ipl = 0x5; 1089*0Sstevel@tonic-gate break; 1090*0Sstevel@tonic-gate case PCI_CLASS_NET: 1091*0Sstevel@tonic-gate ipl = 0x6; 1092*0Sstevel@tonic-gate break; 1093*0Sstevel@tonic-gate case PCI_CLASS_DISPLAY: 1094*0Sstevel@tonic-gate ipl = 0x9; 1095*0Sstevel@tonic-gate break; 1096*0Sstevel@tonic-gate /* 1097*0Sstevel@tonic-gate * for high priority interrupt handlers, use level 12 1098*0Sstevel@tonic-gate * as the highest for device drivers 1099*0Sstevel@tonic-gate */ 1100*0Sstevel@tonic-gate case PCI_CLASS_MM: 1101*0Sstevel@tonic-gate ipl = 0xc; 1102*0Sstevel@tonic-gate break; 1103*0Sstevel@tonic-gate case PCI_CLASS_MEM: 1104*0Sstevel@tonic-gate ipl = 0xc; 1105*0Sstevel@tonic-gate break; 1106*0Sstevel@tonic-gate case PCI_CLASS_BRIDGE: 1107*0Sstevel@tonic-gate ipl = 0xc; 1108*0Sstevel@tonic-gate break; 1109*0Sstevel@tonic-gate } 1110*0Sstevel@tonic-gate return (ipl); 1111*0Sstevel@tonic-gate } 1112*0Sstevel@tonic-gate 1113*0Sstevel@tonic-gate 1114*0Sstevel@tonic-gate /* 1115*0Sstevel@tonic-gate * pci_intx_get_ispec: 1116*0Sstevel@tonic-gate * Get intrspec for PCI devices (legacy support) 1117*0Sstevel@tonic-gate * NOTE: This is moved here from x86 pci.c and is 1118*0Sstevel@tonic-gate * needed here as pci-ide.c uses it as well 1119*0Sstevel@tonic-gate */ 1120*0Sstevel@tonic-gate /*ARGSUSED*/ 1121*0Sstevel@tonic-gate ddi_intrspec_t 1122*0Sstevel@tonic-gate pci_intx_get_ispec(dev_info_t *dip, dev_info_t *rdip, int inum) 1123*0Sstevel@tonic-gate { 1124*0Sstevel@tonic-gate int class, *intpriorities; 1125*0Sstevel@tonic-gate uint_t num_intpriorities; 1126*0Sstevel@tonic-gate struct intrspec *ispec; 1127*0Sstevel@tonic-gate ddi_acc_handle_t cfg_hdl; 1128*0Sstevel@tonic-gate struct ddi_parent_private_data *pdptr; 1129*0Sstevel@tonic-gate 1130*0Sstevel@tonic-gate if ((pdptr = ddi_get_parent_data(rdip)) == NULL) 1131*0Sstevel@tonic-gate return (NULL); 1132*0Sstevel@tonic-gate 1133*0Sstevel@tonic-gate ispec = pdptr->par_intr; 1134*0Sstevel@tonic-gate ASSERT(ispec); 1135*0Sstevel@tonic-gate 1136*0Sstevel@tonic-gate /* check if the intrspec_pri has been initialized */ 1137*0Sstevel@tonic-gate if (!ispec->intrspec_pri) { 1138*0Sstevel@tonic-gate if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, rdip, 1139*0Sstevel@tonic-gate DDI_PROP_DONTPASS, "interrupt-priorities", 1140*0Sstevel@tonic-gate &intpriorities, &num_intpriorities) == DDI_PROP_SUCCESS) { 1141*0Sstevel@tonic-gate if (inum < num_intpriorities) 1142*0Sstevel@tonic-gate ispec->intrspec_pri = intpriorities[inum]; 1143*0Sstevel@tonic-gate ddi_prop_free(intpriorities); 1144*0Sstevel@tonic-gate } 1145*0Sstevel@tonic-gate 1146*0Sstevel@tonic-gate /* If still no priority, guess based on the class code */ 1147*0Sstevel@tonic-gate if (ispec->intrspec_pri == 0) { 1148*0Sstevel@tonic-gate /* get 'class' property to derive the intr priority */ 1149*0Sstevel@tonic-gate class = ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 1150*0Sstevel@tonic-gate DDI_PROP_DONTPASS, "class-code", -1); 1151*0Sstevel@tonic-gate ispec->intrspec_pri = (class == -1) ? 1 : 1152*0Sstevel@tonic-gate pci_devclass_to_ipl(class); 1153*0Sstevel@tonic-gate } 1154*0Sstevel@tonic-gate } 1155*0Sstevel@tonic-gate 1156*0Sstevel@tonic-gate /* Get interrupt line value */ 1157*0Sstevel@tonic-gate if (!ispec->intrspec_vec) { 1158*0Sstevel@tonic-gate if (pci_config_setup(rdip, &cfg_hdl) != DDI_SUCCESS) { 1159*0Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, "pci_intx_get_iline: " 1160*0Sstevel@tonic-gate "can't get config handle\n")); 1161*0Sstevel@tonic-gate return (NULL); 1162*0Sstevel@tonic-gate } 1163*0Sstevel@tonic-gate 1164*0Sstevel@tonic-gate ispec->intrspec_vec = pci_config_get8(cfg_hdl, PCI_CONF_ILINE); 1165*0Sstevel@tonic-gate pci_config_teardown(&cfg_hdl); 1166*0Sstevel@tonic-gate } 1167*0Sstevel@tonic-gate 1168*0Sstevel@tonic-gate return ((ddi_intrspec_t)ispec); 1169*0Sstevel@tonic-gate } 1170