xref: /onnv-gate/usr/src/uts/common/io/nxge/nxge_classify.c (revision 3859:19804e7fd496)
1*3859Sml29623 /*
2*3859Sml29623  * CDDL HEADER START
3*3859Sml29623  *
4*3859Sml29623  * The contents of this file are subject to the terms of the
5*3859Sml29623  * Common Development and Distribution License (the "License").
6*3859Sml29623  * You may not use this file except in compliance with the License.
7*3859Sml29623  *
8*3859Sml29623  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*3859Sml29623  * or http://www.opensolaris.org/os/licensing.
10*3859Sml29623  * See the License for the specific language governing permissions
11*3859Sml29623  * and limitations under the License.
12*3859Sml29623  *
13*3859Sml29623  * When distributing Covered Code, include this CDDL HEADER in each
14*3859Sml29623  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*3859Sml29623  * If applicable, add the following below this CDDL HEADER, with the
16*3859Sml29623  * fields enclosed by brackets "[]" replaced with your own identifying
17*3859Sml29623  * information: Portions Copyright [yyyy] [name of copyright owner]
18*3859Sml29623  *
19*3859Sml29623  * CDDL HEADER END
20*3859Sml29623  */
21*3859Sml29623 /*
22*3859Sml29623  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23*3859Sml29623  * Use is subject to license terms.
24*3859Sml29623  */
25*3859Sml29623 
26*3859Sml29623 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27*3859Sml29623 
28*3859Sml29623 #include <npi_fflp.h>
29*3859Sml29623 #include <nxge_defs.h>
30*3859Sml29623 #include <nxge_fflp.h>
31*3859Sml29623 #include <nxge_flow.h>
32*3859Sml29623 #include <nxge_impl.h>
33*3859Sml29623 #include <nxge_common.h>
34*3859Sml29623 
35*3859Sml29623 /*
36*3859Sml29623  * Globals: tunable parameters (/etc/system or adb)
37*3859Sml29623  *
38*3859Sml29623  */
39*3859Sml29623 int nxge_tcam_class_enable = 0;
40*3859Sml29623 int nxge_tcam_lookup_enable = 0;
41*3859Sml29623 int nxge_flow_dist_enable = NXGE_CLASS_FLOW_USE_DST_PORT |
42*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
43*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
44*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
45*3859Sml29623 
46*3859Sml29623 /*
47*3859Sml29623  * Bit mapped
48*3859Sml29623  * 0x80000000:      Drop
49*3859Sml29623  * 0x0000:      NO TCAM Lookup Needed
50*3859Sml29623  * 0x0001:      TCAM Lookup Needed with Dest Addr (IPv6)
51*3859Sml29623  * 0x0003:      TCAM Lookup Needed with SRC Addr (IPv6)
52*3859Sml29623  * 0x0010:      use MAC Port
53*3859Sml29623  * 0x0020:      use L2DA
54*3859Sml29623  * 0x0040:      use VLAN
55*3859Sml29623  * 0x0080:      use proto
56*3859Sml29623  * 0x0100:      use IP src addr
57*3859Sml29623  * 0x0200:      use IP dest addr
58*3859Sml29623  * 0x0400:      use Src Port
59*3859Sml29623  * 0x0800:      use Dest Port
60*3859Sml29623  * 0x0fff:      enable all options for IPv6 (with src addr)
61*3859Sml29623  * 0x0ffd:      enable all options for IPv6 (with dest addr)
62*3859Sml29623  * 0x0fff:      enable all options for IPv4
63*3859Sml29623  * 0x0ffd:      enable all options for IPv4
64*3859Sml29623  *
65*3859Sml29623  */
66*3859Sml29623 
67*3859Sml29623 /*
68*3859Sml29623  * the default is to distribute as function of:
69*3859Sml29623  * protocol
70*3859Sml29623  * ip src address
71*3859Sml29623  * ip dest address
72*3859Sml29623  * src port
73*3859Sml29623  * dest port
74*3859Sml29623  *
75*3859Sml29623  * 0x0f80
76*3859Sml29623  *
77*3859Sml29623  */
78*3859Sml29623 
79*3859Sml29623 int nxge_tcp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
80*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
81*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
82*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
83*3859Sml29623 
84*3859Sml29623 int nxge_udp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
85*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
86*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
87*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
88*3859Sml29623 
89*3859Sml29623 int nxge_ah4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
90*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
91*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
92*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
93*3859Sml29623 int nxge_sctp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
94*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
95*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
96*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
97*3859Sml29623 
98*3859Sml29623 int nxge_tcp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
99*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
100*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
101*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
102*3859Sml29623 
103*3859Sml29623 int nxge_udp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
104*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
105*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
106*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
107*3859Sml29623 
108*3859Sml29623 int nxge_ah6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
109*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
110*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
111*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
112*3859Sml29623 
113*3859Sml29623 int nxge_sctp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
114*3859Sml29623 	NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
115*3859Sml29623 	NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
116*3859Sml29623 	NXGE_CLASS_FLOW_USE_PORTNUM;
117*3859Sml29623 
118*3859Sml29623 uint32_t nxge_fflp_init_h1 = 0xffffffff;
119*3859Sml29623 uint32_t nxge_fflp_init_h2 = 0xffff;
120*3859Sml29623 
121*3859Sml29623 uint64_t class_quick_config_distribute[NXGE_CLASS_CONFIG_PARAMS] = {
122*3859Sml29623 	0xffffffffULL,		/* h1_init */
123*3859Sml29623 	0xffffULL,		/* h2_init */
124*3859Sml29623 	0x0,			/* cfg_ether_usr1 */
125*3859Sml29623 	0x0,			/* cfg_ether_usr2 */
126*3859Sml29623 	0x0,			/* cfg_ip_usr4 */
127*3859Sml29623 	0x0,			/* cfg_ip_usr5 */
128*3859Sml29623 	0x0,			/* cfg_ip_usr6 */
129*3859Sml29623 	0x0,			/* cfg_ip_usr7 */
130*3859Sml29623 	0x0,			/* opt_ip_usr4 */
131*3859Sml29623 	0x0,			/* opt_ip_usr5 */
132*3859Sml29623 	0x0,			/* opt_ip_usr6 */
133*3859Sml29623 	0x0,			/* opt_ip_usr7 */
134*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_tcp */
135*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_udp */
136*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_ah */
137*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_sctp */
138*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_tcp */
139*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_udp */
140*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_ah */
141*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER	/* opt_ipv6_sctp */
142*3859Sml29623 };
143*3859Sml29623 
144*3859Sml29623 uint64_t class_quick_config_web_server[NXGE_CLASS_CONFIG_PARAMS] = {
145*3859Sml29623 	0xffffffffULL,		/* h1_init */
146*3859Sml29623 	0xffffULL,		/* h2_init */
147*3859Sml29623 	0x0,			/* cfg_ether_usr1 */
148*3859Sml29623 	0x0,			/* cfg_ether_usr2 */
149*3859Sml29623 	0x0,			/* cfg_ip_usr4 */
150*3859Sml29623 	0x0,			/* cfg_ip_usr5 */
151*3859Sml29623 	0x0,			/* cfg_ip_usr6 */
152*3859Sml29623 	0x0,			/* cfg_ip_usr7 */
153*3859Sml29623 	0x0,			/* opt_ip_usr4 */
154*3859Sml29623 	0x0,			/* opt_ip_usr5 */
155*3859Sml29623 	0x0,			/* opt_ip_usr6 */
156*3859Sml29623 	0x0,			/* opt_ip_usr7 */
157*3859Sml29623 	NXGE_CLASS_FLOW_WEB_SERVER,	/* opt_ipv4_tcp */
158*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_udp */
159*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_ah */
160*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv4_sctp */
161*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_tcp */
162*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_udp */
163*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER,	/* opt_ipv6_ah */
164*3859Sml29623 	NXGE_CLASS_FLOW_GEN_SERVER	/* opt_ipv6_sctp */
165*3859Sml29623 };
166*3859Sml29623 
167*3859Sml29623 nxge_status_t
nxge_classify_init(p_nxge_t nxgep)168*3859Sml29623 nxge_classify_init(p_nxge_t nxgep)
169*3859Sml29623 {
170*3859Sml29623 	nxge_status_t status = NXGE_OK;
171*3859Sml29623 
172*3859Sml29623 	status = nxge_classify_init_sw(nxgep);
173*3859Sml29623 	if (status != NXGE_OK)
174*3859Sml29623 		return (status);
175*3859Sml29623 	status = nxge_set_hw_classify_config(nxgep);
176*3859Sml29623 	if (status != NXGE_OK)
177*3859Sml29623 		return (status);
178*3859Sml29623 
179*3859Sml29623 	status = nxge_classify_init_hw(nxgep);
180*3859Sml29623 	if (status != NXGE_OK)
181*3859Sml29623 		return (status);
182*3859Sml29623 
183*3859Sml29623 	return (NXGE_OK);
184*3859Sml29623 }
185*3859Sml29623 
186*3859Sml29623 nxge_status_t
nxge_classify_uninit(p_nxge_t nxgep)187*3859Sml29623 nxge_classify_uninit(p_nxge_t nxgep)
188*3859Sml29623 {
189*3859Sml29623 	nxge_status_t status = NXGE_OK;
190*3859Sml29623 
191*3859Sml29623 	status = nxge_classify_exit_sw(nxgep);
192*3859Sml29623 	if (status != NXGE_OK) {
193*3859Sml29623 		return (status);
194*3859Sml29623 	}
195*3859Sml29623 	return (NXGE_OK);
196*3859Sml29623 }
197*3859Sml29623 
198*3859Sml29623 /* ARGSUSED */
199*3859Sml29623 uint64_t
nxge_classify_get_cfg_value(p_nxge_t nxgep,uint8_t cfg_type,uint8_t cfg_param)200*3859Sml29623 nxge_classify_get_cfg_value(p_nxge_t nxgep, uint8_t cfg_type, uint8_t cfg_param)
201*3859Sml29623 {
202*3859Sml29623 	uint64_t cfg_value;
203*3859Sml29623 
204*3859Sml29623 	if (cfg_param >= NXGE_CLASS_CONFIG_PARAMS)
205*3859Sml29623 		return (-1);
206*3859Sml29623 	switch (cfg_type) {
207*3859Sml29623 	case CFG_L3_WEB:
208*3859Sml29623 		cfg_value = class_quick_config_web_server[cfg_param];
209*3859Sml29623 		break;
210*3859Sml29623 	case CFG_L3_DISTRIBUTE:
211*3859Sml29623 	default:
212*3859Sml29623 		cfg_value = class_quick_config_distribute[cfg_param];
213*3859Sml29623 		break;
214*3859Sml29623 	}
215*3859Sml29623 	return (cfg_value);
216*3859Sml29623 }
217*3859Sml29623 
218*3859Sml29623 nxge_status_t
nxge_set_hw_classify_config(p_nxge_t nxgep)219*3859Sml29623 nxge_set_hw_classify_config(p_nxge_t nxgep)
220*3859Sml29623 {
221*3859Sml29623 	p_nxge_dma_pt_cfg_t p_all_cfgp;
222*3859Sml29623 	p_nxge_hw_pt_cfg_t p_cfgp;
223*3859Sml29623 
224*3859Sml29623 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_get_hw_classify_config"));
225*3859Sml29623 
226*3859Sml29623 	/* Get mac rdc table info from HW/Prom/.conf etc ...... */
227*3859Sml29623 	/* for now, get it from dma configs */
228*3859Sml29623 	p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
229*3859Sml29623 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
230*3859Sml29623 
231*3859Sml29623 	/*
232*3859Sml29623 	 * classify_init needs to call first.
233*3859Sml29623 	 */
234*3859Sml29623 	nxgep->class_config.mac_rdcgrp = p_cfgp->def_mac_rxdma_grpid;
235*3859Sml29623 	nxgep->class_config.mcast_rdcgrp = p_cfgp->def_mac_rxdma_grpid;
236*3859Sml29623 	NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_get_hw_classify_config"));
237*3859Sml29623 
238*3859Sml29623 	return (NXGE_OK);
239*3859Sml29623 }
240