1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_api.h" 32 #include "igb_nvm.h" 33 34 /* 35 * e1000_raise_eec_clk - Raise EEPROM clock 36 * @hw: pointer to the HW structure 37 * @eecd: pointer to the EEPROM 38 * 39 * Enable/Raise the EEPROM clock bit. 40 */ 41 static void 42 e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 43 { 44 *eecd = *eecd | E1000_EECD_SK; 45 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 46 E1000_WRITE_FLUSH(hw); 47 usec_delay(hw->nvm.delay_usec); 48 } 49 50 /* 51 * e1000_lower_eec_clk - Lower EEPROM clock 52 * @hw: pointer to the HW structure 53 * @eecd: pointer to the EEPROM 54 * 55 * Clear/Lower the EEPROM clock bit. 56 */ 57 static void 58 e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 59 { 60 *eecd = *eecd & ~E1000_EECD_SK; 61 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 62 E1000_WRITE_FLUSH(hw); 63 usec_delay(hw->nvm.delay_usec); 64 } 65 66 /* 67 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 68 * @hw: pointer to the HW structure 69 * @data: data to send to the EEPROM 70 * @count: number of bits to shift out 71 * 72 * We need to shift 'count' bits out to the EEPROM. So, the value in the 73 * "data" parameter will be shifted out to the EEPROM one bit at a time. 74 * In order to do this, "data" must be broken down into bits. 75 */ 76 static void 77 e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 78 { 79 struct e1000_nvm_info *nvm = &hw->nvm; 80 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 81 u32 mask; 82 83 DEBUGFUNC("e1000_shift_out_eec_bits"); 84 85 mask = 0x01 << (count - 1); 86 if (nvm->type == e1000_nvm_eeprom_microwire) 87 eecd &= ~E1000_EECD_DO; 88 else if (nvm->type == e1000_nvm_eeprom_spi) 89 eecd |= E1000_EECD_DO; 90 91 do { 92 eecd &= ~E1000_EECD_DI; 93 94 if (data & mask) 95 eecd |= E1000_EECD_DI; 96 97 E1000_WRITE_REG(hw, E1000_EECD, eecd); 98 E1000_WRITE_FLUSH(hw); 99 100 usec_delay(nvm->delay_usec); 101 102 e1000_raise_eec_clk(hw, &eecd); 103 e1000_lower_eec_clk(hw, &eecd); 104 105 mask >>= 1; 106 } while (mask); 107 108 eecd &= ~E1000_EECD_DI; 109 E1000_WRITE_REG(hw, E1000_EECD, eecd); 110 } 111 112 /* 113 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 114 * @hw: pointer to the HW structure 115 * @count: number of bits to shift in 116 * 117 * In order to read a register from the EEPROM, we need to shift 'count' bits 118 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 119 * the EEPROM (setting the SK bit), and then reading the value of the data out 120 * "DO" bit. During this "shifting in" process the data in "DI" bit should 121 * always be clear. 122 */ 123 static u16 124 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 125 { 126 u32 eecd; 127 u32 i; 128 u16 data; 129 130 DEBUGFUNC("e1000_shift_in_eec_bits"); 131 132 eecd = E1000_READ_REG(hw, E1000_EECD); 133 134 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 135 data = 0; 136 137 for (i = 0; i < count; i++) { 138 data <<= 1; 139 e1000_raise_eec_clk(hw, &eecd); 140 141 eecd = E1000_READ_REG(hw, E1000_EECD); 142 143 eecd &= ~E1000_EECD_DI; 144 if (eecd & E1000_EECD_DO) 145 data |= 1; 146 147 e1000_lower_eec_clk(hw, &eecd); 148 } 149 150 return (data); 151 } 152 153 /* 154 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 155 * @hw: pointer to the HW structure 156 * @ee_reg: EEPROM flag for polling 157 * 158 * Polls the EEPROM status bit for either read or write completion based 159 * upon the value of 'ee_reg'. 160 */ 161 s32 162 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 163 { 164 u32 attempts = 100000; 165 u32 i, reg = 0; 166 s32 ret_val = -E1000_ERR_NVM; 167 168 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 169 170 for (i = 0; i < attempts; i++) { 171 if (ee_reg == E1000_NVM_POLL_READ) 172 reg = E1000_READ_REG(hw, E1000_EERD); 173 else 174 reg = E1000_READ_REG(hw, E1000_EEWR); 175 176 if (reg & E1000_NVM_RW_REG_DONE) { 177 ret_val = E1000_SUCCESS; 178 break; 179 } 180 181 usec_delay(5); 182 } 183 184 return (ret_val); 185 } 186 187 /* 188 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 189 * @hw: pointer to the HW structure 190 * 191 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 192 * Return successful if access grant bit set, else clear the request for 193 * EEPROM access and return -E1000_ERR_NVM (-1). 194 */ 195 s32 196 e1000_acquire_nvm_generic(struct e1000_hw *hw) 197 { 198 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 199 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 200 s32 ret_val = E1000_SUCCESS; 201 202 DEBUGFUNC("e1000_acquire_nvm_generic"); 203 204 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 205 eecd = E1000_READ_REG(hw, E1000_EECD); 206 207 while (timeout) { 208 if (eecd & E1000_EECD_GNT) 209 break; 210 usec_delay(5); 211 eecd = E1000_READ_REG(hw, E1000_EECD); 212 timeout--; 213 } 214 215 if (!timeout) { 216 eecd &= ~E1000_EECD_REQ; 217 E1000_WRITE_REG(hw, E1000_EECD, eecd); 218 DEBUGOUT("Could not acquire NVM grant\n"); 219 ret_val = -E1000_ERR_NVM; 220 } 221 222 return (ret_val); 223 } 224 225 /* 226 * e1000_standby_nvm - Return EEPROM to standby state 227 * @hw: pointer to the HW structure 228 * 229 * Return the EEPROM to a standby state. 230 */ 231 static void 232 e1000_standby_nvm(struct e1000_hw *hw) 233 { 234 struct e1000_nvm_info *nvm = &hw->nvm; 235 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 236 237 DEBUGFUNC("e1000_standby_nvm"); 238 239 if (nvm->type == e1000_nvm_eeprom_microwire) { 240 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 241 E1000_WRITE_REG(hw, E1000_EECD, eecd); 242 E1000_WRITE_FLUSH(hw); 243 usec_delay(nvm->delay_usec); 244 245 e1000_raise_eec_clk(hw, &eecd); 246 247 /* Select EEPROM */ 248 eecd |= E1000_EECD_CS; 249 E1000_WRITE_REG(hw, E1000_EECD, eecd); 250 E1000_WRITE_FLUSH(hw); 251 usec_delay(nvm->delay_usec); 252 253 e1000_lower_eec_clk(hw, &eecd); 254 } else if (nvm->type == e1000_nvm_eeprom_spi) { 255 /* Toggle CS to flush commands */ 256 eecd |= E1000_EECD_CS; 257 E1000_WRITE_REG(hw, E1000_EECD, eecd); 258 E1000_WRITE_FLUSH(hw); 259 usec_delay(nvm->delay_usec); 260 eecd &= ~E1000_EECD_CS; 261 E1000_WRITE_REG(hw, E1000_EECD, eecd); 262 E1000_WRITE_FLUSH(hw); 263 usec_delay(nvm->delay_usec); 264 } 265 } 266 267 /* 268 * e1000_stop_nvm - Terminate EEPROM command 269 * @hw: pointer to the HW structure 270 * 271 * Terminates the current command by inverting the EEPROM's chip select pin. 272 */ 273 void 274 e1000_stop_nvm(struct e1000_hw *hw) 275 { 276 u32 eecd; 277 278 DEBUGFUNC("e1000_stop_nvm"); 279 280 eecd = E1000_READ_REG(hw, E1000_EECD); 281 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 282 /* Pull CS high */ 283 eecd |= E1000_EECD_CS; 284 e1000_lower_eec_clk(hw, &eecd); 285 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 286 /* CS on Microcwire is active-high */ 287 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 288 E1000_WRITE_REG(hw, E1000_EECD, eecd); 289 e1000_raise_eec_clk(hw, &eecd); 290 e1000_lower_eec_clk(hw, &eecd); 291 } 292 } 293 294 /* 295 * e1000_release_nvm_generic - Release exclusive access to EEPROM 296 * @hw: pointer to the HW structure 297 * 298 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 299 */ 300 void 301 e1000_release_nvm_generic(struct e1000_hw *hw) 302 { 303 u32 eecd; 304 305 DEBUGFUNC("e1000_release_nvm_generic"); 306 307 e1000_stop_nvm(hw); 308 309 eecd = E1000_READ_REG(hw, E1000_EECD); 310 eecd &= ~E1000_EECD_REQ; 311 E1000_WRITE_REG(hw, E1000_EECD, eecd); 312 } 313 314 /* 315 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 316 * @hw: pointer to the HW structure 317 * 318 * Setups the EEPROM for reading and writing. 319 */ 320 static s32 321 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 322 { 323 struct e1000_nvm_info *nvm = &hw->nvm; 324 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 325 s32 ret_val = E1000_SUCCESS; 326 u16 timeout = 0; 327 u8 spi_stat_reg; 328 329 DEBUGFUNC("e1000_ready_nvm_eeprom"); 330 331 if (nvm->type == e1000_nvm_eeprom_microwire) { 332 /* Clear SK and DI */ 333 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 334 E1000_WRITE_REG(hw, E1000_EECD, eecd); 335 /* Set CS */ 336 eecd |= E1000_EECD_CS; 337 E1000_WRITE_REG(hw, E1000_EECD, eecd); 338 } else if (nvm->type == e1000_nvm_eeprom_spi) { 339 /* Clear SK and CS */ 340 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 341 E1000_WRITE_REG(hw, E1000_EECD, eecd); 342 usec_delay(1); 343 timeout = NVM_MAX_RETRY_SPI; 344 345 /* 346 * Read "Status Register" repeatedly until the LSB is cleared. 347 * The EEPROM will signal that the command has been completed 348 * by clearing bit 0 of the internal status register. If it's 349 * not cleared within 'timeout', then error out. 350 */ 351 while (timeout) { 352 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 353 hw->nvm.opcode_bits); 354 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 355 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 356 break; 357 358 usec_delay(5); 359 e1000_standby_nvm(hw); 360 timeout--; 361 } 362 363 if (!timeout) { 364 DEBUGOUT("SPI NVM Status error\n"); 365 ret_val = -E1000_ERR_NVM; 366 goto out; 367 } 368 } 369 370 out: 371 return (ret_val); 372 } 373 374 /* 375 * e1000_read_nvm_spi - Read EEPROM's using SPI 376 * @hw: pointer to the HW structure 377 * @offset: offset of word in the EEPROM to read 378 * @words: number of words to read 379 * @data: word read from the EEPROM 380 * 381 * Reads a 16 bit word from the EEPROM. 382 */ 383 s32 384 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 385 { 386 struct e1000_nvm_info *nvm = &hw->nvm; 387 u32 i = 0; 388 s32 ret_val; 389 u16 word_in; 390 u8 read_opcode = NVM_READ_OPCODE_SPI; 391 392 DEBUGFUNC("e1000_read_nvm_spi"); 393 394 /* 395 * A check for invalid values: offset too large, too many words, 396 * and not enough words. 397 */ 398 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 399 (words == 0)) { 400 DEBUGOUT("nvm parameter(s) out of bounds\n"); 401 ret_val = -E1000_ERR_NVM; 402 goto out; 403 } 404 405 ret_val = e1000_acquire_nvm(hw); 406 if (ret_val) 407 goto out; 408 409 ret_val = e1000_ready_nvm_eeprom(hw); 410 if (ret_val) 411 goto release; 412 413 e1000_standby_nvm(hw); 414 415 if ((nvm->address_bits == 8) && (offset >= 128)) 416 read_opcode |= NVM_A8_OPCODE_SPI; 417 418 /* Send the READ command (opcode + addr) */ 419 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 420 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 421 422 /* 423 * Read the data. SPI NVMs increment the address with each byte 424 * read and will roll over if reading beyond the end. This allows 425 * us to read the whole NVM from any offset 426 */ 427 for (i = 0; i < words; i++) { 428 word_in = e1000_shift_in_eec_bits(hw, 16); 429 data[i] = (word_in >> 8) | (word_in << 8); 430 } 431 432 release: 433 e1000_release_nvm(hw); 434 435 out: 436 return (ret_val); 437 } 438 439 /* 440 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 441 * @hw: pointer to the HW structure 442 * @offset: offset of word in the EEPROM to read 443 * @words: number of words to read 444 * @data: word read from the EEPROM 445 * 446 * Reads a 16 bit word from the EEPROM. 447 */ 448 s32 449 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 450 u16 *data) 451 { 452 struct e1000_nvm_info *nvm = &hw->nvm; 453 u32 i = 0; 454 s32 ret_val; 455 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 456 457 DEBUGFUNC("e1000_read_nvm_microwire"); 458 459 /* 460 * A check for invalid values: offset too large, too many words, 461 * and not enough words. 462 */ 463 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 464 (words == 0)) { 465 DEBUGOUT("nvm parameter(s) out of bounds\n"); 466 ret_val = -E1000_ERR_NVM; 467 goto out; 468 } 469 470 ret_val = e1000_acquire_nvm(hw); 471 if (ret_val) 472 goto out; 473 474 ret_val = e1000_ready_nvm_eeprom(hw); 475 if (ret_val) 476 goto release; 477 478 for (i = 0; i < words; i++) { 479 /* Send the READ command (opcode + addr) */ 480 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 481 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 482 nvm->address_bits); 483 484 /* 485 * Read the data. For microwire, each word requires the 486 * overhead of setup and tear-down. 487 */ 488 data[i] = e1000_shift_in_eec_bits(hw, 16); 489 e1000_standby_nvm(hw); 490 } 491 492 release: 493 e1000_release_nvm(hw); 494 495 out: 496 return (ret_val); 497 } 498 499 /* 500 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 501 * @hw: pointer to the HW structure 502 * @offset: offset of word in the EEPROM to read 503 * @words: number of words to read 504 * @data: word read from the EEPROM 505 * 506 * Reads a 16 bit word from the EEPROM using the EERD register. 507 */ 508 s32 509 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 510 { 511 struct e1000_nvm_info *nvm = &hw->nvm; 512 u32 i, eerd = 0; 513 s32 ret_val = E1000_SUCCESS; 514 515 DEBUGFUNC("e1000_read_nvm_eerd"); 516 517 /* 518 * A check for invalid values: offset too large, too many words, 519 * too many words for the offset, and not enough words. 520 */ 521 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 522 (words == 0)) { 523 DEBUGOUT("nvm parameter(s) out of bounds\n"); 524 ret_val = -E1000_ERR_NVM; 525 goto out; 526 } 527 528 for (i = 0; i < words; i++) { 529 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 530 E1000_NVM_RW_REG_START; 531 532 E1000_WRITE_REG(hw, E1000_EERD, eerd); 533 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 534 if (ret_val) 535 break; 536 537 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 538 E1000_NVM_RW_REG_DATA); 539 } 540 541 out: 542 return (ret_val); 543 } 544 545 /* 546 * e1000_write_nvm_spi - Write to EEPROM using SPI 547 * @hw: pointer to the HW structure 548 * @offset: offset within the EEPROM to be written to 549 * @words: number of words to write 550 * @data: 16 bit word(s) to be written to the EEPROM 551 * 552 * Writes data to EEPROM at offset using SPI interface. 553 * 554 * If e1000_update_nvm_checksum is not called after this function , the 555 * EEPROM will most likley contain an invalid checksum. 556 */ 557 s32 558 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 559 { 560 struct e1000_nvm_info *nvm = &hw->nvm; 561 s32 ret_val; 562 u16 widx = 0; 563 564 DEBUGFUNC("e1000_write_nvm_spi"); 565 566 /* 567 * A check for invalid values: offset too large, too many words, 568 * and not enough words. 569 */ 570 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 571 (words == 0)) { 572 DEBUGOUT("nvm parameter(s) out of bounds\n"); 573 ret_val = -E1000_ERR_NVM; 574 goto out; 575 } 576 577 ret_val = e1000_acquire_nvm(hw); 578 if (ret_val) 579 goto out; 580 581 msec_delay(10); 582 583 while (widx < words) { 584 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 585 586 ret_val = e1000_ready_nvm_eeprom(hw); 587 if (ret_val) 588 goto release; 589 590 e1000_standby_nvm(hw); 591 592 /* Send the WRITE ENABLE command (8 bit opcode) */ 593 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 594 nvm->opcode_bits); 595 596 e1000_standby_nvm(hw); 597 598 /* 599 * Some SPI eeproms use the 8th address bit embedded in the 600 * opcode 601 */ 602 if ((nvm->address_bits == 8) && (offset >= 128)) 603 write_opcode |= NVM_A8_OPCODE_SPI; 604 605 /* Send the Write command (8-bit opcode + addr) */ 606 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 607 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 608 nvm->address_bits); 609 610 /* Loop to allow for up to whole page write of eeprom */ 611 while (widx < words) { 612 u16 word_out = data[widx]; 613 word_out = (word_out >> 8) | (word_out << 8); 614 e1000_shift_out_eec_bits(hw, word_out, 16); 615 widx++; 616 617 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 618 e1000_standby_nvm(hw); 619 break; 620 } 621 } 622 } 623 624 msec_delay(10); 625 release: 626 e1000_release_nvm(hw); 627 628 out: 629 return (ret_val); 630 } 631 632 /* 633 * e1000_write_nvm_microwire - Writes EEPROM using microwire 634 * @hw: pointer to the HW structure 635 * @offset: offset within the EEPROM to be written to 636 * @words: number of words to write 637 * @data: 16 bit word(s) to be written to the EEPROM 638 * 639 * Writes data to EEPROM at offset using microwire interface. 640 * 641 * If e1000_update_nvm_checksum is not called after this function , the 642 * EEPROM will most likley contain an invalid checksum. 643 */ 644 s32 645 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 646 u16 *data) 647 { 648 struct e1000_nvm_info *nvm = &hw->nvm; 649 s32 ret_val; 650 u32 eecd; 651 u16 words_written = 0; 652 u16 widx = 0; 653 654 DEBUGFUNC("e1000_write_nvm_microwire"); 655 656 /* 657 * A check for invalid values: offset too large, too many words, 658 * and not enough words. 659 */ 660 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 661 (words == 0)) { 662 DEBUGOUT("nvm parameter(s) out of bounds\n"); 663 ret_val = -E1000_ERR_NVM; 664 goto out; 665 } 666 667 ret_val = e1000_acquire_nvm(hw); 668 if (ret_val) 669 goto out; 670 671 ret_val = e1000_ready_nvm_eeprom(hw); 672 if (ret_val) 673 goto release; 674 675 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 676 (u16)(nvm->opcode_bits + 2)); 677 678 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 679 680 e1000_standby_nvm(hw); 681 682 while (words_written < words) { 683 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 684 nvm->opcode_bits); 685 686 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 687 nvm->address_bits); 688 689 e1000_shift_out_eec_bits(hw, data[words_written], 16); 690 691 e1000_standby_nvm(hw); 692 693 for (widx = 0; widx < 200; widx++) { 694 eecd = E1000_READ_REG(hw, E1000_EECD); 695 if (eecd & E1000_EECD_DO) 696 break; 697 usec_delay(50); 698 } 699 700 if (widx == 200) { 701 DEBUGOUT("NVM Write did not complete\n"); 702 ret_val = -E1000_ERR_NVM; 703 goto release; 704 } 705 706 e1000_standby_nvm(hw); 707 708 words_written++; 709 } 710 711 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 712 (u16)(nvm->opcode_bits + 2)); 713 714 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 715 716 release: 717 e1000_release_nvm(hw); 718 719 out: 720 return (ret_val); 721 } 722 723 /* 724 * e1000_read_pba_num_generic - Read device part number 725 * @hw: pointer to the HW structure 726 * @pba_num: pointer to device part number 727 * 728 * Reads the product board assembly (PBA) number from the EEPROM and stores 729 * the value in pba_num. 730 */ 731 s32 732 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 733 { 734 s32 ret_val; 735 u16 nvm_data; 736 737 DEBUGFUNC("e1000_read_pba_num_generic"); 738 739 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 740 if (ret_val) { 741 DEBUGOUT("NVM Read Error\n"); 742 goto out; 743 } 744 *pba_num = (u32)(nvm_data << 16); 745 746 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 747 if (ret_val) { 748 DEBUGOUT("NVM Read Error\n"); 749 goto out; 750 } 751 *pba_num |= nvm_data; 752 753 out: 754 return (ret_val); 755 } 756 757 /* 758 * e1000_read_mac_addr_generic - Read device MAC address 759 * @hw: pointer to the HW structure 760 * 761 * Reads the device MAC address from the EEPROM and stores the value. 762 * Since devices with two ports use the same EEPROM, we increment the 763 * last bit in the MAC address for the second port. 764 */ 765 s32 766 e1000_read_mac_addr_generic(struct e1000_hw *hw) 767 { 768 s32 ret_val = E1000_SUCCESS; 769 u16 offset, nvm_data, i; 770 771 DEBUGFUNC("e1000_read_mac_addr"); 772 773 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 774 offset = i >> 1; 775 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 776 if (ret_val) { 777 DEBUGOUT("NVM Read Error\n"); 778 goto out; 779 } 780 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 781 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 782 } 783 784 /* Flip last bit of mac address if we're on second port */ 785 if (hw->bus.func == E1000_FUNC_1) 786 hw->mac.perm_addr[5] ^= 1; 787 788 for (i = 0; i < ETH_ADDR_LEN; i++) 789 hw->mac.addr[i] = hw->mac.perm_addr[i]; 790 791 out: 792 return (ret_val); 793 } 794 795 /* 796 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 797 * @hw: pointer to the HW structure 798 * 799 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 800 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 801 */ 802 s32 803 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 804 { 805 s32 ret_val = E1000_SUCCESS; 806 u16 checksum = 0; 807 u16 i, nvm_data; 808 809 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 810 811 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 812 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 813 if (ret_val) { 814 DEBUGOUT("NVM Read Error\n"); 815 goto out; 816 } 817 checksum += nvm_data; 818 } 819 820 if (checksum != (u16) NVM_SUM) { 821 DEBUGOUT("NVM Checksum Invalid\n"); 822 ret_val = -E1000_ERR_NVM; 823 goto out; 824 } 825 826 out: 827 return (ret_val); 828 } 829 830 /* 831 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 832 * @hw: pointer to the HW structure 833 * 834 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 835 * up to the checksum. Then calculates the EEPROM checksum and writes the 836 * value to the EEPROM. 837 */ 838 s32 839 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 840 { 841 s32 ret_val; 842 u16 checksum = 0; 843 u16 i, nvm_data; 844 845 DEBUGFUNC("e1000_update_nvm_checksum"); 846 847 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 848 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 849 if (ret_val) { 850 DEBUGOUT("NVM Read Error while updating checksum.\n"); 851 goto out; 852 } 853 checksum += nvm_data; 854 } 855 checksum = (u16) NVM_SUM - checksum; 856 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 857 if (ret_val) { 858 DEBUGOUT("NVM Write Error while updating checksum.\n"); 859 } 860 861 out: 862 return (ret_val); 863 } 864 865 /* 866 * e1000_reload_nvm_generic - Reloads EEPROM 867 * @hw: pointer to the HW structure 868 * 869 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 870 * extended control register. 871 */ 872 void 873 e1000_reload_nvm_generic(struct e1000_hw *hw) 874 { 875 u32 ctrl_ext; 876 877 DEBUGFUNC("e1000_reload_nvm_generic"); 878 879 usec_delay(10); 880 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 881 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 883 E1000_WRITE_FLUSH(hw); 884 } 885 886 /* Function pointers local to this file and not intended for public use */ 887 888 /* 889 * e1000_acquire_nvm - Acquire exclusive access to EEPROM 890 * @hw: pointer to the HW structure 891 * 892 * For those silicon families which have implemented a NVM acquire function, 893 * run the defined function else return success. 894 */ 895 s32 896 e1000_acquire_nvm(struct e1000_hw *hw) 897 { 898 if (hw->func.acquire_nvm) 899 return (hw->func.acquire_nvm(hw)); 900 901 return (E1000_SUCCESS); 902 } 903 904 /* 905 * e1000_release_nvm - Release exclusive access to EEPROM 906 * @hw: pointer to the HW structure 907 * 908 * For those silicon families which have implemented a NVM release function, 909 * run the defined fucntion else return success. 910 */ 911 void 912 e1000_release_nvm(struct e1000_hw *hw) 913 { 914 if (hw->func.release_nvm) 915 hw->func.release_nvm(hw); 916 } 917