xref: /onnv-gate/usr/src/uts/common/io/igb/igb_main.c (revision 11557:2d6ab66229f2)
15779Sxy150489 /*
25779Sxy150489  * CDDL HEADER START
35779Sxy150489  *
48571SChenlu.Chen@Sun.COM  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
55779Sxy150489  * The contents of this file are subject to the terms of the
65779Sxy150489  * Common Development and Distribution License (the "License").
75779Sxy150489  * You may not use this file except in compliance with the License.
85779Sxy150489  *
98571SChenlu.Chen@Sun.COM  * You can obtain a copy of the license at:
108571SChenlu.Chen@Sun.COM  *	http://www.opensolaris.org/os/licensing.
115779Sxy150489  * See the License for the specific language governing permissions
125779Sxy150489  * and limitations under the License.
135779Sxy150489  *
148571SChenlu.Chen@Sun.COM  * When using or redistributing this file, you may do so under the
158571SChenlu.Chen@Sun.COM  * License only. No other modification of this header is permitted.
168571SChenlu.Chen@Sun.COM  *
175779Sxy150489  * If applicable, add the following below this CDDL HEADER, with the
185779Sxy150489  * fields enclosed by brackets "[]" replaced with your own identifying
195779Sxy150489  * information: Portions Copyright [yyyy] [name of copyright owner]
205779Sxy150489  *
215779Sxy150489  * CDDL HEADER END
225779Sxy150489  */
235779Sxy150489 
245779Sxy150489 /*
2511502SChenlu.Chen@Sun.COM  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
269188SPaul.Guo@Sun.COM  * Use is subject to license terms.
275779Sxy150489  */
285779Sxy150489 
295779Sxy150489 #include "igb_sw.h"
305779Sxy150489 
317656SSherry.Moore@Sun.COM static char ident[] = "Intel 1Gb Ethernet";
32*11557SChenlu.Chen@Sun.COM static char igb_version[] = "igb 1.1.12";
335779Sxy150489 
345779Sxy150489 /*
355779Sxy150489  * Local function protoypes
365779Sxy150489  */
375779Sxy150489 static int igb_register_mac(igb_t *);
385779Sxy150489 static int igb_identify_hardware(igb_t *);
395779Sxy150489 static int igb_regs_map(igb_t *);
405779Sxy150489 static void igb_init_properties(igb_t *);
415779Sxy150489 static int igb_init_driver_settings(igb_t *);
425779Sxy150489 static void igb_init_locks(igb_t *);
435779Sxy150489 static void igb_destroy_locks(igb_t *);
448955SChenlu.Chen@Sun.COM static int igb_init_mac_address(igb_t *);
455779Sxy150489 static int igb_init(igb_t *);
468955SChenlu.Chen@Sun.COM static int igb_init_adapter(igb_t *);
478955SChenlu.Chen@Sun.COM static void igb_stop_adapter(igb_t *);
485779Sxy150489 static int igb_reset(igb_t *);
495779Sxy150489 static void igb_tx_clean(igb_t *);
505779Sxy150489 static boolean_t igb_tx_drain(igb_t *);
515779Sxy150489 static boolean_t igb_rx_drain(igb_t *);
525779Sxy150489 static int igb_alloc_rings(igb_t *);
5311502SChenlu.Chen@Sun.COM static int igb_alloc_rx_data(igb_t *);
5411502SChenlu.Chen@Sun.COM static void igb_free_rx_data(igb_t *);
555779Sxy150489 static void igb_free_rings(igb_t *);
565779Sxy150489 static void igb_setup_rings(igb_t *);
575779Sxy150489 static void igb_setup_rx(igb_t *);
585779Sxy150489 static void igb_setup_tx(igb_t *);
595779Sxy150489 static void igb_setup_rx_ring(igb_rx_ring_t *);
605779Sxy150489 static void igb_setup_tx_ring(igb_tx_ring_t *);
615779Sxy150489 static void igb_setup_rss(igb_t *);
628275SEric Cheng static void igb_setup_mac_rss_classify(igb_t *);
638275SEric Cheng static void igb_setup_mac_classify(igb_t *);
645779Sxy150489 static void igb_init_unicst(igb_t *);
655779Sxy150489 static void igb_setup_multicst(igb_t *);
665779Sxy150489 static void igb_get_phy_state(igb_t *);
6711502SChenlu.Chen@Sun.COM static void igb_param_sync(igb_t *);
685779Sxy150489 static void igb_get_conf(igb_t *);
695779Sxy150489 static int igb_get_prop(igb_t *, char *, int, int, int);
705779Sxy150489 static boolean_t igb_is_link_up(igb_t *);
715779Sxy150489 static boolean_t igb_link_check(igb_t *);
725779Sxy150489 static void igb_local_timer(void *);
7311367SJason.Xu@Sun.COM static void igb_link_timer(void *);
745779Sxy150489 static void igb_arm_watchdog_timer(igb_t *);
755779Sxy150489 static void igb_start_watchdog_timer(igb_t *);
765779Sxy150489 static void igb_restart_watchdog_timer(igb_t *);
775779Sxy150489 static void igb_stop_watchdog_timer(igb_t *);
7811367SJason.Xu@Sun.COM static void igb_start_link_timer(igb_t *);
7911367SJason.Xu@Sun.COM static void igb_stop_link_timer(igb_t *);
805779Sxy150489 static void igb_disable_adapter_interrupts(igb_t *);
818571SChenlu.Chen@Sun.COM static void igb_enable_adapter_interrupts_82575(igb_t *);
828571SChenlu.Chen@Sun.COM static void igb_enable_adapter_interrupts_82576(igb_t *);
8311155SJason.Xu@Sun.COM static void igb_enable_adapter_interrupts_82580(igb_t *);
845779Sxy150489 static boolean_t is_valid_mac_addr(uint8_t *);
855779Sxy150489 static boolean_t igb_stall_check(igb_t *);
865779Sxy150489 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t);
875779Sxy150489 static void igb_set_external_loopback(igb_t *);
885779Sxy150489 static void igb_set_internal_mac_loopback(igb_t *);
895779Sxy150489 static void igb_set_internal_phy_loopback(igb_t *);
905779Sxy150489 static void igb_set_internal_serdes_loopback(igb_t *);
915779Sxy150489 static boolean_t igb_find_mac_address(igb_t *);
925779Sxy150489 static int igb_alloc_intrs(igb_t *);
937072Sxy150489 static int igb_alloc_intr_handles(igb_t *, int);
945779Sxy150489 static int igb_add_intr_handlers(igb_t *);
955779Sxy150489 static void igb_rem_intr_handlers(igb_t *);
965779Sxy150489 static void igb_rem_intrs(igb_t *);
975779Sxy150489 static int igb_enable_intrs(igb_t *);
985779Sxy150489 static int igb_disable_intrs(igb_t *);
998571SChenlu.Chen@Sun.COM static void igb_setup_msix_82575(igb_t *);
1008571SChenlu.Chen@Sun.COM static void igb_setup_msix_82576(igb_t *);
10111155SJason.Xu@Sun.COM static void igb_setup_msix_82580(igb_t *);
1025779Sxy150489 static uint_t igb_intr_legacy(void *, void *);
1035779Sxy150489 static uint_t igb_intr_msi(void *, void *);
1045779Sxy150489 static uint_t igb_intr_rx(void *, void *);
1058275SEric Cheng static uint_t igb_intr_tx(void *, void *);
1065779Sxy150489 static uint_t igb_intr_tx_other(void *, void *);
1075779Sxy150489 static void igb_intr_rx_work(igb_rx_ring_t *);
1085779Sxy150489 static void igb_intr_tx_work(igb_tx_ring_t *);
1098275SEric Cheng static void igb_intr_link_work(igb_t *);
1105779Sxy150489 static void igb_get_driver_control(struct e1000_hw *);
1115779Sxy150489 static void igb_release_driver_control(struct e1000_hw *);
1125779Sxy150489 
1135779Sxy150489 static int igb_attach(dev_info_t *, ddi_attach_cmd_t);
1145779Sxy150489 static int igb_detach(dev_info_t *, ddi_detach_cmd_t);
1155779Sxy150489 static int igb_resume(dev_info_t *);
1165779Sxy150489 static int igb_suspend(dev_info_t *);
1177656SSherry.Moore@Sun.COM static int igb_quiesce(dev_info_t *);
1185779Sxy150489 static void igb_unconfigure(dev_info_t *, igb_t *);
1196624Sgl147354 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
1206624Sgl147354     const void *);
1216624Sgl147354 static void igb_fm_init(igb_t *);
1226624Sgl147354 static void igb_fm_fini(igb_t *);
1239775SVitezslav.Batrla@Sun.COM static void igb_release_multicast(igb_t *);
1245779Sxy150489 
12511502SChenlu.Chen@Sun.COM mac_priv_prop_t igb_priv_props[] = {
12611502SChenlu.Chen@Sun.COM 	{"_tx_copy_thresh", MAC_PROP_PERM_RW},
12711502SChenlu.Chen@Sun.COM 	{"_tx_recycle_thresh", MAC_PROP_PERM_RW},
12811502SChenlu.Chen@Sun.COM 	{"_tx_overload_thresh", MAC_PROP_PERM_RW},
12911502SChenlu.Chen@Sun.COM 	{"_tx_resched_thresh", MAC_PROP_PERM_RW},
13011502SChenlu.Chen@Sun.COM 	{"_rx_copy_thresh", MAC_PROP_PERM_RW},
13111502SChenlu.Chen@Sun.COM 	{"_rx_limit_per_intr", MAC_PROP_PERM_RW},
13211502SChenlu.Chen@Sun.COM 	{"_intr_throttling", MAC_PROP_PERM_RW},
13311502SChenlu.Chen@Sun.COM 	{"_adv_pause_cap", MAC_PROP_PERM_READ},
13411502SChenlu.Chen@Sun.COM 	{"_adv_asym_pause_cap", MAC_PROP_PERM_READ}
13511502SChenlu.Chen@Sun.COM };
13611502SChenlu.Chen@Sun.COM 
13711502SChenlu.Chen@Sun.COM #define	IGB_MAX_PRIV_PROPS \
13811502SChenlu.Chen@Sun.COM 	(sizeof (igb_priv_props) / sizeof (mac_priv_prop_t))
13911502SChenlu.Chen@Sun.COM 
1405779Sxy150489 static struct cb_ops igb_cb_ops = {
1415779Sxy150489 	nulldev,		/* cb_open */
1425779Sxy150489 	nulldev,		/* cb_close */
1435779Sxy150489 	nodev,			/* cb_strategy */
1445779Sxy150489 	nodev,			/* cb_print */
1455779Sxy150489 	nodev,			/* cb_dump */
1465779Sxy150489 	nodev,			/* cb_read */
1475779Sxy150489 	nodev,			/* cb_write */
1485779Sxy150489 	nodev,			/* cb_ioctl */
1495779Sxy150489 	nodev,			/* cb_devmap */
1505779Sxy150489 	nodev,			/* cb_mmap */
1515779Sxy150489 	nodev,			/* cb_segmap */
1525779Sxy150489 	nochpoll,		/* cb_chpoll */
1535779Sxy150489 	ddi_prop_op,		/* cb_prop_op */
1545779Sxy150489 	NULL,			/* cb_stream */
1555779Sxy150489 	D_MP | D_HOTPLUG,	/* cb_flag */
1565779Sxy150489 	CB_REV,			/* cb_rev */
1575779Sxy150489 	nodev,			/* cb_aread */
1585779Sxy150489 	nodev			/* cb_awrite */
1595779Sxy150489 };
1605779Sxy150489 
1615779Sxy150489 static struct dev_ops igb_dev_ops = {
1625779Sxy150489 	DEVO_REV,		/* devo_rev */
1635779Sxy150489 	0,			/* devo_refcnt */
1645779Sxy150489 	NULL,			/* devo_getinfo */
1655779Sxy150489 	nulldev,		/* devo_identify */
1665779Sxy150489 	nulldev,		/* devo_probe */
1675779Sxy150489 	igb_attach,		/* devo_attach */
1685779Sxy150489 	igb_detach,		/* devo_detach */
1695779Sxy150489 	nodev,			/* devo_reset */
1705779Sxy150489 	&igb_cb_ops,		/* devo_cb_ops */
1715779Sxy150489 	NULL,			/* devo_bus_ops */
1727656SSherry.Moore@Sun.COM 	ddi_power,		/* devo_power */
1737656SSherry.Moore@Sun.COM 	igb_quiesce,	/* devo_quiesce */
1745779Sxy150489 };
1755779Sxy150489 
1765779Sxy150489 static struct modldrv igb_modldrv = {
1775779Sxy150489 	&mod_driverops,		/* Type of module.  This one is a driver */
1785779Sxy150489 	ident,			/* Discription string */
1795779Sxy150489 	&igb_dev_ops,		/* driver ops */
1805779Sxy150489 };
1815779Sxy150489 
1825779Sxy150489 static struct modlinkage igb_modlinkage = {
1835779Sxy150489 	MODREV_1, &igb_modldrv, NULL
1845779Sxy150489 };
1855779Sxy150489 
1865779Sxy150489 /* Access attributes for register mapping */
1875779Sxy150489 ddi_device_acc_attr_t igb_regs_acc_attr = {
18811236SStephen.Hanson@Sun.COM 	DDI_DEVICE_ATTR_V1,
1895779Sxy150489 	DDI_STRUCTURE_LE_ACC,
1905779Sxy150489 	DDI_STRICTORDER_ACC,
1916624Sgl147354 	DDI_FLAGERR_ACC
1925779Sxy150489 };
1935779Sxy150489 
19411502SChenlu.Chen@Sun.COM #define	IGB_M_CALLBACK_FLAGS \
19511502SChenlu.Chen@Sun.COM 	(MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP)
1965779Sxy150489 
1975779Sxy150489 static mac_callbacks_t igb_m_callbacks = {
1985779Sxy150489 	IGB_M_CALLBACK_FLAGS,
1995779Sxy150489 	igb_m_stat,
2005779Sxy150489 	igb_m_start,
2015779Sxy150489 	igb_m_stop,
2025779Sxy150489 	igb_m_promisc,
2035779Sxy150489 	igb_m_multicst,
2048275SEric Cheng 	NULL,
2055779Sxy150489 	NULL,
2065779Sxy150489 	igb_m_ioctl,
20711502SChenlu.Chen@Sun.COM 	igb_m_getcapab,
20811502SChenlu.Chen@Sun.COM 	NULL,
20911502SChenlu.Chen@Sun.COM 	NULL,
21011502SChenlu.Chen@Sun.COM 	igb_m_setprop,
21111502SChenlu.Chen@Sun.COM 	igb_m_getprop
2125779Sxy150489 };
2135779Sxy150489 
2145779Sxy150489 /*
2158571SChenlu.Chen@Sun.COM  * Initialize capabilities of each supported adapter type
2168571SChenlu.Chen@Sun.COM  */
2178571SChenlu.Chen@Sun.COM static adapter_info_t igb_82575_cap = {
2188571SChenlu.Chen@Sun.COM 	/* limits */
2198571SChenlu.Chen@Sun.COM 	4,		/* maximum number of rx queues */
2208571SChenlu.Chen@Sun.COM 	1,		/* minimum number of rx queues */
2218571SChenlu.Chen@Sun.COM 	4,		/* default number of rx queues */
2228571SChenlu.Chen@Sun.COM 	4,		/* maximum number of tx queues */
2238571SChenlu.Chen@Sun.COM 	1,		/* minimum number of tx queues */
2248571SChenlu.Chen@Sun.COM 	4,		/* default number of tx queues */
2258571SChenlu.Chen@Sun.COM 	65535,		/* maximum interrupt throttle rate */
2268571SChenlu.Chen@Sun.COM 	0,		/* minimum interrupt throttle rate */
2278571SChenlu.Chen@Sun.COM 	200,		/* default interrupt throttle rate */
2288571SChenlu.Chen@Sun.COM 
2298571SChenlu.Chen@Sun.COM 	/* function pointers */
2308571SChenlu.Chen@Sun.COM 	igb_enable_adapter_interrupts_82575,
2318571SChenlu.Chen@Sun.COM 	igb_setup_msix_82575,
2328571SChenlu.Chen@Sun.COM 
2338571SChenlu.Chen@Sun.COM 	/* capabilities */
2348571SChenlu.Chen@Sun.COM 	(IGB_FLAG_HAS_DCA |	/* capability flags */
2358955SChenlu.Chen@Sun.COM 	IGB_FLAG_VMDQ_POOL),
2368955SChenlu.Chen@Sun.COM 
2378955SChenlu.Chen@Sun.COM 	0xffc00000		/* mask for RXDCTL register */
2388571SChenlu.Chen@Sun.COM };
2398571SChenlu.Chen@Sun.COM 
2408571SChenlu.Chen@Sun.COM static adapter_info_t igb_82576_cap = {
2418571SChenlu.Chen@Sun.COM 	/* limits */
2428955SChenlu.Chen@Sun.COM 	16,		/* maximum number of rx queues */
2438571SChenlu.Chen@Sun.COM 	1,		/* minimum number of rx queues */
2448571SChenlu.Chen@Sun.COM 	4,		/* default number of rx queues */
2458955SChenlu.Chen@Sun.COM 	16,		/* maximum number of tx queues */
2468571SChenlu.Chen@Sun.COM 	1,		/* minimum number of tx queues */
2478571SChenlu.Chen@Sun.COM 	4,		/* default number of tx queues */
2488571SChenlu.Chen@Sun.COM 	65535,		/* maximum interrupt throttle rate */
2498571SChenlu.Chen@Sun.COM 	0,		/* minimum interrupt throttle rate */
2508571SChenlu.Chen@Sun.COM 	200,		/* default interrupt throttle rate */
2518571SChenlu.Chen@Sun.COM 
2528571SChenlu.Chen@Sun.COM 	/* function pointers */
2538571SChenlu.Chen@Sun.COM 	igb_enable_adapter_interrupts_82576,
2548571SChenlu.Chen@Sun.COM 	igb_setup_msix_82576,
2558571SChenlu.Chen@Sun.COM 
2568571SChenlu.Chen@Sun.COM 	/* capabilities */
2578571SChenlu.Chen@Sun.COM 	(IGB_FLAG_HAS_DCA |	/* capability flags */
2588571SChenlu.Chen@Sun.COM 	IGB_FLAG_VMDQ_POOL |
2598955SChenlu.Chen@Sun.COM 	IGB_FLAG_NEED_CTX_IDX),
2608955SChenlu.Chen@Sun.COM 
2618955SChenlu.Chen@Sun.COM 	0xffe00000		/* mask for RXDCTL register */
2628571SChenlu.Chen@Sun.COM };
2638571SChenlu.Chen@Sun.COM 
26411155SJason.Xu@Sun.COM static adapter_info_t igb_82580_cap = {
26511155SJason.Xu@Sun.COM 	/* limits */
26611155SJason.Xu@Sun.COM 	8,		/* maximum number of rx queues */
26711155SJason.Xu@Sun.COM 	1,		/* minimum number of rx queues */
26811155SJason.Xu@Sun.COM 	4,		/* default number of rx queues */
26911155SJason.Xu@Sun.COM 	8,		/* maximum number of tx queues */
27011155SJason.Xu@Sun.COM 	1,		/* minimum number of tx queues */
27111155SJason.Xu@Sun.COM 	4,		/* default number of tx queues */
27211155SJason.Xu@Sun.COM 	65535,		/* maximum interrupt throttle rate */
27311155SJason.Xu@Sun.COM 	0,		/* minimum interrupt throttle rate */
27411155SJason.Xu@Sun.COM 	200,		/* default interrupt throttle rate */
27511155SJason.Xu@Sun.COM 
27611155SJason.Xu@Sun.COM 	/* function pointers */
27711155SJason.Xu@Sun.COM 	igb_enable_adapter_interrupts_82580,
27811155SJason.Xu@Sun.COM 	igb_setup_msix_82580,
27911155SJason.Xu@Sun.COM 
28011155SJason.Xu@Sun.COM 	/* capabilities */
28111155SJason.Xu@Sun.COM 	(IGB_FLAG_HAS_DCA |	/* capability flags */
28211155SJason.Xu@Sun.COM 	IGB_FLAG_VMDQ_POOL |
28311155SJason.Xu@Sun.COM 	IGB_FLAG_NEED_CTX_IDX),
28411155SJason.Xu@Sun.COM 
28511155SJason.Xu@Sun.COM 	0xffe00000		/* mask for RXDCTL register */
28611155SJason.Xu@Sun.COM };
28711155SJason.Xu@Sun.COM 
2888571SChenlu.Chen@Sun.COM /*
2895779Sxy150489  * Module Initialization Functions
2905779Sxy150489  */
2915779Sxy150489 
2925779Sxy150489 int
2935779Sxy150489 _init(void)
2945779Sxy150489 {
2955779Sxy150489 	int status;
2965779Sxy150489 
2975779Sxy150489 	mac_init_ops(&igb_dev_ops, MODULE_NAME);
2985779Sxy150489 
2995779Sxy150489 	status = mod_install(&igb_modlinkage);
3005779Sxy150489 
3015779Sxy150489 	if (status != DDI_SUCCESS) {
3025779Sxy150489 		mac_fini_ops(&igb_dev_ops);
3035779Sxy150489 	}
3045779Sxy150489 
3055779Sxy150489 	return (status);
3065779Sxy150489 }
3075779Sxy150489 
3085779Sxy150489 int
3095779Sxy150489 _fini(void)
3105779Sxy150489 {
3115779Sxy150489 	int status;
3125779Sxy150489 
3135779Sxy150489 	status = mod_remove(&igb_modlinkage);
3145779Sxy150489 
3155779Sxy150489 	if (status == DDI_SUCCESS) {
3165779Sxy150489 		mac_fini_ops(&igb_dev_ops);
3175779Sxy150489 	}
3185779Sxy150489 
3195779Sxy150489 	return (status);
3205779Sxy150489 
3215779Sxy150489 }
3225779Sxy150489 
3235779Sxy150489 int
3245779Sxy150489 _info(struct modinfo *modinfop)
3255779Sxy150489 {
3265779Sxy150489 	int status;
3275779Sxy150489 
3285779Sxy150489 	status = mod_info(&igb_modlinkage, modinfop);
3295779Sxy150489 
3305779Sxy150489 	return (status);
3315779Sxy150489 }
3325779Sxy150489 
3335779Sxy150489 /*
3345779Sxy150489  * igb_attach - driver attach
3355779Sxy150489  *
3365779Sxy150489  * This function is the device specific initialization entry
3375779Sxy150489  * point. This entry point is required and must be written.
3385779Sxy150489  * The DDI_ATTACH command must be provided in the attach entry
3395779Sxy150489  * point. When attach() is called with cmd set to DDI_ATTACH,
3405779Sxy150489  * all normal kernel services (such as kmem_alloc(9F)) are
3415779Sxy150489  * available for use by the driver.
3425779Sxy150489  *
3435779Sxy150489  * The attach() function will be called once for each instance
3445779Sxy150489  * of  the  device  on  the  system with cmd set to DDI_ATTACH.
3455779Sxy150489  * Until attach() succeeds, the only driver entry points which
3465779Sxy150489  * may be called are open(9E) and getinfo(9E).
3475779Sxy150489  */
3485779Sxy150489 static int
3495779Sxy150489 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
3505779Sxy150489 {
3515779Sxy150489 	igb_t *igb;
3525779Sxy150489 	struct igb_osdep *osdep;
3535779Sxy150489 	struct e1000_hw *hw;
3545779Sxy150489 	int instance;
3555779Sxy150489 
3565779Sxy150489 	/*
3575779Sxy150489 	 * Check the command and perform corresponding operations
3585779Sxy150489 	 */
3595779Sxy150489 	switch (cmd) {
3605779Sxy150489 	default:
3615779Sxy150489 		return (DDI_FAILURE);
3625779Sxy150489 
3635779Sxy150489 	case DDI_RESUME:
3645779Sxy150489 		return (igb_resume(devinfo));
3655779Sxy150489 
3665779Sxy150489 	case DDI_ATTACH:
3675779Sxy150489 		break;
3685779Sxy150489 	}
3695779Sxy150489 
3705779Sxy150489 	/* Get the device instance */
3715779Sxy150489 	instance = ddi_get_instance(devinfo);
3725779Sxy150489 
3735779Sxy150489 	/* Allocate memory for the instance data structure */
3745779Sxy150489 	igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP);
3755779Sxy150489 
3765779Sxy150489 	igb->dip = devinfo;
3775779Sxy150489 	igb->instance = instance;
3785779Sxy150489 
3795779Sxy150489 	hw = &igb->hw;
3805779Sxy150489 	osdep = &igb->osdep;
3815779Sxy150489 	hw->back = osdep;
3825779Sxy150489 	osdep->igb = igb;
3835779Sxy150489 
3845779Sxy150489 	/* Attach the instance pointer to the dev_info data structure */
3855779Sxy150489 	ddi_set_driver_private(devinfo, igb);
3865779Sxy150489 
3876624Sgl147354 
3886624Sgl147354 	/* Initialize for fma support */
3896624Sgl147354 	igb->fm_capabilities = igb_get_prop(igb, "fm-capable",
3906624Sgl147354 	    0, 0x0f,
3916624Sgl147354 	    DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
3926624Sgl147354 	    DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
3936624Sgl147354 	igb_fm_init(igb);
3946624Sgl147354 	igb->attach_progress |= ATTACH_PROGRESS_FMINIT;
3956624Sgl147354 
3965779Sxy150489 	/*
3975779Sxy150489 	 * Map PCI config space registers
3985779Sxy150489 	 */
3995779Sxy150489 	if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
4005779Sxy150489 		igb_error(igb, "Failed to map PCI configurations");
4015779Sxy150489 		goto attach_fail;
4025779Sxy150489 	}
4035779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
4045779Sxy150489 
4055779Sxy150489 	/*
4065779Sxy150489 	 * Identify the chipset family
4075779Sxy150489 	 */
4085779Sxy150489 	if (igb_identify_hardware(igb) != IGB_SUCCESS) {
4095779Sxy150489 		igb_error(igb, "Failed to identify hardware");
4105779Sxy150489 		goto attach_fail;
4115779Sxy150489 	}
4125779Sxy150489 
4135779Sxy150489 	/*
4145779Sxy150489 	 * Map device registers
4155779Sxy150489 	 */
4165779Sxy150489 	if (igb_regs_map(igb) != IGB_SUCCESS) {
4175779Sxy150489 		igb_error(igb, "Failed to map device registers");
4185779Sxy150489 		goto attach_fail;
4195779Sxy150489 	}
4205779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
4215779Sxy150489 
4225779Sxy150489 	/*
4235779Sxy150489 	 * Initialize driver parameters
4245779Sxy150489 	 */
4255779Sxy150489 	igb_init_properties(igb);
4265779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_PROPS;
4275779Sxy150489 
4285779Sxy150489 	/*
4295779Sxy150489 	 * Allocate interrupts
4305779Sxy150489 	 */
4315779Sxy150489 	if (igb_alloc_intrs(igb) != IGB_SUCCESS) {
4325779Sxy150489 		igb_error(igb, "Failed to allocate interrupts");
4335779Sxy150489 		goto attach_fail;
4345779Sxy150489 	}
4355779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
4365779Sxy150489 
4375779Sxy150489 	/*
4385779Sxy150489 	 * Allocate rx/tx rings based on the ring numbers.
4395779Sxy150489 	 * The actual numbers of rx/tx rings are decided by the number of
4405779Sxy150489 	 * allocated interrupt vectors, so we should allocate the rings after
4415779Sxy150489 	 * interrupts are allocated.
4425779Sxy150489 	 */
4435779Sxy150489 	if (igb_alloc_rings(igb) != IGB_SUCCESS) {
4448275SEric Cheng 		igb_error(igb, "Failed to allocate rx/tx rings or groups");
4455779Sxy150489 		goto attach_fail;
4465779Sxy150489 	}
4475779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
4485779Sxy150489 
4495779Sxy150489 	/*
4505779Sxy150489 	 * Add interrupt handlers
4515779Sxy150489 	 */
4525779Sxy150489 	if (igb_add_intr_handlers(igb) != IGB_SUCCESS) {
4535779Sxy150489 		igb_error(igb, "Failed to add interrupt handlers");
4545779Sxy150489 		goto attach_fail;
4555779Sxy150489 	}
4565779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
4575779Sxy150489 
4585779Sxy150489 	/*
4595779Sxy150489 	 * Initialize driver parameters
4605779Sxy150489 	 */
4615779Sxy150489 	if (igb_init_driver_settings(igb) != IGB_SUCCESS) {
4625779Sxy150489 		igb_error(igb, "Failed to initialize driver settings");
4635779Sxy150489 		goto attach_fail;
4645779Sxy150489 	}
4655779Sxy150489 
4666624Sgl147354 	if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) {
4676624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
4686624Sgl147354 		goto attach_fail;
4696624Sgl147354 	}
4706624Sgl147354 
4715779Sxy150489 	/*
4725779Sxy150489 	 * Initialize mutexes for this device.
4735779Sxy150489 	 * Do this before enabling the interrupt handler and
4745779Sxy150489 	 * register the softint to avoid the condition where
4755779Sxy150489 	 * interrupt handler can try using uninitialized mutex
4765779Sxy150489 	 */
4775779Sxy150489 	igb_init_locks(igb);
4785779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_LOCKS;
4795779Sxy150489 
4805779Sxy150489 	/*
48111502SChenlu.Chen@Sun.COM 	 * Initialize the adapter
4828955SChenlu.Chen@Sun.COM 	 */
4835779Sxy150489 	if (igb_init(igb) != IGB_SUCCESS) {
4845779Sxy150489 		igb_error(igb, "Failed to initialize adapter");
4855779Sxy150489 		goto attach_fail;
4865779Sxy150489 	}
4878955SChenlu.Chen@Sun.COM 	igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
4885779Sxy150489 
4895779Sxy150489 	/*
4905779Sxy150489 	 * Initialize statistics
4915779Sxy150489 	 */
4925779Sxy150489 	if (igb_init_stats(igb) != IGB_SUCCESS) {
4935779Sxy150489 		igb_error(igb, "Failed to initialize statistics");
4945779Sxy150489 		goto attach_fail;
4955779Sxy150489 	}
4965779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_STATS;
4975779Sxy150489 
4985779Sxy150489 	/*
4995779Sxy150489 	 * Register the driver to the MAC
5005779Sxy150489 	 */
5015779Sxy150489 	if (igb_register_mac(igb) != IGB_SUCCESS) {
5025779Sxy150489 		igb_error(igb, "Failed to register MAC");
5035779Sxy150489 		goto attach_fail;
5045779Sxy150489 	}
5055779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_MAC;
5065779Sxy150489 
5075779Sxy150489 	/*
5085779Sxy150489 	 * Now that mutex locks are initialized, and the chip is also
5095779Sxy150489 	 * initialized, enable interrupts.
5105779Sxy150489 	 */
5115779Sxy150489 	if (igb_enable_intrs(igb) != IGB_SUCCESS) {
5125779Sxy150489 		igb_error(igb, "Failed to enable DDI interrupts");
5135779Sxy150489 		goto attach_fail;
5145779Sxy150489 	}
5155779Sxy150489 	igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
5165779Sxy150489 
5178571SChenlu.Chen@Sun.COM 	igb_log(igb, "%s", igb_version);
51811367SJason.Xu@Sun.COM 	atomic_or_32(&igb->igb_state, IGB_INITIALIZED);
5195779Sxy150489 
5205779Sxy150489 	return (DDI_SUCCESS);
5215779Sxy150489 
5225779Sxy150489 attach_fail:
5235779Sxy150489 	igb_unconfigure(devinfo, igb);
5245779Sxy150489 	return (DDI_FAILURE);
5255779Sxy150489 }
5265779Sxy150489 
5275779Sxy150489 /*
5285779Sxy150489  * igb_detach - driver detach
5295779Sxy150489  *
5305779Sxy150489  * The detach() function is the complement of the attach routine.
5315779Sxy150489  * If cmd is set to DDI_DETACH, detach() is used to remove  the
5325779Sxy150489  * state  associated  with  a  given  instance of a device node
5335779Sxy150489  * prior to the removal of that instance from the system.
5345779Sxy150489  *
5355779Sxy150489  * The detach() function will be called once for each  instance
5365779Sxy150489  * of the device for which there has been a successful attach()
5375779Sxy150489  * once there are no longer  any  opens  on  the  device.
5385779Sxy150489  *
5395779Sxy150489  * Interrupts routine are disabled, All memory allocated by this
5405779Sxy150489  * driver are freed.
5415779Sxy150489  */
5425779Sxy150489 static int
5435779Sxy150489 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
5445779Sxy150489 {
5455779Sxy150489 	igb_t *igb;
5465779Sxy150489 
5475779Sxy150489 	/*
5485779Sxy150489 	 * Check detach command
5495779Sxy150489 	 */
5505779Sxy150489 	switch (cmd) {
5515779Sxy150489 	default:
5525779Sxy150489 		return (DDI_FAILURE);
5535779Sxy150489 
5545779Sxy150489 	case DDI_SUSPEND:
5555779Sxy150489 		return (igb_suspend(devinfo));
5565779Sxy150489 
5575779Sxy150489 	case DDI_DETACH:
5585779Sxy150489 		break;
5595779Sxy150489 	}
5605779Sxy150489 
5615779Sxy150489 
5625779Sxy150489 	/*
5635779Sxy150489 	 * Get the pointer to the driver private data structure
5645779Sxy150489 	 */
5655779Sxy150489 	igb = (igb_t *)ddi_get_driver_private(devinfo);
5665779Sxy150489 	if (igb == NULL)
5675779Sxy150489 		return (DDI_FAILURE);
5685779Sxy150489 
5695779Sxy150489 	/*
5705779Sxy150489 	 * Unregister MAC. If failed, we have to fail the detach
5715779Sxy150489 	 */
5725779Sxy150489 	if (mac_unregister(igb->mac_hdl) != 0) {
5735779Sxy150489 		igb_error(igb, "Failed to unregister MAC");
5745779Sxy150489 		return (DDI_FAILURE);
5755779Sxy150489 	}
5765779Sxy150489 	igb->attach_progress &= ~ATTACH_PROGRESS_MAC;
5775779Sxy150489 
5785779Sxy150489 	/*
5795779Sxy150489 	 * If the device is still running, it needs to be stopped first.
5805779Sxy150489 	 * This check is necessary because under some specific circumstances,
5815779Sxy150489 	 * the detach routine can be called without stopping the interface
5825779Sxy150489 	 * first.
5835779Sxy150489 	 */
5845779Sxy150489 	mutex_enter(&igb->gen_lock);
5855779Sxy150489 	if (igb->igb_state & IGB_STARTED) {
58611367SJason.Xu@Sun.COM 		atomic_and_32(&igb->igb_state, ~IGB_STARTED);
58711502SChenlu.Chen@Sun.COM 		igb_stop(igb, B_TRUE);
5885779Sxy150489 		mutex_exit(&igb->gen_lock);
5895779Sxy150489 		/* Disable and stop the watchdog timer */
5905779Sxy150489 		igb_disable_watchdog_timer(igb);
5915779Sxy150489 	} else
5925779Sxy150489 		mutex_exit(&igb->gen_lock);
5935779Sxy150489 
5945779Sxy150489 	/*
5955779Sxy150489 	 * Check if there are still rx buffers held by the upper layer.
5965779Sxy150489 	 * If so, fail the detach.
5975779Sxy150489 	 */
5985779Sxy150489 	if (!igb_rx_drain(igb))
5995779Sxy150489 		return (DDI_FAILURE);
6005779Sxy150489 
6015779Sxy150489 	/*
6025779Sxy150489 	 * Do the remaining unconfigure routines
6035779Sxy150489 	 */
6045779Sxy150489 	igb_unconfigure(devinfo, igb);
6055779Sxy150489 
6065779Sxy150489 	return (DDI_SUCCESS);
6075779Sxy150489 }
6085779Sxy150489 
6097656SSherry.Moore@Sun.COM /*
6107656SSherry.Moore@Sun.COM  * quiesce(9E) entry point.
6117656SSherry.Moore@Sun.COM  *
6127656SSherry.Moore@Sun.COM  * This function is called when the system is single-threaded at high
6137656SSherry.Moore@Sun.COM  * PIL with preemption disabled. Therefore, this function must not be
6147656SSherry.Moore@Sun.COM  * blocked.
6157656SSherry.Moore@Sun.COM  *
6167656SSherry.Moore@Sun.COM  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
6177656SSherry.Moore@Sun.COM  * DDI_FAILURE indicates an error condition and should almost never happen.
6187656SSherry.Moore@Sun.COM  */
6197656SSherry.Moore@Sun.COM static int
6207656SSherry.Moore@Sun.COM igb_quiesce(dev_info_t *devinfo)
6217656SSherry.Moore@Sun.COM {
6227656SSherry.Moore@Sun.COM 	igb_t *igb;
6237656SSherry.Moore@Sun.COM 	struct e1000_hw *hw;
6247656SSherry.Moore@Sun.COM 
6257656SSherry.Moore@Sun.COM 	igb = (igb_t *)ddi_get_driver_private(devinfo);
6267656SSherry.Moore@Sun.COM 
6277656SSherry.Moore@Sun.COM 	if (igb == NULL)
6287656SSherry.Moore@Sun.COM 		return (DDI_FAILURE);
6297656SSherry.Moore@Sun.COM 
6307656SSherry.Moore@Sun.COM 	hw = &igb->hw;
6317656SSherry.Moore@Sun.COM 
6327656SSherry.Moore@Sun.COM 	/*
6337656SSherry.Moore@Sun.COM 	 * Disable the adapter interrupts
6347656SSherry.Moore@Sun.COM 	 */
6357656SSherry.Moore@Sun.COM 	igb_disable_adapter_interrupts(igb);
6367656SSherry.Moore@Sun.COM 
6377656SSherry.Moore@Sun.COM 	/* Tell firmware driver is no longer in control */
6387656SSherry.Moore@Sun.COM 	igb_release_driver_control(hw);
6397656SSherry.Moore@Sun.COM 
6407656SSherry.Moore@Sun.COM 	/*
6417656SSherry.Moore@Sun.COM 	 * Reset the chipset
6427656SSherry.Moore@Sun.COM 	 */
6437656SSherry.Moore@Sun.COM 	(void) e1000_reset_hw(hw);
6447656SSherry.Moore@Sun.COM 
6457656SSherry.Moore@Sun.COM 	/*
6467656SSherry.Moore@Sun.COM 	 * Reset PHY if possible
6477656SSherry.Moore@Sun.COM 	 */
6487656SSherry.Moore@Sun.COM 	if (e1000_check_reset_block(hw) == E1000_SUCCESS)
6497656SSherry.Moore@Sun.COM 		(void) e1000_phy_hw_reset(hw);
6507656SSherry.Moore@Sun.COM 
6517656SSherry.Moore@Sun.COM 	return (DDI_SUCCESS);
6527656SSherry.Moore@Sun.COM }
6537656SSherry.Moore@Sun.COM 
6548955SChenlu.Chen@Sun.COM /*
6558955SChenlu.Chen@Sun.COM  * igb_unconfigure - release all resources held by this instance
6568955SChenlu.Chen@Sun.COM  */
6575779Sxy150489 static void
6585779Sxy150489 igb_unconfigure(dev_info_t *devinfo, igb_t *igb)
6595779Sxy150489 {
6605779Sxy150489 	/*
6615779Sxy150489 	 * Disable interrupt
6625779Sxy150489 	 */
6635779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
6645779Sxy150489 		(void) igb_disable_intrs(igb);
6655779Sxy150489 	}
6665779Sxy150489 
6675779Sxy150489 	/*
6685779Sxy150489 	 * Unregister MAC
6695779Sxy150489 	 */
6705779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_MAC) {
6715779Sxy150489 		(void) mac_unregister(igb->mac_hdl);
6725779Sxy150489 	}
6735779Sxy150489 
6745779Sxy150489 	/*
6755779Sxy150489 	 * Free statistics
6765779Sxy150489 	 */
6775779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_STATS) {
6785779Sxy150489 		kstat_delete((kstat_t *)igb->igb_ks);
6795779Sxy150489 	}
6805779Sxy150489 
6815779Sxy150489 	/*
6825779Sxy150489 	 * Remove interrupt handlers
6835779Sxy150489 	 */
6845779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
6855779Sxy150489 		igb_rem_intr_handlers(igb);
6865779Sxy150489 	}
6875779Sxy150489 
6885779Sxy150489 	/*
6895779Sxy150489 	 * Remove interrupts
6905779Sxy150489 	 */
6915779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
6925779Sxy150489 		igb_rem_intrs(igb);
6935779Sxy150489 	}
6945779Sxy150489 
6955779Sxy150489 	/*
6965779Sxy150489 	 * Remove driver properties
6975779Sxy150489 	 */
6985779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_PROPS) {
6995779Sxy150489 		(void) ddi_prop_remove_all(devinfo);
7005779Sxy150489 	}
7015779Sxy150489 
7025779Sxy150489 	/*
7038955SChenlu.Chen@Sun.COM 	 * Stop the adapter
7045779Sxy150489 	 */
7058955SChenlu.Chen@Sun.COM 	if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) {
7065779Sxy150489 		mutex_enter(&igb->gen_lock);
7078955SChenlu.Chen@Sun.COM 		igb_stop_adapter(igb);
7085779Sxy150489 		mutex_exit(&igb->gen_lock);
7096624Sgl147354 		if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
7106624Sgl147354 			ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED);
7115779Sxy150489 	}
7125779Sxy150489 
7135779Sxy150489 	/*
7149775SVitezslav.Batrla@Sun.COM 	 * Free multicast table
7159775SVitezslav.Batrla@Sun.COM 	 */
7169775SVitezslav.Batrla@Sun.COM 	igb_release_multicast(igb);
7179775SVitezslav.Batrla@Sun.COM 
7189775SVitezslav.Batrla@Sun.COM 	/*
7195779Sxy150489 	 * Free register handle
7205779Sxy150489 	 */
7215779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
7225779Sxy150489 		if (igb->osdep.reg_handle != NULL)
7235779Sxy150489 			ddi_regs_map_free(&igb->osdep.reg_handle);
7245779Sxy150489 	}
7255779Sxy150489 
7265779Sxy150489 	/*
7275779Sxy150489 	 * Free PCI config handle
7285779Sxy150489 	 */
7295779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
7305779Sxy150489 		if (igb->osdep.cfg_handle != NULL)
7315779Sxy150489 			pci_config_teardown(&igb->osdep.cfg_handle);
7325779Sxy150489 	}
7335779Sxy150489 
7345779Sxy150489 	/*
7355779Sxy150489 	 * Free locks
7365779Sxy150489 	 */
7375779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) {
7385779Sxy150489 		igb_destroy_locks(igb);
7395779Sxy150489 	}
7405779Sxy150489 
7415779Sxy150489 	/*
7425779Sxy150489 	 * Free the rx/tx rings
7435779Sxy150489 	 */
7445779Sxy150489 	if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
7455779Sxy150489 		igb_free_rings(igb);
7465779Sxy150489 	}
7475779Sxy150489 
7485779Sxy150489 	/*
7496624Sgl147354 	 * Remove FMA
7506624Sgl147354 	 */
7516624Sgl147354 	if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) {
7526624Sgl147354 		igb_fm_fini(igb);
7536624Sgl147354 	}
7546624Sgl147354 
7556624Sgl147354 	/*
7565779Sxy150489 	 * Free the driver data structure
7575779Sxy150489 	 */
7585779Sxy150489 	kmem_free(igb, sizeof (igb_t));
7595779Sxy150489 
7605779Sxy150489 	ddi_set_driver_private(devinfo, NULL);
7615779Sxy150489 }
7625779Sxy150489 
7635779Sxy150489 /*
7645779Sxy150489  * igb_register_mac - Register the driver and its function pointers with
7655779Sxy150489  * the GLD interface
7665779Sxy150489  */
7675779Sxy150489 static int
7685779Sxy150489 igb_register_mac(igb_t *igb)
7695779Sxy150489 {
7705779Sxy150489 	struct e1000_hw *hw = &igb->hw;
7715779Sxy150489 	mac_register_t *mac;
7725779Sxy150489 	int status;
7735779Sxy150489 
7745779Sxy150489 	if ((mac = mac_alloc(MAC_VERSION)) == NULL)
7755779Sxy150489 		return (IGB_FAILURE);
7765779Sxy150489 
7775779Sxy150489 	mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
7785779Sxy150489 	mac->m_driver = igb;
7795779Sxy150489 	mac->m_dip = igb->dip;
7805779Sxy150489 	mac->m_src_addr = hw->mac.addr;
7815779Sxy150489 	mac->m_callbacks = &igb_m_callbacks;
7825779Sxy150489 	mac->m_min_sdu = 0;
7835779Sxy150489 	mac->m_max_sdu = igb->max_frame_size -
7845779Sxy150489 	    sizeof (struct ether_vlan_header) - ETHERFCSL;
7855895Syz147064 	mac->m_margin = VLAN_TAGSZ;
78611502SChenlu.Chen@Sun.COM 	mac->m_priv_props = igb_priv_props;
78711502SChenlu.Chen@Sun.COM 	mac->m_priv_prop_count = IGB_MAX_PRIV_PROPS;
7888275SEric Cheng 	mac->m_v12n = MAC_VIRT_LEVEL1;
7895779Sxy150489 
7905779Sxy150489 	status = mac_register(mac, &igb->mac_hdl);
7915779Sxy150489 
7925779Sxy150489 	mac_free(mac);
7935779Sxy150489 
7945779Sxy150489 	return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE);
7955779Sxy150489 }
7965779Sxy150489 
7975779Sxy150489 /*
7985779Sxy150489  * igb_identify_hardware - Identify the type of the chipset
7995779Sxy150489  */
8005779Sxy150489 static int
8015779Sxy150489 igb_identify_hardware(igb_t *igb)
8025779Sxy150489 {
8035779Sxy150489 	struct e1000_hw *hw = &igb->hw;
8045779Sxy150489 	struct igb_osdep *osdep = &igb->osdep;
8055779Sxy150489 
8065779Sxy150489 	/*
8075779Sxy150489 	 * Get the device id
8085779Sxy150489 	 */
8095779Sxy150489 	hw->vendor_id =
8105779Sxy150489 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
8115779Sxy150489 	hw->device_id =
8125779Sxy150489 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
8135779Sxy150489 	hw->revision_id =
8145779Sxy150489 	    pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
8155779Sxy150489 	hw->subsystem_device_id =
8165779Sxy150489 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
8175779Sxy150489 	hw->subsystem_vendor_id =
8185779Sxy150489 	    pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
8195779Sxy150489 
8205779Sxy150489 	/*
8215779Sxy150489 	 * Set the mac type of the adapter based on the device id
8225779Sxy150489 	 */
8235779Sxy150489 	if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
8245779Sxy150489 		return (IGB_FAILURE);
8255779Sxy150489 	}
8265779Sxy150489 
8278571SChenlu.Chen@Sun.COM 	/*
8288571SChenlu.Chen@Sun.COM 	 * Install adapter capabilities based on mac type
8298571SChenlu.Chen@Sun.COM 	 */
8308571SChenlu.Chen@Sun.COM 	switch (hw->mac.type) {
8318571SChenlu.Chen@Sun.COM 	case e1000_82575:
8328571SChenlu.Chen@Sun.COM 		igb->capab = &igb_82575_cap;
8338571SChenlu.Chen@Sun.COM 		break;
8348571SChenlu.Chen@Sun.COM 	case e1000_82576:
8358571SChenlu.Chen@Sun.COM 		igb->capab = &igb_82576_cap;
8368571SChenlu.Chen@Sun.COM 		break;
83711155SJason.Xu@Sun.COM 	case e1000_82580:
83811155SJason.Xu@Sun.COM 		igb->capab = &igb_82580_cap;
83911155SJason.Xu@Sun.COM 		break;
8408571SChenlu.Chen@Sun.COM 	default:
8418571SChenlu.Chen@Sun.COM 		return (IGB_FAILURE);
8428571SChenlu.Chen@Sun.COM 	}
8438571SChenlu.Chen@Sun.COM 
8445779Sxy150489 	return (IGB_SUCCESS);
8455779Sxy150489 }
8465779Sxy150489 
8475779Sxy150489 /*
8485779Sxy150489  * igb_regs_map - Map the device registers
8495779Sxy150489  */
8505779Sxy150489 static int
8515779Sxy150489 igb_regs_map(igb_t *igb)
8525779Sxy150489 {
8535779Sxy150489 	dev_info_t *devinfo = igb->dip;
8545779Sxy150489 	struct e1000_hw *hw = &igb->hw;
8555779Sxy150489 	struct igb_osdep *osdep = &igb->osdep;
8565779Sxy150489 	off_t mem_size;
8575779Sxy150489 
8585779Sxy150489 	/*
8595779Sxy150489 	 * First get the size of device registers to be mapped.
8605779Sxy150489 	 */
8618571SChenlu.Chen@Sun.COM 	if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) !=
8628571SChenlu.Chen@Sun.COM 	    DDI_SUCCESS) {
8635779Sxy150489 		return (IGB_FAILURE);
8645779Sxy150489 	}
8655779Sxy150489 
8665779Sxy150489 	/*
8675779Sxy150489 	 * Call ddi_regs_map_setup() to map registers
8685779Sxy150489 	 */
8698571SChenlu.Chen@Sun.COM 	if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET,
8705779Sxy150489 	    (caddr_t *)&hw->hw_addr, 0,
8715779Sxy150489 	    mem_size, &igb_regs_acc_attr,
8725779Sxy150489 	    &osdep->reg_handle)) != DDI_SUCCESS) {
8735779Sxy150489 		return (IGB_FAILURE);
8745779Sxy150489 	}
8755779Sxy150489 
8765779Sxy150489 	return (IGB_SUCCESS);
8775779Sxy150489 }
8785779Sxy150489 
8795779Sxy150489 /*
8805779Sxy150489  * igb_init_properties - Initialize driver properties
8815779Sxy150489  */
8825779Sxy150489 static void
8835779Sxy150489 igb_init_properties(igb_t *igb)
8845779Sxy150489 {
8855779Sxy150489 	/*
8865779Sxy150489 	 * Get conf file properties, including link settings
8875779Sxy150489 	 * jumbo frames, ring number, descriptor number, etc.
8885779Sxy150489 	 */
8895779Sxy150489 	igb_get_conf(igb);
8905779Sxy150489 }
8915779Sxy150489 
8925779Sxy150489 /*
8935779Sxy150489  * igb_init_driver_settings - Initialize driver settings
8945779Sxy150489  *
8955779Sxy150489  * The settings include hardware function pointers, bus information,
8965779Sxy150489  * rx/tx rings settings, link state, and any other parameters that
8975779Sxy150489  * need to be setup during driver initialization.
8985779Sxy150489  */
8995779Sxy150489 static int
9005779Sxy150489 igb_init_driver_settings(igb_t *igb)
9015779Sxy150489 {
9025779Sxy150489 	struct e1000_hw *hw = &igb->hw;
9035779Sxy150489 	igb_rx_ring_t *rx_ring;
9045779Sxy150489 	igb_tx_ring_t *tx_ring;
9055779Sxy150489 	uint32_t rx_size;
9065779Sxy150489 	uint32_t tx_size;
9075779Sxy150489 	int i;
9085779Sxy150489 
9095779Sxy150489 	/*
9105779Sxy150489 	 * Initialize chipset specific hardware function pointers
9115779Sxy150489 	 */
9125779Sxy150489 	if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
9135779Sxy150489 		return (IGB_FAILURE);
9145779Sxy150489 	}
9155779Sxy150489 
9165779Sxy150489 	/*
9175779Sxy150489 	 * Get bus information
9185779Sxy150489 	 */
9195779Sxy150489 	if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
9205779Sxy150489 		return (IGB_FAILURE);
9215779Sxy150489 	}
9225779Sxy150489 
9235779Sxy150489 	/*
9249188SPaul.Guo@Sun.COM 	 * Get the system page size
9259188SPaul.Guo@Sun.COM 	 */
9269188SPaul.Guo@Sun.COM 	igb->page_size = ddi_ptob(igb->dip, (ulong_t)1);
9279188SPaul.Guo@Sun.COM 
9289188SPaul.Guo@Sun.COM 	/*
9295779Sxy150489 	 * Set rx buffer size
9305779Sxy150489 	 * The IP header alignment room is counted in the calculation.
9315779Sxy150489 	 * The rx buffer size is in unit of 1K that is required by the
9325779Sxy150489 	 * chipset hardware.
9335779Sxy150489 	 */
9345779Sxy150489 	rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
9355779Sxy150489 	igb->rx_buf_size = ((rx_size >> 10) +
9365779Sxy150489 	    ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
9375779Sxy150489 
9385779Sxy150489 	/*
9395779Sxy150489 	 * Set tx buffer size
9405779Sxy150489 	 */
9415779Sxy150489 	tx_size = igb->max_frame_size;
9425779Sxy150489 	igb->tx_buf_size = ((tx_size >> 10) +
9435779Sxy150489 	    ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
9445779Sxy150489 
9455779Sxy150489 	/*
9465779Sxy150489 	 * Initialize rx/tx rings parameters
9475779Sxy150489 	 */
9485779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++) {
9495779Sxy150489 		rx_ring = &igb->rx_rings[i];
9505779Sxy150489 		rx_ring->index = i;
9515779Sxy150489 		rx_ring->igb = igb;
9525779Sxy150489 	}
9535779Sxy150489 
9545779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
9555779Sxy150489 		tx_ring = &igb->tx_rings[i];
9565779Sxy150489 		tx_ring->index = i;
9575779Sxy150489 		tx_ring->igb = igb;
9585779Sxy150489 		if (igb->tx_head_wb_enable)
9595779Sxy150489 			tx_ring->tx_recycle = igb_tx_recycle_head_wb;
9605779Sxy150489 		else
9615779Sxy150489 			tx_ring->tx_recycle = igb_tx_recycle_legacy;
9625779Sxy150489 
9635779Sxy150489 		tx_ring->ring_size = igb->tx_ring_size;
9645779Sxy150489 		tx_ring->free_list_size = igb->tx_ring_size +
9655779Sxy150489 		    (igb->tx_ring_size >> 1);
9665779Sxy150489 	}
9675779Sxy150489 
9685779Sxy150489 	/*
9698571SChenlu.Chen@Sun.COM 	 * Initialize values of interrupt throttling rates
9705779Sxy150489 	 */
9715779Sxy150489 	for (i = 1; i < MAX_NUM_EITR; i++)
9725779Sxy150489 		igb->intr_throttling[i] = igb->intr_throttling[0];
9735779Sxy150489 
9745779Sxy150489 	/*
9755779Sxy150489 	 * The initial link state should be "unknown"
9765779Sxy150489 	 */
9775779Sxy150489 	igb->link_state = LINK_STATE_UNKNOWN;
9785779Sxy150489 
9795779Sxy150489 	return (IGB_SUCCESS);
9805779Sxy150489 }
9815779Sxy150489 
9825779Sxy150489 /*
9835779Sxy150489  * igb_init_locks - Initialize locks
9845779Sxy150489  */
9855779Sxy150489 static void
9865779Sxy150489 igb_init_locks(igb_t *igb)
9875779Sxy150489 {
9885779Sxy150489 	igb_rx_ring_t *rx_ring;
9895779Sxy150489 	igb_tx_ring_t *tx_ring;
9905779Sxy150489 	int i;
9915779Sxy150489 
9925779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++) {
9935779Sxy150489 		rx_ring = &igb->rx_rings[i];
9945779Sxy150489 		mutex_init(&rx_ring->rx_lock, NULL,
9955779Sxy150489 		    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
9965779Sxy150489 	}
9975779Sxy150489 
9985779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
9995779Sxy150489 		tx_ring = &igb->tx_rings[i];
10005779Sxy150489 		mutex_init(&tx_ring->tx_lock, NULL,
10015779Sxy150489 		    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10025779Sxy150489 		mutex_init(&tx_ring->recycle_lock, NULL,
10035779Sxy150489 		    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10045779Sxy150489 		mutex_init(&tx_ring->tcb_head_lock, NULL,
10055779Sxy150489 		    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10065779Sxy150489 		mutex_init(&tx_ring->tcb_tail_lock, NULL,
10075779Sxy150489 		    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10085779Sxy150489 	}
10095779Sxy150489 
10105779Sxy150489 	mutex_init(&igb->gen_lock, NULL,
10115779Sxy150489 	    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10125779Sxy150489 
10135779Sxy150489 	mutex_init(&igb->watchdog_lock, NULL,
10145779Sxy150489 	    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
101511367SJason.Xu@Sun.COM 
101611367SJason.Xu@Sun.COM 	mutex_init(&igb->link_lock, NULL,
101711367SJason.Xu@Sun.COM 	    MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
10185779Sxy150489 }
10195779Sxy150489 
10205779Sxy150489 /*
10215779Sxy150489  * igb_destroy_locks - Destroy locks
10225779Sxy150489  */
10235779Sxy150489 static void
10245779Sxy150489 igb_destroy_locks(igb_t *igb)
10255779Sxy150489 {
10265779Sxy150489 	igb_rx_ring_t *rx_ring;
10275779Sxy150489 	igb_tx_ring_t *tx_ring;
10285779Sxy150489 	int i;
10295779Sxy150489 
10305779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++) {
10315779Sxy150489 		rx_ring = &igb->rx_rings[i];
10325779Sxy150489 		mutex_destroy(&rx_ring->rx_lock);
10335779Sxy150489 	}
10345779Sxy150489 
10355779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
10365779Sxy150489 		tx_ring = &igb->tx_rings[i];
10375779Sxy150489 		mutex_destroy(&tx_ring->tx_lock);
10385779Sxy150489 		mutex_destroy(&tx_ring->recycle_lock);
10395779Sxy150489 		mutex_destroy(&tx_ring->tcb_head_lock);
10405779Sxy150489 		mutex_destroy(&tx_ring->tcb_tail_lock);
10415779Sxy150489 	}
10425779Sxy150489 
10435779Sxy150489 	mutex_destroy(&igb->gen_lock);
10445779Sxy150489 	mutex_destroy(&igb->watchdog_lock);
104511367SJason.Xu@Sun.COM 	mutex_destroy(&igb->link_lock);
10465779Sxy150489 }
10475779Sxy150489 
10485779Sxy150489 static int
10495779Sxy150489 igb_resume(dev_info_t *devinfo)
10505779Sxy150489 {
10515779Sxy150489 	igb_t *igb;
10525779Sxy150489 
10535779Sxy150489 	igb = (igb_t *)ddi_get_driver_private(devinfo);
10545779Sxy150489 	if (igb == NULL)
10555779Sxy150489 		return (DDI_FAILURE);
10565779Sxy150489 
10575779Sxy150489 	mutex_enter(&igb->gen_lock);
10585779Sxy150489 
10595779Sxy150489 	if (igb->igb_state & IGB_STARTED) {
106011502SChenlu.Chen@Sun.COM 		if (igb_start(igb, B_FALSE) != IGB_SUCCESS) {
10615779Sxy150489 			mutex_exit(&igb->gen_lock);
10625779Sxy150489 			return (DDI_FAILURE);
10635779Sxy150489 		}
10645779Sxy150489 
10655779Sxy150489 		/*
10665779Sxy150489 		 * Enable and start the watchdog timer
10675779Sxy150489 		 */
10685779Sxy150489 		igb_enable_watchdog_timer(igb);
10695779Sxy150489 	}
10705779Sxy150489 
107111367SJason.Xu@Sun.COM 	atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED);
10725779Sxy150489 
10735779Sxy150489 	mutex_exit(&igb->gen_lock);
10745779Sxy150489 
10755779Sxy150489 	return (DDI_SUCCESS);
10765779Sxy150489 }
10775779Sxy150489 
10785779Sxy150489 static int
10795779Sxy150489 igb_suspend(dev_info_t *devinfo)
10805779Sxy150489 {
10815779Sxy150489 	igb_t *igb;
10825779Sxy150489 
10835779Sxy150489 	igb = (igb_t *)ddi_get_driver_private(devinfo);
10845779Sxy150489 	if (igb == NULL)
10855779Sxy150489 		return (DDI_FAILURE);
10865779Sxy150489 
10875779Sxy150489 	mutex_enter(&igb->gen_lock);
10885779Sxy150489 
108911367SJason.Xu@Sun.COM 	atomic_or_32(&igb->igb_state, IGB_SUSPENDED);
10905779Sxy150489 
10918955SChenlu.Chen@Sun.COM 	if (!(igb->igb_state & IGB_STARTED)) {
10928955SChenlu.Chen@Sun.COM 		mutex_exit(&igb->gen_lock);
10938955SChenlu.Chen@Sun.COM 		return (DDI_SUCCESS);
10948955SChenlu.Chen@Sun.COM 	}
10958955SChenlu.Chen@Sun.COM 
109611502SChenlu.Chen@Sun.COM 	igb_stop(igb, B_FALSE);
10975779Sxy150489 
10985779Sxy150489 	mutex_exit(&igb->gen_lock);
10995779Sxy150489 
11005779Sxy150489 	/*
11015779Sxy150489 	 * Disable and stop the watchdog timer
11025779Sxy150489 	 */
11035779Sxy150489 	igb_disable_watchdog_timer(igb);
11045779Sxy150489 
11055779Sxy150489 	return (DDI_SUCCESS);
11065779Sxy150489 }
11075779Sxy150489 
11085779Sxy150489 static int
11095779Sxy150489 igb_init(igb_t *igb)
11105779Sxy150489 {
11118955SChenlu.Chen@Sun.COM 	mutex_enter(&igb->gen_lock);
11128955SChenlu.Chen@Sun.COM 
11138955SChenlu.Chen@Sun.COM 	/*
11148955SChenlu.Chen@Sun.COM 	 * Initilize the adapter
11158955SChenlu.Chen@Sun.COM 	 */
11168955SChenlu.Chen@Sun.COM 	if (igb_init_adapter(igb) != IGB_SUCCESS) {
11178955SChenlu.Chen@Sun.COM 		mutex_exit(&igb->gen_lock);
11188955SChenlu.Chen@Sun.COM 		igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
11198955SChenlu.Chen@Sun.COM 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
11208955SChenlu.Chen@Sun.COM 		return (IGB_FAILURE);
11218955SChenlu.Chen@Sun.COM 	}
11228955SChenlu.Chen@Sun.COM 
11238955SChenlu.Chen@Sun.COM 	mutex_exit(&igb->gen_lock);
11248955SChenlu.Chen@Sun.COM 
11258955SChenlu.Chen@Sun.COM 	return (IGB_SUCCESS);
11268955SChenlu.Chen@Sun.COM }
11278955SChenlu.Chen@Sun.COM 
11288955SChenlu.Chen@Sun.COM /*
11298955SChenlu.Chen@Sun.COM  * igb_init_mac_address - Initialize the default MAC address
11308955SChenlu.Chen@Sun.COM  *
11318955SChenlu.Chen@Sun.COM  * On success, the MAC address is entered in the igb->hw.mac.addr
11328955SChenlu.Chen@Sun.COM  * and hw->mac.perm_addr fields and the adapter's RAR(0) receive
11338955SChenlu.Chen@Sun.COM  * address register.
11348955SChenlu.Chen@Sun.COM  *
11358955SChenlu.Chen@Sun.COM  * Important side effects:
11368955SChenlu.Chen@Sun.COM  * 1. adapter is reset - this is required to put it in a known state.
11378955SChenlu.Chen@Sun.COM  * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where
11388955SChenlu.Chen@Sun.COM  * MAC address and all default settings are stored, so a valid checksum
11398955SChenlu.Chen@Sun.COM  * is required.
11408955SChenlu.Chen@Sun.COM  */
11418955SChenlu.Chen@Sun.COM static int
11428955SChenlu.Chen@Sun.COM igb_init_mac_address(igb_t *igb)
11438955SChenlu.Chen@Sun.COM {
11445779Sxy150489 	struct e1000_hw *hw = &igb->hw;
11455779Sxy150489 
11468275SEric Cheng 	ASSERT(mutex_owned(&igb->gen_lock));
11475779Sxy150489 
11485779Sxy150489 	/*
11495779Sxy150489 	 * Reset chipset to put the hardware in a known state
11508955SChenlu.Chen@Sun.COM 	 * before we try to get MAC address from NVM.
11515779Sxy150489 	 */
11526624Sgl147354 	if (e1000_reset_hw(hw) != E1000_SUCCESS) {
11538955SChenlu.Chen@Sun.COM 		igb_error(igb, "Adapter reset failed.");
11548955SChenlu.Chen@Sun.COM 		goto init_mac_fail;
11556624Sgl147354 	}
11565779Sxy150489 
11575779Sxy150489 	/*
11585779Sxy150489 	 * NVM validation
11595779Sxy150489 	 */
11605779Sxy150489 	if (e1000_validate_nvm_checksum(hw) < 0) {
11615779Sxy150489 		/*
11625779Sxy150489 		 * Some PCI-E parts fail the first check due to
11635779Sxy150489 		 * the link being in sleep state.  Call it again,
11645779Sxy150489 		 * if it fails a second time its a real issue.
11655779Sxy150489 		 */
11665779Sxy150489 		if (e1000_validate_nvm_checksum(hw) < 0) {
11675779Sxy150489 			igb_error(igb,
11685779Sxy150489 			    "Invalid NVM checksum. Please contact "
11695779Sxy150489 			    "the vendor to update the NVM.");
11708955SChenlu.Chen@Sun.COM 			goto init_mac_fail;
11715779Sxy150489 		}
11725779Sxy150489 	}
11735779Sxy150489 
11745779Sxy150489 	/*
11758955SChenlu.Chen@Sun.COM 	 * Get the mac address
11768955SChenlu.Chen@Sun.COM 	 * This function should handle SPARC case correctly.
11778955SChenlu.Chen@Sun.COM 	 */
11788955SChenlu.Chen@Sun.COM 	if (!igb_find_mac_address(igb)) {
11798955SChenlu.Chen@Sun.COM 		igb_error(igb, "Failed to get the mac address");
11808955SChenlu.Chen@Sun.COM 		goto init_mac_fail;
11818955SChenlu.Chen@Sun.COM 	}
11828955SChenlu.Chen@Sun.COM 
11838955SChenlu.Chen@Sun.COM 	/* Validate mac address */
11848955SChenlu.Chen@Sun.COM 	if (!is_valid_mac_addr(hw->mac.addr)) {
11858955SChenlu.Chen@Sun.COM 		igb_error(igb, "Invalid mac address");
11868955SChenlu.Chen@Sun.COM 		goto init_mac_fail;
11878955SChenlu.Chen@Sun.COM 	}
11888955SChenlu.Chen@Sun.COM 
11898955SChenlu.Chen@Sun.COM 	return (IGB_SUCCESS);
11908955SChenlu.Chen@Sun.COM 
11918955SChenlu.Chen@Sun.COM init_mac_fail:
11928955SChenlu.Chen@Sun.COM 	return (IGB_FAILURE);
11938955SChenlu.Chen@Sun.COM }
11948955SChenlu.Chen@Sun.COM 
11958955SChenlu.Chen@Sun.COM /*
11968955SChenlu.Chen@Sun.COM  * igb_init_adapter - Initialize the adapter
11978955SChenlu.Chen@Sun.COM  */
11988955SChenlu.Chen@Sun.COM static int
11998955SChenlu.Chen@Sun.COM igb_init_adapter(igb_t *igb)
12008955SChenlu.Chen@Sun.COM {
12018955SChenlu.Chen@Sun.COM 	struct e1000_hw *hw = &igb->hw;
12028955SChenlu.Chen@Sun.COM 	uint32_t pba;
12038955SChenlu.Chen@Sun.COM 	uint32_t high_water;
12048955SChenlu.Chen@Sun.COM 	int i;
12058955SChenlu.Chen@Sun.COM 
12068955SChenlu.Chen@Sun.COM 	ASSERT(mutex_owned(&igb->gen_lock));
12078955SChenlu.Chen@Sun.COM 
12088955SChenlu.Chen@Sun.COM 	/*
12098955SChenlu.Chen@Sun.COM 	 * In order to obtain the default MAC address, this will reset the
12108955SChenlu.Chen@Sun.COM 	 * adapter and validate the NVM that the address and many other
12118955SChenlu.Chen@Sun.COM 	 * default settings come from.
12128955SChenlu.Chen@Sun.COM 	 */
12138955SChenlu.Chen@Sun.COM 	if (igb_init_mac_address(igb) != IGB_SUCCESS) {
12148955SChenlu.Chen@Sun.COM 		igb_error(igb, "Failed to initialize MAC address");
12158955SChenlu.Chen@Sun.COM 		goto init_adapter_fail;
12168955SChenlu.Chen@Sun.COM 	}
12178955SChenlu.Chen@Sun.COM 
12188955SChenlu.Chen@Sun.COM 	/*
12195779Sxy150489 	 * Setup flow control
12205779Sxy150489 	 *
12215779Sxy150489 	 * These parameters set thresholds for the adapter's generation(Tx)
12225779Sxy150489 	 * and response(Rx) to Ethernet PAUSE frames.  These are just threshold
12235779Sxy150489 	 * settings.  Flow control is enabled or disabled in the configuration
12245779Sxy150489 	 * file.
12255779Sxy150489 	 * High-water mark is set down from the top of the rx fifo (not
12265779Sxy150489 	 * sensitive to max_frame_size) and low-water is set just below
12275779Sxy150489 	 * high-water mark.
12285779Sxy150489 	 * The high water mark must be low enough to fit one full frame above
12295779Sxy150489 	 * it in the rx FIFO.  Should be the lower of:
12305779Sxy150489 	 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full
12315779Sxy150489 	 * frame.
12325779Sxy150489 	 */
12338955SChenlu.Chen@Sun.COM 	/*
12348955SChenlu.Chen@Sun.COM 	 * The default setting of PBA is correct for 82575 and other supported
12358955SChenlu.Chen@Sun.COM 	 * adapters do not have the E1000_PBA register, so PBA value is only
12368955SChenlu.Chen@Sun.COM 	 * used for calculation here and is never written to the adapter.
12378955SChenlu.Chen@Sun.COM 	 */
12388571SChenlu.Chen@Sun.COM 	if (hw->mac.type == e1000_82575) {
12398571SChenlu.Chen@Sun.COM 		pba = E1000_PBA_34K;
12408571SChenlu.Chen@Sun.COM 	} else {
12418571SChenlu.Chen@Sun.COM 		pba = E1000_PBA_64K;
12428571SChenlu.Chen@Sun.COM 	}
12438571SChenlu.Chen@Sun.COM 
12445779Sxy150489 	high_water = min(((pba << 10) * 9 / 10),
12455779Sxy150489 	    ((pba << 10) - igb->max_frame_size));
12465779Sxy150489 
12478571SChenlu.Chen@Sun.COM 	if (hw->mac.type == e1000_82575) {
12488571SChenlu.Chen@Sun.COM 		/* 8-byte granularity */
12498571SChenlu.Chen@Sun.COM 		hw->fc.high_water = high_water & 0xFFF8;
12508571SChenlu.Chen@Sun.COM 		hw->fc.low_water = hw->fc.high_water - 8;
12518571SChenlu.Chen@Sun.COM 	} else {
12528571SChenlu.Chen@Sun.COM 		/* 16-byte granularity */
12538571SChenlu.Chen@Sun.COM 		hw->fc.high_water = high_water & 0xFFF0;
12548571SChenlu.Chen@Sun.COM 		hw->fc.low_water = hw->fc.high_water - 16;
12558571SChenlu.Chen@Sun.COM 	}
12568571SChenlu.Chen@Sun.COM 
12575779Sxy150489 	hw->fc.pause_time = E1000_FC_PAUSE_TIME;
12585779Sxy150489 	hw->fc.send_xon = B_TRUE;
12595779Sxy150489 
126011155SJason.Xu@Sun.COM 	(void) e1000_validate_mdi_setting(hw);
12618955SChenlu.Chen@Sun.COM 
12625779Sxy150489 	/*
12638955SChenlu.Chen@Sun.COM 	 * Reset the chipset hardware the second time to put PBA settings
12648955SChenlu.Chen@Sun.COM 	 * into effect.
12655779Sxy150489 	 */
12666624Sgl147354 	if (e1000_reset_hw(hw) != E1000_SUCCESS) {
12678955SChenlu.Chen@Sun.COM 		igb_error(igb, "Second reset failed");
12688955SChenlu.Chen@Sun.COM 		goto init_adapter_fail;
12696624Sgl147354 	}
12705779Sxy150489 
12715779Sxy150489 	/*
12725779Sxy150489 	 * Don't wait for auto-negotiation to complete
12735779Sxy150489 	 */
12745779Sxy150489 	hw->phy.autoneg_wait_to_complete = B_FALSE;
12755779Sxy150489 
12765779Sxy150489 	/*
12775779Sxy150489 	 * Copper options
12785779Sxy150489 	 */
12795779Sxy150489 	if (hw->phy.media_type == e1000_media_type_copper) {
12805779Sxy150489 		hw->phy.mdix = 0;	/* AUTO_ALL_MODES */
12815779Sxy150489 		hw->phy.disable_polarity_correction = B_FALSE;
12825779Sxy150489 		hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
12835779Sxy150489 	}
12845779Sxy150489 
12855779Sxy150489 	/*
12865779Sxy150489 	 * Initialize link settings
12875779Sxy150489 	 */
12885779Sxy150489 	(void) igb_setup_link(igb, B_FALSE);
12895779Sxy150489 
12905779Sxy150489 	/*
12915779Sxy150489 	 * Configure/Initialize hardware
12925779Sxy150489 	 */
12935779Sxy150489 	if (e1000_init_hw(hw) != E1000_SUCCESS) {
12945779Sxy150489 		igb_error(igb, "Failed to initialize hardware");
12958955SChenlu.Chen@Sun.COM 		goto init_adapter_fail;
12965779Sxy150489 	}
12975779Sxy150489 
12985779Sxy150489 	/*
129911367SJason.Xu@Sun.COM 	 *  Start the link setup timer
130011367SJason.Xu@Sun.COM 	 */
130111367SJason.Xu@Sun.COM 	igb_start_link_timer(igb);
130211367SJason.Xu@Sun.COM 
130311367SJason.Xu@Sun.COM 	/*
13048955SChenlu.Chen@Sun.COM 	 * Disable wakeup control by default
13058955SChenlu.Chen@Sun.COM 	 */
13068955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_WUC, 0);
13078955SChenlu.Chen@Sun.COM 
13088955SChenlu.Chen@Sun.COM 	/*
13098955SChenlu.Chen@Sun.COM 	 * Record phy info in hw struct
13108955SChenlu.Chen@Sun.COM 	 */
13118955SChenlu.Chen@Sun.COM 	(void) e1000_get_phy_info(hw);
13128955SChenlu.Chen@Sun.COM 
13138955SChenlu.Chen@Sun.COM 	/*
13145779Sxy150489 	 * Make sure driver has control
13155779Sxy150489 	 */
13165779Sxy150489 	igb_get_driver_control(hw);
13175779Sxy150489 
13185779Sxy150489 	/*
13198955SChenlu.Chen@Sun.COM 	 * Restore LED settings to the default from EEPROM
13208955SChenlu.Chen@Sun.COM 	 * to meet the standard for Sun platforms.
13218955SChenlu.Chen@Sun.COM 	 */
13228955SChenlu.Chen@Sun.COM 	(void) e1000_cleanup_led(hw);
13238955SChenlu.Chen@Sun.COM 
13248955SChenlu.Chen@Sun.COM 	/*
13255779Sxy150489 	 * Setup MSI-X interrupts
13265779Sxy150489 	 */
13275779Sxy150489 	if (igb->intr_type == DDI_INTR_TYPE_MSIX)
13288571SChenlu.Chen@Sun.COM 		igb->capab->setup_msix(igb);
13295779Sxy150489 
13305779Sxy150489 	/*
13315779Sxy150489 	 * Initialize unicast addresses.
13325779Sxy150489 	 */
13335779Sxy150489 	igb_init_unicst(igb);
13345779Sxy150489 
13355779Sxy150489 	/*
13365779Sxy150489 	 * Setup and initialize the mctable structures.
13375779Sxy150489 	 */
13385779Sxy150489 	igb_setup_multicst(igb);
13395779Sxy150489 
13405779Sxy150489 	/*
13415779Sxy150489 	 * Set interrupt throttling rate
13425779Sxy150489 	 */
13435779Sxy150489 	for (i = 0; i < igb->intr_cnt; i++)
13445779Sxy150489 		E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]);
13455779Sxy150489 
13465779Sxy150489 	/*
13475779Sxy150489 	 * Save the state of the phy
13485779Sxy150489 	 */
13495779Sxy150489 	igb_get_phy_state(igb);
13505779Sxy150489 
135111502SChenlu.Chen@Sun.COM 	igb_param_sync(igb);
135211502SChenlu.Chen@Sun.COM 
13535779Sxy150489 	return (IGB_SUCCESS);
13548955SChenlu.Chen@Sun.COM 
13558955SChenlu.Chen@Sun.COM init_adapter_fail:
13568955SChenlu.Chen@Sun.COM 	/*
13578955SChenlu.Chen@Sun.COM 	 * Reset PHY if possible
13588955SChenlu.Chen@Sun.COM 	 */
13598955SChenlu.Chen@Sun.COM 	if (e1000_check_reset_block(hw) == E1000_SUCCESS)
13608955SChenlu.Chen@Sun.COM 		(void) e1000_phy_hw_reset(hw);
13618955SChenlu.Chen@Sun.COM 
13628955SChenlu.Chen@Sun.COM 	return (IGB_FAILURE);
13635779Sxy150489 }
13645779Sxy150489 
13655779Sxy150489 /*
13668955SChenlu.Chen@Sun.COM  * igb_stop_adapter - Stop the adapter
13675779Sxy150489  */
13685779Sxy150489 static void
13698955SChenlu.Chen@Sun.COM igb_stop_adapter(igb_t *igb)
13705779Sxy150489 {
13715779Sxy150489 	struct e1000_hw *hw = &igb->hw;
13725779Sxy150489 
13735779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
13745779Sxy150489 
137511367SJason.Xu@Sun.COM 	/* Stop the link setup timer */
137611367SJason.Xu@Sun.COM 	igb_stop_link_timer(igb);
137711367SJason.Xu@Sun.COM 
13785779Sxy150489 	/* Tell firmware driver is no longer in control */
13795779Sxy150489 	igb_release_driver_control(hw);
13805779Sxy150489 
13815779Sxy150489 	/*
13825779Sxy150489 	 * Reset the chipset
13835779Sxy150489 	 */
13846624Sgl147354 	if (e1000_reset_hw(hw) != E1000_SUCCESS) {
13856624Sgl147354 		igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
13866624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
13876624Sgl147354 	}
13885779Sxy150489 
13895779Sxy150489 	/*
13908955SChenlu.Chen@Sun.COM 	 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient
13915779Sxy150489 	 */
13925779Sxy150489 }
13935779Sxy150489 
13945779Sxy150489 /*
13955779Sxy150489  * igb_reset - Reset the chipset and restart the driver.
13965779Sxy150489  *
13975779Sxy150489  * It involves stopping and re-starting the chipset,
13985779Sxy150489  * and re-configuring the rx/tx rings.
13995779Sxy150489  */
14005779Sxy150489 static int
14015779Sxy150489 igb_reset(igb_t *igb)
14025779Sxy150489 {
14035779Sxy150489 	int i;
14045779Sxy150489 
14055779Sxy150489 	mutex_enter(&igb->gen_lock);
14065779Sxy150489 
14075779Sxy150489 	ASSERT(igb->igb_state & IGB_STARTED);
140811367SJason.Xu@Sun.COM 	atomic_and_32(&igb->igb_state, ~IGB_STARTED);
14095779Sxy150489 
14105779Sxy150489 	/*
14115779Sxy150489 	 * Disable the adapter interrupts to stop any rx/tx activities
14125779Sxy150489 	 * before draining pending data and resetting hardware.
14135779Sxy150489 	 */
14145779Sxy150489 	igb_disable_adapter_interrupts(igb);
14155779Sxy150489 
14165779Sxy150489 	/*
14175779Sxy150489 	 * Drain the pending transmit packets
14185779Sxy150489 	 */
14195779Sxy150489 	(void) igb_tx_drain(igb);
14205779Sxy150489 
14215779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++)
14225779Sxy150489 		mutex_enter(&igb->rx_rings[i].rx_lock);
14235779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++)
14245779Sxy150489 		mutex_enter(&igb->tx_rings[i].tx_lock);
14255779Sxy150489 
14265779Sxy150489 	/*
14278955SChenlu.Chen@Sun.COM 	 * Stop the adapter
14285779Sxy150489 	 */
14298955SChenlu.Chen@Sun.COM 	igb_stop_adapter(igb);
14305779Sxy150489 
14315779Sxy150489 	/*
14325779Sxy150489 	 * Clean the pending tx data/resources
14335779Sxy150489 	 */
14345779Sxy150489 	igb_tx_clean(igb);
14355779Sxy150489 
14365779Sxy150489 	/*
14378955SChenlu.Chen@Sun.COM 	 * Start the adapter
14385779Sxy150489 	 */
14398955SChenlu.Chen@Sun.COM 	if (igb_init_adapter(igb) != IGB_SUCCESS) {
14406624Sgl147354 		igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
14415779Sxy150489 		goto reset_failure;
14425779Sxy150489 	}
14435779Sxy150489 
14445779Sxy150489 	/*
14455779Sxy150489 	 * Setup the rx/tx rings
14465779Sxy150489 	 */
144711502SChenlu.Chen@Sun.COM 	igb->tx_ring_init = B_FALSE;
14485779Sxy150489 	igb_setup_rings(igb);
14495779Sxy150489 
145011367SJason.Xu@Sun.COM 	atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL));
145111367SJason.Xu@Sun.COM 
14525779Sxy150489 	/*
14535779Sxy150489 	 * Enable adapter interrupts
14545779Sxy150489 	 * The interrupts must be enabled after the driver state is START
14555779Sxy150489 	 */
14568571SChenlu.Chen@Sun.COM 	igb->capab->enable_intr(igb);
14575779Sxy150489 
14586624Sgl147354 	if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
14596624Sgl147354 		goto reset_failure;
14606624Sgl147354 
14616624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
14626624Sgl147354 		goto reset_failure;
14636624Sgl147354 
14645779Sxy150489 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
14655779Sxy150489 		mutex_exit(&igb->tx_rings[i].tx_lock);
14665779Sxy150489 	for (i = igb->num_rx_rings - 1; i >= 0; i--)
14675779Sxy150489 		mutex_exit(&igb->rx_rings[i].rx_lock);
14685779Sxy150489 
146911367SJason.Xu@Sun.COM 	atomic_or_32(&igb->igb_state, IGB_STARTED);
147011367SJason.Xu@Sun.COM 
14715779Sxy150489 	mutex_exit(&igb->gen_lock);
14725779Sxy150489 
14735779Sxy150489 	return (IGB_SUCCESS);
14745779Sxy150489 
14755779Sxy150489 reset_failure:
14765779Sxy150489 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
14775779Sxy150489 		mutex_exit(&igb->tx_rings[i].tx_lock);
14785779Sxy150489 	for (i = igb->num_rx_rings - 1; i >= 0; i--)
14795779Sxy150489 		mutex_exit(&igb->rx_rings[i].rx_lock);
14805779Sxy150489 
14815779Sxy150489 	mutex_exit(&igb->gen_lock);
14825779Sxy150489 
14836624Sgl147354 	ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
14846624Sgl147354 
14855779Sxy150489 	return (IGB_FAILURE);
14865779Sxy150489 }
14875779Sxy150489 
14885779Sxy150489 /*
14895779Sxy150489  * igb_tx_clean - Clean the pending transmit packets and DMA resources
14905779Sxy150489  */
14915779Sxy150489 static void
14925779Sxy150489 igb_tx_clean(igb_t *igb)
14935779Sxy150489 {
14945779Sxy150489 	igb_tx_ring_t *tx_ring;
14955779Sxy150489 	tx_control_block_t *tcb;
14965779Sxy150489 	link_list_t pending_list;
14975779Sxy150489 	uint32_t desc_num;
14985779Sxy150489 	int i, j;
14995779Sxy150489 
15005779Sxy150489 	LINK_LIST_INIT(&pending_list);
15015779Sxy150489 
15025779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
15035779Sxy150489 		tx_ring = &igb->tx_rings[i];
15045779Sxy150489 
15055779Sxy150489 		mutex_enter(&tx_ring->recycle_lock);
15065779Sxy150489 
15075779Sxy150489 		/*
15085779Sxy150489 		 * Clean the pending tx data - the pending packets in the
15095779Sxy150489 		 * work_list that have no chances to be transmitted again.
15105779Sxy150489 		 *
15115779Sxy150489 		 * We must ensure the chipset is stopped or the link is down
15125779Sxy150489 		 * before cleaning the transmit packets.
15135779Sxy150489 		 */
15145779Sxy150489 		desc_num = 0;
15155779Sxy150489 		for (j = 0; j < tx_ring->ring_size; j++) {
15165779Sxy150489 			tcb = tx_ring->work_list[j];
15175779Sxy150489 			if (tcb != NULL) {
15185779Sxy150489 				desc_num += tcb->desc_num;
15195779Sxy150489 
15205779Sxy150489 				tx_ring->work_list[j] = NULL;
15215779Sxy150489 
15225779Sxy150489 				igb_free_tcb(tcb);
15235779Sxy150489 
15245779Sxy150489 				LIST_PUSH_TAIL(&pending_list, &tcb->link);
15255779Sxy150489 			}
15265779Sxy150489 		}
15275779Sxy150489 
15285779Sxy150489 		if (desc_num > 0) {
15295779Sxy150489 			atomic_add_32(&tx_ring->tbd_free, desc_num);
15305779Sxy150489 			ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
15315779Sxy150489 
15325779Sxy150489 			/*
15337072Sxy150489 			 * Reset the head and tail pointers of the tbd ring;
15347072Sxy150489 			 * Reset the head write-back if it is enabled.
15355779Sxy150489 			 */
15365779Sxy150489 			tx_ring->tbd_head = 0;
15375779Sxy150489 			tx_ring->tbd_tail = 0;
15387072Sxy150489 			if (igb->tx_head_wb_enable)
15397072Sxy150489 				*tx_ring->tbd_head_wb = 0;
15405779Sxy150489 
15415779Sxy150489 			E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0);
15425779Sxy150489 			E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0);
15435779Sxy150489 		}
15445779Sxy150489 
15455779Sxy150489 		mutex_exit(&tx_ring->recycle_lock);
15465779Sxy150489 
15475779Sxy150489 		/*
15485779Sxy150489 		 * Add the tx control blocks in the pending list to
15495779Sxy150489 		 * the free list.
15505779Sxy150489 		 */
15515779Sxy150489 		igb_put_free_list(tx_ring, &pending_list);
15525779Sxy150489 	}
15535779Sxy150489 }
15545779Sxy150489 
15555779Sxy150489 /*
15565779Sxy150489  * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted
15575779Sxy150489  */
15585779Sxy150489 static boolean_t
15595779Sxy150489 igb_tx_drain(igb_t *igb)
15605779Sxy150489 {
15615779Sxy150489 	igb_tx_ring_t *tx_ring;
15625779Sxy150489 	boolean_t done;
15635779Sxy150489 	int i, j;
15645779Sxy150489 
15655779Sxy150489 	/*
15665779Sxy150489 	 * Wait for a specific time to allow pending tx packets
15675779Sxy150489 	 * to be transmitted.
15685779Sxy150489 	 *
15695779Sxy150489 	 * Check the counter tbd_free to see if transmission is done.
15705779Sxy150489 	 * No lock protection is needed here.
15715779Sxy150489 	 *
15725779Sxy150489 	 * Return B_TRUE if all pending packets have been transmitted;
15735779Sxy150489 	 * Otherwise return B_FALSE;
15745779Sxy150489 	 */
15755779Sxy150489 	for (i = 0; i < TX_DRAIN_TIME; i++) {
15765779Sxy150489 
15775779Sxy150489 		done = B_TRUE;
15785779Sxy150489 		for (j = 0; j < igb->num_tx_rings; j++) {
15795779Sxy150489 			tx_ring = &igb->tx_rings[j];
15805779Sxy150489 			done = done &&
15815779Sxy150489 			    (tx_ring->tbd_free == tx_ring->ring_size);
15825779Sxy150489 		}
15835779Sxy150489 
15845779Sxy150489 		if (done)
15855779Sxy150489 			break;
15865779Sxy150489 
15875779Sxy150489 		msec_delay(1);
15885779Sxy150489 	}
15895779Sxy150489 
15905779Sxy150489 	return (done);
15915779Sxy150489 }
15925779Sxy150489 
15935779Sxy150489 /*
15945779Sxy150489  * igb_rx_drain - Wait for all rx buffers to be released by upper layer
15955779Sxy150489  */
15965779Sxy150489 static boolean_t
15975779Sxy150489 igb_rx_drain(igb_t *igb)
15985779Sxy150489 {
15995779Sxy150489 	boolean_t done;
160011502SChenlu.Chen@Sun.COM 	int i;
16015779Sxy150489 
16025779Sxy150489 	/*
16035779Sxy150489 	 * Polling the rx free list to check if those rx buffers held by
16045779Sxy150489 	 * the upper layer are released.
16055779Sxy150489 	 *
16065779Sxy150489 	 * Check the counter rcb_free to see if all pending buffers are
16075779Sxy150489 	 * released. No lock protection is needed here.
16085779Sxy150489 	 *
16095779Sxy150489 	 * Return B_TRUE if all pending buffers have been released;
16105779Sxy150489 	 * Otherwise return B_FALSE;
16115779Sxy150489 	 */
16125779Sxy150489 	for (i = 0; i < RX_DRAIN_TIME; i++) {
161311502SChenlu.Chen@Sun.COM 		done = (igb->rcb_pending == 0);
16145779Sxy150489 
16155779Sxy150489 		if (done)
16165779Sxy150489 			break;
16175779Sxy150489 
16185779Sxy150489 		msec_delay(1);
16195779Sxy150489 	}
16205779Sxy150489 
16215779Sxy150489 	return (done);
16225779Sxy150489 }
16235779Sxy150489 
16245779Sxy150489 /*
16255779Sxy150489  * igb_start - Start the driver/chipset
16265779Sxy150489  */
16275779Sxy150489 int
162811502SChenlu.Chen@Sun.COM igb_start(igb_t *igb, boolean_t alloc_buffer)
16295779Sxy150489 {
16305779Sxy150489 	int i;
16315779Sxy150489 
16325779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
16335779Sxy150489 
163411502SChenlu.Chen@Sun.COM 	if (alloc_buffer) {
163511502SChenlu.Chen@Sun.COM 		if (igb_alloc_rx_data(igb) != IGB_SUCCESS) {
163611502SChenlu.Chen@Sun.COM 			igb_error(igb,
163711502SChenlu.Chen@Sun.COM 			    "Failed to allocate software receive rings");
163811502SChenlu.Chen@Sun.COM 			return (IGB_FAILURE);
163911502SChenlu.Chen@Sun.COM 		}
164011502SChenlu.Chen@Sun.COM 
164111502SChenlu.Chen@Sun.COM 		/* Allocate buffers for all the rx/tx rings */
164211502SChenlu.Chen@Sun.COM 		if (igb_alloc_dma(igb) != IGB_SUCCESS) {
164311502SChenlu.Chen@Sun.COM 			igb_error(igb, "Failed to allocate DMA resource");
164411502SChenlu.Chen@Sun.COM 			return (IGB_FAILURE);
164511502SChenlu.Chen@Sun.COM 		}
164611502SChenlu.Chen@Sun.COM 
164711502SChenlu.Chen@Sun.COM 		igb->tx_ring_init = B_TRUE;
164811502SChenlu.Chen@Sun.COM 	} else {
164911502SChenlu.Chen@Sun.COM 		igb->tx_ring_init = B_FALSE;
165011502SChenlu.Chen@Sun.COM 	}
165111502SChenlu.Chen@Sun.COM 
16525779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++)
16535779Sxy150489 		mutex_enter(&igb->rx_rings[i].rx_lock);
16545779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++)
16555779Sxy150489 		mutex_enter(&igb->tx_rings[i].tx_lock);
16565779Sxy150489 
16575779Sxy150489 	/*
16588955SChenlu.Chen@Sun.COM 	 * Start the adapter
16595779Sxy150489 	 */
16608955SChenlu.Chen@Sun.COM 	if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) {
16618955SChenlu.Chen@Sun.COM 		if (igb_init_adapter(igb) != IGB_SUCCESS) {
16628275SEric Cheng 			igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
16638275SEric Cheng 			goto start_failure;
16648275SEric Cheng 		}
16658955SChenlu.Chen@Sun.COM 		igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
16665779Sxy150489 	}
16675779Sxy150489 
16685779Sxy150489 	/*
166911502SChenlu.Chen@Sun.COM 	 * Setup the rx/tx rings
167011502SChenlu.Chen@Sun.COM 	 */
167111502SChenlu.Chen@Sun.COM 	igb_setup_rings(igb);
167211502SChenlu.Chen@Sun.COM 
167311502SChenlu.Chen@Sun.COM 	/*
16745779Sxy150489 	 * Enable adapter interrupts
16755779Sxy150489 	 * The interrupts must be enabled after the driver state is START
16765779Sxy150489 	 */
16778571SChenlu.Chen@Sun.COM 	igb->capab->enable_intr(igb);
16785779Sxy150489 
16796624Sgl147354 	if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
16806624Sgl147354 		goto start_failure;
16816624Sgl147354 
16826624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
16836624Sgl147354 		goto start_failure;
16846624Sgl147354 
16855779Sxy150489 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
16865779Sxy150489 		mutex_exit(&igb->tx_rings[i].tx_lock);
16875779Sxy150489 	for (i = igb->num_rx_rings - 1; i >= 0; i--)
16885779Sxy150489 		mutex_exit(&igb->rx_rings[i].rx_lock);
16895779Sxy150489 
16905779Sxy150489 	return (IGB_SUCCESS);
16915779Sxy150489 
16925779Sxy150489 start_failure:
16935779Sxy150489 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
16945779Sxy150489 		mutex_exit(&igb->tx_rings[i].tx_lock);
16955779Sxy150489 	for (i = igb->num_rx_rings - 1; i >= 0; i--)
16965779Sxy150489 		mutex_exit(&igb->rx_rings[i].rx_lock);
16975779Sxy150489 
16986624Sgl147354 	ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
16996624Sgl147354 
17005779Sxy150489 	return (IGB_FAILURE);
17015779Sxy150489 }
17025779Sxy150489 
17035779Sxy150489 /*
17045779Sxy150489  * igb_stop - Stop the driver/chipset
17055779Sxy150489  */
17065779Sxy150489 void
170711502SChenlu.Chen@Sun.COM igb_stop(igb_t *igb, boolean_t free_buffer)
17085779Sxy150489 {
17095779Sxy150489 	int i;
17105779Sxy150489 
17115779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
17125779Sxy150489 
17138955SChenlu.Chen@Sun.COM 	igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER;
17148275SEric Cheng 
17155779Sxy150489 	/*
17165779Sxy150489 	 * Disable the adapter interrupts
17175779Sxy150489 	 */
17185779Sxy150489 	igb_disable_adapter_interrupts(igb);
17195779Sxy150489 
17205779Sxy150489 	/*
17215779Sxy150489 	 * Drain the pending tx packets
17225779Sxy150489 	 */
17235779Sxy150489 	(void) igb_tx_drain(igb);
17245779Sxy150489 
17255779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++)
17265779Sxy150489 		mutex_enter(&igb->rx_rings[i].rx_lock);
17275779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++)
17285779Sxy150489 		mutex_enter(&igb->tx_rings[i].tx_lock);
17295779Sxy150489 
17305779Sxy150489 	/*
17318955SChenlu.Chen@Sun.COM 	 * Stop the adapter
17325779Sxy150489 	 */
17338955SChenlu.Chen@Sun.COM 	igb_stop_adapter(igb);
17345779Sxy150489 
17355779Sxy150489 	/*
17365779Sxy150489 	 * Clean the pending tx data/resources
17375779Sxy150489 	 */
17385779Sxy150489 	igb_tx_clean(igb);
17395779Sxy150489 
17405779Sxy150489 	for (i = igb->num_tx_rings - 1; i >= 0; i--)
17415779Sxy150489 		mutex_exit(&igb->tx_rings[i].tx_lock);
17425779Sxy150489 	for (i = igb->num_rx_rings - 1; i >= 0; i--)
17435779Sxy150489 		mutex_exit(&igb->rx_rings[i].rx_lock);
17446624Sgl147354 
17456624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
17466624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
174711502SChenlu.Chen@Sun.COM 
174811502SChenlu.Chen@Sun.COM 	if (igb->link_state == LINK_STATE_UP) {
174911502SChenlu.Chen@Sun.COM 		igb->link_state = LINK_STATE_UNKNOWN;
175011502SChenlu.Chen@Sun.COM 		mac_link_update(igb->mac_hdl, igb->link_state);
175111502SChenlu.Chen@Sun.COM 	}
175211502SChenlu.Chen@Sun.COM 
175311502SChenlu.Chen@Sun.COM 	if (free_buffer) {
175411502SChenlu.Chen@Sun.COM 		/*
175511502SChenlu.Chen@Sun.COM 		 * Release the DMA/memory resources of rx/tx rings
175611502SChenlu.Chen@Sun.COM 		 */
175711502SChenlu.Chen@Sun.COM 		igb_free_dma(igb);
175811502SChenlu.Chen@Sun.COM 		igb_free_rx_data(igb);
175911502SChenlu.Chen@Sun.COM 	}
17605779Sxy150489 }
17615779Sxy150489 
17625779Sxy150489 /*
17635779Sxy150489  * igb_alloc_rings - Allocate memory space for rx/tx rings
17645779Sxy150489  */
17655779Sxy150489 static int
17665779Sxy150489 igb_alloc_rings(igb_t *igb)
17675779Sxy150489 {
17685779Sxy150489 	/*
17695779Sxy150489 	 * Allocate memory space for rx rings
17705779Sxy150489 	 */
17715779Sxy150489 	igb->rx_rings = kmem_zalloc(
17725779Sxy150489 	    sizeof (igb_rx_ring_t) * igb->num_rx_rings,
17735779Sxy150489 	    KM_NOSLEEP);
17745779Sxy150489 
17755779Sxy150489 	if (igb->rx_rings == NULL) {
17765779Sxy150489 		return (IGB_FAILURE);
17775779Sxy150489 	}
17785779Sxy150489 
17795779Sxy150489 	/*
17805779Sxy150489 	 * Allocate memory space for tx rings
17815779Sxy150489 	 */
17825779Sxy150489 	igb->tx_rings = kmem_zalloc(
17835779Sxy150489 	    sizeof (igb_tx_ring_t) * igb->num_tx_rings,
17845779Sxy150489 	    KM_NOSLEEP);
17855779Sxy150489 
17865779Sxy150489 	if (igb->tx_rings == NULL) {
17875779Sxy150489 		kmem_free(igb->rx_rings,
17885779Sxy150489 		    sizeof (igb_rx_ring_t) * igb->num_rx_rings);
17895779Sxy150489 		igb->rx_rings = NULL;
17905779Sxy150489 		return (IGB_FAILURE);
17915779Sxy150489 	}
17925779Sxy150489 
17938275SEric Cheng 	/*
17948275SEric Cheng 	 * Allocate memory space for rx ring groups
17958275SEric Cheng 	 */
17968275SEric Cheng 	igb->rx_groups = kmem_zalloc(
17978275SEric Cheng 	    sizeof (igb_rx_group_t) * igb->num_rx_groups,
17988275SEric Cheng 	    KM_NOSLEEP);
17998275SEric Cheng 
18008275SEric Cheng 	if (igb->rx_groups == NULL) {
18018275SEric Cheng 		kmem_free(igb->rx_rings,
18028275SEric Cheng 		    sizeof (igb_rx_ring_t) * igb->num_rx_rings);
18038275SEric Cheng 		kmem_free(igb->tx_rings,
18048275SEric Cheng 		    sizeof (igb_tx_ring_t) * igb->num_tx_rings);
18058275SEric Cheng 		igb->rx_rings = NULL;
18068275SEric Cheng 		igb->tx_rings = NULL;
18078275SEric Cheng 		return (IGB_FAILURE);
18088275SEric Cheng 	}
18098275SEric Cheng 
18105779Sxy150489 	return (IGB_SUCCESS);
18115779Sxy150489 }
18125779Sxy150489 
18135779Sxy150489 /*
18145779Sxy150489  * igb_free_rings - Free the memory space of rx/tx rings.
18155779Sxy150489  */
18165779Sxy150489 static void
18175779Sxy150489 igb_free_rings(igb_t *igb)
18185779Sxy150489 {
18195779Sxy150489 	if (igb->rx_rings != NULL) {
18205779Sxy150489 		kmem_free(igb->rx_rings,
18215779Sxy150489 		    sizeof (igb_rx_ring_t) * igb->num_rx_rings);
18225779Sxy150489 		igb->rx_rings = NULL;
18235779Sxy150489 	}
18245779Sxy150489 
18255779Sxy150489 	if (igb->tx_rings != NULL) {
18265779Sxy150489 		kmem_free(igb->tx_rings,
18275779Sxy150489 		    sizeof (igb_tx_ring_t) * igb->num_tx_rings);
18285779Sxy150489 		igb->tx_rings = NULL;
18295779Sxy150489 	}
18308275SEric Cheng 
18318275SEric Cheng 	if (igb->rx_groups != NULL) {
18328275SEric Cheng 		kmem_free(igb->rx_groups,
18338275SEric Cheng 		    sizeof (igb_rx_group_t) * igb->num_rx_groups);
18348275SEric Cheng 		igb->rx_groups = NULL;
18358275SEric Cheng 	}
18365779Sxy150489 }
18375779Sxy150489 
183811502SChenlu.Chen@Sun.COM static int
183911502SChenlu.Chen@Sun.COM igb_alloc_rx_data(igb_t *igb)
184011502SChenlu.Chen@Sun.COM {
184111502SChenlu.Chen@Sun.COM 	igb_rx_ring_t *rx_ring;
184211502SChenlu.Chen@Sun.COM 	int i;
184311502SChenlu.Chen@Sun.COM 
184411502SChenlu.Chen@Sun.COM 	for (i = 0; i < igb->num_rx_rings; i++) {
184511502SChenlu.Chen@Sun.COM 		rx_ring = &igb->rx_rings[i];
184611502SChenlu.Chen@Sun.COM 		if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS)
184711502SChenlu.Chen@Sun.COM 			goto alloc_rx_rings_failure;
184811502SChenlu.Chen@Sun.COM 	}
184911502SChenlu.Chen@Sun.COM 	return (IGB_SUCCESS);
185011502SChenlu.Chen@Sun.COM 
185111502SChenlu.Chen@Sun.COM alloc_rx_rings_failure:
185211502SChenlu.Chen@Sun.COM 	igb_free_rx_data(igb);
185311502SChenlu.Chen@Sun.COM 	return (IGB_FAILURE);
185411502SChenlu.Chen@Sun.COM }
185511502SChenlu.Chen@Sun.COM 
185611502SChenlu.Chen@Sun.COM static void
185711502SChenlu.Chen@Sun.COM igb_free_rx_data(igb_t *igb)
185811502SChenlu.Chen@Sun.COM {
185911502SChenlu.Chen@Sun.COM 	igb_rx_ring_t *rx_ring;
186011502SChenlu.Chen@Sun.COM 	igb_rx_data_t *rx_data;
186111502SChenlu.Chen@Sun.COM 	int i;
186211502SChenlu.Chen@Sun.COM 
186311502SChenlu.Chen@Sun.COM 	for (i = 0; i < igb->num_rx_rings; i++) {
186411502SChenlu.Chen@Sun.COM 		rx_ring = &igb->rx_rings[i];
186511502SChenlu.Chen@Sun.COM 
186611502SChenlu.Chen@Sun.COM 		mutex_enter(&igb->rx_pending_lock);
186711502SChenlu.Chen@Sun.COM 		rx_data = rx_ring->rx_data;
186811502SChenlu.Chen@Sun.COM 
186911502SChenlu.Chen@Sun.COM 		if (rx_data != NULL) {
187011502SChenlu.Chen@Sun.COM 			rx_data->flag |= IGB_RX_STOPPED;
187111502SChenlu.Chen@Sun.COM 
187211502SChenlu.Chen@Sun.COM 			if (rx_data->rcb_pending == 0) {
187311502SChenlu.Chen@Sun.COM 				igb_free_rx_ring_data(rx_data);
187411502SChenlu.Chen@Sun.COM 				rx_ring->rx_data = NULL;
187511502SChenlu.Chen@Sun.COM 			}
187611502SChenlu.Chen@Sun.COM 		}
187711502SChenlu.Chen@Sun.COM 
187811502SChenlu.Chen@Sun.COM 		mutex_exit(&igb->rx_pending_lock);
187911502SChenlu.Chen@Sun.COM 	}
188011502SChenlu.Chen@Sun.COM }
188111502SChenlu.Chen@Sun.COM 
18825779Sxy150489 /*
18835779Sxy150489  * igb_setup_rings - Setup rx/tx rings
18845779Sxy150489  */
18855779Sxy150489 static void
18865779Sxy150489 igb_setup_rings(igb_t *igb)
18875779Sxy150489 {
18885779Sxy150489 	/*
18895779Sxy150489 	 * Setup the rx/tx rings, including the following:
18905779Sxy150489 	 *
18915779Sxy150489 	 * 1. Setup the descriptor ring and the control block buffers;
18925779Sxy150489 	 * 2. Initialize necessary registers for receive/transmit;
18935779Sxy150489 	 * 3. Initialize software pointers/parameters for receive/transmit;
18945779Sxy150489 	 */
18955779Sxy150489 	igb_setup_rx(igb);
18965779Sxy150489 
18975779Sxy150489 	igb_setup_tx(igb);
18985779Sxy150489 }
18995779Sxy150489 
19005779Sxy150489 static void
19015779Sxy150489 igb_setup_rx_ring(igb_rx_ring_t *rx_ring)
19025779Sxy150489 {
19035779Sxy150489 	igb_t *igb = rx_ring->igb;
190411502SChenlu.Chen@Sun.COM 	igb_rx_data_t *rx_data = rx_ring->rx_data;
19055779Sxy150489 	struct e1000_hw *hw = &igb->hw;
19065779Sxy150489 	rx_control_block_t *rcb;
19075779Sxy150489 	union e1000_adv_rx_desc	*rbd;
19085779Sxy150489 	uint32_t size;
19095779Sxy150489 	uint32_t buf_low;
19105779Sxy150489 	uint32_t buf_high;
19118955SChenlu.Chen@Sun.COM 	uint32_t rxdctl;
19125779Sxy150489 	int i;
19135779Sxy150489 
19145779Sxy150489 	ASSERT(mutex_owned(&rx_ring->rx_lock));
19155779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
19165779Sxy150489 
19178955SChenlu.Chen@Sun.COM 	/*
19188955SChenlu.Chen@Sun.COM 	 * Initialize descriptor ring with buffer addresses
19198955SChenlu.Chen@Sun.COM 	 */
19205779Sxy150489 	for (i = 0; i < igb->rx_ring_size; i++) {
192111502SChenlu.Chen@Sun.COM 		rcb = rx_data->work_list[i];
192211502SChenlu.Chen@Sun.COM 		rbd = &rx_data->rbd_ring[i];
19235779Sxy150489 
19245779Sxy150489 		rbd->read.pkt_addr = rcb->rx_buf.dma_address;
19255779Sxy150489 		rbd->read.hdr_addr = NULL;
19265779Sxy150489 	}
19275779Sxy150489 
19285779Sxy150489 	/*
19295779Sxy150489 	 * Initialize the base address registers
19305779Sxy150489 	 */
193111502SChenlu.Chen@Sun.COM 	buf_low = (uint32_t)rx_data->rbd_area.dma_address;
193211502SChenlu.Chen@Sun.COM 	buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
19335779Sxy150489 	E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high);
19345779Sxy150489 	E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low);
19355779Sxy150489 
19365779Sxy150489 	/*
19378955SChenlu.Chen@Sun.COM 	 * Initialize the length register
19388955SChenlu.Chen@Sun.COM 	 */
193911502SChenlu.Chen@Sun.COM 	size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc);
19408955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size);
19418955SChenlu.Chen@Sun.COM 
19428955SChenlu.Chen@Sun.COM 	/*
19438955SChenlu.Chen@Sun.COM 	 * Initialize buffer size & descriptor type
19445779Sxy150489 	 */
19458955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index),
19468955SChenlu.Chen@Sun.COM 	    ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) |
19478955SChenlu.Chen@Sun.COM 	    E1000_SRRCTL_DESCTYPE_ADV_ONEBUF));
19488955SChenlu.Chen@Sun.COM 
19498955SChenlu.Chen@Sun.COM 	/*
19508955SChenlu.Chen@Sun.COM 	 * Setup the Receive Descriptor Control Register (RXDCTL)
19518955SChenlu.Chen@Sun.COM 	 */
19528955SChenlu.Chen@Sun.COM 	rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index));
19538955SChenlu.Chen@Sun.COM 	rxdctl &= igb->capab->rxdctl_mask;
19548955SChenlu.Chen@Sun.COM 	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
19558955SChenlu.Chen@Sun.COM 	rxdctl |= 16;		/* pthresh */
19568955SChenlu.Chen@Sun.COM 	rxdctl |= 8 << 8;	/* hthresh */
19578955SChenlu.Chen@Sun.COM 	rxdctl |= 1 << 16;	/* wthresh */
19588955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl);
19595779Sxy150489 
196011502SChenlu.Chen@Sun.COM 	rx_data->rbd_next = 0;
19615779Sxy150489 }
19625779Sxy150489 
19635779Sxy150489 static void
19645779Sxy150489 igb_setup_rx(igb_t *igb)
19655779Sxy150489 {
19665779Sxy150489 	igb_rx_ring_t *rx_ring;
196711502SChenlu.Chen@Sun.COM 	igb_rx_data_t *rx_data;
19688275SEric Cheng 	igb_rx_group_t *rx_group;
19695779Sxy150489 	struct e1000_hw *hw = &igb->hw;
19708955SChenlu.Chen@Sun.COM 	uint32_t rctl, rxcsum;
19718275SEric Cheng 	uint32_t ring_per_group;
19725779Sxy150489 	int i;
19735779Sxy150489 
19745779Sxy150489 	/*
19758955SChenlu.Chen@Sun.COM 	 * Setup the Receive Control Register (RCTL), and enable the
19768955SChenlu.Chen@Sun.COM 	 * receiver. The initial configuration is to: enable the receiver,
19778955SChenlu.Chen@Sun.COM 	 * accept broadcasts, discard bad packets, accept long packets,
19788955SChenlu.Chen@Sun.COM 	 * disable VLAN filter checking, and set receive buffer size to
19798955SChenlu.Chen@Sun.COM 	 * 2k.  For 82575, also set the receive descriptor minimum
19808955SChenlu.Chen@Sun.COM 	 * threshold size to 1/2 the ring.
19815779Sxy150489 	 */
19828571SChenlu.Chen@Sun.COM 	rctl = E1000_READ_REG(hw, E1000_RCTL);
19838571SChenlu.Chen@Sun.COM 
19848571SChenlu.Chen@Sun.COM 	/*
19858955SChenlu.Chen@Sun.COM 	 * Clear the field used for wakeup control.  This driver doesn't do
19868955SChenlu.Chen@Sun.COM 	 * wakeup but leave this here for completeness.
19878571SChenlu.Chen@Sun.COM 	 */
19888571SChenlu.Chen@Sun.COM 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
198911155SJason.Xu@Sun.COM 	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
199011155SJason.Xu@Sun.COM 
199111155SJason.Xu@Sun.COM 	rctl |= (E1000_RCTL_EN |	/* Enable Receive Unit */
199211155SJason.Xu@Sun.COM 	    E1000_RCTL_BAM |		/* Accept Broadcast Packets */
199311155SJason.Xu@Sun.COM 	    E1000_RCTL_LPE |		/* Large Packet Enable */
199411155SJason.Xu@Sun.COM 					/* Multicast filter offset */
199511155SJason.Xu@Sun.COM 	    (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
199611155SJason.Xu@Sun.COM 	    E1000_RCTL_RDMTS_HALF |	/* rx descriptor threshold */
199711155SJason.Xu@Sun.COM 	    E1000_RCTL_SECRC);		/* Strip Ethernet CRC */
19985779Sxy150489 
19998275SEric Cheng 	for (i = 0; i < igb->num_rx_groups; i++) {
20008275SEric Cheng 		rx_group = &igb->rx_groups[i];
20018275SEric Cheng 		rx_group->index = i;
20028275SEric Cheng 		rx_group->igb = igb;
20038275SEric Cheng 	}
20048275SEric Cheng 
20055779Sxy150489 	/*
20068955SChenlu.Chen@Sun.COM 	 * Set up all rx descriptor rings - must be called before receive unit
20078955SChenlu.Chen@Sun.COM 	 * enabled.
20085812Sxy150489 	 */
20098275SEric Cheng 	ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
20105812Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++) {
20115812Sxy150489 		rx_ring = &igb->rx_rings[i];
20125812Sxy150489 		igb_setup_rx_ring(rx_ring);
20138275SEric Cheng 
20148275SEric Cheng 		/*
20158275SEric Cheng 		 * Map a ring to a group by assigning a group index
20168275SEric Cheng 		 */
20178275SEric Cheng 		rx_ring->group_index = i / ring_per_group;
20185812Sxy150489 	}
20195812Sxy150489 
20205812Sxy150489 	/*
20215779Sxy150489 	 * Setup the Rx Long Packet Max Length register
20225779Sxy150489 	 */
20235779Sxy150489 	E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size);
20245779Sxy150489 
20255779Sxy150489 	/*
20265779Sxy150489 	 * Hardware checksum settings
20275779Sxy150489 	 */
20285779Sxy150489 	if (igb->rx_hcksum_enable) {
20298955SChenlu.Chen@Sun.COM 		rxcsum =
20305779Sxy150489 		    E1000_RXCSUM_TUOFL |	/* TCP/UDP checksum */
20315779Sxy150489 		    E1000_RXCSUM_IPOFL;		/* IP checksum */
20325779Sxy150489 
20338955SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
20345779Sxy150489 	}
20355779Sxy150489 
20365779Sxy150489 	/*
20378275SEric Cheng 	 * Setup classify and RSS for multiple receive queues
20385779Sxy150489 	 */
20398275SEric Cheng 	switch (igb->vmdq_mode) {
20408275SEric Cheng 	case E1000_VMDQ_OFF:
20418275SEric Cheng 		/*
20428275SEric Cheng 		 * One ring group, only RSS is needed when more than
20438275SEric Cheng 		 * one ring enabled.
20448275SEric Cheng 		 */
20458275SEric Cheng 		if (igb->num_rx_rings > 1)
20468275SEric Cheng 			igb_setup_rss(igb);
20478275SEric Cheng 		break;
20488275SEric Cheng 	case E1000_VMDQ_MAC:
20498275SEric Cheng 		/*
20508275SEric Cheng 		 * Multiple groups, each group has one ring,
20518275SEric Cheng 		 * only the MAC classification is needed.
20528275SEric Cheng 		 */
20538275SEric Cheng 		igb_setup_mac_classify(igb);
20548275SEric Cheng 		break;
20558275SEric Cheng 	case E1000_VMDQ_MAC_RSS:
20568275SEric Cheng 		/*
20578275SEric Cheng 		 * Multiple groups and multiple rings, both
20588275SEric Cheng 		 * MAC classification and RSS are needed.
20598275SEric Cheng 		 */
20608275SEric Cheng 		igb_setup_mac_rss_classify(igb);
20618275SEric Cheng 		break;
20628275SEric Cheng 	}
20638955SChenlu.Chen@Sun.COM 
20648955SChenlu.Chen@Sun.COM 	/*
20658955SChenlu.Chen@Sun.COM 	 * Enable the receive unit - must be done after all
20668955SChenlu.Chen@Sun.COM 	 * the rx setup above.
20678955SChenlu.Chen@Sun.COM 	 */
20688955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
20698955SChenlu.Chen@Sun.COM 
20708955SChenlu.Chen@Sun.COM 	/*
20718955SChenlu.Chen@Sun.COM 	 * Initialize all adapter ring head & tail pointers - must
20728955SChenlu.Chen@Sun.COM 	 * be done after receive unit is enabled
20738955SChenlu.Chen@Sun.COM 	 */
20748955SChenlu.Chen@Sun.COM 	for (i = 0; i < igb->num_rx_rings; i++) {
20758955SChenlu.Chen@Sun.COM 		rx_ring = &igb->rx_rings[i];
207611502SChenlu.Chen@Sun.COM 		rx_data = rx_ring->rx_data;
20778955SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_RDH(i), 0);
207811502SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1);
20798955SChenlu.Chen@Sun.COM 	}
20808955SChenlu.Chen@Sun.COM 
20818955SChenlu.Chen@Sun.COM 	/*
20828955SChenlu.Chen@Sun.COM 	 * 82575 with manageability enabled needs a special flush to make
20838955SChenlu.Chen@Sun.COM 	 * sure the fifos start clean.
20848955SChenlu.Chen@Sun.COM 	 */
20858955SChenlu.Chen@Sun.COM 	if ((hw->mac.type == e1000_82575) &&
20868955SChenlu.Chen@Sun.COM 	    (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) {
20878955SChenlu.Chen@Sun.COM 		e1000_rx_fifo_flush_82575(hw);
20888955SChenlu.Chen@Sun.COM 	}
20895779Sxy150489 }
20905779Sxy150489 
20915779Sxy150489 static void
20925779Sxy150489 igb_setup_tx_ring(igb_tx_ring_t *tx_ring)
20935779Sxy150489 {
20945779Sxy150489 	igb_t *igb = tx_ring->igb;
20955779Sxy150489 	struct e1000_hw *hw = &igb->hw;
20965779Sxy150489 	uint32_t size;
20975779Sxy150489 	uint32_t buf_low;
20985779Sxy150489 	uint32_t buf_high;
20995779Sxy150489 	uint32_t reg_val;
21005779Sxy150489 
21015779Sxy150489 	ASSERT(mutex_owned(&tx_ring->tx_lock));
21025779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
21035779Sxy150489 
21048275SEric Cheng 
21055779Sxy150489 	/*
21065779Sxy150489 	 * Initialize the length register
21075779Sxy150489 	 */
21085779Sxy150489 	size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc);
21095779Sxy150489 	E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size);
21105779Sxy150489 
21115779Sxy150489 	/*
21125779Sxy150489 	 * Initialize the base address registers
21135779Sxy150489 	 */
21145779Sxy150489 	buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
21155779Sxy150489 	buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
21165779Sxy150489 	E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low);
21175779Sxy150489 	E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high);
21185779Sxy150489 
21195779Sxy150489 	/*
21205779Sxy150489 	 * Setup head & tail pointers
21215779Sxy150489 	 */
21225779Sxy150489 	E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0);
21235779Sxy150489 	E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0);
21245779Sxy150489 
21255779Sxy150489 	/*
21265779Sxy150489 	 * Setup head write-back
21275779Sxy150489 	 */
21285779Sxy150489 	if (igb->tx_head_wb_enable) {
21295779Sxy150489 		/*
21305779Sxy150489 		 * The memory of the head write-back is allocated using
21315779Sxy150489 		 * the extra tbd beyond the tail of the tbd ring.
21325779Sxy150489 		 */
21335779Sxy150489 		tx_ring->tbd_head_wb = (uint32_t *)
21345779Sxy150489 		    ((uintptr_t)tx_ring->tbd_area.address + size);
21357072Sxy150489 		*tx_ring->tbd_head_wb = 0;
21365779Sxy150489 
21375779Sxy150489 		buf_low = (uint32_t)
21385779Sxy150489 		    (tx_ring->tbd_area.dma_address + size);
21395779Sxy150489 		buf_high = (uint32_t)
21405779Sxy150489 		    ((tx_ring->tbd_area.dma_address + size) >> 32);
21415779Sxy150489 
21425779Sxy150489 		/* Set the head write-back enable bit */
21435779Sxy150489 		buf_low |= E1000_TX_HEAD_WB_ENABLE;
21445779Sxy150489 
21455779Sxy150489 		E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low);
21465779Sxy150489 		E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high);
21475779Sxy150489 
21485779Sxy150489 		/*
21495779Sxy150489 		 * Turn off relaxed ordering for head write back or it will
21505779Sxy150489 		 * cause problems with the tx recycling
21515779Sxy150489 		 */
21525779Sxy150489 		reg_val = E1000_READ_REG(hw,
21535779Sxy150489 		    E1000_DCA_TXCTRL(tx_ring->index));
21545779Sxy150489 		reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
21555779Sxy150489 		E1000_WRITE_REG(hw,
21565779Sxy150489 		    E1000_DCA_TXCTRL(tx_ring->index), reg_val);
21575779Sxy150489 	} else {
21585779Sxy150489 		tx_ring->tbd_head_wb = NULL;
21595779Sxy150489 	}
21605779Sxy150489 
21615779Sxy150489 	tx_ring->tbd_head = 0;
21625779Sxy150489 	tx_ring->tbd_tail = 0;
21635779Sxy150489 	tx_ring->tbd_free = tx_ring->ring_size;
21645779Sxy150489 
216511502SChenlu.Chen@Sun.COM 	if (igb->tx_ring_init == B_TRUE) {
21665779Sxy150489 		tx_ring->tcb_head = 0;
21675779Sxy150489 		tx_ring->tcb_tail = 0;
21685779Sxy150489 		tx_ring->tcb_free = tx_ring->free_list_size;
21695779Sxy150489 	}
21705779Sxy150489 
21715779Sxy150489 	/*
21728571SChenlu.Chen@Sun.COM 	 * Enable TXDCTL per queue
21738571SChenlu.Chen@Sun.COM 	 */
21748571SChenlu.Chen@Sun.COM 	reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
21758571SChenlu.Chen@Sun.COM 	reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
21768571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
21779188SPaul.Guo@Sun.COM 
21789188SPaul.Guo@Sun.COM 	/*
21799188SPaul.Guo@Sun.COM 	 * Initialize hardware checksum offload settings
21809188SPaul.Guo@Sun.COM 	 */
21819188SPaul.Guo@Sun.COM 	bzero(&tx_ring->tx_context, sizeof (tx_context_t));
21825779Sxy150489 }
21835779Sxy150489 
21845779Sxy150489 static void
21855779Sxy150489 igb_setup_tx(igb_t *igb)
21865779Sxy150489 {
21875779Sxy150489 	igb_tx_ring_t *tx_ring;
21885779Sxy150489 	struct e1000_hw *hw = &igb->hw;
21895779Sxy150489 	uint32_t reg_val;
21905779Sxy150489 	int i;
21915779Sxy150489 
21925779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
21935779Sxy150489 		tx_ring = &igb->tx_rings[i];
21945779Sxy150489 		igb_setup_tx_ring(tx_ring);
21955779Sxy150489 	}
21965779Sxy150489 
21975779Sxy150489 	/*
21985779Sxy150489 	 * Setup the Transmit Control Register (TCTL)
21995779Sxy150489 	 */
22008571SChenlu.Chen@Sun.COM 	reg_val = E1000_READ_REG(hw, E1000_TCTL);
22018571SChenlu.Chen@Sun.COM 	reg_val &= ~E1000_TCTL_CT;
22028571SChenlu.Chen@Sun.COM 	reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
22038571SChenlu.Chen@Sun.COM 	    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
22048571SChenlu.Chen@Sun.COM 
22058571SChenlu.Chen@Sun.COM 	/* Enable transmits */
22068571SChenlu.Chen@Sun.COM 	reg_val |= E1000_TCTL_EN;
22075779Sxy150489 
22085779Sxy150489 	E1000_WRITE_REG(hw, E1000_TCTL, reg_val);
22095779Sxy150489 }
22105779Sxy150489 
22115779Sxy150489 /*
22125779Sxy150489  * igb_setup_rss - Setup receive-side scaling feature
22135779Sxy150489  */
22145779Sxy150489 static void
22155779Sxy150489 igb_setup_rss(igb_t *igb)
22165779Sxy150489 {
22175779Sxy150489 	struct e1000_hw *hw = &igb->hw;
22185779Sxy150489 	uint32_t i, mrqc, rxcsum;
22198571SChenlu.Chen@Sun.COM 	int shift = 0;
22205779Sxy150489 	uint32_t random;
22215779Sxy150489 	union e1000_reta {
22225779Sxy150489 		uint32_t	dword;
22235779Sxy150489 		uint8_t		bytes[4];
22245779Sxy150489 	} reta;
22255779Sxy150489 
22265779Sxy150489 	/* Setup the Redirection Table */
22278571SChenlu.Chen@Sun.COM 	if (hw->mac.type == e1000_82576) {
222811155SJason.Xu@Sun.COM 		shift = 3;
22298571SChenlu.Chen@Sun.COM 	} else if (hw->mac.type == e1000_82575) {
22308571SChenlu.Chen@Sun.COM 		shift = 6;
22318571SChenlu.Chen@Sun.COM 	}
22325779Sxy150489 	for (i = 0; i < (32 * 4); i++) {
22335779Sxy150489 		reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift;
22345779Sxy150489 		if ((i & 3) == 3) {
22355779Sxy150489 			E1000_WRITE_REG(hw,
22365779Sxy150489 			    (E1000_RETA(0) + (i & ~3)), reta.dword);
22375779Sxy150489 		}
22385779Sxy150489 	}
22395779Sxy150489 
22405779Sxy150489 	/* Fill out hash function seeds */
22415779Sxy150489 	for (i = 0; i < 10; i++) {
22425779Sxy150489 		(void) random_get_pseudo_bytes((uint8_t *)&random,
22435779Sxy150489 		    sizeof (uint32_t));
22445779Sxy150489 		E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
22455779Sxy150489 	}
22465779Sxy150489 
22475779Sxy150489 	/* Setup the Multiple Receive Queue Control register */
22485779Sxy150489 	mrqc = E1000_MRQC_ENABLE_RSS_4Q;
22495779Sxy150489 	mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
22505779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV4_TCP |
22515779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV6 |
22525779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV6_TCP |
22535779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV4_UDP |
22545779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV6_UDP |
22555779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
22565779Sxy150489 	    E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
22575779Sxy150489 
22585779Sxy150489 	E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
22595779Sxy150489 
22605779Sxy150489 	/*
22615779Sxy150489 	 * Disable Packet Checksum to enable RSS for multiple receive queues.
22625779Sxy150489 	 *
22635779Sxy150489 	 * The Packet Checksum is not ethernet CRC. It is another kind of
22645779Sxy150489 	 * checksum offloading provided by the 82575 chipset besides the IP
22655779Sxy150489 	 * header checksum offloading and the TCP/UDP checksum offloading.
22665779Sxy150489 	 * The Packet Checksum is by default computed over the entire packet
22675779Sxy150489 	 * from the first byte of the DA through the last byte of the CRC,
22685779Sxy150489 	 * including the Ethernet and IP headers.
22695779Sxy150489 	 *
22705779Sxy150489 	 * It is a hardware limitation that Packet Checksum is mutually
22715779Sxy150489 	 * exclusive with RSS.
22725779Sxy150489 	 */
22735779Sxy150489 	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
22745779Sxy150489 	rxcsum |= E1000_RXCSUM_PCSD;
22755779Sxy150489 	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
22765779Sxy150489 }
22775779Sxy150489 
22785779Sxy150489 /*
22798275SEric Cheng  * igb_setup_mac_rss_classify - Setup MAC classification and rss
22808275SEric Cheng  */
22818275SEric Cheng static void
22828275SEric Cheng igb_setup_mac_rss_classify(igb_t *igb)
22838275SEric Cheng {
22848275SEric Cheng 	struct e1000_hw *hw = &igb->hw;
22858275SEric Cheng 	uint32_t i, mrqc, vmdctl, rxcsum;
22868275SEric Cheng 	uint32_t ring_per_group;
22878275SEric Cheng 	int shift_group0, shift_group1;
22888275SEric Cheng 	uint32_t random;
22898275SEric Cheng 	union e1000_reta {
22908275SEric Cheng 		uint32_t	dword;
22918275SEric Cheng 		uint8_t		bytes[4];
22928275SEric Cheng 	} reta;
22938275SEric Cheng 
22948275SEric Cheng 	ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
22958275SEric Cheng 
22968275SEric Cheng 	/* Setup the Redirection Table, it is shared between two groups */
22978275SEric Cheng 	shift_group0 = 2;
22988275SEric Cheng 	shift_group1 = 6;
22998275SEric Cheng 	for (i = 0; i < (32 * 4); i++) {
23008275SEric Cheng 		reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) |
23018275SEric Cheng 		    ((ring_per_group + (i % ring_per_group)) << shift_group1);
23028275SEric Cheng 		if ((i & 3) == 3) {
23038275SEric Cheng 			E1000_WRITE_REG(hw,
23048275SEric Cheng 			    (E1000_RETA(0) + (i & ~3)), reta.dword);
23058275SEric Cheng 		}
23068275SEric Cheng 	}
23078275SEric Cheng 
23088275SEric Cheng 	/* Fill out hash function seeds */
23098275SEric Cheng 	for (i = 0; i < 10; i++) {
23108275SEric Cheng 		(void) random_get_pseudo_bytes((uint8_t *)&random,
23118275SEric Cheng 		    sizeof (uint32_t));
23128275SEric Cheng 		E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
23138275SEric Cheng 	}
23148275SEric Cheng 
23158275SEric Cheng 	/*
23168275SEric Cheng 	 * Setup the Multiple Receive Queue Control register,
23178275SEric Cheng 	 * enable VMDq based on packet destination MAC address and RSS.
23188275SEric Cheng 	 */
23198275SEric Cheng 	mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP;
23208275SEric Cheng 	mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
23218275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV4_TCP |
23228275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV6 |
23238275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV6_TCP |
23248275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV4_UDP |
23258275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV6_UDP |
23268275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
23278275SEric Cheng 	    E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
23288275SEric Cheng 
23298275SEric Cheng 	E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
23308275SEric Cheng 
23318275SEric Cheng 
23328275SEric Cheng 	/* Define the default group and default queues */
23338275SEric Cheng 	vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE;
23348571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl);
23358275SEric Cheng 
23368275SEric Cheng 	/*
23378275SEric Cheng 	 * Disable Packet Checksum to enable RSS for multiple receive queues.
23388275SEric Cheng 	 *
23398275SEric Cheng 	 * The Packet Checksum is not ethernet CRC. It is another kind of
23408275SEric Cheng 	 * checksum offloading provided by the 82575 chipset besides the IP
23418275SEric Cheng 	 * header checksum offloading and the TCP/UDP checksum offloading.
23428275SEric Cheng 	 * The Packet Checksum is by default computed over the entire packet
23438275SEric Cheng 	 * from the first byte of the DA through the last byte of the CRC,
23448275SEric Cheng 	 * including the Ethernet and IP headers.
23458275SEric Cheng 	 *
23468275SEric Cheng 	 * It is a hardware limitation that Packet Checksum is mutually
23478275SEric Cheng 	 * exclusive with RSS.
23488275SEric Cheng 	 */
23498275SEric Cheng 	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
23508275SEric Cheng 	rxcsum |= E1000_RXCSUM_PCSD;
23518275SEric Cheng 	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
23528275SEric Cheng }
23538275SEric Cheng 
23548275SEric Cheng /*
23558275SEric Cheng  * igb_setup_mac_classify - Setup MAC classification feature
23568275SEric Cheng  */
23578275SEric Cheng static void
23588275SEric Cheng igb_setup_mac_classify(igb_t *igb)
23598275SEric Cheng {
23608275SEric Cheng 	struct e1000_hw *hw = &igb->hw;
23618275SEric Cheng 	uint32_t mrqc, rxcsum;
23628275SEric Cheng 
23638275SEric Cheng 	/*
23648275SEric Cheng 	 * Setup the Multiple Receive Queue Control register,
23658275SEric Cheng 	 * enable VMDq based on packet destination MAC address.
23668275SEric Cheng 	 */
23678275SEric Cheng 	mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP;
23688275SEric Cheng 	E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
23698275SEric Cheng 
23708275SEric Cheng 	/*
23718275SEric Cheng 	 * Disable Packet Checksum to enable RSS for multiple receive queues.
23728275SEric Cheng 	 *
23738275SEric Cheng 	 * The Packet Checksum is not ethernet CRC. It is another kind of
23748275SEric Cheng 	 * checksum offloading provided by the 82575 chipset besides the IP
23758275SEric Cheng 	 * header checksum offloading and the TCP/UDP checksum offloading.
23768275SEric Cheng 	 * The Packet Checksum is by default computed over the entire packet
23778275SEric Cheng 	 * from the first byte of the DA through the last byte of the CRC,
23788275SEric Cheng 	 * including the Ethernet and IP headers.
23798275SEric Cheng 	 *
23808275SEric Cheng 	 * It is a hardware limitation that Packet Checksum is mutually
23818275SEric Cheng 	 * exclusive with RSS.
23828275SEric Cheng 	 */
23838275SEric Cheng 	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
23848275SEric Cheng 	rxcsum |= E1000_RXCSUM_PCSD;
23858275SEric Cheng 	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
23868275SEric Cheng 
23878275SEric Cheng }
23888275SEric Cheng 
23898275SEric Cheng /*
23905779Sxy150489  * igb_init_unicst - Initialize the unicast addresses
23915779Sxy150489  */
23925779Sxy150489 static void
23935779Sxy150489 igb_init_unicst(igb_t *igb)
23945779Sxy150489 {
23955779Sxy150489 	struct e1000_hw *hw = &igb->hw;
23965779Sxy150489 	int slot;
23975779Sxy150489 
23985779Sxy150489 	/*
23995779Sxy150489 	 * Here we should consider two situations:
24005779Sxy150489 	 *
24015779Sxy150489 	 * 1. Chipset is initialized the first time
24025779Sxy150489 	 *    Initialize the multiple unicast addresses, and
24038275SEric Cheng 	 *    save the default MAC address.
24045779Sxy150489 	 *
24055779Sxy150489 	 * 2. Chipset is reset
24065779Sxy150489 	 *    Recover the multiple unicast addresses from the
24075779Sxy150489 	 *    software data structure to the RAR registers.
24085779Sxy150489 	 */
24098275SEric Cheng 
24108275SEric Cheng 	/*
24118275SEric Cheng 	 * Clear the default MAC address in the RAR0 rgister,
24128275SEric Cheng 	 * which is loaded from EEPROM when system boot or chipreset,
24138275SEric Cheng 	 * this will cause the conficts with add_mac/rem_mac entry
24148275SEric Cheng 	 * points when VMDq is enabled. For this reason, the RAR0
24158275SEric Cheng 	 * must be cleared for both cases mentioned above.
24168275SEric Cheng 	 */
24178275SEric Cheng 	e1000_rar_clear(hw, 0);
24188275SEric Cheng 
24195779Sxy150489 	if (!igb->unicst_init) {
24208275SEric Cheng 
24215779Sxy150489 		/* Initialize the multiple unicast addresses */
24225779Sxy150489 		igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
24238275SEric Cheng 		igb->unicst_avail = igb->unicst_total;
24248275SEric Cheng 
24258275SEric Cheng 		for (slot = 0; slot < igb->unicst_total; slot++)
24265779Sxy150489 			igb->unicst_addr[slot].mac.set = 0;
24275779Sxy150489 
24285779Sxy150489 		igb->unicst_init = B_TRUE;
24295779Sxy150489 	} else {
24305779Sxy150489 		/* Re-configure the RAR registers */
24318275SEric Cheng 		for (slot = 0; slot < igb->unicst_total; slot++) {
24328275SEric Cheng 			e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr,
24338275SEric Cheng 			    slot, igb->vmdq_mode,
24348275SEric Cheng 			    igb->unicst_addr[slot].mac.group_index);
24358275SEric Cheng 		}
24365779Sxy150489 	}
24375779Sxy150489 }
24385779Sxy150489 
24395779Sxy150489 /*
24408275SEric Cheng  * igb_unicst_find - Find the slot for the specified unicast address
24418275SEric Cheng  */
24428275SEric Cheng int
24438275SEric Cheng igb_unicst_find(igb_t *igb, const uint8_t *mac_addr)
24448275SEric Cheng {
24458275SEric Cheng 	int slot;
24468275SEric Cheng 
24478275SEric Cheng 	ASSERT(mutex_owned(&igb->gen_lock));
24488275SEric Cheng 
24498275SEric Cheng 	for (slot = 0; slot < igb->unicst_total; slot++) {
24508275SEric Cheng 		if (bcmp(igb->unicst_addr[slot].mac.addr,
24518275SEric Cheng 		    mac_addr, ETHERADDRL) == 0)
24528275SEric Cheng 			return (slot);
24538275SEric Cheng 	}
24548275SEric Cheng 
24558275SEric Cheng 	return (-1);
24568275SEric Cheng }
24578275SEric Cheng 
24588275SEric Cheng /*
24595779Sxy150489  * igb_unicst_set - Set the unicast address to the specified slot
24605779Sxy150489  */
24615779Sxy150489 int
24625779Sxy150489 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr,
24638275SEric Cheng     int slot)
24645779Sxy150489 {
24655779Sxy150489 	struct e1000_hw *hw = &igb->hw;
24665779Sxy150489 
24675779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
24685779Sxy150489 
24695779Sxy150489 	/*
24705779Sxy150489 	 * Save the unicast address in the software data structure
24715779Sxy150489 	 */
24725779Sxy150489 	bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
24735779Sxy150489 
24745779Sxy150489 	/*
24755779Sxy150489 	 * Set the unicast address to the RAR register
24765779Sxy150489 	 */
24775779Sxy150489 	e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
24785779Sxy150489 
24796624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
24806624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
24816624Sgl147354 		return (EIO);
24826624Sgl147354 	}
24836624Sgl147354 
24845779Sxy150489 	return (0);
24855779Sxy150489 }
24865779Sxy150489 
24875779Sxy150489 /*
24885779Sxy150489  * igb_multicst_add - Add a multicst address
24895779Sxy150489  */
24905779Sxy150489 int
24915779Sxy150489 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr)
24925779Sxy150489 {
24939775SVitezslav.Batrla@Sun.COM 	struct ether_addr *new_table;
24949775SVitezslav.Batrla@Sun.COM 	size_t new_len;
24959775SVitezslav.Batrla@Sun.COM 	size_t old_len;
24969775SVitezslav.Batrla@Sun.COM 
24975779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
24985779Sxy150489 
24995779Sxy150489 	if ((multiaddr[0] & 01) == 0) {
25009775SVitezslav.Batrla@Sun.COM 		igb_error(igb, "Illegal multicast address");
25015779Sxy150489 		return (EINVAL);
25025779Sxy150489 	}
25035779Sxy150489 
25049775SVitezslav.Batrla@Sun.COM 	if (igb->mcast_count >= igb->mcast_max_num) {
25059775SVitezslav.Batrla@Sun.COM 		igb_error(igb, "Adapter requested more than %d mcast addresses",
25069775SVitezslav.Batrla@Sun.COM 		    igb->mcast_max_num);
25075779Sxy150489 		return (ENOENT);
25085779Sxy150489 	}
25095779Sxy150489 
25109775SVitezslav.Batrla@Sun.COM 	if (igb->mcast_count == igb->mcast_alloc_count) {
25119775SVitezslav.Batrla@Sun.COM 		old_len = igb->mcast_alloc_count *
25129775SVitezslav.Batrla@Sun.COM 		    sizeof (struct ether_addr);
25139775SVitezslav.Batrla@Sun.COM 		new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) *
25149775SVitezslav.Batrla@Sun.COM 		    sizeof (struct ether_addr);
25159775SVitezslav.Batrla@Sun.COM 
25169775SVitezslav.Batrla@Sun.COM 		new_table = kmem_alloc(new_len, KM_NOSLEEP);
25179775SVitezslav.Batrla@Sun.COM 		if (new_table == NULL) {
25189775SVitezslav.Batrla@Sun.COM 			igb_error(igb,
25199775SVitezslav.Batrla@Sun.COM 			    "Not enough memory to alloc mcast table");
25209775SVitezslav.Batrla@Sun.COM 			return (ENOMEM);
25219775SVitezslav.Batrla@Sun.COM 		}
25229775SVitezslav.Batrla@Sun.COM 
25239775SVitezslav.Batrla@Sun.COM 		if (igb->mcast_table != NULL) {
25249775SVitezslav.Batrla@Sun.COM 			bcopy(igb->mcast_table, new_table, old_len);
25259775SVitezslav.Batrla@Sun.COM 			kmem_free(igb->mcast_table, old_len);
25269775SVitezslav.Batrla@Sun.COM 		}
25279775SVitezslav.Batrla@Sun.COM 		igb->mcast_alloc_count += MCAST_ALLOC_COUNT;
25289775SVitezslav.Batrla@Sun.COM 		igb->mcast_table = new_table;
25299775SVitezslav.Batrla@Sun.COM 	}
25309775SVitezslav.Batrla@Sun.COM 
25315779Sxy150489 	bcopy(multiaddr,
25325779Sxy150489 	    &igb->mcast_table[igb->mcast_count], ETHERADDRL);
25335779Sxy150489 	igb->mcast_count++;
25345779Sxy150489 
25355779Sxy150489 	/*
25365779Sxy150489 	 * Update the multicast table in the hardware
25375779Sxy150489 	 */
25385779Sxy150489 	igb_setup_multicst(igb);
25395779Sxy150489 
25406624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
25416624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
25426624Sgl147354 		return (EIO);
25436624Sgl147354 	}
25446624Sgl147354 
25455779Sxy150489 	return (0);
25465779Sxy150489 }
25475779Sxy150489 
25485779Sxy150489 /*
25495779Sxy150489  * igb_multicst_remove - Remove a multicst address
25505779Sxy150489  */
25515779Sxy150489 int
25525779Sxy150489 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr)
25535779Sxy150489 {
25549775SVitezslav.Batrla@Sun.COM 	struct ether_addr *new_table;
25559775SVitezslav.Batrla@Sun.COM 	size_t new_len;
25569775SVitezslav.Batrla@Sun.COM 	size_t old_len;
25575779Sxy150489 	int i;
25585779Sxy150489 
25595779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
25605779Sxy150489 
25615779Sxy150489 	for (i = 0; i < igb->mcast_count; i++) {
25625779Sxy150489 		if (bcmp(multiaddr, &igb->mcast_table[i],
25635779Sxy150489 		    ETHERADDRL) == 0) {
25645779Sxy150489 			for (i++; i < igb->mcast_count; i++) {
25655779Sxy150489 				igb->mcast_table[i - 1] =
25665779Sxy150489 				    igb->mcast_table[i];
25675779Sxy150489 			}
25685779Sxy150489 			igb->mcast_count--;
25695779Sxy150489 			break;
25705779Sxy150489 		}
25715779Sxy150489 	}
25725779Sxy150489 
25739775SVitezslav.Batrla@Sun.COM 	if ((igb->mcast_alloc_count - igb->mcast_count) >
25749775SVitezslav.Batrla@Sun.COM 	    MCAST_ALLOC_COUNT) {
25759775SVitezslav.Batrla@Sun.COM 		old_len = igb->mcast_alloc_count *
25769775SVitezslav.Batrla@Sun.COM 		    sizeof (struct ether_addr);
25779775SVitezslav.Batrla@Sun.COM 		new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) *
25789775SVitezslav.Batrla@Sun.COM 		    sizeof (struct ether_addr);
25799775SVitezslav.Batrla@Sun.COM 
25809775SVitezslav.Batrla@Sun.COM 		new_table = kmem_alloc(new_len, KM_NOSLEEP);
25819775SVitezslav.Batrla@Sun.COM 		if (new_table != NULL) {
25829775SVitezslav.Batrla@Sun.COM 			bcopy(igb->mcast_table, new_table, new_len);
25839775SVitezslav.Batrla@Sun.COM 			kmem_free(igb->mcast_table, old_len);
25849775SVitezslav.Batrla@Sun.COM 			igb->mcast_alloc_count -= MCAST_ALLOC_COUNT;
25859775SVitezslav.Batrla@Sun.COM 			igb->mcast_table = new_table;
25869775SVitezslav.Batrla@Sun.COM 		}
25879775SVitezslav.Batrla@Sun.COM 	}
25889775SVitezslav.Batrla@Sun.COM 
25895779Sxy150489 	/*
25905779Sxy150489 	 * Update the multicast table in the hardware
25915779Sxy150489 	 */
25925779Sxy150489 	igb_setup_multicst(igb);
25935779Sxy150489 
25946624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
25956624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
25966624Sgl147354 		return (EIO);
25976624Sgl147354 	}
25986624Sgl147354 
25995779Sxy150489 	return (0);
26005779Sxy150489 }
26015779Sxy150489 
26029775SVitezslav.Batrla@Sun.COM static void
26039775SVitezslav.Batrla@Sun.COM igb_release_multicast(igb_t *igb)
26049775SVitezslav.Batrla@Sun.COM {
26059775SVitezslav.Batrla@Sun.COM 	if (igb->mcast_table != NULL) {
26069775SVitezslav.Batrla@Sun.COM 		kmem_free(igb->mcast_table,
26079775SVitezslav.Batrla@Sun.COM 		    igb->mcast_alloc_count * sizeof (struct ether_addr));
26089775SVitezslav.Batrla@Sun.COM 		igb->mcast_table = NULL;
26099775SVitezslav.Batrla@Sun.COM 	}
26109775SVitezslav.Batrla@Sun.COM }
26119775SVitezslav.Batrla@Sun.COM 
26125779Sxy150489 /*
26135779Sxy150489  * igb_setup_multicast - setup multicast data structures
26145779Sxy150489  *
26155779Sxy150489  * This routine initializes all of the multicast related structures
26165779Sxy150489  * and save them in the hardware registers.
26175779Sxy150489  */
26185779Sxy150489 static void
26195779Sxy150489 igb_setup_multicst(igb_t *igb)
26205779Sxy150489 {
26215779Sxy150489 	uint8_t *mc_addr_list;
26225779Sxy150489 	uint32_t mc_addr_count;
26235779Sxy150489 	struct e1000_hw *hw = &igb->hw;
26245779Sxy150489 
26255779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
26269775SVitezslav.Batrla@Sun.COM 	ASSERT(igb->mcast_count <= igb->mcast_max_num);
26275779Sxy150489 
26285779Sxy150489 	mc_addr_list = (uint8_t *)igb->mcast_table;
26295779Sxy150489 	mc_addr_count = igb->mcast_count;
26305779Sxy150489 
26315779Sxy150489 	/*
26325779Sxy150489 	 * Update the multicase addresses to the MTA registers
26335779Sxy150489 	 */
263410319SJason.Xu@Sun.COM 	e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
26355779Sxy150489 }
26365779Sxy150489 
26375779Sxy150489 /*
26385779Sxy150489  * igb_get_conf - Get driver configurations set in driver.conf
26395779Sxy150489  *
26405779Sxy150489  * This routine gets user-configured values out of the configuration
26415779Sxy150489  * file igb.conf.
26425779Sxy150489  *
26435779Sxy150489  * For each configurable value, there is a minimum, a maximum, and a
26445779Sxy150489  * default.
26455779Sxy150489  * If user does not configure a value, use the default.
26465779Sxy150489  * If user configures below the minimum, use the minumum.
26475779Sxy150489  * If user configures above the maximum, use the maxumum.
26485779Sxy150489  */
26495779Sxy150489 static void
26505779Sxy150489 igb_get_conf(igb_t *igb)
26515779Sxy150489 {
26525779Sxy150489 	struct e1000_hw *hw = &igb->hw;
26535779Sxy150489 	uint32_t default_mtu;
26545779Sxy150489 	uint32_t flow_control;
26558275SEric Cheng 	uint32_t ring_per_group;
26568275SEric Cheng 	int i;
26575779Sxy150489 
26585779Sxy150489 	/*
26595779Sxy150489 	 * igb driver supports the following user configurations:
26605779Sxy150489 	 *
26615779Sxy150489 	 * Link configurations:
26625779Sxy150489 	 *    adv_autoneg_cap
26635779Sxy150489 	 *    adv_1000fdx_cap
26645779Sxy150489 	 *    adv_100fdx_cap
26655779Sxy150489 	 *    adv_100hdx_cap
26665779Sxy150489 	 *    adv_10fdx_cap
26675779Sxy150489 	 *    adv_10hdx_cap
26685779Sxy150489 	 * Note: 1000hdx is not supported.
26695779Sxy150489 	 *
26705779Sxy150489 	 * Jumbo frame configuration:
26715779Sxy150489 	 *    default_mtu
26725779Sxy150489 	 *
26735779Sxy150489 	 * Ethernet flow control configuration:
26745779Sxy150489 	 *    flow_control
26755779Sxy150489 	 *
26765779Sxy150489 	 * Multiple rings configurations:
26775779Sxy150489 	 *    tx_queue_number
26785779Sxy150489 	 *    tx_ring_size
26795779Sxy150489 	 *    rx_queue_number
26805779Sxy150489 	 *    rx_ring_size
26815779Sxy150489 	 *
26825779Sxy150489 	 * Call igb_get_prop() to get the value for a specific
26835779Sxy150489 	 * configuration parameter.
26845779Sxy150489 	 */
26855779Sxy150489 
26865779Sxy150489 	/*
26875779Sxy150489 	 * Link configurations
26885779Sxy150489 	 */
26895779Sxy150489 	igb->param_adv_autoneg_cap = igb_get_prop(igb,
26905779Sxy150489 	    PROP_ADV_AUTONEG_CAP, 0, 1, 1);
26915779Sxy150489 	igb->param_adv_1000fdx_cap = igb_get_prop(igb,
26925779Sxy150489 	    PROP_ADV_1000FDX_CAP, 0, 1, 1);
26935779Sxy150489 	igb->param_adv_100fdx_cap = igb_get_prop(igb,
26945779Sxy150489 	    PROP_ADV_100FDX_CAP, 0, 1, 1);
26955779Sxy150489 	igb->param_adv_100hdx_cap = igb_get_prop(igb,
26965779Sxy150489 	    PROP_ADV_100HDX_CAP, 0, 1, 1);
26975779Sxy150489 	igb->param_adv_10fdx_cap = igb_get_prop(igb,
26985779Sxy150489 	    PROP_ADV_10FDX_CAP, 0, 1, 1);
26995779Sxy150489 	igb->param_adv_10hdx_cap = igb_get_prop(igb,
27005779Sxy150489 	    PROP_ADV_10HDX_CAP, 0, 1, 1);
27015779Sxy150489 
27025779Sxy150489 	/*
27035779Sxy150489 	 * Jumbo frame configurations
27045779Sxy150489 	 */
27055779Sxy150489 	default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
27065779Sxy150489 	    MIN_MTU, MAX_MTU, DEFAULT_MTU);
27075779Sxy150489 
27085779Sxy150489 	igb->max_frame_size = default_mtu +
27095779Sxy150489 	    sizeof (struct ether_vlan_header) + ETHERFCSL;
27105779Sxy150489 
27115779Sxy150489 	/*
27125779Sxy150489 	 * Ethernet flow control configuration
27135779Sxy150489 	 */
27145779Sxy150489 	flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL,
27155779Sxy150489 	    e1000_fc_none, 4, e1000_fc_full);
27165779Sxy150489 	if (flow_control == 4)
27175779Sxy150489 		flow_control = e1000_fc_default;
27185779Sxy150489 
27198571SChenlu.Chen@Sun.COM 	hw->fc.requested_mode = flow_control;
27205779Sxy150489 
27215779Sxy150489 	/*
27225779Sxy150489 	 * Multiple rings configurations
27235779Sxy150489 	 */
27245779Sxy150489 	igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE,
27255779Sxy150489 	    MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
27265779Sxy150489 	igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE,
27275779Sxy150489 	    MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
27285779Sxy150489 
272910319SJason.Xu@Sun.COM 	igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0);
27308275SEric Cheng 	igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM,
27318275SEric Cheng 	    MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM);
27328571SChenlu.Chen@Sun.COM 	/*
273311155SJason.Xu@Sun.COM 	 * Currently we do not support VMDq for 82576 and 82580.
27348571SChenlu.Chen@Sun.COM 	 * If it is e1000_82576, set num_rx_groups to 1.
27358571SChenlu.Chen@Sun.COM 	 */
273611155SJason.Xu@Sun.COM 	if (hw->mac.type >= e1000_82576)
27378571SChenlu.Chen@Sun.COM 		igb->num_rx_groups = 1;
27388275SEric Cheng 
27398275SEric Cheng 	if (igb->mr_enable) {
27408571SChenlu.Chen@Sun.COM 		igb->num_tx_rings = igb->capab->def_tx_que_num;
27418571SChenlu.Chen@Sun.COM 		igb->num_rx_rings = igb->capab->def_rx_que_num;
27428275SEric Cheng 	} else {
27438275SEric Cheng 		igb->num_tx_rings = 1;
27448275SEric Cheng 		igb->num_rx_rings = 1;
27458275SEric Cheng 
27468275SEric Cheng 		if (igb->num_rx_groups > 1) {
27478275SEric Cheng 			igb_error(igb,
27488275SEric Cheng 			    "Invalid rx groups number. Please enable multiple "
27498275SEric Cheng 			    "rings first");
27508275SEric Cheng 			igb->num_rx_groups = 1;
27518275SEric Cheng 		}
27528275SEric Cheng 	}
27538275SEric Cheng 
27548275SEric Cheng 	/*
27558275SEric Cheng 	 * Check the divisibility between rx rings and rx groups.
27568275SEric Cheng 	 */
27578275SEric Cheng 	for (i = igb->num_rx_groups; i > 0; i--) {
27588275SEric Cheng 		if ((igb->num_rx_rings % i) == 0)
27598275SEric Cheng 			break;
27608275SEric Cheng 	}
27618275SEric Cheng 	if (i != igb->num_rx_groups) {
27628275SEric Cheng 		igb_error(igb,
27638275SEric Cheng 		    "Invalid rx groups number. Downgrade the rx group "
27648275SEric Cheng 		    "number to %d.", i);
27658275SEric Cheng 		igb->num_rx_groups = i;
27668275SEric Cheng 	}
27678275SEric Cheng 
27688275SEric Cheng 	/*
27698275SEric Cheng 	 * Get the ring number per group.
27708275SEric Cheng 	 */
27718275SEric Cheng 	ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
27728275SEric Cheng 
27738275SEric Cheng 	if (igb->num_rx_groups == 1) {
27748275SEric Cheng 		/*
27758275SEric Cheng 		 * One rx ring group, the rx ring number is num_rx_rings.
27768275SEric Cheng 		 */
27778275SEric Cheng 		igb->vmdq_mode = E1000_VMDQ_OFF;
27788275SEric Cheng 	} else if (ring_per_group == 1) {
27798275SEric Cheng 		/*
27808275SEric Cheng 		 * Multiple rx groups, each group has one rx ring.
27818275SEric Cheng 		 */
27828275SEric Cheng 		igb->vmdq_mode = E1000_VMDQ_MAC;
27838275SEric Cheng 	} else {
27848275SEric Cheng 		/*
27858275SEric Cheng 		 * Multiple groups and multiple rings.
27868275SEric Cheng 		 */
27878275SEric Cheng 		igb->vmdq_mode = E1000_VMDQ_MAC_RSS;
27888275SEric Cheng 	}
27898275SEric Cheng 
27905779Sxy150489 	/*
27915779Sxy150489 	 * Tunable used to force an interrupt type. The only use is
27925779Sxy150489 	 * for testing of the lesser interrupt types.
27935779Sxy150489 	 * 0 = don't force interrupt type
27945779Sxy150489 	 * 1 = force interrupt type MSIX
27955779Sxy150489 	 * 2 = force interrupt type MSI
27965779Sxy150489 	 * 3 = force interrupt type Legacy
27975779Sxy150489 	 */
27985779Sxy150489 	igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE,
27995812Sxy150489 	    IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE);
28005779Sxy150489 
28015779Sxy150489 	igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE,
28025779Sxy150489 	    0, 1, 1);
28035779Sxy150489 	igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE,
28045779Sxy150489 	    0, 1, 1);
28055779Sxy150489 	igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE,
28069188SPaul.Guo@Sun.COM 	    0, 1, 1);
28075779Sxy150489 	igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE,
28085779Sxy150489 	    0, 1, 1);
28095779Sxy150489 
28109188SPaul.Guo@Sun.COM 	/*
28119188SPaul.Guo@Sun.COM 	 * igb LSO needs the tx h/w checksum support.
28129188SPaul.Guo@Sun.COM 	 * Here LSO will be disabled if tx h/w checksum has been disabled.
28139188SPaul.Guo@Sun.COM 	 */
28149188SPaul.Guo@Sun.COM 	if (igb->tx_hcksum_enable == B_FALSE)
28159188SPaul.Guo@Sun.COM 		igb->lso_enable = B_FALSE;
28169188SPaul.Guo@Sun.COM 
28175779Sxy150489 	igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD,
28185779Sxy150489 	    MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
28195779Sxy150489 	    DEFAULT_TX_COPY_THRESHOLD);
28205779Sxy150489 	igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD,
28215779Sxy150489 	    MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD,
28225779Sxy150489 	    DEFAULT_TX_RECYCLE_THRESHOLD);
28235779Sxy150489 	igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD,
28245779Sxy150489 	    MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD,
28255779Sxy150489 	    DEFAULT_TX_OVERLOAD_THRESHOLD);
28265779Sxy150489 	igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD,
28275779Sxy150489 	    MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD,
28285779Sxy150489 	    DEFAULT_TX_RESCHED_THRESHOLD);
28295779Sxy150489 
28305779Sxy150489 	igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD,
28315779Sxy150489 	    MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
28325779Sxy150489 	    DEFAULT_RX_COPY_THRESHOLD);
28335779Sxy150489 	igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR,
28345779Sxy150489 	    MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
28355779Sxy150489 	    DEFAULT_RX_LIMIT_PER_INTR);
28365779Sxy150489 
28375779Sxy150489 	igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING,
28388571SChenlu.Chen@Sun.COM 	    igb->capab->min_intr_throttle,
28398571SChenlu.Chen@Sun.COM 	    igb->capab->max_intr_throttle,
28408571SChenlu.Chen@Sun.COM 	    igb->capab->def_intr_throttle);
28419775SVitezslav.Batrla@Sun.COM 
28429775SVitezslav.Batrla@Sun.COM 	/*
28439775SVitezslav.Batrla@Sun.COM 	 * Max number of multicast addresses
28449775SVitezslav.Batrla@Sun.COM 	 */
28459775SVitezslav.Batrla@Sun.COM 	igb->mcast_max_num =
28469775SVitezslav.Batrla@Sun.COM 	    igb_get_prop(igb, PROP_MCAST_MAX_NUM,
28479775SVitezslav.Batrla@Sun.COM 	    MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM);
28485779Sxy150489 }
28495779Sxy150489 
28505779Sxy150489 /*
28515779Sxy150489  * igb_get_prop - Get a property value out of the configuration file igb.conf
28525779Sxy150489  *
28535779Sxy150489  * Caller provides the name of the property, a default value, a minimum
28545779Sxy150489  * value, and a maximum value.
28555779Sxy150489  *
28565779Sxy150489  * Return configured value of the property, with default, minimum and
28575779Sxy150489  * maximum properly applied.
28585779Sxy150489  */
28595779Sxy150489 static int
28605779Sxy150489 igb_get_prop(igb_t *igb,
28615779Sxy150489     char *propname,	/* name of the property */
28625779Sxy150489     int minval,		/* minimum acceptable value */
28635779Sxy150489     int maxval,		/* maximim acceptable value */
28645779Sxy150489     int defval)		/* default value */
28655779Sxy150489 {
28665779Sxy150489 	int value;
28675779Sxy150489 
28685779Sxy150489 	/*
28695779Sxy150489 	 * Call ddi_prop_get_int() to read the conf settings
28705779Sxy150489 	 */
28715779Sxy150489 	value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip,
28725779Sxy150489 	    DDI_PROP_DONTPASS, propname, defval);
28735779Sxy150489 
28745779Sxy150489 	if (value > maxval)
28755779Sxy150489 		value = maxval;
28765779Sxy150489 
28775779Sxy150489 	if (value < minval)
28785779Sxy150489 		value = minval;
28795779Sxy150489 
28805779Sxy150489 	return (value);
28815779Sxy150489 }
28825779Sxy150489 
28835779Sxy150489 /*
28845779Sxy150489  * igb_setup_link - Using the link properties to setup the link
28855779Sxy150489  */
28865779Sxy150489 int
28875779Sxy150489 igb_setup_link(igb_t *igb, boolean_t setup_hw)
28885779Sxy150489 {
28895779Sxy150489 	struct e1000_mac_info *mac;
28905779Sxy150489 	struct e1000_phy_info *phy;
28915779Sxy150489 	boolean_t invalid;
28925779Sxy150489 
28935779Sxy150489 	mac = &igb->hw.mac;
28945779Sxy150489 	phy = &igb->hw.phy;
28955779Sxy150489 	invalid = B_FALSE;
28965779Sxy150489 
28975779Sxy150489 	if (igb->param_adv_autoneg_cap == 1) {
28985779Sxy150489 		mac->autoneg = B_TRUE;
28995779Sxy150489 		phy->autoneg_advertised = 0;
29005779Sxy150489 
29015779Sxy150489 		/*
29025779Sxy150489 		 * 1000hdx is not supported for autonegotiation
29035779Sxy150489 		 */
29045779Sxy150489 		if (igb->param_adv_1000fdx_cap == 1)
29055779Sxy150489 			phy->autoneg_advertised |= ADVERTISE_1000_FULL;
29065779Sxy150489 
29075779Sxy150489 		if (igb->param_adv_100fdx_cap == 1)
29085779Sxy150489 			phy->autoneg_advertised |= ADVERTISE_100_FULL;
29095779Sxy150489 
29105779Sxy150489 		if (igb->param_adv_100hdx_cap == 1)
29115779Sxy150489 			phy->autoneg_advertised |= ADVERTISE_100_HALF;
29125779Sxy150489 
29135779Sxy150489 		if (igb->param_adv_10fdx_cap == 1)
29145779Sxy150489 			phy->autoneg_advertised |= ADVERTISE_10_FULL;
29155779Sxy150489 
29165779Sxy150489 		if (igb->param_adv_10hdx_cap == 1)
29175779Sxy150489 			phy->autoneg_advertised |= ADVERTISE_10_HALF;
29185779Sxy150489 
29195779Sxy150489 		if (phy->autoneg_advertised == 0)
29205779Sxy150489 			invalid = B_TRUE;
29215779Sxy150489 	} else {
29225779Sxy150489 		mac->autoneg = B_FALSE;
29235779Sxy150489 
29245779Sxy150489 		/*
29255779Sxy150489 		 * 1000fdx and 1000hdx are not supported for forced link
29265779Sxy150489 		 */
29275779Sxy150489 		if (igb->param_adv_100fdx_cap == 1)
29285779Sxy150489 			mac->forced_speed_duplex = ADVERTISE_100_FULL;
29295779Sxy150489 		else if (igb->param_adv_100hdx_cap == 1)
29305779Sxy150489 			mac->forced_speed_duplex = ADVERTISE_100_HALF;
29315779Sxy150489 		else if (igb->param_adv_10fdx_cap == 1)
29325779Sxy150489 			mac->forced_speed_duplex = ADVERTISE_10_FULL;
29335779Sxy150489 		else if (igb->param_adv_10hdx_cap == 1)
29345779Sxy150489 			mac->forced_speed_duplex = ADVERTISE_10_HALF;
29355779Sxy150489 		else
29365779Sxy150489 			invalid = B_TRUE;
29375779Sxy150489 	}
29385779Sxy150489 
29395779Sxy150489 	if (invalid) {
29405779Sxy150489 		igb_notice(igb, "Invalid link settings. Setup link to "
29415779Sxy150489 		    "autonegotiation with full link capabilities.");
29425779Sxy150489 		mac->autoneg = B_TRUE;
29435779Sxy150489 		phy->autoneg_advertised = ADVERTISE_1000_FULL |
29445779Sxy150489 		    ADVERTISE_100_FULL | ADVERTISE_100_HALF |
29455779Sxy150489 		    ADVERTISE_10_FULL | ADVERTISE_10_HALF;
29465779Sxy150489 	}
29475779Sxy150489 
29485779Sxy150489 	if (setup_hw) {
29495779Sxy150489 		if (e1000_setup_link(&igb->hw) != E1000_SUCCESS)
29505779Sxy150489 			return (IGB_FAILURE);
29515779Sxy150489 	}
29525779Sxy150489 
29535779Sxy150489 	return (IGB_SUCCESS);
29545779Sxy150489 }
29555779Sxy150489 
29565779Sxy150489 
29575779Sxy150489 /*
29585779Sxy150489  * igb_is_link_up - Check if the link is up
29595779Sxy150489  */
29605779Sxy150489 static boolean_t
29615779Sxy150489 igb_is_link_up(igb_t *igb)
29625779Sxy150489 {
29635779Sxy150489 	struct e1000_hw *hw = &igb->hw;
29648955SChenlu.Chen@Sun.COM 	boolean_t link_up = B_FALSE;
29655779Sxy150489 
29665779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
29675779Sxy150489 
29688955SChenlu.Chen@Sun.COM 	/*
29698955SChenlu.Chen@Sun.COM 	 * get_link_status is set in the interrupt handler on link-status-change
29708955SChenlu.Chen@Sun.COM 	 * or rx sequence error interrupt.  get_link_status will stay
29718955SChenlu.Chen@Sun.COM 	 * false until the e1000_check_for_link establishes link only
29728955SChenlu.Chen@Sun.COM 	 * for copper adapters.
29738955SChenlu.Chen@Sun.COM 	 */
29748955SChenlu.Chen@Sun.COM 	switch (hw->phy.media_type) {
29758955SChenlu.Chen@Sun.COM 	case e1000_media_type_copper:
29768955SChenlu.Chen@Sun.COM 		if (hw->mac.get_link_status) {
29778955SChenlu.Chen@Sun.COM 			(void) e1000_check_for_link(hw);
29788955SChenlu.Chen@Sun.COM 			link_up = !hw->mac.get_link_status;
29798955SChenlu.Chen@Sun.COM 		} else {
29808955SChenlu.Chen@Sun.COM 			link_up = B_TRUE;
29818955SChenlu.Chen@Sun.COM 		}
29828955SChenlu.Chen@Sun.COM 		break;
29838955SChenlu.Chen@Sun.COM 	case e1000_media_type_fiber:
29848955SChenlu.Chen@Sun.COM 		(void) e1000_check_for_link(hw);
29858955SChenlu.Chen@Sun.COM 		link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
29868955SChenlu.Chen@Sun.COM 		break;
29878955SChenlu.Chen@Sun.COM 	case e1000_media_type_internal_serdes:
29888955SChenlu.Chen@Sun.COM 		(void) e1000_check_for_link(hw);
29898955SChenlu.Chen@Sun.COM 		link_up = hw->mac.serdes_has_link;
29908955SChenlu.Chen@Sun.COM 		break;
29915779Sxy150489 	}
29925779Sxy150489 
29935779Sxy150489 	return (link_up);
29945779Sxy150489 }
29955779Sxy150489 
29965779Sxy150489 /*
29975779Sxy150489  * igb_link_check - Link status processing
29985779Sxy150489  */
29995779Sxy150489 static boolean_t
30005779Sxy150489 igb_link_check(igb_t *igb)
30015779Sxy150489 {
30025779Sxy150489 	struct e1000_hw *hw = &igb->hw;
30035779Sxy150489 	uint16_t speed = 0, duplex = 0;
30045779Sxy150489 	boolean_t link_changed = B_FALSE;
30055779Sxy150489 
30065779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
30075779Sxy150489 
30085779Sxy150489 	if (igb_is_link_up(igb)) {
30095779Sxy150489 		/*
30105779Sxy150489 		 * The Link is up, check whether it was marked as down earlier
30115779Sxy150489 		 */
30125779Sxy150489 		if (igb->link_state != LINK_STATE_UP) {
30135779Sxy150489 			(void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
30145779Sxy150489 			igb->link_speed = speed;
30155779Sxy150489 			igb->link_duplex = duplex;
30165779Sxy150489 			igb->link_state = LINK_STATE_UP;
30175779Sxy150489 			igb->link_down_timeout = 0;
30185779Sxy150489 			link_changed = B_TRUE;
301911367SJason.Xu@Sun.COM 			if (!igb->link_complete)
302011367SJason.Xu@Sun.COM 				igb_stop_link_timer(igb);
30215779Sxy150489 		}
302211367SJason.Xu@Sun.COM 	} else if (igb->link_complete) {
30235779Sxy150489 		if (igb->link_state != LINK_STATE_DOWN) {
30245779Sxy150489 			igb->link_speed = 0;
30255779Sxy150489 			igb->link_duplex = 0;
30265779Sxy150489 			igb->link_state = LINK_STATE_DOWN;
30275779Sxy150489 			link_changed = B_TRUE;
30285779Sxy150489 		}
30295779Sxy150489 
30305779Sxy150489 		if (igb->igb_state & IGB_STARTED) {
30315779Sxy150489 			if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) {
30325779Sxy150489 				igb->link_down_timeout++;
30335779Sxy150489 			} else if (igb->link_down_timeout ==
30345779Sxy150489 			    MAX_LINK_DOWN_TIMEOUT) {
30355779Sxy150489 				igb_tx_clean(igb);
30365779Sxy150489 				igb->link_down_timeout++;
30375779Sxy150489 			}
30385779Sxy150489 		}
30395779Sxy150489 	}
30405779Sxy150489 
304111367SJason.Xu@Sun.COM 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
30426624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
304311367SJason.Xu@Sun.COM 		return (B_FALSE);
304411367SJason.Xu@Sun.COM 	}
30456624Sgl147354 
30465779Sxy150489 	return (link_changed);
30475779Sxy150489 }
30485779Sxy150489 
30495779Sxy150489 /*
30505779Sxy150489  * igb_local_timer - driver watchdog function
30515779Sxy150489  *
305211155SJason.Xu@Sun.COM  * This function will handle the hardware stall check, link status
305311155SJason.Xu@Sun.COM  * check and other routines.
30545779Sxy150489  */
30555779Sxy150489 static void
30565779Sxy150489 igb_local_timer(void *arg)
30575779Sxy150489 {
30585779Sxy150489 	igb_t *igb = (igb_t *)arg;
30598955SChenlu.Chen@Sun.COM 	boolean_t link_changed = B_FALSE;
30605779Sxy150489 
306111367SJason.Xu@Sun.COM 	if (igb->igb_state & IGB_ERROR) {
306211367SJason.Xu@Sun.COM 		igb->reset_count++;
306311367SJason.Xu@Sun.COM 		if (igb_reset(igb) == IGB_SUCCESS)
306411367SJason.Xu@Sun.COM 			ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
306511367SJason.Xu@Sun.COM 
306611367SJason.Xu@Sun.COM 		igb_restart_watchdog_timer(igb);
306711367SJason.Xu@Sun.COM 		return;
306811367SJason.Xu@Sun.COM 	}
306911367SJason.Xu@Sun.COM 
307011367SJason.Xu@Sun.COM 	if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) {
30716624Sgl147354 		igb_fm_ereport(igb, DDI_FM_DEVICE_STALL);
30728955SChenlu.Chen@Sun.COM 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
30735779Sxy150489 		igb->reset_count++;
30746624Sgl147354 		if (igb_reset(igb) == IGB_SUCCESS)
307511367SJason.Xu@Sun.COM 			ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
307611367SJason.Xu@Sun.COM 
307711367SJason.Xu@Sun.COM 		igb_restart_watchdog_timer(igb);
307811367SJason.Xu@Sun.COM 		return;
30795779Sxy150489 	}
30805779Sxy150489 
30815779Sxy150489 	mutex_enter(&igb->gen_lock);
30828955SChenlu.Chen@Sun.COM 	if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED))
30838955SChenlu.Chen@Sun.COM 		link_changed = igb_link_check(igb);
30845779Sxy150489 	mutex_exit(&igb->gen_lock);
30855779Sxy150489 
30865779Sxy150489 	if (link_changed)
30875779Sxy150489 		mac_link_update(igb->mac_hdl, igb->link_state);
30885779Sxy150489 
30895779Sxy150489 	igb_restart_watchdog_timer(igb);
30905779Sxy150489 }
30915779Sxy150489 
30925779Sxy150489 /*
309311367SJason.Xu@Sun.COM  * igb_link_timer - link setup timer function
309411367SJason.Xu@Sun.COM  *
309511367SJason.Xu@Sun.COM  * It is called when the timer for link setup is expired, which indicates
309611367SJason.Xu@Sun.COM  * the completion of the link setup. The link state will not be updated
309711367SJason.Xu@Sun.COM  * until the link setup is completed. And the link state will not be sent
309811367SJason.Xu@Sun.COM  * to the upper layer through mac_link_update() in this function. It will
309911367SJason.Xu@Sun.COM  * be updated in the local timer routine or the interrupts service routine
310011367SJason.Xu@Sun.COM  * after the interface is started (plumbed).
310111367SJason.Xu@Sun.COM  */
310211367SJason.Xu@Sun.COM static void
310311367SJason.Xu@Sun.COM igb_link_timer(void *arg)
310411367SJason.Xu@Sun.COM {
310511367SJason.Xu@Sun.COM 	igb_t *igb = (igb_t *)arg;
310611367SJason.Xu@Sun.COM 
310711367SJason.Xu@Sun.COM 	mutex_enter(&igb->link_lock);
310811367SJason.Xu@Sun.COM 	igb->link_complete = B_TRUE;
310911367SJason.Xu@Sun.COM 	igb->link_tid = 0;
311011367SJason.Xu@Sun.COM 	mutex_exit(&igb->link_lock);
311111367SJason.Xu@Sun.COM }
311211367SJason.Xu@Sun.COM /*
31135779Sxy150489  * igb_stall_check - check for transmit stall
31145779Sxy150489  *
31155779Sxy150489  * This function checks if the adapter is stalled (in transmit).
31165779Sxy150489  *
31175779Sxy150489  * It is called each time the watchdog timeout is invoked.
31185779Sxy150489  * If the transmit descriptor reclaim continuously fails,
31195779Sxy150489  * the watchdog value will increment by 1. If the watchdog
31205779Sxy150489  * value exceeds the threshold, the igb is assumed to
31215779Sxy150489  * have stalled and need to be reset.
31225779Sxy150489  */
31235779Sxy150489 static boolean_t
31245779Sxy150489 igb_stall_check(igb_t *igb)
31255779Sxy150489 {
31265779Sxy150489 	igb_tx_ring_t *tx_ring;
312711155SJason.Xu@Sun.COM 	struct e1000_hw *hw = &igb->hw;
31285779Sxy150489 	boolean_t result;
31295779Sxy150489 	int i;
31305779Sxy150489 
31315779Sxy150489 	if (igb->link_state != LINK_STATE_UP)
31325779Sxy150489 		return (B_FALSE);
31335779Sxy150489 
31345779Sxy150489 	/*
31355779Sxy150489 	 * If any tx ring is stalled, we'll reset the chipset
31365779Sxy150489 	 */
31375779Sxy150489 	result = B_FALSE;
31385779Sxy150489 	for (i = 0; i < igb->num_tx_rings; i++) {
31395779Sxy150489 		tx_ring = &igb->tx_rings[i];
31405779Sxy150489 
31415779Sxy150489 		if (tx_ring->recycle_fail > 0)
31425779Sxy150489 			tx_ring->stall_watchdog++;
31435779Sxy150489 		else
31445779Sxy150489 			tx_ring->stall_watchdog = 0;
31455779Sxy150489 
31465779Sxy150489 		if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
31475779Sxy150489 			result = B_TRUE;
314811155SJason.Xu@Sun.COM 			if (hw->mac.type == e1000_82580) {
314911155SJason.Xu@Sun.COM 				hw->dev_spec._82575.global_device_reset
315011155SJason.Xu@Sun.COM 				    = B_TRUE;
315111155SJason.Xu@Sun.COM 			}
31525779Sxy150489 			break;
31535779Sxy150489 		}
31545779Sxy150489 	}
31555779Sxy150489 
31565779Sxy150489 	if (result) {
31575779Sxy150489 		tx_ring->stall_watchdog = 0;
31585779Sxy150489 		tx_ring->recycle_fail = 0;
31595779Sxy150489 	}
31605779Sxy150489 
31615779Sxy150489 	return (result);
31625779Sxy150489 }
31635779Sxy150489 
31645779Sxy150489 
31655779Sxy150489 /*
31665779Sxy150489  * is_valid_mac_addr - Check if the mac address is valid
31675779Sxy150489  */
31685779Sxy150489 static boolean_t
31695779Sxy150489 is_valid_mac_addr(uint8_t *mac_addr)
31705779Sxy150489 {
31715779Sxy150489 	const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
31725779Sxy150489 	const uint8_t addr_test2[6] =
31735779Sxy150489 	    { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
31745779Sxy150489 
31755779Sxy150489 	if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
31765779Sxy150489 	    !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
31775779Sxy150489 		return (B_FALSE);
31785779Sxy150489 
31795779Sxy150489 	return (B_TRUE);
31805779Sxy150489 }
31815779Sxy150489 
31825779Sxy150489 static boolean_t
31835779Sxy150489 igb_find_mac_address(igb_t *igb)
31845779Sxy150489 {
31855779Sxy150489 	struct e1000_hw *hw = &igb->hw;
31865779Sxy150489 #ifdef __sparc
31875779Sxy150489 	uchar_t *bytes;
31885779Sxy150489 	struct ether_addr sysaddr;
31895779Sxy150489 	uint_t nelts;
31905779Sxy150489 	int err;
31915779Sxy150489 	boolean_t found = B_FALSE;
31925779Sxy150489 
31935779Sxy150489 	/*
31945779Sxy150489 	 * The "vendor's factory-set address" may already have
31955779Sxy150489 	 * been extracted from the chip, but if the property
31965779Sxy150489 	 * "local-mac-address" is set we use that instead.
31975779Sxy150489 	 *
31985779Sxy150489 	 * We check whether it looks like an array of 6
31995779Sxy150489 	 * bytes (which it should, if OBP set it).  If we can't
32005779Sxy150489 	 * make sense of it this way, we'll ignore it.
32015779Sxy150489 	 */
32025779Sxy150489 	err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
32035779Sxy150489 	    DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
32045779Sxy150489 	if (err == DDI_PROP_SUCCESS) {
32055779Sxy150489 		if (nelts == ETHERADDRL) {
32065779Sxy150489 			while (nelts--)
32075779Sxy150489 				hw->mac.addr[nelts] = bytes[nelts];
32085779Sxy150489 			found = B_TRUE;
32095779Sxy150489 		}
32105779Sxy150489 		ddi_prop_free(bytes);
32115779Sxy150489 	}
32125779Sxy150489 
32135779Sxy150489 	/*
32145779Sxy150489 	 * Look up the OBP property "local-mac-address?". If the user has set
32155779Sxy150489 	 * 'local-mac-address? = false', use "the system address" instead.
32165779Sxy150489 	 */
32175779Sxy150489 	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0,
32185779Sxy150489 	    "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
32195779Sxy150489 		if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
32205779Sxy150489 			if (localetheraddr(NULL, &sysaddr) != 0) {
32215779Sxy150489 				bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
32225779Sxy150489 				found = B_TRUE;
32235779Sxy150489 			}
32245779Sxy150489 		}
32255779Sxy150489 		ddi_prop_free(bytes);
32265779Sxy150489 	}
32275779Sxy150489 
32285779Sxy150489 	/*
32295779Sxy150489 	 * Finally(!), if there's a valid "mac-address" property (created
32305779Sxy150489 	 * if we netbooted from this interface), we must use this instead
32315779Sxy150489 	 * of any of the above to ensure that the NFS/install server doesn't
32325779Sxy150489 	 * get confused by the address changing as Solaris takes over!
32335779Sxy150489 	 */
32345779Sxy150489 	err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
32355779Sxy150489 	    DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
32365779Sxy150489 	if (err == DDI_PROP_SUCCESS) {
32375779Sxy150489 		if (nelts == ETHERADDRL) {
32385779Sxy150489 			while (nelts--)
32395779Sxy150489 				hw->mac.addr[nelts] = bytes[nelts];
32405779Sxy150489 			found = B_TRUE;
32415779Sxy150489 		}
32425779Sxy150489 		ddi_prop_free(bytes);
32435779Sxy150489 	}
32445779Sxy150489 
32455779Sxy150489 	if (found) {
32465779Sxy150489 		bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
32475779Sxy150489 		return (B_TRUE);
32485779Sxy150489 	}
32495779Sxy150489 #endif
32505779Sxy150489 
32515779Sxy150489 	/*
32525779Sxy150489 	 * Read the device MAC address from the EEPROM
32535779Sxy150489 	 */
32545779Sxy150489 	if (e1000_read_mac_addr(hw) != E1000_SUCCESS)
32555779Sxy150489 		return (B_FALSE);
32565779Sxy150489 
32575779Sxy150489 	return (B_TRUE);
32585779Sxy150489 }
32595779Sxy150489 
32605779Sxy150489 #pragma inline(igb_arm_watchdog_timer)
32615779Sxy150489 
32625779Sxy150489 static void
32635779Sxy150489 igb_arm_watchdog_timer(igb_t *igb)
32645779Sxy150489 {
32655779Sxy150489 	/*
32665779Sxy150489 	 * Fire a watchdog timer
32675779Sxy150489 	 */
32685779Sxy150489 	igb->watchdog_tid =
32695779Sxy150489 	    timeout(igb_local_timer,
32705779Sxy150489 	    (void *)igb, 1 * drv_usectohz(1000000));
32715779Sxy150489 
32725779Sxy150489 }
32735779Sxy150489 
32745779Sxy150489 /*
32755779Sxy150489  * igb_enable_watchdog_timer - Enable and start the driver watchdog timer
32765779Sxy150489  */
32775779Sxy150489 void
32785779Sxy150489 igb_enable_watchdog_timer(igb_t *igb)
32795779Sxy150489 {
32805779Sxy150489 	mutex_enter(&igb->watchdog_lock);
32815779Sxy150489 
32825779Sxy150489 	if (!igb->watchdog_enable) {
32835779Sxy150489 		igb->watchdog_enable = B_TRUE;
32845779Sxy150489 		igb->watchdog_start = B_TRUE;
32855779Sxy150489 		igb_arm_watchdog_timer(igb);
32865779Sxy150489 	}
32875779Sxy150489 
32885779Sxy150489 	mutex_exit(&igb->watchdog_lock);
32895779Sxy150489 
32905779Sxy150489 }
32915779Sxy150489 
32925779Sxy150489 /*
32935779Sxy150489  * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer
32945779Sxy150489  */
32955779Sxy150489 void
32965779Sxy150489 igb_disable_watchdog_timer(igb_t *igb)
32975779Sxy150489 {
32985779Sxy150489 	timeout_id_t tid;
32995779Sxy150489 
33005779Sxy150489 	mutex_enter(&igb->watchdog_lock);
33015779Sxy150489 
33025779Sxy150489 	igb->watchdog_enable = B_FALSE;
33035779Sxy150489 	igb->watchdog_start = B_FALSE;
33045779Sxy150489 	tid = igb->watchdog_tid;
33055779Sxy150489 	igb->watchdog_tid = 0;
33065779Sxy150489 
33075779Sxy150489 	mutex_exit(&igb->watchdog_lock);
33085779Sxy150489 
33095779Sxy150489 	if (tid != 0)
33105779Sxy150489 		(void) untimeout(tid);
33115779Sxy150489 
33125779Sxy150489 }
33135779Sxy150489 
33145779Sxy150489 /*
33155779Sxy150489  * igb_start_watchdog_timer - Start the driver watchdog timer
33165779Sxy150489  */
33175779Sxy150489 static void
33185779Sxy150489 igb_start_watchdog_timer(igb_t *igb)
33195779Sxy150489 {
33205779Sxy150489 	mutex_enter(&igb->watchdog_lock);
33215779Sxy150489 
33225779Sxy150489 	if (igb->watchdog_enable) {
33235779Sxy150489 		if (!igb->watchdog_start) {
33245779Sxy150489 			igb->watchdog_start = B_TRUE;
33255779Sxy150489 			igb_arm_watchdog_timer(igb);
33265779Sxy150489 		}
33275779Sxy150489 	}
33285779Sxy150489 
33295779Sxy150489 	mutex_exit(&igb->watchdog_lock);
33305779Sxy150489 }
33315779Sxy150489 
33325779Sxy150489 /*
33335779Sxy150489  * igb_restart_watchdog_timer - Restart the driver watchdog timer
33345779Sxy150489  */
33355779Sxy150489 static void
33365779Sxy150489 igb_restart_watchdog_timer(igb_t *igb)
33375779Sxy150489 {
33385779Sxy150489 	mutex_enter(&igb->watchdog_lock);
33395779Sxy150489 
33405779Sxy150489 	if (igb->watchdog_start)
33415779Sxy150489 		igb_arm_watchdog_timer(igb);
33425779Sxy150489 
33435779Sxy150489 	mutex_exit(&igb->watchdog_lock);
33445779Sxy150489 }
33455779Sxy150489 
33465779Sxy150489 /*
33475779Sxy150489  * igb_stop_watchdog_timer - Stop the driver watchdog timer
33485779Sxy150489  */
33495779Sxy150489 static void
33505779Sxy150489 igb_stop_watchdog_timer(igb_t *igb)
33515779Sxy150489 {
33525779Sxy150489 	timeout_id_t tid;
33535779Sxy150489 
33545779Sxy150489 	mutex_enter(&igb->watchdog_lock);
33555779Sxy150489 
33565779Sxy150489 	igb->watchdog_start = B_FALSE;
33575779Sxy150489 	tid = igb->watchdog_tid;
33585779Sxy150489 	igb->watchdog_tid = 0;
33595779Sxy150489 
33605779Sxy150489 	mutex_exit(&igb->watchdog_lock);
33615779Sxy150489 
33625779Sxy150489 	if (tid != 0)
33635779Sxy150489 		(void) untimeout(tid);
33645779Sxy150489 }
33655779Sxy150489 
33665779Sxy150489 /*
336711367SJason.Xu@Sun.COM  * igb_start_link_timer - Start the link setup timer
336811367SJason.Xu@Sun.COM  */
336911367SJason.Xu@Sun.COM static void
337011367SJason.Xu@Sun.COM igb_start_link_timer(struct igb *igb)
337111367SJason.Xu@Sun.COM {
337211367SJason.Xu@Sun.COM 	struct e1000_hw *hw = &igb->hw;
337311367SJason.Xu@Sun.COM 	clock_t link_timeout;
337411367SJason.Xu@Sun.COM 
337511367SJason.Xu@Sun.COM 	if (hw->mac.autoneg)
337611367SJason.Xu@Sun.COM 		link_timeout = PHY_AUTO_NEG_LIMIT *
337711367SJason.Xu@Sun.COM 		    drv_usectohz(100000);
337811367SJason.Xu@Sun.COM 	else
337911367SJason.Xu@Sun.COM 		link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
338011367SJason.Xu@Sun.COM 
338111367SJason.Xu@Sun.COM 	mutex_enter(&igb->link_lock);
338211367SJason.Xu@Sun.COM 	if (hw->phy.autoneg_wait_to_complete) {
338311367SJason.Xu@Sun.COM 		igb->link_complete = B_TRUE;
338411367SJason.Xu@Sun.COM 	} else {
338511367SJason.Xu@Sun.COM 		igb->link_complete = B_FALSE;
338611367SJason.Xu@Sun.COM 		igb->link_tid = timeout(igb_link_timer, (void *)igb,
338711367SJason.Xu@Sun.COM 		    link_timeout);
338811367SJason.Xu@Sun.COM 	}
338911367SJason.Xu@Sun.COM 	mutex_exit(&igb->link_lock);
339011367SJason.Xu@Sun.COM }
339111367SJason.Xu@Sun.COM 
339211367SJason.Xu@Sun.COM /*
339311367SJason.Xu@Sun.COM  * igb_stop_link_timer - Stop the link setup timer
339411367SJason.Xu@Sun.COM  */
339511367SJason.Xu@Sun.COM static void
339611367SJason.Xu@Sun.COM igb_stop_link_timer(struct igb *igb)
339711367SJason.Xu@Sun.COM {
339811367SJason.Xu@Sun.COM 	timeout_id_t tid;
339911367SJason.Xu@Sun.COM 
340011367SJason.Xu@Sun.COM 	mutex_enter(&igb->link_lock);
340111367SJason.Xu@Sun.COM 	igb->link_complete = B_TRUE;
340211367SJason.Xu@Sun.COM 	tid = igb->link_tid;
340311367SJason.Xu@Sun.COM 	igb->link_tid = 0;
340411367SJason.Xu@Sun.COM 	mutex_exit(&igb->link_lock);
340511367SJason.Xu@Sun.COM 
340611367SJason.Xu@Sun.COM 	if (tid != 0)
340711367SJason.Xu@Sun.COM 		(void) untimeout(tid);
340811367SJason.Xu@Sun.COM }
340911367SJason.Xu@Sun.COM 
341011367SJason.Xu@Sun.COM /*
34115779Sxy150489  * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts
34125779Sxy150489  */
34135779Sxy150489 static void
34145779Sxy150489 igb_disable_adapter_interrupts(igb_t *igb)
34155779Sxy150489 {
34165779Sxy150489 	struct e1000_hw *hw = &igb->hw;
34175779Sxy150489 
34185779Sxy150489 	/*
34195779Sxy150489 	 * Set the IMC register to mask all the interrupts,
34205779Sxy150489 	 * including the tx interrupts.
34215779Sxy150489 	 */
34228571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_IMC, ~0);
34238571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_IAM, 0);
34245779Sxy150489 
34255779Sxy150489 	/*
34265779Sxy150489 	 * Additional disabling for MSI-X
34275779Sxy150489 	 */
34285779Sxy150489 	if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
34298571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIMC, ~0);
34308571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIAC, 0);
34318571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIAM, 0);
34325779Sxy150489 	}
34335779Sxy150489 
34345779Sxy150489 	E1000_WRITE_FLUSH(hw);
34355779Sxy150489 }
34365779Sxy150489 
34375779Sxy150489 /*
343811155SJason.Xu@Sun.COM  * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580
343911155SJason.Xu@Sun.COM  */
344011155SJason.Xu@Sun.COM static void
344111155SJason.Xu@Sun.COM igb_enable_adapter_interrupts_82580(igb_t *igb)
344211155SJason.Xu@Sun.COM {
344311155SJason.Xu@Sun.COM 	struct e1000_hw *hw = &igb->hw;
344411155SJason.Xu@Sun.COM 
344511155SJason.Xu@Sun.COM 	/* Clear any pending interrupts */
344611155SJason.Xu@Sun.COM 	(void) E1000_READ_REG(hw, E1000_ICR);
344711155SJason.Xu@Sun.COM 	igb->ims_mask |= E1000_IMS_DRSTA;
344811155SJason.Xu@Sun.COM 
344911155SJason.Xu@Sun.COM 	if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
345011155SJason.Xu@Sun.COM 
345111155SJason.Xu@Sun.COM 		/* Interrupt enabling for MSI-X */
345211155SJason.Xu@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
345311155SJason.Xu@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
345411155SJason.Xu@Sun.COM 		igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA);
345511155SJason.Xu@Sun.COM 		E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
345611155SJason.Xu@Sun.COM 	} else { /* Interrupt enabling for MSI and legacy */
345711155SJason.Xu@Sun.COM 		E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
345811155SJason.Xu@Sun.COM 		igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
345911155SJason.Xu@Sun.COM 		igb->ims_mask |= E1000_IMS_DRSTA;
346011155SJason.Xu@Sun.COM 		E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
346111155SJason.Xu@Sun.COM 	}
346211155SJason.Xu@Sun.COM 
346311155SJason.Xu@Sun.COM 	/* Disable auto-mask for ICR interrupt bits */
346411155SJason.Xu@Sun.COM 	E1000_WRITE_REG(hw, E1000_IAM, 0);
346511155SJason.Xu@Sun.COM 
346611155SJason.Xu@Sun.COM 	E1000_WRITE_FLUSH(hw);
346711155SJason.Xu@Sun.COM }
346811155SJason.Xu@Sun.COM 
346911155SJason.Xu@Sun.COM /*
34708571SChenlu.Chen@Sun.COM  * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576
34715779Sxy150489  */
34725779Sxy150489 static void
34738571SChenlu.Chen@Sun.COM igb_enable_adapter_interrupts_82576(igb_t *igb)
34748571SChenlu.Chen@Sun.COM {
34758571SChenlu.Chen@Sun.COM 	struct e1000_hw *hw = &igb->hw;
34768571SChenlu.Chen@Sun.COM 
34778955SChenlu.Chen@Sun.COM 	/* Clear any pending interrupts */
34788955SChenlu.Chen@Sun.COM 	(void) E1000_READ_REG(hw, E1000_ICR);
34798955SChenlu.Chen@Sun.COM 
34808571SChenlu.Chen@Sun.COM 	if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
34818571SChenlu.Chen@Sun.COM 
34828571SChenlu.Chen@Sun.COM 		/* Interrupt enabling for MSI-X */
34838571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
34848571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
34858571SChenlu.Chen@Sun.COM 		igb->ims_mask = E1000_IMS_LSC;
34868571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
34878571SChenlu.Chen@Sun.COM 	} else {
34888571SChenlu.Chen@Sun.COM 		/* Interrupt enabling for MSI and legacy */
34898571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
34908571SChenlu.Chen@Sun.COM 		igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
34918571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG(hw, E1000_IMS,
34928571SChenlu.Chen@Sun.COM 		    (IMS_ENABLE_MASK | E1000_IMS_TXQE));
34938571SChenlu.Chen@Sun.COM 	}
34948571SChenlu.Chen@Sun.COM 
34958571SChenlu.Chen@Sun.COM 	/* Disable auto-mask for ICR interrupt bits */
34968571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_IAM, 0);
34978571SChenlu.Chen@Sun.COM 
34988571SChenlu.Chen@Sun.COM 	E1000_WRITE_FLUSH(hw);
34998571SChenlu.Chen@Sun.COM }
35008571SChenlu.Chen@Sun.COM 
35018571SChenlu.Chen@Sun.COM /*
35028571SChenlu.Chen@Sun.COM  * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575
35038571SChenlu.Chen@Sun.COM  */
35048571SChenlu.Chen@Sun.COM static void
35058571SChenlu.Chen@Sun.COM igb_enable_adapter_interrupts_82575(igb_t *igb)
35065779Sxy150489 {
35075779Sxy150489 	struct e1000_hw *hw = &igb->hw;
35085779Sxy150489 	uint32_t reg;
35095779Sxy150489 
35108955SChenlu.Chen@Sun.COM 	/* Clear any pending interrupts */
35118955SChenlu.Chen@Sun.COM 	(void) E1000_READ_REG(hw, E1000_ICR);
35128955SChenlu.Chen@Sun.COM 
35135779Sxy150489 	if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
35145779Sxy150489 		/* Interrupt enabling for MSI-X */
35155779Sxy150489 		E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
35165779Sxy150489 		E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
35178275SEric Cheng 		igb->ims_mask = E1000_IMS_LSC;
35185779Sxy150489 		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
35195779Sxy150489 
35205779Sxy150489 		/* Enable MSI-X PBA support */
35215779Sxy150489 		reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
35225779Sxy150489 		reg |= E1000_CTRL_EXT_PBA_CLR;
35235779Sxy150489 
35245779Sxy150489 		/* Non-selective interrupt clear-on-read */
35255779Sxy150489 		reg |= E1000_CTRL_EXT_IRCA;	/* Called NSICR in the EAS */
35265779Sxy150489 
35275779Sxy150489 		E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
35285779Sxy150489 	} else {
35295779Sxy150489 		/* Interrupt enabling for MSI and legacy */
35308275SEric Cheng 		igb->ims_mask = IMS_ENABLE_MASK;
35315779Sxy150489 		E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
35325779Sxy150489 	}
35335779Sxy150489 
35345779Sxy150489 	E1000_WRITE_FLUSH(hw);
35355779Sxy150489 }
35365779Sxy150489 
35375779Sxy150489 /*
35385779Sxy150489  * Loopback Support
35395779Sxy150489  */
35405779Sxy150489 static lb_property_t lb_normal =
35415779Sxy150489 	{ normal,	"normal",	IGB_LB_NONE		};
35425779Sxy150489 static lb_property_t lb_external =
35435779Sxy150489 	{ external,	"External",	IGB_LB_EXTERNAL		};
35445779Sxy150489 static lb_property_t lb_mac =
35455779Sxy150489 	{ internal,	"MAC",		IGB_LB_INTERNAL_MAC	};
35465779Sxy150489 static lb_property_t lb_phy =
35475779Sxy150489 	{ internal,	"PHY",		IGB_LB_INTERNAL_PHY	};
35485779Sxy150489 static lb_property_t lb_serdes =
35495779Sxy150489 	{ internal,	"SerDes",	IGB_LB_INTERNAL_SERDES	};
35505779Sxy150489 
35515779Sxy150489 enum ioc_reply
35525779Sxy150489 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp)
35535779Sxy150489 {
35545779Sxy150489 	lb_info_sz_t *lbsp;
35555779Sxy150489 	lb_property_t *lbpp;
35565779Sxy150489 	struct e1000_hw *hw;
35575779Sxy150489 	uint32_t *lbmp;
35585779Sxy150489 	uint32_t size;
35595779Sxy150489 	uint32_t value;
35605779Sxy150489 
35615779Sxy150489 	hw = &igb->hw;
35625779Sxy150489 
35635779Sxy150489 	if (mp->b_cont == NULL)
35645779Sxy150489 		return (IOC_INVAL);
35655779Sxy150489 
35665779Sxy150489 	switch (iocp->ioc_cmd) {
35675779Sxy150489 	default:
35685779Sxy150489 		return (IOC_INVAL);
35695779Sxy150489 
35705779Sxy150489 	case LB_GET_INFO_SIZE:
35715779Sxy150489 		size = sizeof (lb_info_sz_t);
35725779Sxy150489 		if (iocp->ioc_count != size)
35735779Sxy150489 			return (IOC_INVAL);
35745779Sxy150489 
35755779Sxy150489 		value = sizeof (lb_normal);
35765779Sxy150489 		value += sizeof (lb_mac);
35775779Sxy150489 		if (hw->phy.media_type == e1000_media_type_copper)
35785779Sxy150489 			value += sizeof (lb_phy);
35795779Sxy150489 		else
35805779Sxy150489 			value += sizeof (lb_serdes);
35815779Sxy150489 		value += sizeof (lb_external);
35825779Sxy150489 
35835779Sxy150489 		lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
35845779Sxy150489 		*lbsp = value;
35855779Sxy150489 		break;
35865779Sxy150489 
35875779Sxy150489 	case LB_GET_INFO:
35885779Sxy150489 		value = sizeof (lb_normal);
35895779Sxy150489 		value += sizeof (lb_mac);
35905779Sxy150489 		if (hw->phy.media_type == e1000_media_type_copper)
35915779Sxy150489 			value += sizeof (lb_phy);
35925779Sxy150489 		else
35935779Sxy150489 			value += sizeof (lb_serdes);
35945779Sxy150489 		value += sizeof (lb_external);
35955779Sxy150489 
35965779Sxy150489 		size = value;
35975779Sxy150489 		if (iocp->ioc_count != size)
35985779Sxy150489 			return (IOC_INVAL);
35995779Sxy150489 
36005779Sxy150489 		value = 0;
36015779Sxy150489 		lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
36025779Sxy150489 
36035779Sxy150489 		lbpp[value++] = lb_normal;
36045779Sxy150489 		lbpp[value++] = lb_mac;
36055779Sxy150489 		if (hw->phy.media_type == e1000_media_type_copper)
36065779Sxy150489 			lbpp[value++] = lb_phy;
36075779Sxy150489 		else
36085779Sxy150489 			lbpp[value++] = lb_serdes;
36095779Sxy150489 		lbpp[value++] = lb_external;
36105779Sxy150489 		break;
36115779Sxy150489 
36125779Sxy150489 	case LB_GET_MODE:
36135779Sxy150489 		size = sizeof (uint32_t);
36145779Sxy150489 		if (iocp->ioc_count != size)
36155779Sxy150489 			return (IOC_INVAL);
36165779Sxy150489 
36175779Sxy150489 		lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
36185779Sxy150489 		*lbmp = igb->loopback_mode;
36195779Sxy150489 		break;
36205779Sxy150489 
36215779Sxy150489 	case LB_SET_MODE:
36225779Sxy150489 		size = 0;
36235779Sxy150489 		if (iocp->ioc_count != sizeof (uint32_t))
36245779Sxy150489 			return (IOC_INVAL);
36255779Sxy150489 
36265779Sxy150489 		lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
36275779Sxy150489 		if (!igb_set_loopback_mode(igb, *lbmp))
36285779Sxy150489 			return (IOC_INVAL);
36295779Sxy150489 		break;
36305779Sxy150489 	}
36315779Sxy150489 
36325779Sxy150489 	iocp->ioc_count = size;
36335779Sxy150489 	iocp->ioc_error = 0;
36345779Sxy150489 
36356624Sgl147354 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
36366624Sgl147354 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
36376624Sgl147354 		return (IOC_INVAL);
36386624Sgl147354 	}
36396624Sgl147354 
36405779Sxy150489 	return (IOC_REPLY);
36415779Sxy150489 }
36425779Sxy150489 
36435779Sxy150489 /*
36445779Sxy150489  * igb_set_loopback_mode - Setup loopback based on the loopback mode
36455779Sxy150489  */
36465779Sxy150489 static boolean_t
36475779Sxy150489 igb_set_loopback_mode(igb_t *igb, uint32_t mode)
36485779Sxy150489 {
36495779Sxy150489 	struct e1000_hw *hw;
365011502SChenlu.Chen@Sun.COM 	int i;
36515779Sxy150489 
36525779Sxy150489 	if (mode == igb->loopback_mode)
36535779Sxy150489 		return (B_TRUE);
36545779Sxy150489 
36555779Sxy150489 	hw = &igb->hw;
36565779Sxy150489 
36575779Sxy150489 	igb->loopback_mode = mode;
36585779Sxy150489 
36595779Sxy150489 	if (mode == IGB_LB_NONE) {
36605779Sxy150489 		/* Reset the chip */
36615779Sxy150489 		hw->phy.autoneg_wait_to_complete = B_TRUE;
36625779Sxy150489 		(void) igb_reset(igb);
36635779Sxy150489 		hw->phy.autoneg_wait_to_complete = B_FALSE;
36645779Sxy150489 		return (B_TRUE);
36655779Sxy150489 	}
36665779Sxy150489 
36675779Sxy150489 	mutex_enter(&igb->gen_lock);
36685779Sxy150489 
36695779Sxy150489 	switch (mode) {
36705779Sxy150489 	default:
36715779Sxy150489 		mutex_exit(&igb->gen_lock);
36725779Sxy150489 		return (B_FALSE);
36735779Sxy150489 
36745779Sxy150489 	case IGB_LB_EXTERNAL:
36755779Sxy150489 		igb_set_external_loopback(igb);
36765779Sxy150489 		break;
36775779Sxy150489 
36785779Sxy150489 	case IGB_LB_INTERNAL_MAC:
36795779Sxy150489 		igb_set_internal_mac_loopback(igb);
36805779Sxy150489 		break;
36815779Sxy150489 
36825779Sxy150489 	case IGB_LB_INTERNAL_PHY:
36835779Sxy150489 		igb_set_internal_phy_loopback(igb);
36845779Sxy150489 		break;
36855779Sxy150489 
36865779Sxy150489 	case IGB_LB_INTERNAL_SERDES:
36875779Sxy150489 		igb_set_internal_serdes_loopback(igb);
36885779Sxy150489 		break;
36895779Sxy150489 	}
36905779Sxy150489 
36915779Sxy150489 	mutex_exit(&igb->gen_lock);
36925779Sxy150489 
369311502SChenlu.Chen@Sun.COM 	/*
369411502SChenlu.Chen@Sun.COM 	 * When external loopback is set, wait up to 1000ms to get the link up.
369511502SChenlu.Chen@Sun.COM 	 * According to test, 1000ms can work and it's an experimental value.
369611502SChenlu.Chen@Sun.COM 	 */
369711502SChenlu.Chen@Sun.COM 	if (mode == IGB_LB_EXTERNAL) {
369811502SChenlu.Chen@Sun.COM 		for (i = 0; i <= 10; i++) {
369911502SChenlu.Chen@Sun.COM 			mutex_enter(&igb->gen_lock);
370011502SChenlu.Chen@Sun.COM 			(void) igb_link_check(igb);
370111502SChenlu.Chen@Sun.COM 			mutex_exit(&igb->gen_lock);
370211502SChenlu.Chen@Sun.COM 
370311502SChenlu.Chen@Sun.COM 			if (igb->link_state == LINK_STATE_UP)
370411502SChenlu.Chen@Sun.COM 				break;
370511502SChenlu.Chen@Sun.COM 
370611502SChenlu.Chen@Sun.COM 			msec_delay(100);
370711502SChenlu.Chen@Sun.COM 		}
370811502SChenlu.Chen@Sun.COM 
370911502SChenlu.Chen@Sun.COM 		if (igb->link_state != LINK_STATE_UP) {
371011502SChenlu.Chen@Sun.COM 			/*
371111502SChenlu.Chen@Sun.COM 			 * Does not support external loopback.
371211502SChenlu.Chen@Sun.COM 			 * Reset driver to loopback none.
371311502SChenlu.Chen@Sun.COM 			 */
371411502SChenlu.Chen@Sun.COM 			igb->loopback_mode = IGB_LB_NONE;
371511502SChenlu.Chen@Sun.COM 
371611502SChenlu.Chen@Sun.COM 			/* Reset the chip */
371711502SChenlu.Chen@Sun.COM 			hw->phy.autoneg_wait_to_complete = B_TRUE;
371811502SChenlu.Chen@Sun.COM 			(void) igb_reset(igb);
371911502SChenlu.Chen@Sun.COM 			hw->phy.autoneg_wait_to_complete = B_FALSE;
372011502SChenlu.Chen@Sun.COM 
372111502SChenlu.Chen@Sun.COM 			IGB_DEBUGLOG_0(igb, "Set external loopback failed, "
372211502SChenlu.Chen@Sun.COM 			    "reset to loopback none.");
372311502SChenlu.Chen@Sun.COM 
372411502SChenlu.Chen@Sun.COM 			return (B_FALSE);
372511502SChenlu.Chen@Sun.COM 		}
372611502SChenlu.Chen@Sun.COM 	}
372711502SChenlu.Chen@Sun.COM 
37285779Sxy150489 	return (B_TRUE);
37295779Sxy150489 }
37305779Sxy150489 
37315779Sxy150489 /*
37325779Sxy150489  * igb_set_external_loopback - Set the external loopback mode
37335779Sxy150489  */
37345779Sxy150489 static void
37355779Sxy150489 igb_set_external_loopback(igb_t *igb)
37365779Sxy150489 {
37375779Sxy150489 	struct e1000_hw *hw;
37385779Sxy150489 
37395779Sxy150489 	hw = &igb->hw;
37405779Sxy150489 
37415779Sxy150489 	/* Set phy to known state */
37425779Sxy150489 	(void) e1000_phy_hw_reset(hw);
37435779Sxy150489 
37445779Sxy150489 	(void) e1000_write_phy_reg(hw, 0x0, 0x0140);
37455779Sxy150489 	(void) e1000_write_phy_reg(hw, 0x9, 0x1b00);
37465779Sxy150489 	(void) e1000_write_phy_reg(hw, 0x12, 0x1610);
37475779Sxy150489 	(void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c);
37485779Sxy150489 }
37495779Sxy150489 
37505779Sxy150489 /*
37515779Sxy150489  * igb_set_internal_mac_loopback - Set the internal MAC loopback mode
37525779Sxy150489  */
37535779Sxy150489 static void
37545779Sxy150489 igb_set_internal_mac_loopback(igb_t *igb)
37555779Sxy150489 {
37565779Sxy150489 	struct e1000_hw *hw;
37575779Sxy150489 	uint32_t ctrl;
37585779Sxy150489 	uint32_t rctl;
37598955SChenlu.Chen@Sun.COM 	uint32_t ctrl_ext;
37608955SChenlu.Chen@Sun.COM 	uint16_t phy_ctrl;
37618955SChenlu.Chen@Sun.COM 	uint16_t phy_status;
37625779Sxy150489 
37635779Sxy150489 	hw = &igb->hw;
37645779Sxy150489 
37658955SChenlu.Chen@Sun.COM 	(void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
37668955SChenlu.Chen@Sun.COM 	phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
37678955SChenlu.Chen@Sun.COM 	(void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
37688955SChenlu.Chen@Sun.COM 
37698955SChenlu.Chen@Sun.COM 	(void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
37708955SChenlu.Chen@Sun.COM 
37718955SChenlu.Chen@Sun.COM 	/* Set link mode to PHY (00b) in the Extended Control register */
37728955SChenlu.Chen@Sun.COM 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
37738955SChenlu.Chen@Sun.COM 	ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
37748955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
37758955SChenlu.Chen@Sun.COM 
37768955SChenlu.Chen@Sun.COM 	/* Set the Device Control register */
37778955SChenlu.Chen@Sun.COM 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
37788955SChenlu.Chen@Sun.COM 	if (!(phy_status & MII_SR_LINK_STATUS))
37798955SChenlu.Chen@Sun.COM 		ctrl |= E1000_CTRL_ILOS; /* Set ILOS when the link is down */
37808955SChenlu.Chen@Sun.COM 	ctrl &= ~E1000_CTRL_SPD_SEL;	/* Clear the speed sel bits */
37818955SChenlu.Chen@Sun.COM 	ctrl |= (E1000_CTRL_SLU |	/* Force link up */
37828955SChenlu.Chen@Sun.COM 	    E1000_CTRL_FRCSPD |		/* Force speed */
37838955SChenlu.Chen@Sun.COM 	    E1000_CTRL_FRCDPX |		/* Force duplex */
37848955SChenlu.Chen@Sun.COM 	    E1000_CTRL_SPD_1000 |	/* Force speed to 1000 */
37858955SChenlu.Chen@Sun.COM 	    E1000_CTRL_FD);		/* Force full duplex */
37868955SChenlu.Chen@Sun.COM 
37878955SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
37888955SChenlu.Chen@Sun.COM 
37895779Sxy150489 	/* Set the Receive Control register */
37905779Sxy150489 	rctl = E1000_READ_REG(hw, E1000_RCTL);
37915779Sxy150489 	rctl &= ~E1000_RCTL_LBM_TCVR;
37925779Sxy150489 	rctl |= E1000_RCTL_LBM_MAC;
37935779Sxy150489 	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
37945779Sxy150489 }
37955779Sxy150489 
37965779Sxy150489 /*
37975779Sxy150489  * igb_set_internal_phy_loopback - Set the internal PHY loopback mode
37985779Sxy150489  */
37995779Sxy150489 static void
38005779Sxy150489 igb_set_internal_phy_loopback(igb_t *igb)
38015779Sxy150489 {
38025779Sxy150489 	struct e1000_hw *hw;
38035779Sxy150489 	uint32_t ctrl_ext;
38045779Sxy150489 	uint16_t phy_ctrl;
38055779Sxy150489 	uint16_t phy_pconf;
38065779Sxy150489 
38075779Sxy150489 	hw = &igb->hw;
38085779Sxy150489 
38095779Sxy150489 	/* Set link mode to PHY (00b) in the Extended Control register */
38105779Sxy150489 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
38115779Sxy150489 	ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
38125779Sxy150489 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
38135779Sxy150489 
38145779Sxy150489 	/*
38155779Sxy150489 	 * Set PHY control register (0x4140):
38165779Sxy150489 	 *    Set full duplex mode
38175779Sxy150489 	 *    Set loopback bit
38185779Sxy150489 	 *    Clear auto-neg enable bit
38195779Sxy150489 	 *    Set PHY speed
38205779Sxy150489 	 */
38215779Sxy150489 	phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK;
38225779Sxy150489 	(void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
38235779Sxy150489 
38245779Sxy150489 	/* Set the link disable bit in the Port Configuration register */
38255779Sxy150489 	(void) e1000_read_phy_reg(hw, 0x10, &phy_pconf);
38265779Sxy150489 	phy_pconf |= (uint16_t)1 << 14;
38275779Sxy150489 	(void) e1000_write_phy_reg(hw, 0x10, phy_pconf);
38285779Sxy150489 }
38295779Sxy150489 
38305779Sxy150489 /*
38315779Sxy150489  * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode
38325779Sxy150489  */
38335779Sxy150489 static void
38345779Sxy150489 igb_set_internal_serdes_loopback(igb_t *igb)
38355779Sxy150489 {
38365779Sxy150489 	struct e1000_hw *hw;
38375779Sxy150489 	uint32_t ctrl_ext;
38385779Sxy150489 	uint32_t ctrl;
38395779Sxy150489 	uint32_t pcs_lctl;
38405779Sxy150489 	uint32_t connsw;
38415779Sxy150489 
38425779Sxy150489 	hw = &igb->hw;
38435779Sxy150489 
38445779Sxy150489 	/* Set link mode to SerDes (11b) in the Extended Control register */
38455779Sxy150489 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
38465779Sxy150489 	ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
38475779Sxy150489 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
38485779Sxy150489 
38495779Sxy150489 	/* Configure the SerDes to loopback */
38505779Sxy150489 	E1000_WRITE_REG(hw, E1000_SCTL, 0x410);
38515779Sxy150489 
38525779Sxy150489 	/* Set Device Control register */
38535779Sxy150489 	ctrl = E1000_READ_REG(hw, E1000_CTRL);
38545779Sxy150489 	ctrl |= (E1000_CTRL_FD |	/* Force full duplex */
38555779Sxy150489 	    E1000_CTRL_SLU);		/* Force link up */
38565779Sxy150489 	ctrl &= ~(E1000_CTRL_RFCE |	/* Disable receive flow control */
38575779Sxy150489 	    E1000_CTRL_TFCE |		/* Disable transmit flow control */
38585779Sxy150489 	    E1000_CTRL_LRST);		/* Clear link reset */
38595779Sxy150489 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
38605779Sxy150489 
38615779Sxy150489 	/* Set PCS Link Control register */
38625779Sxy150489 	pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL);
38635779Sxy150489 	pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK |
38645779Sxy150489 	    E1000_PCS_LCTL_FSD |
38655779Sxy150489 	    E1000_PCS_LCTL_FDV_FULL |
38665779Sxy150489 	    E1000_PCS_LCTL_FLV_LINK_UP);
38675779Sxy150489 	pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE;
38685779Sxy150489 	E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl);
38695779Sxy150489 
38705779Sxy150489 	/* Set the Copper/Fiber Switch Control - CONNSW register */
38715779Sxy150489 	connsw = E1000_READ_REG(hw, E1000_CONNSW);
38725779Sxy150489 	connsw &= ~E1000_CONNSW_ENRGSRC;
38735779Sxy150489 	E1000_WRITE_REG(hw, E1000_CONNSW, connsw);
38745779Sxy150489 }
38755779Sxy150489 
38765779Sxy150489 #pragma inline(igb_intr_rx_work)
38775779Sxy150489 /*
38785779Sxy150489  * igb_intr_rx_work - rx processing of ISR
38795779Sxy150489  */
38805779Sxy150489 static void
38815779Sxy150489 igb_intr_rx_work(igb_rx_ring_t *rx_ring)
38825779Sxy150489 {
38835779Sxy150489 	mblk_t *mp;
38845779Sxy150489 
38855779Sxy150489 	mutex_enter(&rx_ring->rx_lock);
38868275SEric Cheng 	mp = igb_rx(rx_ring, IGB_NO_POLL);
38875779Sxy150489 	mutex_exit(&rx_ring->rx_lock);
38885779Sxy150489 
38895779Sxy150489 	if (mp != NULL)
38908275SEric Cheng 		mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp,
38918275SEric Cheng 		    rx_ring->ring_gen_num);
38925779Sxy150489 }
38935779Sxy150489 
38945779Sxy150489 #pragma inline(igb_intr_tx_work)
38955779Sxy150489 /*
38965779Sxy150489  * igb_intr_tx_work - tx processing of ISR
38975779Sxy150489  */
38985779Sxy150489 static void
38995779Sxy150489 igb_intr_tx_work(igb_tx_ring_t *tx_ring)
39005779Sxy150489 {
390111502SChenlu.Chen@Sun.COM 	igb_t *igb = tx_ring->igb;
390211502SChenlu.Chen@Sun.COM 
39035779Sxy150489 	/* Recycle the tx descriptors */
39045779Sxy150489 	tx_ring->tx_recycle(tx_ring);
39055779Sxy150489 
39065779Sxy150489 	/* Schedule the re-transmit */
39075779Sxy150489 	if (tx_ring->reschedule &&
390811502SChenlu.Chen@Sun.COM 	    (tx_ring->tbd_free >= igb->tx_resched_thresh)) {
39095779Sxy150489 		tx_ring->reschedule = B_FALSE;
39108275SEric Cheng 		mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle);
39115779Sxy150489 		IGB_DEBUG_STAT(tx_ring->stat_reschedule);
39125779Sxy150489 	}
39135779Sxy150489 }
39145779Sxy150489 
39158275SEric Cheng #pragma inline(igb_intr_link_work)
39165779Sxy150489 /*
39178275SEric Cheng  * igb_intr_link_work - link-status-change processing of ISR
39185779Sxy150489  */
39195779Sxy150489 static void
39208275SEric Cheng igb_intr_link_work(igb_t *igb)
39215779Sxy150489 {
39225779Sxy150489 	boolean_t link_changed;
39235779Sxy150489 
39245779Sxy150489 	igb_stop_watchdog_timer(igb);
39255779Sxy150489 
39265779Sxy150489 	mutex_enter(&igb->gen_lock);
39275779Sxy150489 
39285779Sxy150489 	/*
39295779Sxy150489 	 * Because we got a link-status-change interrupt, force
39305779Sxy150489 	 * e1000_check_for_link() to look at phy
39315779Sxy150489 	 */
39325779Sxy150489 	igb->hw.mac.get_link_status = B_TRUE;
39335779Sxy150489 
39345779Sxy150489 	/* igb_link_check takes care of link status change */
39355779Sxy150489 	link_changed = igb_link_check(igb);
39365779Sxy150489 
39375779Sxy150489 	/* Get new phy state */
39385779Sxy150489 	igb_get_phy_state(igb);
39395779Sxy150489 
39405779Sxy150489 	mutex_exit(&igb->gen_lock);
39415779Sxy150489 
39425779Sxy150489 	if (link_changed)
39435779Sxy150489 		mac_link_update(igb->mac_hdl, igb->link_state);
39445779Sxy150489 
39455779Sxy150489 	igb_start_watchdog_timer(igb);
39465779Sxy150489 }
39475779Sxy150489 
39485779Sxy150489 /*
39495779Sxy150489  * igb_intr_legacy - Interrupt handler for legacy interrupts
39505779Sxy150489  */
39515779Sxy150489 static uint_t
39525779Sxy150489 igb_intr_legacy(void *arg1, void *arg2)
39535779Sxy150489 {
39545779Sxy150489 	igb_t *igb = (igb_t *)arg1;
39555779Sxy150489 	igb_tx_ring_t *tx_ring;
39565779Sxy150489 	uint32_t icr;
39575779Sxy150489 	mblk_t *mp;
39585779Sxy150489 	boolean_t tx_reschedule;
39595779Sxy150489 	boolean_t link_changed;
39605779Sxy150489 	uint_t result;
39615779Sxy150489 
39625779Sxy150489 	_NOTE(ARGUNUSED(arg2));
39635779Sxy150489 
39645779Sxy150489 	mutex_enter(&igb->gen_lock);
39655779Sxy150489 
39665779Sxy150489 	if (igb->igb_state & IGB_SUSPENDED) {
39675779Sxy150489 		mutex_exit(&igb->gen_lock);
39685779Sxy150489 		return (DDI_INTR_UNCLAIMED);
39695779Sxy150489 	}
39705779Sxy150489 
39715779Sxy150489 	mp = NULL;
39725779Sxy150489 	tx_reschedule = B_FALSE;
39735779Sxy150489 	link_changed = B_FALSE;
39745779Sxy150489 	icr = E1000_READ_REG(&igb->hw, E1000_ICR);
39755779Sxy150489 
397611367SJason.Xu@Sun.COM 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3977*11557SChenlu.Chen@Sun.COM 		mutex_exit(&igb->gen_lock);
397811367SJason.Xu@Sun.COM 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
397911367SJason.Xu@Sun.COM 		atomic_or_32(&igb->igb_state, IGB_ERROR);
398011367SJason.Xu@Sun.COM 		return (DDI_INTR_UNCLAIMED);
398111367SJason.Xu@Sun.COM 	}
398211367SJason.Xu@Sun.COM 
39835779Sxy150489 	if (icr & E1000_ICR_INT_ASSERTED) {
39845779Sxy150489 		/*
39855779Sxy150489 		 * E1000_ICR_INT_ASSERTED bit was set:
39865779Sxy150489 		 * Read(Clear) the ICR, claim this interrupt,
39875779Sxy150489 		 * look for work to do.
39885779Sxy150489 		 */
39895779Sxy150489 		ASSERT(igb->num_rx_rings == 1);
39905779Sxy150489 		ASSERT(igb->num_tx_rings == 1);
39915779Sxy150489 
39928571SChenlu.Chen@Sun.COM 		/* Make sure all interrupt causes cleared */
39938571SChenlu.Chen@Sun.COM 		(void) E1000_READ_REG(&igb->hw, E1000_EICR);
39948571SChenlu.Chen@Sun.COM 
39955779Sxy150489 		if (icr & E1000_ICR_RXT0) {
39968275SEric Cheng 			mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL);
39975779Sxy150489 		}
39985779Sxy150489 
39995779Sxy150489 		if (icr & E1000_ICR_TXDW) {
40005779Sxy150489 			tx_ring = &igb->tx_rings[0];
40015779Sxy150489 
40025779Sxy150489 			/* Recycle the tx descriptors */
40035779Sxy150489 			tx_ring->tx_recycle(tx_ring);
40045779Sxy150489 
40055779Sxy150489 			/* Schedule the re-transmit */
40065779Sxy150489 			tx_reschedule = (tx_ring->reschedule &&
400711502SChenlu.Chen@Sun.COM 			    (tx_ring->tbd_free >= igb->tx_resched_thresh));
40085779Sxy150489 		}
40095779Sxy150489 
40105779Sxy150489 		if (icr & E1000_ICR_LSC) {
40115779Sxy150489 			/*
40125779Sxy150489 			 * Because we got a link-status-change interrupt, force
40135779Sxy150489 			 * e1000_check_for_link() to look at phy
40145779Sxy150489 			 */
40155779Sxy150489 			igb->hw.mac.get_link_status = B_TRUE;
40165779Sxy150489 
40175779Sxy150489 			/* igb_link_check takes care of link status change */
40185779Sxy150489 			link_changed = igb_link_check(igb);
40195779Sxy150489 
40205779Sxy150489 			/* Get new phy state */
40215779Sxy150489 			igb_get_phy_state(igb);
40225779Sxy150489 		}
40235779Sxy150489 
402411155SJason.Xu@Sun.COM 		if (icr & E1000_ICR_DRSTA) {
402511155SJason.Xu@Sun.COM 			/* 82580 Full Device Reset needed */
402611367SJason.Xu@Sun.COM 			atomic_or_32(&igb->igb_state, IGB_STALL);
402711155SJason.Xu@Sun.COM 		}
402811155SJason.Xu@Sun.COM 
40295779Sxy150489 		result = DDI_INTR_CLAIMED;
40305779Sxy150489 	} else {
40315779Sxy150489 		/*
40325779Sxy150489 		 * E1000_ICR_INT_ASSERTED bit was not set:
40335779Sxy150489 		 * Don't claim this interrupt.
40345779Sxy150489 		 */
40355779Sxy150489 		result = DDI_INTR_UNCLAIMED;
40365779Sxy150489 	}
40375779Sxy150489 
40385779Sxy150489 	mutex_exit(&igb->gen_lock);
40395779Sxy150489 
40405779Sxy150489 	/*
40415779Sxy150489 	 * Do the following work outside of the gen_lock
40425779Sxy150489 	 */
40435779Sxy150489 	if (mp != NULL)
40445779Sxy150489 		mac_rx(igb->mac_hdl, NULL, mp);
40455779Sxy150489 
40465779Sxy150489 	if (tx_reschedule)  {
40475779Sxy150489 		tx_ring->reschedule = B_FALSE;
40488275SEric Cheng 		mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle);
40495779Sxy150489 		IGB_DEBUG_STAT(tx_ring->stat_reschedule);
40505779Sxy150489 	}
40515779Sxy150489 
40525779Sxy150489 	if (link_changed)
40535779Sxy150489 		mac_link_update(igb->mac_hdl, igb->link_state);
40545779Sxy150489 
40555779Sxy150489 	return (result);
40565779Sxy150489 }
40575779Sxy150489 
40585779Sxy150489 /*
40595779Sxy150489  * igb_intr_msi - Interrupt handler for MSI
40605779Sxy150489  */
40615779Sxy150489 static uint_t
40625779Sxy150489 igb_intr_msi(void *arg1, void *arg2)
40635779Sxy150489 {
40645779Sxy150489 	igb_t *igb = (igb_t *)arg1;
40655779Sxy150489 	uint32_t icr;
40665779Sxy150489 
40675779Sxy150489 	_NOTE(ARGUNUSED(arg2));
40685779Sxy150489 
40695779Sxy150489 	icr = E1000_READ_REG(&igb->hw, E1000_ICR);
40705779Sxy150489 
407111367SJason.Xu@Sun.COM 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
407211367SJason.Xu@Sun.COM 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
407311367SJason.Xu@Sun.COM 		atomic_or_32(&igb->igb_state, IGB_ERROR);
407411367SJason.Xu@Sun.COM 		return (DDI_INTR_CLAIMED);
407511367SJason.Xu@Sun.COM 	}
407611367SJason.Xu@Sun.COM 
40778571SChenlu.Chen@Sun.COM 	/* Make sure all interrupt causes cleared */
40788571SChenlu.Chen@Sun.COM 	(void) E1000_READ_REG(&igb->hw, E1000_EICR);
40798571SChenlu.Chen@Sun.COM 
40805779Sxy150489 	/*
40815779Sxy150489 	 * For MSI interrupt, we have only one vector,
40825779Sxy150489 	 * so we have only one rx ring and one tx ring enabled.
40835779Sxy150489 	 */
40845779Sxy150489 	ASSERT(igb->num_rx_rings == 1);
40855779Sxy150489 	ASSERT(igb->num_tx_rings == 1);
40865779Sxy150489 
40875779Sxy150489 	if (icr & E1000_ICR_RXT0) {
40885779Sxy150489 		igb_intr_rx_work(&igb->rx_rings[0]);
40895779Sxy150489 	}
40905779Sxy150489 
40915779Sxy150489 	if (icr & E1000_ICR_TXDW) {
40925779Sxy150489 		igb_intr_tx_work(&igb->tx_rings[0]);
40935779Sxy150489 	}
40945779Sxy150489 
40955779Sxy150489 	if (icr & E1000_ICR_LSC) {
40968275SEric Cheng 		igb_intr_link_work(igb);
40975779Sxy150489 	}
40985779Sxy150489 
409911155SJason.Xu@Sun.COM 	if (icr & E1000_ICR_DRSTA) {
410011155SJason.Xu@Sun.COM 		/* 82580 Full Device Reset needed */
410111367SJason.Xu@Sun.COM 		atomic_or_32(&igb->igb_state, IGB_STALL);
410211155SJason.Xu@Sun.COM 	}
410311155SJason.Xu@Sun.COM 
41045779Sxy150489 	return (DDI_INTR_CLAIMED);
41055779Sxy150489 }
41065779Sxy150489 
41075779Sxy150489 /*
41085779Sxy150489  * igb_intr_rx - Interrupt handler for rx
41095779Sxy150489  */
41105779Sxy150489 static uint_t
41115779Sxy150489 igb_intr_rx(void *arg1, void *arg2)
41125779Sxy150489 {
41135779Sxy150489 	igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1;
41145779Sxy150489 
41155779Sxy150489 	_NOTE(ARGUNUSED(arg2));
41165779Sxy150489 
41175779Sxy150489 	/*
41185779Sxy150489 	 * Only used via MSI-X vector so don't check cause bits
41195779Sxy150489 	 * and only clean the given ring.
41205779Sxy150489 	 */
41215779Sxy150489 	igb_intr_rx_work(rx_ring);
41225779Sxy150489 
41235779Sxy150489 	return (DDI_INTR_CLAIMED);
41245779Sxy150489 }
41255779Sxy150489 
41265779Sxy150489 /*
41278275SEric Cheng  * igb_intr_tx - Interrupt handler for tx
41288275SEric Cheng  */
41298275SEric Cheng static uint_t
41308275SEric Cheng igb_intr_tx(void *arg1, void *arg2)
41318275SEric Cheng {
41328275SEric Cheng 	igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1;
41338275SEric Cheng 
41348275SEric Cheng 	_NOTE(ARGUNUSED(arg2));
41358275SEric Cheng 
41368275SEric Cheng 	/*
41378275SEric Cheng 	 * Only used via MSI-X vector so don't check cause bits
41388275SEric Cheng 	 * and only clean the given ring.
41398275SEric Cheng 	 */
41408275SEric Cheng 	igb_intr_tx_work(tx_ring);
41418275SEric Cheng 
41428275SEric Cheng 	return (DDI_INTR_CLAIMED);
41438275SEric Cheng }
41448275SEric Cheng 
41458275SEric Cheng /*
41465779Sxy150489  * igb_intr_tx_other - Interrupt handler for both tx and other
41475779Sxy150489  *
41485779Sxy150489  */
41495779Sxy150489 static uint_t
41505779Sxy150489 igb_intr_tx_other(void *arg1, void *arg2)
41515779Sxy150489 {
41525779Sxy150489 	igb_t *igb = (igb_t *)arg1;
41535779Sxy150489 	uint32_t icr;
41545779Sxy150489 
41555779Sxy150489 	_NOTE(ARGUNUSED(arg2));
41565779Sxy150489 
41575779Sxy150489 	icr = E1000_READ_REG(&igb->hw, E1000_ICR);
41585779Sxy150489 
415911367SJason.Xu@Sun.COM 	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
416011367SJason.Xu@Sun.COM 		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
416111367SJason.Xu@Sun.COM 		atomic_or_32(&igb->igb_state, IGB_ERROR);
416211367SJason.Xu@Sun.COM 		return (DDI_INTR_CLAIMED);
416311367SJason.Xu@Sun.COM 	}
416411367SJason.Xu@Sun.COM 
41655779Sxy150489 	/*
41668275SEric Cheng 	 * Look for tx reclaiming work first. Remember, in the
41678275SEric Cheng 	 * case of only interrupt sharing, only one tx ring is
41688275SEric Cheng 	 * used
41695779Sxy150489 	 */
41705779Sxy150489 	igb_intr_tx_work(&igb->tx_rings[0]);
41715779Sxy150489 
41725779Sxy150489 	/*
41738955SChenlu.Chen@Sun.COM 	 * Check for "other" causes.
41745779Sxy150489 	 */
41755779Sxy150489 	if (icr & E1000_ICR_LSC) {
41768275SEric Cheng 		igb_intr_link_work(igb);
41775779Sxy150489 	}
41785779Sxy150489 
41798955SChenlu.Chen@Sun.COM 	/*
41808955SChenlu.Chen@Sun.COM 	 * The DOUTSYNC bit indicates a tx packet dropped because
41818955SChenlu.Chen@Sun.COM 	 * DMA engine gets "out of sync". There isn't a real fix
41828955SChenlu.Chen@Sun.COM 	 * for this. The Intel recommendation is to count the number
41838955SChenlu.Chen@Sun.COM 	 * of occurrences so user can detect when it is happening.
41848955SChenlu.Chen@Sun.COM 	 * The issue is non-fatal and there's no recovery action
41858955SChenlu.Chen@Sun.COM 	 * available.
41868955SChenlu.Chen@Sun.COM 	 */
41878955SChenlu.Chen@Sun.COM 	if (icr & E1000_ICR_DOUTSYNC) {
41888955SChenlu.Chen@Sun.COM 		IGB_STAT(igb->dout_sync);
41898955SChenlu.Chen@Sun.COM 	}
41908955SChenlu.Chen@Sun.COM 
419111155SJason.Xu@Sun.COM 	if (icr & E1000_ICR_DRSTA) {
419211155SJason.Xu@Sun.COM 		/* 82580 Full Device Reset needed */
419311367SJason.Xu@Sun.COM 		atomic_or_32(&igb->igb_state, IGB_STALL);
419411155SJason.Xu@Sun.COM 	}
419511155SJason.Xu@Sun.COM 
41965779Sxy150489 	return (DDI_INTR_CLAIMED);
41975779Sxy150489 }
41985779Sxy150489 
41995779Sxy150489 /*
42005779Sxy150489  * igb_alloc_intrs - Allocate interrupts for the driver
42015779Sxy150489  *
42025779Sxy150489  * Normal sequence is to try MSI-X; if not sucessful, try MSI;
42035779Sxy150489  * if not successful, try Legacy.
42045779Sxy150489  * igb->intr_force can be used to force sequence to start with
42055779Sxy150489  * any of the 3 types.
42065779Sxy150489  * If MSI-X is not used, number of tx/rx rings is forced to 1.
42075779Sxy150489  */
42085779Sxy150489 static int
42095779Sxy150489 igb_alloc_intrs(igb_t *igb)
42105779Sxy150489 {
42115779Sxy150489 	dev_info_t *devinfo;
42125779Sxy150489 	int intr_types;
42135779Sxy150489 	int rc;
42145779Sxy150489 
42155779Sxy150489 	devinfo = igb->dip;
42165779Sxy150489 
42175779Sxy150489 	/* Get supported interrupt types */
42185779Sxy150489 	rc = ddi_intr_get_supported_types(devinfo, &intr_types);
42195779Sxy150489 
42205779Sxy150489 	if (rc != DDI_SUCCESS) {
42215779Sxy150489 		igb_log(igb,
42225779Sxy150489 		    "Get supported interrupt types failed: %d", rc);
42235779Sxy150489 		return (IGB_FAILURE);
42245779Sxy150489 	}
42255779Sxy150489 	IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types);
42265779Sxy150489 
42275779Sxy150489 	igb->intr_type = 0;
42285779Sxy150489 
42295779Sxy150489 	/* Install MSI-X interrupts */
42305779Sxy150489 	if ((intr_types & DDI_INTR_TYPE_MSIX) &&
42315779Sxy150489 	    (igb->intr_force <= IGB_INTR_MSIX)) {
42327072Sxy150489 		rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX);
42335779Sxy150489 
42345779Sxy150489 		if (rc == IGB_SUCCESS)
42355779Sxy150489 			return (IGB_SUCCESS);
42365779Sxy150489 
42375779Sxy150489 		igb_log(igb,
42385779Sxy150489 		    "Allocate MSI-X failed, trying MSI interrupts...");
42395779Sxy150489 	}
42405779Sxy150489 
42415779Sxy150489 	/* MSI-X not used, force rings to 1 */
42425779Sxy150489 	igb->num_rx_rings = 1;
42435779Sxy150489 	igb->num_tx_rings = 1;
42445779Sxy150489 	igb_log(igb,
42455779Sxy150489 	    "MSI-X not used, force rx and tx queue number to 1");
42465779Sxy150489 
42475779Sxy150489 	/* Install MSI interrupts */
42485779Sxy150489 	if ((intr_types & DDI_INTR_TYPE_MSI) &&
42495779Sxy150489 	    (igb->intr_force <= IGB_INTR_MSI)) {
42507072Sxy150489 		rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI);
42515779Sxy150489 
42525779Sxy150489 		if (rc == IGB_SUCCESS)
42535779Sxy150489 			return (IGB_SUCCESS);
42545779Sxy150489 
42555779Sxy150489 		igb_log(igb,
42565779Sxy150489 		    "Allocate MSI failed, trying Legacy interrupts...");
42575779Sxy150489 	}
42585779Sxy150489 
42595779Sxy150489 	/* Install legacy interrupts */
42605779Sxy150489 	if (intr_types & DDI_INTR_TYPE_FIXED) {
42617072Sxy150489 		rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED);
42625779Sxy150489 
42635779Sxy150489 		if (rc == IGB_SUCCESS)
42645779Sxy150489 			return (IGB_SUCCESS);
42655779Sxy150489 
42665779Sxy150489 		igb_log(igb,
42675779Sxy150489 		    "Allocate Legacy interrupts failed");
42685779Sxy150489 	}
42695779Sxy150489 
42705779Sxy150489 	/* If none of the 3 types succeeded, return failure */
42715779Sxy150489 	return (IGB_FAILURE);
42725779Sxy150489 }
42735779Sxy150489 
42745779Sxy150489 /*
42757072Sxy150489  * igb_alloc_intr_handles - Allocate interrupt handles.
42765779Sxy150489  *
42777072Sxy150489  * For legacy and MSI, only 1 handle is needed.  For MSI-X,
42787072Sxy150489  * if fewer than 2 handles are available, return failure.
42795779Sxy150489  * Upon success, this sets the number of Rx rings to a number that
42807072Sxy150489  * matches the handles available for Rx interrupts.
42815779Sxy150489  */
42825779Sxy150489 static int
42837072Sxy150489 igb_alloc_intr_handles(igb_t *igb, int intr_type)
42845779Sxy150489 {
42855779Sxy150489 	dev_info_t *devinfo;
42868275SEric Cheng 	int orig, request, count, avail, actual;
42878275SEric Cheng 	int diff, minimum;
42885779Sxy150489 	int rc;
42895779Sxy150489 
42905779Sxy150489 	devinfo = igb->dip;
42915779Sxy150489 
42927072Sxy150489 	switch (intr_type) {
42937072Sxy150489 	case DDI_INTR_TYPE_FIXED:
42947072Sxy150489 		request = 1;	/* Request 1 legacy interrupt handle */
42957072Sxy150489 		minimum = 1;
42967072Sxy150489 		IGB_DEBUGLOG_0(igb, "interrupt type: legacy");
42977072Sxy150489 		break;
42987072Sxy150489 
42997072Sxy150489 	case DDI_INTR_TYPE_MSI:
43007072Sxy150489 		request = 1;	/* Request 1 MSI interrupt handle */
43017072Sxy150489 		minimum = 1;
43027072Sxy150489 		IGB_DEBUGLOG_0(igb, "interrupt type: MSI");
43037072Sxy150489 		break;
43047072Sxy150489 
43057072Sxy150489 	case DDI_INTR_TYPE_MSIX:
43067072Sxy150489 		/*
43078275SEric Cheng 		 * Number of vectors for the adapter is
43088275SEric Cheng 		 * # rx rings + # tx rings
43098275SEric Cheng 		 * One of tx vectors is for tx & other
43107072Sxy150489 		 */
43118275SEric Cheng 		request = igb->num_rx_rings + igb->num_tx_rings;
43128275SEric Cheng 		orig = request;
43137072Sxy150489 		minimum = 2;
43147072Sxy150489 		IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X");
43157072Sxy150489 		break;
43167072Sxy150489 
43177072Sxy150489 	default:
43185779Sxy150489 		igb_log(igb,
43197072Sxy150489 		    "invalid call to igb_alloc_intr_handles(): %d\n",
43207072Sxy150489 		    intr_type);
43215779Sxy150489 		return (IGB_FAILURE);
43225779Sxy150489 	}
43237072Sxy150489 	IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d  minimum: %d",
43247072Sxy150489 	    request, minimum);
43257072Sxy150489 
43267072Sxy150489 	/*
43277072Sxy150489 	 * Get number of supported interrupts
43287072Sxy150489 	 */
43297072Sxy150489 	rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
43307072Sxy150489 	if ((rc != DDI_SUCCESS) || (count < minimum)) {
43315779Sxy150489 		igb_log(igb,
43327072Sxy150489 		    "Get supported interrupt number failed. "
43337072Sxy150489 		    "Return: %d, count: %d", rc, count);
43347072Sxy150489 		return (IGB_FAILURE);
43357072Sxy150489 	}
43367072Sxy150489 	IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count);
43377072Sxy150489 
43387072Sxy150489 	/*
43397072Sxy150489 	 * Get number of available interrupts
43407072Sxy150489 	 */
43417072Sxy150489 	rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
43427072Sxy150489 	if ((rc != DDI_SUCCESS) || (avail < minimum)) {
43437072Sxy150489 		igb_log(igb,
43447072Sxy150489 		    "Get available interrupt number failed. "
43455779Sxy150489 		    "Return: %d, available: %d", rc, avail);
43465779Sxy150489 		return (IGB_FAILURE);
43475779Sxy150489 	}
43487072Sxy150489 	IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail);
43495779Sxy150489 
43505779Sxy150489 	if (avail < request) {
43517072Sxy150489 		igb_log(igb, "Request %d handles, %d available",
43525779Sxy150489 		    request, avail);
43535779Sxy150489 		request = avail;
43545779Sxy150489 	}
43555779Sxy150489 
43565779Sxy150489 	actual = 0;
43575779Sxy150489 	igb->intr_cnt = 0;
43585779Sxy150489 
43597072Sxy150489 	/*
43607072Sxy150489 	 * Allocate an array of interrupt handles
43617072Sxy150489 	 */
43625779Sxy150489 	igb->intr_size = request * sizeof (ddi_intr_handle_t);
43635779Sxy150489 	igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP);
43645779Sxy150489 
43657072Sxy150489 	rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0,
43665779Sxy150489 	    request, &actual, DDI_INTR_ALLOC_NORMAL);
43675779Sxy150489 	if (rc != DDI_SUCCESS) {
43687072Sxy150489 		igb_log(igb, "Allocate interrupts failed. "
43695779Sxy150489 		    "return: %d, request: %d, actual: %d",
43705779Sxy150489 		    rc, request, actual);
43717072Sxy150489 		goto alloc_handle_fail;
43725779Sxy150489 	}
43737072Sxy150489 	IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual);
43745779Sxy150489 
43755779Sxy150489 	igb->intr_cnt = actual;
43765779Sxy150489 
43777072Sxy150489 	if (actual < minimum) {
43787072Sxy150489 		igb_log(igb, "Insufficient interrupt handles allocated: %d",
43797072Sxy150489 		    actual);
43807072Sxy150489 		goto alloc_handle_fail;
43817072Sxy150489 	}
43827072Sxy150489 
43835779Sxy150489 	/*
43848275SEric Cheng 	 * For MSI-X, actual might force us to reduce number of tx & rx rings
43855779Sxy150489 	 */
43868275SEric Cheng 	if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) {
43878275SEric Cheng 		diff = orig - actual;
43888275SEric Cheng 		if (diff < igb->num_tx_rings) {
43898275SEric Cheng 			igb_log(igb,
43908275SEric Cheng 			    "MSI-X vectors force Tx queue number to %d",
43918275SEric Cheng 			    igb->num_tx_rings - diff);
43928275SEric Cheng 			igb->num_tx_rings -= diff;
43938275SEric Cheng 		} else {
43948275SEric Cheng 			igb_log(igb,
43958275SEric Cheng 			    "MSI-X vectors force Tx queue number to 1");
43968275SEric Cheng 			igb->num_tx_rings = 1;
43978275SEric Cheng 
43987072Sxy150489 			igb_log(igb,
43997072Sxy150489 			    "MSI-X vectors force Rx queue number to %d",
44008275SEric Cheng 			    actual - 1);
44018275SEric Cheng 			igb->num_rx_rings = actual - 1;
44027072Sxy150489 		}
44035779Sxy150489 	}
44045779Sxy150489 
44057072Sxy150489 	/*
44067072Sxy150489 	 * Get priority for first vector, assume remaining are all the same
44077072Sxy150489 	 */
44085779Sxy150489 	rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri);
44095779Sxy150489 	if (rc != DDI_SUCCESS) {
44105779Sxy150489 		igb_log(igb,
44115779Sxy150489 		    "Get interrupt priority failed: %d", rc);
44127072Sxy150489 		goto alloc_handle_fail;
44135779Sxy150489 	}
44145779Sxy150489 
44155779Sxy150489 	rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap);
44165779Sxy150489 	if (rc != DDI_SUCCESS) {
44175779Sxy150489 		igb_log(igb,
44185779Sxy150489 		    "Get interrupt cap failed: %d", rc);
44197072Sxy150489 		goto alloc_handle_fail;
44205779Sxy150489 	}
44215779Sxy150489 
44227072Sxy150489 	igb->intr_type = intr_type;
44235779Sxy150489 
44245779Sxy150489 	return (IGB_SUCCESS);
44255779Sxy150489 
44267072Sxy150489 alloc_handle_fail:
44275779Sxy150489 	igb_rem_intrs(igb);
44285779Sxy150489 
44295779Sxy150489 	return (IGB_FAILURE);
44305779Sxy150489 }
44315779Sxy150489 
44325779Sxy150489 /*
44335779Sxy150489  * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type
44345779Sxy150489  *
44355779Sxy150489  * Before adding the interrupt handlers, the interrupt vectors have
44365779Sxy150489  * been allocated, and the rx/tx rings have also been allocated.
44375779Sxy150489  */
44385779Sxy150489 static int
44395779Sxy150489 igb_add_intr_handlers(igb_t *igb)
44405779Sxy150489 {
44415779Sxy150489 	igb_rx_ring_t *rx_ring;
44428275SEric Cheng 	igb_tx_ring_t *tx_ring;
44435779Sxy150489 	int vector;
44445779Sxy150489 	int rc;
44455779Sxy150489 	int i;
44465779Sxy150489 
44475779Sxy150489 	vector = 0;
44485779Sxy150489 
44495779Sxy150489 	switch (igb->intr_type) {
44505779Sxy150489 	case DDI_INTR_TYPE_MSIX:
44515779Sxy150489 		/* Add interrupt handler for tx + other */
44528275SEric Cheng 		tx_ring = &igb->tx_rings[0];
44535779Sxy150489 		rc = ddi_intr_add_handler(igb->htable[vector],
44545779Sxy150489 		    (ddi_intr_handler_t *)igb_intr_tx_other,
44555779Sxy150489 		    (void *)igb, NULL);
44568275SEric Cheng 
44575779Sxy150489 		if (rc != DDI_SUCCESS) {
44585779Sxy150489 			igb_log(igb,
44595779Sxy150489 			    "Add tx/other interrupt handler failed: %d", rc);
44605779Sxy150489 			return (IGB_FAILURE);
44615779Sxy150489 		}
44628275SEric Cheng 		tx_ring->intr_vector = vector;
44635779Sxy150489 		vector++;
44645779Sxy150489 
44655779Sxy150489 		/* Add interrupt handler for each rx ring */
44665779Sxy150489 		for (i = 0; i < igb->num_rx_rings; i++) {
44675779Sxy150489 			rx_ring = &igb->rx_rings[i];
44685779Sxy150489 
44695779Sxy150489 			rc = ddi_intr_add_handler(igb->htable[vector],
44705779Sxy150489 			    (ddi_intr_handler_t *)igb_intr_rx,
44715779Sxy150489 			    (void *)rx_ring, NULL);
44725779Sxy150489 
44735779Sxy150489 			if (rc != DDI_SUCCESS) {
44745779Sxy150489 				igb_log(igb,
44755779Sxy150489 				    "Add rx interrupt handler failed. "
44765779Sxy150489 				    "return: %d, rx ring: %d", rc, i);
44775779Sxy150489 				for (vector--; vector >= 0; vector--) {
44785779Sxy150489 					(void) ddi_intr_remove_handler(
44795779Sxy150489 					    igb->htable[vector]);
44805779Sxy150489 				}
44815779Sxy150489 				return (IGB_FAILURE);
44825779Sxy150489 			}
44835779Sxy150489 
44845779Sxy150489 			rx_ring->intr_vector = vector;
44855779Sxy150489 
44865779Sxy150489 			vector++;
44875779Sxy150489 		}
44888275SEric Cheng 
44898275SEric Cheng 		/* Add interrupt handler for each tx ring from 2nd ring */
44908275SEric Cheng 		for (i = 1; i < igb->num_tx_rings; i++) {
44918275SEric Cheng 			tx_ring = &igb->tx_rings[i];
44928275SEric Cheng 
44938275SEric Cheng 			rc = ddi_intr_add_handler(igb->htable[vector],
44948275SEric Cheng 			    (ddi_intr_handler_t *)igb_intr_tx,
44958275SEric Cheng 			    (void *)tx_ring, NULL);
44968275SEric Cheng 
44978275SEric Cheng 			if (rc != DDI_SUCCESS) {
44988275SEric Cheng 				igb_log(igb,
44998275SEric Cheng 				    "Add tx interrupt handler failed. "
45008275SEric Cheng 				    "return: %d, tx ring: %d", rc, i);
45018275SEric Cheng 				for (vector--; vector >= 0; vector--) {
45028275SEric Cheng 					(void) ddi_intr_remove_handler(
45038275SEric Cheng 					    igb->htable[vector]);
45048275SEric Cheng 				}
45058275SEric Cheng 				return (IGB_FAILURE);
45068275SEric Cheng 			}
45078275SEric Cheng 
45088275SEric Cheng 			tx_ring->intr_vector = vector;
45098275SEric Cheng 
45108275SEric Cheng 			vector++;
45118275SEric Cheng 		}
45128275SEric Cheng 
45135779Sxy150489 		break;
45145779Sxy150489 
45155779Sxy150489 	case DDI_INTR_TYPE_MSI:
45165779Sxy150489 		/* Add interrupt handlers for the only vector */
45175779Sxy150489 		rc = ddi_intr_add_handler(igb->htable[vector],
45185779Sxy150489 		    (ddi_intr_handler_t *)igb_intr_msi,
45195779Sxy150489 		    (void *)igb, NULL);
45205779Sxy150489 
45215779Sxy150489 		if (rc != DDI_SUCCESS) {
45225779Sxy150489 			igb_log(igb,
45235779Sxy150489 			    "Add MSI interrupt handler failed: %d", rc);
45245779Sxy150489 			return (IGB_FAILURE);
45255779Sxy150489 		}
45265779Sxy150489 
45275779Sxy150489 		rx_ring = &igb->rx_rings[0];
45285779Sxy150489 		rx_ring->intr_vector = vector;
45295779Sxy150489 
45305779Sxy150489 		vector++;
45315779Sxy150489 		break;
45325779Sxy150489 
45335779Sxy150489 	case DDI_INTR_TYPE_FIXED:
45345779Sxy150489 		/* Add interrupt handlers for the only vector */
45355779Sxy150489 		rc = ddi_intr_add_handler(igb->htable[vector],
45365779Sxy150489 		    (ddi_intr_handler_t *)igb_intr_legacy,
45375779Sxy150489 		    (void *)igb, NULL);
45385779Sxy150489 
45395779Sxy150489 		if (rc != DDI_SUCCESS) {
45405779Sxy150489 			igb_log(igb,
45415779Sxy150489 			    "Add legacy interrupt handler failed: %d", rc);
45425779Sxy150489 			return (IGB_FAILURE);
45435779Sxy150489 		}
45445779Sxy150489 
45455779Sxy150489 		rx_ring = &igb->rx_rings[0];
45465779Sxy150489 		rx_ring->intr_vector = vector;
45475779Sxy150489 
45485779Sxy150489 		vector++;
45495779Sxy150489 		break;
45505779Sxy150489 
45515779Sxy150489 	default:
45525779Sxy150489 		return (IGB_FAILURE);
45535779Sxy150489 	}
45545779Sxy150489 
45555779Sxy150489 	ASSERT(vector == igb->intr_cnt);
45565779Sxy150489 
45575779Sxy150489 	return (IGB_SUCCESS);
45585779Sxy150489 }
45595779Sxy150489 
45605779Sxy150489 /*
45618571SChenlu.Chen@Sun.COM  * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts
45625779Sxy150489  *
45635779Sxy150489  * For each vector enabled on the adapter, Set the MSIXBM register accordingly
45645779Sxy150489  */
45655779Sxy150489 static void
45668571SChenlu.Chen@Sun.COM igb_setup_msix_82575(igb_t *igb)
45675779Sxy150489 {
45685779Sxy150489 	uint32_t eims = 0;
45695779Sxy150489 	int i, vector;
45705779Sxy150489 	struct e1000_hw *hw = &igb->hw;
45715779Sxy150489 
45725779Sxy150489 	/*
45738571SChenlu.Chen@Sun.COM 	 * Set vector for tx ring 0 and other causes.
45748571SChenlu.Chen@Sun.COM 	 * NOTE assumption that it is vector 0.
45755779Sxy150489 	 */
45765779Sxy150489 	vector = 0;
45778275SEric Cheng 
45785779Sxy150489 	igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER;
45795779Sxy150489 	E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask);
45805779Sxy150489 	vector++;
45818275SEric Cheng 
45825779Sxy150489 	for (i = 0; i < igb->num_rx_rings; i++) {
45835779Sxy150489 		/*
45845779Sxy150489 		 * Set vector for each rx ring
45855779Sxy150489 		 */
45865779Sxy150489 		eims = (E1000_EICR_RX_QUEUE0 << i);
45875779Sxy150489 		E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
45885779Sxy150489 
45895779Sxy150489 		/*
45908571SChenlu.Chen@Sun.COM 		 * Accumulate bits to enable in
45918571SChenlu.Chen@Sun.COM 		 * igb_enable_adapter_interrupts_82575()
45925779Sxy150489 		 */
45935779Sxy150489 		igb->eims_mask |= eims;
45945779Sxy150489 
45955779Sxy150489 		vector++;
45965779Sxy150489 	}
45975779Sxy150489 
45988275SEric Cheng 	for (i = 1; i < igb->num_tx_rings; i++) {
45998275SEric Cheng 		/*
46008275SEric Cheng 		 * Set vector for each tx ring from 2nd tx ring
46018275SEric Cheng 		 */
46028275SEric Cheng 		eims = (E1000_EICR_TX_QUEUE0 << i);
46038275SEric Cheng 		E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
46048275SEric Cheng 
46058275SEric Cheng 		/*
46068571SChenlu.Chen@Sun.COM 		 * Accumulate bits to enable in
46078571SChenlu.Chen@Sun.COM 		 * igb_enable_adapter_interrupts_82575()
46088275SEric Cheng 		 */
46098275SEric Cheng 		igb->eims_mask |= eims;
46108275SEric Cheng 
46118275SEric Cheng 		vector++;
46128275SEric Cheng 	}
46138275SEric Cheng 
46145779Sxy150489 	ASSERT(vector == igb->intr_cnt);
46155779Sxy150489 
46165779Sxy150489 	/*
46175779Sxy150489 	 * Disable IAM for ICR interrupt bits
46185779Sxy150489 	 */
46195779Sxy150489 	E1000_WRITE_REG(hw, E1000_IAM, 0);
46205779Sxy150489 	E1000_WRITE_FLUSH(hw);
46215779Sxy150489 }
46225779Sxy150489 
46235779Sxy150489 /*
46248571SChenlu.Chen@Sun.COM  * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts
46258571SChenlu.Chen@Sun.COM  *
46268571SChenlu.Chen@Sun.COM  * 82576 uses a table based method for assigning vectors.  Each queue has a
46278571SChenlu.Chen@Sun.COM  * single entry in the table to which we write a vector number along with a
46288571SChenlu.Chen@Sun.COM  * "valid" bit.  The entry is a single byte in a 4-byte register.  Vectors
46298571SChenlu.Chen@Sun.COM  * take a different position in the 4-byte register depending on whether
46308571SChenlu.Chen@Sun.COM  * they are numbered above or below 8.
46318571SChenlu.Chen@Sun.COM  */
46328571SChenlu.Chen@Sun.COM static void
46338571SChenlu.Chen@Sun.COM igb_setup_msix_82576(igb_t *igb)
46348571SChenlu.Chen@Sun.COM {
46358571SChenlu.Chen@Sun.COM 	struct e1000_hw *hw = &igb->hw;
46368571SChenlu.Chen@Sun.COM 	uint32_t ivar, index, vector;
46378571SChenlu.Chen@Sun.COM 	int i;
46388571SChenlu.Chen@Sun.COM 
46398571SChenlu.Chen@Sun.COM 	/* must enable msi-x capability before IVAR settings */
46408571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_GPIE,
46418571SChenlu.Chen@Sun.COM 	    (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR));
46428571SChenlu.Chen@Sun.COM 
46438571SChenlu.Chen@Sun.COM 	/*
46448571SChenlu.Chen@Sun.COM 	 * Set vector for tx ring 0 and other causes.
46458571SChenlu.Chen@Sun.COM 	 * NOTE assumption that it is vector 0.
46468571SChenlu.Chen@Sun.COM 	 * This is also interdependent with installation of interrupt service
46478571SChenlu.Chen@Sun.COM 	 * routines in igb_add_intr_handlers().
46488571SChenlu.Chen@Sun.COM 	 */
46498571SChenlu.Chen@Sun.COM 
46508571SChenlu.Chen@Sun.COM 	/* assign "other" causes to vector 0 */
46518571SChenlu.Chen@Sun.COM 	vector = 0;
46528571SChenlu.Chen@Sun.COM 	ivar = ((vector | E1000_IVAR_VALID) << 8);
46538571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
46548571SChenlu.Chen@Sun.COM 
46558571SChenlu.Chen@Sun.COM 	/* assign tx ring 0 to vector 0 */
46568571SChenlu.Chen@Sun.COM 	ivar = ((vector | E1000_IVAR_VALID) << 8);
46578571SChenlu.Chen@Sun.COM 	E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
46588571SChenlu.Chen@Sun.COM 
46598571SChenlu.Chen@Sun.COM 	/* prepare to enable tx & other interrupt causes */
46608571SChenlu.Chen@Sun.COM 	igb->eims_mask = (1 << vector);
46618571SChenlu.Chen@Sun.COM 
46628571SChenlu.Chen@Sun.COM 	vector ++;
46638571SChenlu.Chen@Sun.COM 	for (i = 0; i < igb->num_rx_rings; i++) {
46648571SChenlu.Chen@Sun.COM 		/*
46658571SChenlu.Chen@Sun.COM 		 * Set vector for each rx ring
46668571SChenlu.Chen@Sun.COM 		 */
46678571SChenlu.Chen@Sun.COM 		index = (i & 0x7);
46688571SChenlu.Chen@Sun.COM 		ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
46698571SChenlu.Chen@Sun.COM 
46708571SChenlu.Chen@Sun.COM 		if (i < 8) {
46718571SChenlu.Chen@Sun.COM 			/* vector goes into low byte of register */
46728571SChenlu.Chen@Sun.COM 			ivar = ivar & 0xFFFFFF00;
46738571SChenlu.Chen@Sun.COM 			ivar |= (vector | E1000_IVAR_VALID);
46748571SChenlu.Chen@Sun.COM 		} else {
46758571SChenlu.Chen@Sun.COM 			/* vector goes into third byte of register */
46768571SChenlu.Chen@Sun.COM 			ivar = ivar & 0xFF00FFFF;
46778571SChenlu.Chen@Sun.COM 			ivar |= ((vector | E1000_IVAR_VALID) << 16);
46788571SChenlu.Chen@Sun.COM 		}
46798571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
46808571SChenlu.Chen@Sun.COM 
46818571SChenlu.Chen@Sun.COM 		/* Accumulate interrupt-cause bits to enable */
46828571SChenlu.Chen@Sun.COM 		igb->eims_mask |= (1 << vector);
46838571SChenlu.Chen@Sun.COM 
46848571SChenlu.Chen@Sun.COM 		vector ++;
46858571SChenlu.Chen@Sun.COM 	}
46868571SChenlu.Chen@Sun.COM 
46878571SChenlu.Chen@Sun.COM 	for (i = 1; i < igb->num_tx_rings; i++) {
46888571SChenlu.Chen@Sun.COM 		/*
46898571SChenlu.Chen@Sun.COM 		 * Set vector for each tx ring from 2nd tx ring.
46908571SChenlu.Chen@Sun.COM 		 * Note assumption that tx vectors numericall follow rx vectors.
46918571SChenlu.Chen@Sun.COM 		 */
46928571SChenlu.Chen@Sun.COM 		index = (i & 0x7);
46938571SChenlu.Chen@Sun.COM 		ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
46948571SChenlu.Chen@Sun.COM 
46958571SChenlu.Chen@Sun.COM 		if (i < 8) {
46968571SChenlu.Chen@Sun.COM 			/* vector goes into second byte of register */
46978571SChenlu.Chen@Sun.COM 			ivar = ivar & 0xFFFF00FF;
46988571SChenlu.Chen@Sun.COM 			ivar |= ((vector | E1000_IVAR_VALID) << 8);
46998571SChenlu.Chen@Sun.COM 		} else {
47008571SChenlu.Chen@Sun.COM 			/* vector goes into fourth byte of register */
47018571SChenlu.Chen@Sun.COM 			ivar = ivar & 0x00FFFFFF;
47028571SChenlu.Chen@Sun.COM 			ivar |= (vector | E1000_IVAR_VALID) << 24;
47038571SChenlu.Chen@Sun.COM 		}
47048571SChenlu.Chen@Sun.COM 		E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
47058571SChenlu.Chen@Sun.COM 
47068571SChenlu.Chen@Sun.COM 		/* Accumulate interrupt-cause bits to enable */
47078571SChenlu.Chen@Sun.COM 		igb->eims_mask |= (1 << vector);
47088571SChenlu.Chen@Sun.COM 
47098571SChenlu.Chen@Sun.COM 		vector ++;
47108571SChenlu.Chen@Sun.COM 	}
47118571SChenlu.Chen@Sun.COM 
47128571SChenlu.Chen@Sun.COM 	ASSERT(vector == igb->intr_cnt);
47138571SChenlu.Chen@Sun.COM }
47148571SChenlu.Chen@Sun.COM 
47158571SChenlu.Chen@Sun.COM /*
471611155SJason.Xu@Sun.COM  * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts
471711155SJason.Xu@Sun.COM  *
471811155SJason.Xu@Sun.COM  * 82580 uses same table approach at 82576 but has fewer entries.  Each
471911155SJason.Xu@Sun.COM  * queue has a single entry in the table to which we write a vector number
472011155SJason.Xu@Sun.COM  * along with a "valid" bit.  Vectors take a different position in the
472111155SJason.Xu@Sun.COM  * register depending on * whether * they are numbered above or below 4.
472211155SJason.Xu@Sun.COM  */
472311155SJason.Xu@Sun.COM static void
472411155SJason.Xu@Sun.COM igb_setup_msix_82580(igb_t *igb)
472511155SJason.Xu@Sun.COM {
472611155SJason.Xu@Sun.COM 	struct e1000_hw *hw = &igb->hw;
472711155SJason.Xu@Sun.COM 	uint32_t ivar, index, vector;
472811155SJason.Xu@Sun.COM 	int i;
472911155SJason.Xu@Sun.COM 
473011155SJason.Xu@Sun.COM 	/* must enable msi-x capability before IVAR settings */
473111155SJason.Xu@Sun.COM 	E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE |
473211155SJason.Xu@Sun.COM 	    E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME));
473311155SJason.Xu@Sun.COM 	/*
473411155SJason.Xu@Sun.COM 	 * Set vector for tx ring 0 and other causes.
473511155SJason.Xu@Sun.COM 	 * NOTE assumption that it is vector 0.
473611155SJason.Xu@Sun.COM 	 * This is also interdependent with installation of interrupt service
473711155SJason.Xu@Sun.COM 	 * routines in igb_add_intr_handlers().
473811155SJason.Xu@Sun.COM 	 */
473911155SJason.Xu@Sun.COM 
474011155SJason.Xu@Sun.COM 	/* assign "other" causes to vector 0 */
474111155SJason.Xu@Sun.COM 	vector = 0;
474211155SJason.Xu@Sun.COM 	ivar = ((vector | E1000_IVAR_VALID) << 8);
474311155SJason.Xu@Sun.COM 	E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
474411155SJason.Xu@Sun.COM 
474511155SJason.Xu@Sun.COM 	/* assign tx ring 0 to vector 0 */
474611155SJason.Xu@Sun.COM 	ivar = ((vector | E1000_IVAR_VALID) << 8);
474711155SJason.Xu@Sun.COM 	E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
474811155SJason.Xu@Sun.COM 
474911155SJason.Xu@Sun.COM 	/* prepare to enable tx & other interrupt causes */
475011155SJason.Xu@Sun.COM 	igb->eims_mask = (1 << vector);
475111155SJason.Xu@Sun.COM 
475211155SJason.Xu@Sun.COM 	vector ++;
475311155SJason.Xu@Sun.COM 
475411155SJason.Xu@Sun.COM 	for (i = 0; i < igb->num_rx_rings; i++) {
475511155SJason.Xu@Sun.COM 		/*
475611155SJason.Xu@Sun.COM 		 * Set vector for each rx ring
475711155SJason.Xu@Sun.COM 		 */
475811155SJason.Xu@Sun.COM 		index = (i >> 1);
475911155SJason.Xu@Sun.COM 		ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
476011155SJason.Xu@Sun.COM 
476111155SJason.Xu@Sun.COM 		if (i & 1) {
476211155SJason.Xu@Sun.COM 			/* vector goes into third byte of register */
476311155SJason.Xu@Sun.COM 			ivar = ivar & 0xFF00FFFF;
476411155SJason.Xu@Sun.COM 			ivar |= ((vector | E1000_IVAR_VALID) << 16);
476511155SJason.Xu@Sun.COM 		} else {
476611155SJason.Xu@Sun.COM 			/* vector goes into low byte of register */
476711155SJason.Xu@Sun.COM 			ivar = ivar & 0xFFFFFF00;
476811155SJason.Xu@Sun.COM 			ivar |= (vector | E1000_IVAR_VALID);
476911155SJason.Xu@Sun.COM 		}
477011155SJason.Xu@Sun.COM 		E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
477111155SJason.Xu@Sun.COM 
477211155SJason.Xu@Sun.COM 		/* Accumulate interrupt-cause bits to enable */
477311155SJason.Xu@Sun.COM 		igb->eims_mask |= (1 << vector);
477411155SJason.Xu@Sun.COM 
477511155SJason.Xu@Sun.COM 		vector ++;
477611155SJason.Xu@Sun.COM 	}
477711155SJason.Xu@Sun.COM 
477811155SJason.Xu@Sun.COM 	for (i = 1; i < igb->num_tx_rings; i++) {
477911155SJason.Xu@Sun.COM 		/*
478011155SJason.Xu@Sun.COM 		 * Set vector for each tx ring from 2nd tx ring.
478111155SJason.Xu@Sun.COM 		 * Note assumption that tx vectors numericall follow rx vectors.
478211155SJason.Xu@Sun.COM 		 */
478311155SJason.Xu@Sun.COM 		index = (i >> 1);
478411155SJason.Xu@Sun.COM 		ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
478511155SJason.Xu@Sun.COM 
478611155SJason.Xu@Sun.COM 		if (i & 1) {
478711155SJason.Xu@Sun.COM 			/* vector goes into high byte of register */
478811155SJason.Xu@Sun.COM 			ivar = ivar & 0x00FFFFFF;
478911155SJason.Xu@Sun.COM 			ivar |= ((vector | E1000_IVAR_VALID) << 24);
479011155SJason.Xu@Sun.COM 		} else {
479111155SJason.Xu@Sun.COM 			/* vector goes into second byte of register */
479211155SJason.Xu@Sun.COM 			ivar = ivar & 0xFFFF00FF;
479311155SJason.Xu@Sun.COM 			ivar |= (vector | E1000_IVAR_VALID) << 8;
479411155SJason.Xu@Sun.COM 		}
479511155SJason.Xu@Sun.COM 		E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
479611155SJason.Xu@Sun.COM 
479711155SJason.Xu@Sun.COM 		/* Accumulate interrupt-cause bits to enable */
479811155SJason.Xu@Sun.COM 		igb->eims_mask |= (1 << vector);
479911155SJason.Xu@Sun.COM 
480011155SJason.Xu@Sun.COM 		vector ++;
480111155SJason.Xu@Sun.COM 	}
480211155SJason.Xu@Sun.COM 	ASSERT(vector == igb->intr_cnt);
480311155SJason.Xu@Sun.COM }
480411155SJason.Xu@Sun.COM 
480511155SJason.Xu@Sun.COM /*
48065779Sxy150489  * igb_rem_intr_handlers - remove the interrupt handlers
48075779Sxy150489  */
48085779Sxy150489 static void
48095779Sxy150489 igb_rem_intr_handlers(igb_t *igb)
48105779Sxy150489 {
48115779Sxy150489 	int i;
48125779Sxy150489 	int rc;
48135779Sxy150489 
48145779Sxy150489 	for (i = 0; i < igb->intr_cnt; i++) {
48155779Sxy150489 		rc = ddi_intr_remove_handler(igb->htable[i]);
48165779Sxy150489 		if (rc != DDI_SUCCESS) {
48175779Sxy150489 			IGB_DEBUGLOG_1(igb,
48185779Sxy150489 			    "Remove intr handler failed: %d", rc);
48195779Sxy150489 		}
48205779Sxy150489 	}
48215779Sxy150489 }
48225779Sxy150489 
48235779Sxy150489 /*
48245779Sxy150489  * igb_rem_intrs - remove the allocated interrupts
48255779Sxy150489  */
48265779Sxy150489 static void
48275779Sxy150489 igb_rem_intrs(igb_t *igb)
48285779Sxy150489 {
48295779Sxy150489 	int i;
48305779Sxy150489 	int rc;
48315779Sxy150489 
48325779Sxy150489 	for (i = 0; i < igb->intr_cnt; i++) {
48335779Sxy150489 		rc = ddi_intr_free(igb->htable[i]);
48345779Sxy150489 		if (rc != DDI_SUCCESS) {
48355779Sxy150489 			IGB_DEBUGLOG_1(igb,
48365779Sxy150489 			    "Free intr failed: %d", rc);
48375779Sxy150489 		}
48385779Sxy150489 	}
48395779Sxy150489 
48405779Sxy150489 	kmem_free(igb->htable, igb->intr_size);
48415779Sxy150489 	igb->htable = NULL;
48425779Sxy150489 }
48435779Sxy150489 
48445779Sxy150489 /*
48455779Sxy150489  * igb_enable_intrs - enable all the ddi interrupts
48465779Sxy150489  */
48475779Sxy150489 static int
48485779Sxy150489 igb_enable_intrs(igb_t *igb)
48495779Sxy150489 {
48505779Sxy150489 	int i;
48515779Sxy150489 	int rc;
48525779Sxy150489 
48535779Sxy150489 	/* Enable interrupts */
48545779Sxy150489 	if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
48555779Sxy150489 		/* Call ddi_intr_block_enable() for MSI */
48565779Sxy150489 		rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt);
48575779Sxy150489 		if (rc != DDI_SUCCESS) {
48585779Sxy150489 			igb_log(igb,
48595779Sxy150489 			    "Enable block intr failed: %d", rc);
48605779Sxy150489 			return (IGB_FAILURE);
48615779Sxy150489 		}
48625779Sxy150489 	} else {
48635779Sxy150489 		/* Call ddi_intr_enable() for Legacy/MSI non block enable */
48645779Sxy150489 		for (i = 0; i < igb->intr_cnt; i++) {
48655779Sxy150489 			rc = ddi_intr_enable(igb->htable[i]);
48665779Sxy150489 			if (rc != DDI_SUCCESS) {
48675779Sxy150489 				igb_log(igb,
48685779Sxy150489 				    "Enable intr failed: %d", rc);
48695779Sxy150489 				return (IGB_FAILURE);
48705779Sxy150489 			}
48715779Sxy150489 		}
48725779Sxy150489 	}
48735779Sxy150489 
48745779Sxy150489 	return (IGB_SUCCESS);
48755779Sxy150489 }
48765779Sxy150489 
48775779Sxy150489 /*
48785779Sxy150489  * igb_disable_intrs - disable all the ddi interrupts
48795779Sxy150489  */
48805779Sxy150489 static int
48815779Sxy150489 igb_disable_intrs(igb_t *igb)
48825779Sxy150489 {
48835779Sxy150489 	int i;
48845779Sxy150489 	int rc;
48855779Sxy150489 
48865779Sxy150489 	/* Disable all interrupts */
48875779Sxy150489 	if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
48885779Sxy150489 		rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt);
48895779Sxy150489 		if (rc != DDI_SUCCESS) {
48905779Sxy150489 			igb_log(igb,
48915779Sxy150489 			    "Disable block intr failed: %d", rc);
48925779Sxy150489 			return (IGB_FAILURE);
48935779Sxy150489 		}
48945779Sxy150489 	} else {
48955779Sxy150489 		for (i = 0; i < igb->intr_cnt; i++) {
48965779Sxy150489 			rc = ddi_intr_disable(igb->htable[i]);
48975779Sxy150489 			if (rc != DDI_SUCCESS) {
48985779Sxy150489 				igb_log(igb,
48995779Sxy150489 				    "Disable intr failed: %d", rc);
49005779Sxy150489 				return (IGB_FAILURE);
49015779Sxy150489 			}
49025779Sxy150489 		}
49035779Sxy150489 	}
49045779Sxy150489 
49055779Sxy150489 	return (IGB_SUCCESS);
49065779Sxy150489 }
49075779Sxy150489 
49085779Sxy150489 /*
49095779Sxy150489  * igb_get_phy_state - Get and save the parameters read from PHY registers
49105779Sxy150489  */
49115779Sxy150489 static void
49125779Sxy150489 igb_get_phy_state(igb_t *igb)
49135779Sxy150489 {
49145779Sxy150489 	struct e1000_hw *hw = &igb->hw;
49155779Sxy150489 	uint16_t phy_ctrl;
49165779Sxy150489 	uint16_t phy_status;
49175779Sxy150489 	uint16_t phy_an_adv;
49185779Sxy150489 	uint16_t phy_an_exp;
49195779Sxy150489 	uint16_t phy_ext_status;
49205779Sxy150489 	uint16_t phy_1000t_ctrl;
49215779Sxy150489 	uint16_t phy_1000t_status;
49225779Sxy150489 	uint16_t phy_lp_able;
49235779Sxy150489 
49245779Sxy150489 	ASSERT(mutex_owned(&igb->gen_lock));
49255779Sxy150489 
492611502SChenlu.Chen@Sun.COM 	if (hw->phy.media_type == e1000_media_type_copper) {
492711502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
492811502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
492911502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv);
493011502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp);
493111502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status);
493211502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl);
493311502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw,
493411502SChenlu.Chen@Sun.COM 		    PHY_1000T_STATUS, &phy_1000t_status);
493511502SChenlu.Chen@Sun.COM 		(void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able);
493611502SChenlu.Chen@Sun.COM 
493711502SChenlu.Chen@Sun.COM 		igb->param_autoneg_cap =
493811502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
493911502SChenlu.Chen@Sun.COM 		igb->param_pause_cap =
494011502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
494111502SChenlu.Chen@Sun.COM 		igb->param_asym_pause_cap =
494211502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
494311502SChenlu.Chen@Sun.COM 		igb->param_1000fdx_cap =
494411502SChenlu.Chen@Sun.COM 		    ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
494511502SChenlu.Chen@Sun.COM 		    (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
494611502SChenlu.Chen@Sun.COM 		igb->param_1000hdx_cap =
494711502SChenlu.Chen@Sun.COM 		    ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
494811502SChenlu.Chen@Sun.COM 		    (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
494911502SChenlu.Chen@Sun.COM 		igb->param_100t4_cap =
495011502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
495111502SChenlu.Chen@Sun.COM 		igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) ||
495211502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
495311502SChenlu.Chen@Sun.COM 		igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) ||
495411502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
495511502SChenlu.Chen@Sun.COM 		igb->param_10fdx_cap =
495611502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
495711502SChenlu.Chen@Sun.COM 		igb->param_10hdx_cap =
495811502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
495911502SChenlu.Chen@Sun.COM 		igb->param_rem_fault =
496011502SChenlu.Chen@Sun.COM 		    (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0;
496111502SChenlu.Chen@Sun.COM 
496211502SChenlu.Chen@Sun.COM 		igb->param_adv_autoneg_cap = hw->mac.autoneg;
496311502SChenlu.Chen@Sun.COM 		igb->param_adv_pause_cap =
496411502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
496511502SChenlu.Chen@Sun.COM 		igb->param_adv_asym_pause_cap =
496611502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
496711502SChenlu.Chen@Sun.COM 		igb->param_adv_1000hdx_cap =
496811502SChenlu.Chen@Sun.COM 		    (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
496911502SChenlu.Chen@Sun.COM 		igb->param_adv_100t4_cap =
497011502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
497111502SChenlu.Chen@Sun.COM 		igb->param_adv_rem_fault =
497211502SChenlu.Chen@Sun.COM 		    (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0;
497311502SChenlu.Chen@Sun.COM 		if (igb->param_adv_autoneg_cap == 1) {
497411502SChenlu.Chen@Sun.COM 			igb->param_adv_1000fdx_cap =
497511502SChenlu.Chen@Sun.COM 			    (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
497611502SChenlu.Chen@Sun.COM 			igb->param_adv_100fdx_cap =
497711502SChenlu.Chen@Sun.COM 			    (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
497811502SChenlu.Chen@Sun.COM 			igb->param_adv_100hdx_cap =
497911502SChenlu.Chen@Sun.COM 			    (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
498011502SChenlu.Chen@Sun.COM 			igb->param_adv_10fdx_cap =
498111502SChenlu.Chen@Sun.COM 			    (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
498211502SChenlu.Chen@Sun.COM 			igb->param_adv_10hdx_cap =
498311502SChenlu.Chen@Sun.COM 			    (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
498411502SChenlu.Chen@Sun.COM 		}
498511502SChenlu.Chen@Sun.COM 
498611502SChenlu.Chen@Sun.COM 		igb->param_lp_autoneg_cap =
498711502SChenlu.Chen@Sun.COM 		    (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
498811502SChenlu.Chen@Sun.COM 		igb->param_lp_pause_cap =
498911502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
499011502SChenlu.Chen@Sun.COM 		igb->param_lp_asym_pause_cap =
499111502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
499211502SChenlu.Chen@Sun.COM 		igb->param_lp_1000fdx_cap =
499311502SChenlu.Chen@Sun.COM 		    (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
499411502SChenlu.Chen@Sun.COM 		igb->param_lp_1000hdx_cap =
499511502SChenlu.Chen@Sun.COM 		    (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
499611502SChenlu.Chen@Sun.COM 		igb->param_lp_100t4_cap =
499711502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
499811502SChenlu.Chen@Sun.COM 		igb->param_lp_100fdx_cap =
499911502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
500011502SChenlu.Chen@Sun.COM 		igb->param_lp_100hdx_cap =
500111502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
500211502SChenlu.Chen@Sun.COM 		igb->param_lp_10fdx_cap =
500311502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
500411502SChenlu.Chen@Sun.COM 		igb->param_lp_10hdx_cap =
500511502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
500611502SChenlu.Chen@Sun.COM 		igb->param_lp_rem_fault =
500711502SChenlu.Chen@Sun.COM 		    (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0;
500811502SChenlu.Chen@Sun.COM 	} else {
500911502SChenlu.Chen@Sun.COM 		/*
501011502SChenlu.Chen@Sun.COM 		 * 1Gig Fiber adapter only offers 1Gig Full Duplex.
501111502SChenlu.Chen@Sun.COM 		 */
501211502SChenlu.Chen@Sun.COM 		igb->param_autoneg_cap = 0;
501311502SChenlu.Chen@Sun.COM 		igb->param_pause_cap = 1;
501411502SChenlu.Chen@Sun.COM 		igb->param_asym_pause_cap = 1;
501511502SChenlu.Chen@Sun.COM 		igb->param_1000fdx_cap = 1;
501611502SChenlu.Chen@Sun.COM 		igb->param_1000hdx_cap = 0;
501711502SChenlu.Chen@Sun.COM 		igb->param_100t4_cap = 0;
501811502SChenlu.Chen@Sun.COM 		igb->param_100fdx_cap = 0;
501911502SChenlu.Chen@Sun.COM 		igb->param_100hdx_cap = 0;
502011502SChenlu.Chen@Sun.COM 		igb->param_10fdx_cap = 0;
502111502SChenlu.Chen@Sun.COM 		igb->param_10hdx_cap = 0;
502211502SChenlu.Chen@Sun.COM 
502311502SChenlu.Chen@Sun.COM 		igb->param_adv_autoneg_cap = 0;
502411502SChenlu.Chen@Sun.COM 		igb->param_adv_pause_cap = 1;
502511502SChenlu.Chen@Sun.COM 		igb->param_adv_asym_pause_cap = 1;
502611502SChenlu.Chen@Sun.COM 		igb->param_adv_1000fdx_cap = 1;
502711502SChenlu.Chen@Sun.COM 		igb->param_adv_1000hdx_cap = 0;
502811502SChenlu.Chen@Sun.COM 		igb->param_adv_100t4_cap = 0;
502911502SChenlu.Chen@Sun.COM 		igb->param_adv_100fdx_cap = 0;
503011502SChenlu.Chen@Sun.COM 		igb->param_adv_100hdx_cap = 0;
503111502SChenlu.Chen@Sun.COM 		igb->param_adv_10fdx_cap = 0;
503211502SChenlu.Chen@Sun.COM 		igb->param_adv_10hdx_cap = 0;
503311502SChenlu.Chen@Sun.COM 
503411502SChenlu.Chen@Sun.COM 		igb->param_lp_autoneg_cap = 0;
503511502SChenlu.Chen@Sun.COM 		igb->param_lp_pause_cap = 0;
503611502SChenlu.Chen@Sun.COM 		igb->param_lp_asym_pause_cap = 0;
503711502SChenlu.Chen@Sun.COM 		igb->param_lp_1000fdx_cap = 0;
503811502SChenlu.Chen@Sun.COM 		igb->param_lp_1000hdx_cap = 0;
503911502SChenlu.Chen@Sun.COM 		igb->param_lp_100t4_cap = 0;
504011502SChenlu.Chen@Sun.COM 		igb->param_lp_100fdx_cap = 0;
504111502SChenlu.Chen@Sun.COM 		igb->param_lp_100hdx_cap = 0;
504211502SChenlu.Chen@Sun.COM 		igb->param_lp_10fdx_cap = 0;
504311502SChenlu.Chen@Sun.COM 		igb->param_lp_10hdx_cap = 0;
504411502SChenlu.Chen@Sun.COM 		igb->param_lp_rem_fault = 0;
50455779Sxy150489 	}
504611502SChenlu.Chen@Sun.COM }
504711502SChenlu.Chen@Sun.COM 
504811502SChenlu.Chen@Sun.COM /*
504911502SChenlu.Chen@Sun.COM  * synchronize the adv* and en* parameters.
505011502SChenlu.Chen@Sun.COM  *
505111502SChenlu.Chen@Sun.COM  * See comments in <sys/dld.h> for details of the *_en_*
505211502SChenlu.Chen@Sun.COM  * parameters. The usage of ndd for setting adv parameters will
505311502SChenlu.Chen@Sun.COM  * synchronize all the en parameters with the e1000g parameters,
505411502SChenlu.Chen@Sun.COM  * implicitly disabling any settings made via dladm.
505511502SChenlu.Chen@Sun.COM  */
505611502SChenlu.Chen@Sun.COM static void
505711502SChenlu.Chen@Sun.COM igb_param_sync(igb_t *igb)
505811502SChenlu.Chen@Sun.COM {
505911502SChenlu.Chen@Sun.COM 	igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap;
506011502SChenlu.Chen@Sun.COM 	igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap;
506111502SChenlu.Chen@Sun.COM 	igb->param_en_100t4_cap = igb->param_adv_100t4_cap;
506211502SChenlu.Chen@Sun.COM 	igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap;
506311502SChenlu.Chen@Sun.COM 	igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap;
506411502SChenlu.Chen@Sun.COM 	igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap;
506511502SChenlu.Chen@Sun.COM 	igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap;
50665779Sxy150489 }
50675779Sxy150489 
50685779Sxy150489 /*
50695779Sxy150489  * igb_get_driver_control
50705779Sxy150489  */
50715779Sxy150489 static void
50725779Sxy150489 igb_get_driver_control(struct e1000_hw *hw)
50735779Sxy150489 {
50745779Sxy150489 	uint32_t ctrl_ext;
50755779Sxy150489 
50765779Sxy150489 	/* Notify firmware that driver is in control of device */
50775779Sxy150489 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
50785779Sxy150489 	ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD;
50795779Sxy150489 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
50805779Sxy150489 }
50815779Sxy150489 
50825779Sxy150489 /*
50835779Sxy150489  * igb_release_driver_control
50845779Sxy150489  */
50855779Sxy150489 static void
50865779Sxy150489 igb_release_driver_control(struct e1000_hw *hw)
50875779Sxy150489 {
50885779Sxy150489 	uint32_t ctrl_ext;
50895779Sxy150489 
50905779Sxy150489 	/* Notify firmware that driver is no longer in control of device */
50915779Sxy150489 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
50925779Sxy150489 	ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD;
50935779Sxy150489 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
50945779Sxy150489 }
50955779Sxy150489 
50965779Sxy150489 /*
50975779Sxy150489  * igb_atomic_reserve - Atomic decrease operation
50985779Sxy150489  */
50995779Sxy150489 int
51005779Sxy150489 igb_atomic_reserve(uint32_t *count_p, uint32_t n)
51015779Sxy150489 {
51025779Sxy150489 	uint32_t oldval;
51035779Sxy150489 	uint32_t newval;
51045779Sxy150489 
51055779Sxy150489 	/* ATOMICALLY */
51065779Sxy150489 	do {
51075779Sxy150489 		oldval = *count_p;
51085779Sxy150489 		if (oldval < n)
51095779Sxy150489 			return (-1);
51105779Sxy150489 		newval = oldval - n;
51115779Sxy150489 	} while (atomic_cas_32(count_p, oldval, newval) != oldval);
51125779Sxy150489 
51135779Sxy150489 	return (newval);
51145779Sxy150489 }
51156624Sgl147354 
51166624Sgl147354 /*
51176624Sgl147354  * FMA support
51186624Sgl147354  */
51196624Sgl147354 
51206624Sgl147354 int
51216624Sgl147354 igb_check_acc_handle(ddi_acc_handle_t handle)
51226624Sgl147354 {
51236624Sgl147354 	ddi_fm_error_t de;
51246624Sgl147354 
51256624Sgl147354 	ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
51266624Sgl147354 	ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
51276624Sgl147354 	return (de.fme_status);
51286624Sgl147354 }
51296624Sgl147354 
51306624Sgl147354 int
51316624Sgl147354 igb_check_dma_handle(ddi_dma_handle_t handle)
51326624Sgl147354 {
51336624Sgl147354 	ddi_fm_error_t de;
51346624Sgl147354 
51356624Sgl147354 	ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
51366624Sgl147354 	return (de.fme_status);
51376624Sgl147354 }
51386624Sgl147354 
51396624Sgl147354 /*
51406624Sgl147354  * The IO fault service error handling callback function
51416624Sgl147354  */
51426624Sgl147354 /*ARGSUSED*/
51436624Sgl147354 static int
51446624Sgl147354 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
51456624Sgl147354 {
51466624Sgl147354 	/*
51476624Sgl147354 	 * as the driver can always deal with an error in any dma or
51486624Sgl147354 	 * access handle, we can just return the fme_status value.
51496624Sgl147354 	 */
51506624Sgl147354 	pci_ereport_post(dip, err, NULL);
51516624Sgl147354 	return (err->fme_status);
51526624Sgl147354 }
51536624Sgl147354 
51546624Sgl147354 static void
51556624Sgl147354 igb_fm_init(igb_t *igb)
51566624Sgl147354 {
51576624Sgl147354 	ddi_iblock_cookie_t iblk;
515811236SStephen.Hanson@Sun.COM 	int fma_dma_flag;
51596624Sgl147354 
51606624Sgl147354 	/* Only register with IO Fault Services if we have some capability */
51616624Sgl147354 	if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
51626624Sgl147354 		igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
51636624Sgl147354 	} else {
51646624Sgl147354 		igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
51656624Sgl147354 	}
51666624Sgl147354 
51676624Sgl147354 	if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
51686624Sgl147354 		fma_dma_flag = 1;
51696624Sgl147354 	} else {
51706624Sgl147354 		fma_dma_flag = 0;
51716624Sgl147354 	}
51726624Sgl147354 
517311236SStephen.Hanson@Sun.COM 	(void) igb_set_fma_flags(fma_dma_flag);
51746624Sgl147354 
51756624Sgl147354 	if (igb->fm_capabilities) {
51766624Sgl147354 
51776624Sgl147354 		/* Register capabilities with IO Fault Services */
51786624Sgl147354 		ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk);
51796624Sgl147354 
51806624Sgl147354 		/*
51816624Sgl147354 		 * Initialize pci ereport capabilities if ereport capable
51826624Sgl147354 		 */
51836624Sgl147354 		if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
51846624Sgl147354 		    DDI_FM_ERRCB_CAP(igb->fm_capabilities))
51856624Sgl147354 			pci_ereport_setup(igb->dip);
51866624Sgl147354 
51876624Sgl147354 		/*
51886624Sgl147354 		 * Register error callback if error callback capable
51896624Sgl147354 		 */
51906624Sgl147354 		if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
51916624Sgl147354 			ddi_fm_handler_register(igb->dip,
51926624Sgl147354 			    igb_fm_error_cb, (void*) igb);
51936624Sgl147354 	}
51946624Sgl147354 }
51956624Sgl147354 
51966624Sgl147354 static void
51976624Sgl147354 igb_fm_fini(igb_t *igb)
51986624Sgl147354 {
51996624Sgl147354 	/* Only unregister FMA capabilities if we registered some */
52006624Sgl147354 	if (igb->fm_capabilities) {
52016624Sgl147354 
52026624Sgl147354 		/*
52036624Sgl147354 		 * Release any resources allocated by pci_ereport_setup()
52046624Sgl147354 		 */
52056624Sgl147354 		if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
52066624Sgl147354 		    DDI_FM_ERRCB_CAP(igb->fm_capabilities))
52076624Sgl147354 			pci_ereport_teardown(igb->dip);
52086624Sgl147354 
52096624Sgl147354 		/*
52106624Sgl147354 		 * Un-register error callback if error callback capable
52116624Sgl147354 		 */
52126624Sgl147354 		if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
52136624Sgl147354 			ddi_fm_handler_unregister(igb->dip);
52146624Sgl147354 
52156624Sgl147354 		/* Unregister from IO Fault Services */
52166624Sgl147354 		ddi_fm_fini(igb->dip);
52176624Sgl147354 	}
52186624Sgl147354 }
52196624Sgl147354 
52206624Sgl147354 void
52216624Sgl147354 igb_fm_ereport(igb_t *igb, char *detail)
52226624Sgl147354 {
52236624Sgl147354 	uint64_t ena;
52246624Sgl147354 	char buf[FM_MAX_CLASS];
52256624Sgl147354 
52266624Sgl147354 	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
52276624Sgl147354 	ena = fm_ena_generate(0, FM_ENA_FMT1);
52286624Sgl147354 	if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) {
52296624Sgl147354 		ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP,
52306624Sgl147354 		    FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
52316624Sgl147354 	}
52326624Sgl147354 }
5233