1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
28*0Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
29*0Sstevel@tonic-gate /* All Rights Reserved */
30*0Sstevel@tonic-gate
31*0Sstevel@tonic-gate /* Copyright (c) 1988, 1989 Intel Corp. */
32*0Sstevel@tonic-gate /* All Rights Reserved */
33*0Sstevel@tonic-gate
34*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
35*0Sstevel@tonic-gate
36*0Sstevel@tonic-gate /*
37*0Sstevel@tonic-gate * Set features for each architecture. List of features:
38*0Sstevel@tonic-gate * ADDR_32: Address is 32 bits
39*0Sstevel@tonic-gate * COUNT_24: Count is 24 bits
40*0Sstevel@tonic-gate * DMA_4CSCD: DMA channel 4 is used for cascade of channels 0-3)
41*0Sstevel@tonic-gate * DMA_INTR: DMA interrupt is available (always with DMA_BUF_CHAIN)
42*0Sstevel@tonic-gate * DMA_BUF_CHAIN: DMA buffer chaining is available (always with DMA_INTR)
43*0Sstevel@tonic-gate * MEM_TO_MEM: Memory to memory transfers available
44*0Sstevel@tonic-gate * NO_PROG_WIDTH: Channel data width is NOT programmable
45*0Sstevel@tonic-gate * SCATER_GATHER Scatter-gather DMA is available (code not implemented)
46*0Sstevel@tonic-gate * ISA_MODE Standard ISA modes available
47*0Sstevel@tonic-gate * EISA_EXT_MODE: EISA extension modes available
48*0Sstevel@tonic-gate */
49*0Sstevel@tonic-gate
50*0Sstevel@tonic-gate /*
51*0Sstevel@tonic-gate * Address is 24 bits (default) with no carry between lo word and hi byte
52*0Sstevel@tonic-gate * Count is 16 bits (default)
53*0Sstevel@tonic-gate */
54*0Sstevel@tonic-gate #define DMA_4CSCD
55*0Sstevel@tonic-gate #define NO_PROG_WIDTH
56*0Sstevel@tonic-gate #define ISA_MODE
57*0Sstevel@tonic-gate
58*0Sstevel@tonic-gate #include <sys/types.h>
59*0Sstevel@tonic-gate #include <sys/cpuvar.h>
60*0Sstevel@tonic-gate #include <sys/disp.h>
61*0Sstevel@tonic-gate #include <sys/sunddi.h>
62*0Sstevel@tonic-gate #include <sys/cmn_err.h>
63*0Sstevel@tonic-gate #include <sys/dma_engine.h>
64*0Sstevel@tonic-gate #include <sys/dma_i8237A.h>
65*0Sstevel@tonic-gate
66*0Sstevel@tonic-gate #if defined(DEBUG)
67*0Sstevel@tonic-gate #include <sys/promif.h>
68*0Sstevel@tonic-gate static int i8237debug = 0;
69*0Sstevel@tonic-gate #define dprintf(x) if (i8237debug) (void)prom_printf x
70*0Sstevel@tonic-gate #else
71*0Sstevel@tonic-gate #define dprintf(x)
72*0Sstevel@tonic-gate #endif /* defined(DEBUG) */
73*0Sstevel@tonic-gate
74*0Sstevel@tonic-gate
75*0Sstevel@tonic-gate extern int EISA_chaining;
76*0Sstevel@tonic-gate
77*0Sstevel@tonic-gate /*
78*0Sstevel@tonic-gate * data structures for maintaining the DMACs
79*0Sstevel@tonic-gate */
80*0Sstevel@tonic-gate static kmutex_t dma_engine_lock;
81*0Sstevel@tonic-gate static struct d37A_chan_reg_addr chan_addr[] = { D37A_BASE_REGS_VALUES };
82*0Sstevel@tonic-gate static ushort_t d37A_chnl_path[] = {
83*0Sstevel@tonic-gate DMAE_PATH_8, /* first 4 DMA channels default to 8-bit xfers */
84*0Sstevel@tonic-gate DMAE_PATH_8,
85*0Sstevel@tonic-gate DMAE_PATH_8,
86*0Sstevel@tonic-gate DMAE_PATH_8,
87*0Sstevel@tonic-gate 0,
88*0Sstevel@tonic-gate DMAE_PATH_16, /* last 3 DMA channels default to 16-bit xfers */
89*0Sstevel@tonic-gate DMAE_PATH_16,
90*0Sstevel@tonic-gate DMAE_PATH_16};
91*0Sstevel@tonic-gate static ushort_t d37A_chnl_mode[] = {
92*0Sstevel@tonic-gate DMAE_TRANS_SNGL, DMAE_TRANS_SNGL, DMAE_TRANS_SNGL, DMAE_TRANS_SNGL,
93*0Sstevel@tonic-gate #ifdef DMA_4CSCD
94*0Sstevel@tonic-gate DMAE_TRANS_CSCD,
95*0Sstevel@tonic-gate #else /* !DMA_4CSCD */
96*0Sstevel@tonic-gate DMAE_TRANS_SNGL,
97*0Sstevel@tonic-gate #endif /* !DMA_4CSCD */
98*0Sstevel@tonic-gate DMAE_TRANS_SNGL, DMAE_TRANS_SNGL, DMAE_TRANS_SNGL};
99*0Sstevel@tonic-gate #ifdef DMA_BUF_CHAIN
100*0Sstevel@tonic-gate static ddi_dma_cookie_t *d37A_next_cookie[] =
101*0Sstevel@tonic-gate {0, 0, 0, 0, 0, 0, 0, 0};
102*0Sstevel@tonic-gate #endif /* DMA_BUF_CHAIN */
103*0Sstevel@tonic-gate
104*0Sstevel@tonic-gate
105*0Sstevel@tonic-gate #ifdef DMA_INTR
106*0Sstevel@tonic-gate static uint_t d37A_intr(caddr_t);
107*0Sstevel@tonic-gate #endif
108*0Sstevel@tonic-gate static int d37A_set_mode(struct ddi_dmae_req *, int);
109*0Sstevel@tonic-gate static int d37A_write_addr(ulong_t, int);
110*0Sstevel@tonic-gate static ulong_t d37A_read_addr(int);
111*0Sstevel@tonic-gate static int d37A_write_count(long, int);
112*0Sstevel@tonic-gate static long d37A_read_count(int);
113*0Sstevel@tonic-gate
114*0Sstevel@tonic-gate #ifdef DMA_BUF_CHAIN
115*0Sstevel@tonic-gate static void dEISA_setchain(ddi_dma_cookie_t *cp, int chnl);
116*0Sstevel@tonic-gate #endif
117*0Sstevel@tonic-gate
118*0Sstevel@tonic-gate /*
119*0Sstevel@tonic-gate * Routine: d37A_init()
120*0Sstevel@tonic-gate * purpose: initializes the 8237A.
121*0Sstevel@tonic-gate * caller: dma_init()
122*0Sstevel@tonic-gate * calls: d37A macros, d37A_init()
123*0Sstevel@tonic-gate */
124*0Sstevel@tonic-gate
125*0Sstevel@tonic-gate /*ARGSUSED*/
126*0Sstevel@tonic-gate int
d37A_init(dev_info_t * dip)127*0Sstevel@tonic-gate d37A_init(dev_info_t *dip)
128*0Sstevel@tonic-gate {
129*0Sstevel@tonic-gate #ifdef DMA_INTR
130*0Sstevel@tonic-gate ddi_iblock_cookie_t iblk_cookie = 0;
131*0Sstevel@tonic-gate int error;
132*0Sstevel@tonic-gate
133*0Sstevel@tonic-gate if ((error = ddi_add_intr(dip, (uint_t)0, &iblk_cookie,
134*0Sstevel@tonic-gate (ddi_idevice_cookie_t *)0, d37A_intr, (caddr_t)NULL)) !=
135*0Sstevel@tonic-gate DDI_SUCCESS) {
136*0Sstevel@tonic-gate if (error != DDI_INTR_NOTFOUND)
137*0Sstevel@tonic-gate cmn_err(CE_WARN, "!d37A_init: cannot add dma intr\n");
138*0Sstevel@tonic-gate EISA_chaining = 0;
139*0Sstevel@tonic-gate }
140*0Sstevel@tonic-gate mutex_init(&dma_engine_lock, NULL, MUTEX_DRIVER, (void *)iblk_cookie);
141*0Sstevel@tonic-gate #else /* !DMA_INTR */
142*0Sstevel@tonic-gate mutex_init(&dma_engine_lock, NULL, MUTEX_DRIVER, NULL);
143*0Sstevel@tonic-gate #endif /* !DMA_INTR */
144*0Sstevel@tonic-gate
145*0Sstevel@tonic-gate return (DDI_SUCCESS);
146*0Sstevel@tonic-gate }
147*0Sstevel@tonic-gate
148*0Sstevel@tonic-gate /*
149*0Sstevel@tonic-gate * Routine: d37A_valid()
150*0Sstevel@tonic-gate * purpose: validates the channel to be acquired.
151*0Sstevel@tonic-gate * caller: i_dmae_acquire()
152*0Sstevel@tonic-gate * calls:
153*0Sstevel@tonic-gate */
154*0Sstevel@tonic-gate
155*0Sstevel@tonic-gate int
d37A_dma_valid(int chnl)156*0Sstevel@tonic-gate d37A_dma_valid(int chnl)
157*0Sstevel@tonic-gate {
158*0Sstevel@tonic-gate #ifdef DMA_4CSCD
159*0Sstevel@tonic-gate if (chnl == 4)
160*0Sstevel@tonic-gate return (0);
161*0Sstevel@tonic-gate #endif /* DMA_4CSCD */
162*0Sstevel@tonic-gate return (1);
163*0Sstevel@tonic-gate }
164*0Sstevel@tonic-gate
165*0Sstevel@tonic-gate /*
166*0Sstevel@tonic-gate * Routine: d37A_release()
167*0Sstevel@tonic-gate * purpose: resets the 8237A mode.
168*0Sstevel@tonic-gate * caller: i_dmae_free()
169*0Sstevel@tonic-gate * calls:
170*0Sstevel@tonic-gate */
171*0Sstevel@tonic-gate
172*0Sstevel@tonic-gate void
d37A_dma_release(int chnl)173*0Sstevel@tonic-gate d37A_dma_release(int chnl)
174*0Sstevel@tonic-gate {
175*0Sstevel@tonic-gate #ifdef DMA_4CSCD
176*0Sstevel@tonic-gate if (chnl == 4)
177*0Sstevel@tonic-gate return;
178*0Sstevel@tonic-gate #endif /* DMA_4CSCD */
179*0Sstevel@tonic-gate d37A_chnl_mode[chnl] = DMAE_TRANS_SNGL;
180*0Sstevel@tonic-gate }
181*0Sstevel@tonic-gate
182*0Sstevel@tonic-gate /*
183*0Sstevel@tonic-gate * routine: d37A_dma_disable()
184*0Sstevel@tonic-gate * purpose: Prevent the DMAC from responding to external hardware
185*0Sstevel@tonic-gate * requests for DMA service on the given channel
186*0Sstevel@tonic-gate * caller: dma_disable()
187*0Sstevel@tonic-gate * calls: d37A macros
188*0Sstevel@tonic-gate */
189*0Sstevel@tonic-gate void
d37A_dma_disable(int chnl)190*0Sstevel@tonic-gate d37A_dma_disable(int chnl)
191*0Sstevel@tonic-gate {
192*0Sstevel@tonic-gate dprintf(("d37A_dma_disable: chnl=%d mask_reg=0x%x\n",
193*0Sstevel@tonic-gate chnl, chan_addr[chnl].mask_reg));
194*0Sstevel@tonic-gate
195*0Sstevel@tonic-gate outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);
196*0Sstevel@tonic-gate }
197*0Sstevel@tonic-gate
198*0Sstevel@tonic-gate
199*0Sstevel@tonic-gate /*
200*0Sstevel@tonic-gate * routine: d37A_dma_enable()
201*0Sstevel@tonic-gate * purpose: Enable to DMAC to respond to hardware requests for DMA
202*0Sstevel@tonic-gate * service on the specified channel.
203*0Sstevel@tonic-gate * caller: dma_enable()
204*0Sstevel@tonic-gate * calls: d37A macros
205*0Sstevel@tonic-gate */
206*0Sstevel@tonic-gate
207*0Sstevel@tonic-gate void
d37A_dma_enable(int chnl)208*0Sstevel@tonic-gate d37A_dma_enable(int chnl)
209*0Sstevel@tonic-gate {
210*0Sstevel@tonic-gate dprintf(("d37A_dma_enable: chnl=%d mask_reg=0x%x val=0x%x\n",
211*0Sstevel@tonic-gate chnl, chan_addr[chnl].mask_reg, chnl & 3));
212*0Sstevel@tonic-gate
213*0Sstevel@tonic-gate /* mutex_enter(&dma_engine_lock); */
214*0Sstevel@tonic-gate outb(chan_addr[chnl].mask_reg, chnl & 3);
215*0Sstevel@tonic-gate /* mutex_exit(&dma_engine_lock); */
216*0Sstevel@tonic-gate }
217*0Sstevel@tonic-gate
218*0Sstevel@tonic-gate
219*0Sstevel@tonic-gate /*
220*0Sstevel@tonic-gate * routine: d37A_get_best_mode()
221*0Sstevel@tonic-gate * purpose: stub routine - determine optimum transfer method
222*0Sstevel@tonic-gate * caller: dma_get_best_mode().
223*0Sstevel@tonic-gate * calls:
224*0Sstevel@tonic-gate */
225*0Sstevel@tonic-gate /* ARGSUSED */
226*0Sstevel@tonic-gate uchar_t
d37A_get_best_mode(struct ddi_dmae_req * dmaereqp)227*0Sstevel@tonic-gate d37A_get_best_mode(struct ddi_dmae_req *dmaereqp)
228*0Sstevel@tonic-gate {
229*0Sstevel@tonic-gate return (DMAE_CYCLES_2);
230*0Sstevel@tonic-gate }
231*0Sstevel@tonic-gate
232*0Sstevel@tonic-gate #ifdef DMA_INTR
233*0Sstevel@tonic-gate /*
234*0Sstevel@tonic-gate * routine: d37A_intr()
235*0Sstevel@tonic-gate * purpose: stub routine
236*0Sstevel@tonic-gate * caller:
237*0Sstevel@tonic-gate * calls: dma_intr().
238*0Sstevel@tonic-gate */
239*0Sstevel@tonic-gate /*ARGSUSED*/
240*0Sstevel@tonic-gate static uint_t
d37A_intr(caddr_t arg)241*0Sstevel@tonic-gate d37A_intr(caddr_t arg)
242*0Sstevel@tonic-gate {
243*0Sstevel@tonic-gate int chnl, istate, nstate;
244*0Sstevel@tonic-gate uint_t mask;
245*0Sstevel@tonic-gate
246*0Sstevel@tonic-gate if ((istate = (inb(EISA_DMAIS) & 0xef)) != 0) {
247*0Sstevel@tonic-gate /* channel 4 can't interrupt */
248*0Sstevel@tonic-gate chnl = 0;
249*0Sstevel@tonic-gate nstate = istate;
250*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
251*0Sstevel@tonic-gate do {
252*0Sstevel@tonic-gate if (istate & 1) {
253*0Sstevel@tonic-gate dEISA_setchain(d37A_next_cookie[chnl], chnl);
254*0Sstevel@tonic-gate #ifdef DEBUG
255*0Sstevel@tonic-gate if (chnl < 4)
256*0Sstevel@tonic-gate mask = inb(DMAC1_ALLMASK) >> (chnl);
257*0Sstevel@tonic-gate else
258*0Sstevel@tonic-gate mask = inb(DMAC2_ALLMASK) >> (chnl - 4);
259*0Sstevel@tonic-gate if (mask & 1)
260*0Sstevel@tonic-gate prom_printf("eisa: dma buffer chaining failure chnl %d!\n", chnl);
261*0Sstevel@tonic-gate
262*0Sstevel@tonic-gate #endif /* DEBUG */
263*0Sstevel@tonic-gate }
264*0Sstevel@tonic-gate chnl++;
265*0Sstevel@tonic-gate istate >>= 1;
266*0Sstevel@tonic-gate } while (istate);
267*0Sstevel@tonic-gate chnl = 0;
268*0Sstevel@tonic-gate do {
269*0Sstevel@tonic-gate if ((nstate & 1) && d37A_next_cookie[chnl])
270*0Sstevel@tonic-gate d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);
271*0Sstevel@tonic-gate chnl++;
272*0Sstevel@tonic-gate nstate >>= 1;
273*0Sstevel@tonic-gate } while (nstate);
274*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
275*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED);
276*0Sstevel@tonic-gate }
277*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED);
278*0Sstevel@tonic-gate }
279*0Sstevel@tonic-gate #endif /* DMA_INTR */
280*0Sstevel@tonic-gate
281*0Sstevel@tonic-gate
282*0Sstevel@tonic-gate #ifdef DMA_BUF_CHAIN
283*0Sstevel@tonic-gate /*
284*0Sstevel@tonic-gate * routine: dEISA_setchain()
285*0Sstevel@tonic-gate * purpose: Set next buffer address/count from chain
286*0Sstevel@tonic-gate * caller: d37A_intr()
287*0Sstevel@tonic-gate * calls: d37A macros
288*0Sstevel@tonic-gate */
289*0Sstevel@tonic-gate static void
dEISA_setchain(ddi_dma_cookie_t * cp,int chnl)290*0Sstevel@tonic-gate dEISA_setchain(ddi_dma_cookie_t *cp, int chnl)
291*0Sstevel@tonic-gate {
292*0Sstevel@tonic-gate if (cp) {
293*0Sstevel@tonic-gate dprintf(("dEISA_setchain: chnl=%d next_addr=%x count=%lx\n",
294*0Sstevel@tonic-gate chnl, cp->dmac_address, cp->dmac_size));
295*0Sstevel@tonic-gate (void) d37A_write_addr(cp->dmac_address, chnl);
296*0Sstevel@tonic-gate (void) d37A_write_count(cp->dmac_size, chnl);
297*0Sstevel@tonic-gate outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);
298*0Sstevel@tonic-gate } else {
299*0Sstevel@tonic-gate /*
300*0Sstevel@tonic-gate * clear chain enable bit
301*0Sstevel@tonic-gate */
302*0Sstevel@tonic-gate outb(chan_addr[chnl].scm_reg, chnl);
303*0Sstevel@tonic-gate dprintf(("dEISA_setchain: chnl=%d end\n", chnl));
304*0Sstevel@tonic-gate }
305*0Sstevel@tonic-gate }
306*0Sstevel@tonic-gate #endif /* DMA_BUF_CHAIN */
307*0Sstevel@tonic-gate
308*0Sstevel@tonic-gate
309*0Sstevel@tonic-gate /*
310*0Sstevel@tonic-gate * routine: d37A_prog_chan()
311*0Sstevel@tonic-gate * purpose: program the Mode registers and the Base registers of a
312*0Sstevel@tonic-gate * DMA channel for a subsequent hardware-initiated transfer.
313*0Sstevel@tonic-gate * caller: dma_prog_chan()
314*0Sstevel@tonic-gate * calls: d37A_write_addr(), d37A_write_count(), d37A macros.
315*0Sstevel@tonic-gate */
316*0Sstevel@tonic-gate
317*0Sstevel@tonic-gate int
d37A_prog_chan(struct ddi_dmae_req * dmaereqp,ddi_dma_cookie_t * cp,int chnl)318*0Sstevel@tonic-gate d37A_prog_chan(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)
319*0Sstevel@tonic-gate {
320*0Sstevel@tonic-gate if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {
321*0Sstevel@tonic-gate dprintf(("d37A_prog_chan err: chnl=%d in cascade mode\n",
322*0Sstevel@tonic-gate chnl));
323*0Sstevel@tonic-gate return (DDI_FAILURE);
324*0Sstevel@tonic-gate }
325*0Sstevel@tonic-gate #ifndef MEM_TO_MEM
326*0Sstevel@tonic-gate if (dmaereqp && dmaereqp->der_dest == DMAE_DEST_MEM) {
327*0Sstevel@tonic-gate dprintf(("d37A_prog_chan err: memory to memory mode not supported.\n"));
328*0Sstevel@tonic-gate return (DDI_FAILURE);
329*0Sstevel@tonic-gate }
330*0Sstevel@tonic-gate #endif /* !MEM_TO_MEM */
331*0Sstevel@tonic-gate
332*0Sstevel@tonic-gate dprintf(("d37A_prog_chan: chnl=%d dmaereq=%p\n",
333*0Sstevel@tonic-gate chnl, (void *)dmaereqp));
334*0Sstevel@tonic-gate
335*0Sstevel@tonic-gate if (dmaereqp) {
336*0Sstevel@tonic-gate switch (chnl) {
337*0Sstevel@tonic-gate case DMAE_CH0:
338*0Sstevel@tonic-gate case DMAE_CH1:
339*0Sstevel@tonic-gate case DMAE_CH2:
340*0Sstevel@tonic-gate case DMAE_CH3:
341*0Sstevel@tonic-gate #ifdef NO_PROG_WIDTH
342*0Sstevel@tonic-gate if (dmaereqp->der_path &&
343*0Sstevel@tonic-gate dmaereqp->der_path != DMAE_PATH_8) {
344*0Sstevel@tonic-gate dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
345*0Sstevel@tonic-gate return (DDI_FAILURE);
346*0Sstevel@tonic-gate }
347*0Sstevel@tonic-gate #endif /* NO_PROG_WIDTH */
348*0Sstevel@tonic-gate break;
349*0Sstevel@tonic-gate
350*0Sstevel@tonic-gate #ifndef DMA_4CSCD
351*0Sstevel@tonic-gate case DMAE_CH4:
352*0Sstevel@tonic-gate #endif /* !DMA_4CSCD */
353*0Sstevel@tonic-gate case DMAE_CH5:
354*0Sstevel@tonic-gate case DMAE_CH6:
355*0Sstevel@tonic-gate case DMAE_CH7:
356*0Sstevel@tonic-gate #ifdef NO_PROG_WIDTH
357*0Sstevel@tonic-gate if (dmaereqp->der_path &&
358*0Sstevel@tonic-gate dmaereqp->der_path != DMAE_PATH_16) {
359*0Sstevel@tonic-gate dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
360*0Sstevel@tonic-gate return (DDI_FAILURE);
361*0Sstevel@tonic-gate }
362*0Sstevel@tonic-gate #endif /* NO_PROG_WIDTH */
363*0Sstevel@tonic-gate break;
364*0Sstevel@tonic-gate
365*0Sstevel@tonic-gate default:
366*0Sstevel@tonic-gate dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
367*0Sstevel@tonic-gate return (DDI_FAILURE);
368*0Sstevel@tonic-gate }
369*0Sstevel@tonic-gate } else
370*0Sstevel@tonic-gate chnl &= 3;
371*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
372*0Sstevel@tonic-gate
373*0Sstevel@tonic-gate d37A_dma_disable(chnl);
374*0Sstevel@tonic-gate if (dmaereqp)
375*0Sstevel@tonic-gate (void) d37A_set_mode(dmaereqp, chnl);
376*0Sstevel@tonic-gate
377*0Sstevel@tonic-gate if (cp) {
378*0Sstevel@tonic-gate (void) d37A_write_addr(cp->dmac_address, chnl);
379*0Sstevel@tonic-gate (void) d37A_write_count(cp->dmac_size, chnl);
380*0Sstevel@tonic-gate
381*0Sstevel@tonic-gate #ifdef DMA_BUF_CHAIN
382*0Sstevel@tonic-gate if (dmaereqp && dmaereqp->der_bufprocess == DMAE_BUF_CHAIN &&
383*0Sstevel@tonic-gate (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {
384*0Sstevel@tonic-gate /*
385*0Sstevel@tonic-gate * i/o operation has more than 1 cookie
386*0Sstevel@tonic-gate * so enable dma buffer chaining
387*0Sstevel@tonic-gate */
388*0Sstevel@tonic-gate drv_usecwait(10);
389*0Sstevel@tonic-gate outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
390*0Sstevel@tonic-gate drv_usecwait(15);
391*0Sstevel@tonic-gate dEISA_setchain(d37A_next_cookie[chnl], chnl);
392*0Sstevel@tonic-gate d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);
393*0Sstevel@tonic-gate }
394*0Sstevel@tonic-gate #endif /* DMA_BUF_CHAIN */
395*0Sstevel@tonic-gate }
396*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
397*0Sstevel@tonic-gate return (DDI_SUCCESS);
398*0Sstevel@tonic-gate }
399*0Sstevel@tonic-gate
400*0Sstevel@tonic-gate
401*0Sstevel@tonic-gate /*
402*0Sstevel@tonic-gate * routine: d37A_dma_swsetup()
403*0Sstevel@tonic-gate * purpose: program the Mode registers and the Base register for the
404*0Sstevel@tonic-gate * specified channel.
405*0Sstevel@tonic-gate * caller: dma_swsetup()
406*0Sstevel@tonic-gate * calls: d37A_write_addr(), d37A_write_count(), d37A macros.
407*0Sstevel@tonic-gate */
408*0Sstevel@tonic-gate
409*0Sstevel@tonic-gate int
d37A_dma_swsetup(struct ddi_dmae_req * dmaereqp,ddi_dma_cookie_t * cp,int chnl)410*0Sstevel@tonic-gate d37A_dma_swsetup(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)
411*0Sstevel@tonic-gate {
412*0Sstevel@tonic-gate if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {
413*0Sstevel@tonic-gate dprintf(("d37A_dma_swsetup err: chnl %d not programmed\n",
414*0Sstevel@tonic-gate chnl));
415*0Sstevel@tonic-gate return (DDI_FAILURE);
416*0Sstevel@tonic-gate }
417*0Sstevel@tonic-gate
418*0Sstevel@tonic-gate dprintf(("d37A_dma_swsetup: chnl=%d dmaereq=%p.\n",
419*0Sstevel@tonic-gate chnl, (void *)dmaereqp));
420*0Sstevel@tonic-gate
421*0Sstevel@tonic-gate /* MUST BE IN BLOCK MODE FOR SOFTWARE INITIATED REQUESTS */
422*0Sstevel@tonic-gate if (dmaereqp->der_trans != DMAE_TRANS_BLCK)
423*0Sstevel@tonic-gate dmaereqp->der_trans = DMAE_TRANS_BLCK;
424*0Sstevel@tonic-gate
425*0Sstevel@tonic-gate switch (chnl) {
426*0Sstevel@tonic-gate case DMAE_CH0:
427*0Sstevel@tonic-gate case DMAE_CH1:
428*0Sstevel@tonic-gate case DMAE_CH2:
429*0Sstevel@tonic-gate case DMAE_CH3:
430*0Sstevel@tonic-gate #ifdef NO_PROG_WIDTH
431*0Sstevel@tonic-gate if (dmaereqp->der_path && dmaereqp->der_path != DMAE_PATH_8) {
432*0Sstevel@tonic-gate dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));
433*0Sstevel@tonic-gate return (DDI_FAILURE);
434*0Sstevel@tonic-gate }
435*0Sstevel@tonic-gate #endif /* NO_PROG_WIDTH */
436*0Sstevel@tonic-gate break;
437*0Sstevel@tonic-gate
438*0Sstevel@tonic-gate #ifndef DMA_4CSCD
439*0Sstevel@tonic-gate case DMAE_CH4:
440*0Sstevel@tonic-gate #endif /* !DMA_4CSCD */
441*0Sstevel@tonic-gate case DMAE_CH5:
442*0Sstevel@tonic-gate case DMAE_CH6:
443*0Sstevel@tonic-gate case DMAE_CH7:
444*0Sstevel@tonic-gate #ifdef NO_PROG_WIDTH
445*0Sstevel@tonic-gate if (dmaereqp->der_path && dmaereqp->der_path != DMAE_PATH_16) {
446*0Sstevel@tonic-gate dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));
447*0Sstevel@tonic-gate return (DDI_FAILURE);
448*0Sstevel@tonic-gate }
449*0Sstevel@tonic-gate #endif /* NO_PROG_WIDTH */
450*0Sstevel@tonic-gate break;
451*0Sstevel@tonic-gate
452*0Sstevel@tonic-gate default:
453*0Sstevel@tonic-gate dprintf(("d37A_dma_swsetup err: chnl %d not set up.\n", chnl));
454*0Sstevel@tonic-gate return (DDI_FAILURE);
455*0Sstevel@tonic-gate };
456*0Sstevel@tonic-gate
457*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
458*0Sstevel@tonic-gate
459*0Sstevel@tonic-gate d37A_dma_disable(chnl);
460*0Sstevel@tonic-gate (void) d37A_set_mode(dmaereqp, chnl);
461*0Sstevel@tonic-gate
462*0Sstevel@tonic-gate (void) d37A_write_addr(cp->dmac_address, chnl);
463*0Sstevel@tonic-gate (void) d37A_write_count(cp->dmac_size, chnl);
464*0Sstevel@tonic-gate
465*0Sstevel@tonic-gate #ifdef DMA_BUF_CHAIN
466*0Sstevel@tonic-gate if (dmaereqp->der_bufprocess == DMAE_BUF_CHAIN &&
467*0Sstevel@tonic-gate (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {
468*0Sstevel@tonic-gate /*
469*0Sstevel@tonic-gate * i/o operation has more than 1 cookie
470*0Sstevel@tonic-gate * so enable dma buffer chaining
471*0Sstevel@tonic-gate */
472*0Sstevel@tonic-gate outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);
473*0Sstevel@tonic-gate dEISA_setchain(d37A_next_cookie[chnl], chnl);
474*0Sstevel@tonic-gate d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);
475*0Sstevel@tonic-gate }
476*0Sstevel@tonic-gate #endif /* DMA_BUF_CHAIN */
477*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
478*0Sstevel@tonic-gate return (DDI_SUCCESS);
479*0Sstevel@tonic-gate }
480*0Sstevel@tonic-gate
481*0Sstevel@tonic-gate
482*0Sstevel@tonic-gate /*
483*0Sstevel@tonic-gate * routine: d37A_dma_swstart()
484*0Sstevel@tonic-gate * purpose: SW start transfer setup on the indicated channel.
485*0Sstevel@tonic-gate * caller: dma_swstart()
486*0Sstevel@tonic-gate * calls: d37A_dma_enable(), d37A macros
487*0Sstevel@tonic-gate */
488*0Sstevel@tonic-gate
489*0Sstevel@tonic-gate void
d37A_dma_swstart(int chnl)490*0Sstevel@tonic-gate d37A_dma_swstart(int chnl)
491*0Sstevel@tonic-gate {
492*0Sstevel@tonic-gate dprintf(("d37A_dma_swstart: chnl=%d\n", chnl));
493*0Sstevel@tonic-gate
494*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
495*0Sstevel@tonic-gate d37A_dma_enable(chnl);
496*0Sstevel@tonic-gate outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */
497*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
498*0Sstevel@tonic-gate }
499*0Sstevel@tonic-gate
500*0Sstevel@tonic-gate
501*0Sstevel@tonic-gate /*
502*0Sstevel@tonic-gate * routine: d37A_dma_stop()
503*0Sstevel@tonic-gate * purpose: Stop any activity on the indicated channel.
504*0Sstevel@tonic-gate * caller: dma_stop()
505*0Sstevel@tonic-gate * calls: d37A macros
506*0Sstevel@tonic-gate */
507*0Sstevel@tonic-gate
508*0Sstevel@tonic-gate void
d37A_dma_stop(int chnl)509*0Sstevel@tonic-gate d37A_dma_stop(int chnl)
510*0Sstevel@tonic-gate {
511*0Sstevel@tonic-gate dprintf(("d37A_dma_stop: chnl=%d\n", chnl));
512*0Sstevel@tonic-gate
513*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
514*0Sstevel@tonic-gate d37A_dma_disable(chnl);
515*0Sstevel@tonic-gate outb(chan_addr[chnl].reqt_reg, chnl & 3); /* reset request bit */
516*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
517*0Sstevel@tonic-gate }
518*0Sstevel@tonic-gate
519*0Sstevel@tonic-gate
520*0Sstevel@tonic-gate /*
521*0Sstevel@tonic-gate * routine: d37A_get_chan_stat()
522*0Sstevel@tonic-gate * purpose: retrieve the Current Address and Count registers for the
523*0Sstevel@tonic-gate * specified channel.
524*0Sstevel@tonic-gate * caller: dma_get_chan_stat()
525*0Sstevel@tonic-gate * calls: d37A_read_addr(), d37A_read_count().
526*0Sstevel@tonic-gate */
527*0Sstevel@tonic-gate void
d37A_get_chan_stat(int chnl,ulong_t * addressp,int * countp)528*0Sstevel@tonic-gate d37A_get_chan_stat(int chnl, ulong_t *addressp, int *countp)
529*0Sstevel@tonic-gate {
530*0Sstevel@tonic-gate ulong_t taddr;
531*0Sstevel@tonic-gate int tcount;
532*0Sstevel@tonic-gate
533*0Sstevel@tonic-gate mutex_enter(&dma_engine_lock);
534*0Sstevel@tonic-gate taddr = d37A_read_addr(chnl);
535*0Sstevel@tonic-gate tcount = d37A_read_count(chnl);
536*0Sstevel@tonic-gate mutex_exit(&dma_engine_lock);
537*0Sstevel@tonic-gate if (addressp)
538*0Sstevel@tonic-gate *addressp = taddr;
539*0Sstevel@tonic-gate if (countp)
540*0Sstevel@tonic-gate *countp = tcount;
541*0Sstevel@tonic-gate dprintf(("d37A_get_chan_stat: chnl=%d address=%lx count=%x\n",
542*0Sstevel@tonic-gate chnl, taddr, tcount));
543*0Sstevel@tonic-gate }
544*0Sstevel@tonic-gate
545*0Sstevel@tonic-gate
546*0Sstevel@tonic-gate /*
547*0Sstevel@tonic-gate * routine: d37A_set_mode()
548*0Sstevel@tonic-gate * purpose: program the Mode registers of the
549*0Sstevel@tonic-gate * DMAC for a subsequent hardware-initiated transfer.
550*0Sstevel@tonic-gate * caller: d37A_prog_chan(), d37A_dma_swsetup
551*0Sstevel@tonic-gate * calls:
552*0Sstevel@tonic-gate */
553*0Sstevel@tonic-gate
554*0Sstevel@tonic-gate static int
d37A_set_mode(struct ddi_dmae_req * dmaereqp,int chnl)555*0Sstevel@tonic-gate d37A_set_mode(struct ddi_dmae_req *dmaereqp, int chnl)
556*0Sstevel@tonic-gate {
557*0Sstevel@tonic-gate uchar_t mode = 0, emode = 0;
558*0Sstevel@tonic-gate
559*0Sstevel@tonic-gate #ifdef ISA_MODE
560*0Sstevel@tonic-gate #if defined(lint)
561*0Sstevel@tonic-gate emode = emode;
562*0Sstevel@tonic-gate #endif
563*0Sstevel@tonic-gate mode = chnl & 3;
564*0Sstevel@tonic-gate
565*0Sstevel@tonic-gate switch (dmaereqp->der_command) {
566*0Sstevel@tonic-gate case DMAE_CMD_READ:
567*0Sstevel@tonic-gate mode |= DMAMODE_READ;
568*0Sstevel@tonic-gate break;
569*0Sstevel@tonic-gate case DMAE_CMD_WRITE:
570*0Sstevel@tonic-gate mode |= DMAMODE_WRITE;
571*0Sstevel@tonic-gate break;
572*0Sstevel@tonic-gate case DMAE_CMD_VRFY:
573*0Sstevel@tonic-gate mode |= DMAMODE_VERF;
574*0Sstevel@tonic-gate break;
575*0Sstevel@tonic-gate case DMAE_CMD_TRAN:
576*0Sstevel@tonic-gate mode |= 0x0C; /* for Adaptec 1st party DMA on chnl 0 */
577*0Sstevel@tonic-gate break;
578*0Sstevel@tonic-gate default:
579*0Sstevel@tonic-gate return (DDI_FAILURE);
580*0Sstevel@tonic-gate }
581*0Sstevel@tonic-gate
582*0Sstevel@tonic-gate if (dmaereqp->der_bufprocess == DMAE_BUF_AUTO)
583*0Sstevel@tonic-gate mode |= DMAMODE_AUTO;
584*0Sstevel@tonic-gate
585*0Sstevel@tonic-gate if (dmaereqp->der_step == DMAE_STEP_DEC)
586*0Sstevel@tonic-gate mode |= DMAMODE_DECR;
587*0Sstevel@tonic-gate
588*0Sstevel@tonic-gate switch (dmaereqp->der_trans) {
589*0Sstevel@tonic-gate case DMAE_TRANS_SNGL:
590*0Sstevel@tonic-gate mode |= DMAMODE_SINGLE;
591*0Sstevel@tonic-gate break;
592*0Sstevel@tonic-gate case DMAE_TRANS_BLCK:
593*0Sstevel@tonic-gate mode |= DMAMODE_BLOCK;
594*0Sstevel@tonic-gate break;
595*0Sstevel@tonic-gate case DMAE_TRANS_DMND:
596*0Sstevel@tonic-gate break;
597*0Sstevel@tonic-gate case DMAE_TRANS_CSCD:
598*0Sstevel@tonic-gate mode |= DMAMODE_CASC;
599*0Sstevel@tonic-gate break;
600*0Sstevel@tonic-gate default:
601*0Sstevel@tonic-gate return (DDI_FAILURE);
602*0Sstevel@tonic-gate }
603*0Sstevel@tonic-gate d37A_chnl_mode[chnl] = dmaereqp->der_trans;
604*0Sstevel@tonic-gate
605*0Sstevel@tonic-gate dprintf(("d37A_set_mode: chnl=%d mode_reg=0x%x mode=0x%x\n",
606*0Sstevel@tonic-gate chnl, chan_addr[chnl].mode_reg, mode));
607*0Sstevel@tonic-gate outb(chan_addr[chnl].mode_reg, mode);
608*0Sstevel@tonic-gate #endif /* ISA_MODE */
609*0Sstevel@tonic-gate
610*0Sstevel@tonic-gate #ifdef EISA_EXT_MODE
611*0Sstevel@tonic-gate emode = chnl & 3;
612*0Sstevel@tonic-gate d37A_chnl_path[chnl] = dmaereqp->der_path;
613*0Sstevel@tonic-gate
614*0Sstevel@tonic-gate switch (dmaereqp->der_path) {
615*0Sstevel@tonic-gate case DMAE_PATH_8:
616*0Sstevel@tonic-gate /* emode |= EISA_DMA_8; */
617*0Sstevel@tonic-gate break;
618*0Sstevel@tonic-gate case DMAE_PATH_16:
619*0Sstevel@tonic-gate emode |= EISA_DMA_16;
620*0Sstevel@tonic-gate break;
621*0Sstevel@tonic-gate case DMAE_PATH_32:
622*0Sstevel@tonic-gate emode |= EISA_DMA_32;
623*0Sstevel@tonic-gate break;
624*0Sstevel@tonic-gate case DMAE_PATH_16B:
625*0Sstevel@tonic-gate emode |= EISA_DMA_16B;
626*0Sstevel@tonic-gate break;
627*0Sstevel@tonic-gate default:
628*0Sstevel@tonic-gate switch (chnl) {
629*0Sstevel@tonic-gate case DMAE_CH0:
630*0Sstevel@tonic-gate case DMAE_CH1:
631*0Sstevel@tonic-gate case DMAE_CH2:
632*0Sstevel@tonic-gate case DMAE_CH3:
633*0Sstevel@tonic-gate d37A_chnl_path[chnl] = DMAE_PATH_8;
634*0Sstevel@tonic-gate /* emode |= EISA_DMA_8; */
635*0Sstevel@tonic-gate break;
636*0Sstevel@tonic-gate case DMAE_CH5:
637*0Sstevel@tonic-gate case DMAE_CH6:
638*0Sstevel@tonic-gate case DMAE_CH7:
639*0Sstevel@tonic-gate d37A_chnl_path[chnl] = DMAE_PATH_16;
640*0Sstevel@tonic-gate emode |= EISA_DMA_16;
641*0Sstevel@tonic-gate break;
642*0Sstevel@tonic-gate }
643*0Sstevel@tonic-gate }
644*0Sstevel@tonic-gate emode |= (dmaereqp->der_cycles & 3) << 4;
645*0Sstevel@tonic-gate outb(chan_addr[chnl].emode_reg, emode);
646*0Sstevel@tonic-gate
647*0Sstevel@tonic-gate dprintf(("d37A_set_mode: chnl=%d em_reg=0x%x emode=0x%x\n",
648*0Sstevel@tonic-gate chnl, chan_addr[chnl].emode_reg, emode));
649*0Sstevel@tonic-gate #endif /* EISA_EXT_MODE */
650*0Sstevel@tonic-gate return (DDI_SUCCESS);
651*0Sstevel@tonic-gate }
652*0Sstevel@tonic-gate
653*0Sstevel@tonic-gate
654*0Sstevel@tonic-gate /*
655*0Sstevel@tonic-gate * routine: d37A_write_addr()
656*0Sstevel@tonic-gate * purpose: write the 24- or 32-bit physical address into the Base Address
657*0Sstevel@tonic-gate * Register for the indicated channel.
658*0Sstevel@tonic-gate * caller: d37A_prog_chan(), d37A_dma_swsetup().
659*0Sstevel@tonic-gate * calls: d37A macros
660*0Sstevel@tonic-gate */
661*0Sstevel@tonic-gate
662*0Sstevel@tonic-gate static int
d37A_write_addr(ulong_t paddress,int chnl)663*0Sstevel@tonic-gate d37A_write_addr(ulong_t paddress, int chnl)
664*0Sstevel@tonic-gate {
665*0Sstevel@tonic-gate uchar_t *adr_byte;
666*0Sstevel@tonic-gate
667*0Sstevel@tonic-gate dprintf(("d37A_write_addr: chnl=%d address=%lx\n", chnl, paddress));
668*0Sstevel@tonic-gate
669*0Sstevel@tonic-gate switch (d37A_chnl_path[chnl]) {
670*0Sstevel@tonic-gate case DMAE_PATH_8:
671*0Sstevel@tonic-gate case DMAE_PATH_16B:
672*0Sstevel@tonic-gate case DMAE_PATH_32:
673*0Sstevel@tonic-gate /*
674*0Sstevel@tonic-gate * program DMA controller with byte address
675*0Sstevel@tonic-gate */
676*0Sstevel@tonic-gate break;
677*0Sstevel@tonic-gate
678*0Sstevel@tonic-gate case DMAE_PATH_16:
679*0Sstevel@tonic-gate /*
680*0Sstevel@tonic-gate * convert byte address to shifted word address
681*0Sstevel@tonic-gate */
682*0Sstevel@tonic-gate paddress = (paddress & ~0x1ffff) | ((paddress & 0x1ffff) >> 1);
683*0Sstevel@tonic-gate break;
684*0Sstevel@tonic-gate
685*0Sstevel@tonic-gate default:
686*0Sstevel@tonic-gate return (DDI_FAILURE);
687*0Sstevel@tonic-gate }
688*0Sstevel@tonic-gate kpreempt_disable(); /* don't preempt thread while using flip-flop */
689*0Sstevel@tonic-gate outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
690*0Sstevel@tonic-gate
691*0Sstevel@tonic-gate adr_byte = (uchar_t *)&paddress;
692*0Sstevel@tonic-gate outb(chan_addr[chnl].addr_reg, adr_byte[0]);
693*0Sstevel@tonic-gate outb(chan_addr[chnl].addr_reg, adr_byte[1]);
694*0Sstevel@tonic-gate outb(chan_addr[chnl].page_reg, adr_byte[2]);
695*0Sstevel@tonic-gate #ifdef ADDR_32
696*0Sstevel@tonic-gate outb(chan_addr[chnl].hpage_reg, adr_byte[3]);
697*0Sstevel@tonic-gate #endif /* ADDR_32 */
698*0Sstevel@tonic-gate
699*0Sstevel@tonic-gate kpreempt_enable();
700*0Sstevel@tonic-gate return (DDI_SUCCESS);
701*0Sstevel@tonic-gate }
702*0Sstevel@tonic-gate
703*0Sstevel@tonic-gate
704*0Sstevel@tonic-gate /*
705*0Sstevel@tonic-gate * routine: d37A_read_addr()
706*0Sstevel@tonic-gate * purpose: read the 24- or 32-bit physical address from the Current Address
707*0Sstevel@tonic-gate * Register for the indicated channel.
708*0Sstevel@tonic-gate * caller: d37A_get_chan_stat().
709*0Sstevel@tonic-gate * calls: d37A macros
710*0Sstevel@tonic-gate */
711*0Sstevel@tonic-gate
712*0Sstevel@tonic-gate static ulong_t
d37A_read_addr(int chnl)713*0Sstevel@tonic-gate d37A_read_addr(int chnl)
714*0Sstevel@tonic-gate {
715*0Sstevel@tonic-gate ulong_t paddress = 0;
716*0Sstevel@tonic-gate uchar_t *adr_byte;
717*0Sstevel@tonic-gate
718*0Sstevel@tonic-gate kpreempt_disable(); /* don't preempt thread while using flip-flop */
719*0Sstevel@tonic-gate adr_byte = (uchar_t *)&paddress;
720*0Sstevel@tonic-gate outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
721*0Sstevel@tonic-gate
722*0Sstevel@tonic-gate adr_byte[0] = inb(chan_addr[chnl].addr_reg);
723*0Sstevel@tonic-gate adr_byte[1] = inb(chan_addr[chnl].addr_reg);
724*0Sstevel@tonic-gate adr_byte[2] = inb(chan_addr[chnl].page_reg);
725*0Sstevel@tonic-gate #ifdef ADDR_32
726*0Sstevel@tonic-gate adr_byte[3] = inb(chan_addr[chnl].hpage_reg);
727*0Sstevel@tonic-gate #endif /* ADDR_32 */
728*0Sstevel@tonic-gate
729*0Sstevel@tonic-gate kpreempt_enable();
730*0Sstevel@tonic-gate
731*0Sstevel@tonic-gate switch (d37A_chnl_path[chnl]) {
732*0Sstevel@tonic-gate case DMAE_PATH_8:
733*0Sstevel@tonic-gate case DMAE_PATH_16B:
734*0Sstevel@tonic-gate case DMAE_PATH_32:
735*0Sstevel@tonic-gate /*
736*0Sstevel@tonic-gate * return with byte address
737*0Sstevel@tonic-gate */
738*0Sstevel@tonic-gate break;
739*0Sstevel@tonic-gate
740*0Sstevel@tonic-gate case DMAE_PATH_16:
741*0Sstevel@tonic-gate /*
742*0Sstevel@tonic-gate * convert shifted word address to byte address
743*0Sstevel@tonic-gate */
744*0Sstevel@tonic-gate paddress = (paddress & ~0x1ffff) | ((paddress & 0x0ffff) << 1);
745*0Sstevel@tonic-gate break;
746*0Sstevel@tonic-gate
747*0Sstevel@tonic-gate default:
748*0Sstevel@tonic-gate return ((ulong_t)DDI_FAILURE);
749*0Sstevel@tonic-gate }
750*0Sstevel@tonic-gate
751*0Sstevel@tonic-gate dprintf(("d37A_read_addr: chnl=%d address=%lx.\n", chnl, paddress));
752*0Sstevel@tonic-gate return (paddress);
753*0Sstevel@tonic-gate }
754*0Sstevel@tonic-gate
755*0Sstevel@tonic-gate
756*0Sstevel@tonic-gate /*
757*0Sstevel@tonic-gate * routine: d37A_write_count()
758*0Sstevel@tonic-gate * purpose: write the 16- or 24-bit count into the Base Count Register for
759*0Sstevel@tonic-gate * the indicated channel.
760*0Sstevel@tonic-gate * caller: d37A_prog_chan(), d37A_dma_swsetup()
761*0Sstevel@tonic-gate * calls: d37A macros
762*0Sstevel@tonic-gate */
763*0Sstevel@tonic-gate
764*0Sstevel@tonic-gate static int
d37A_write_count(long count,int chnl)765*0Sstevel@tonic-gate d37A_write_count(long count, int chnl)
766*0Sstevel@tonic-gate {
767*0Sstevel@tonic-gate uchar_t *count_byte;
768*0Sstevel@tonic-gate
769*0Sstevel@tonic-gate dprintf(("d37A_write_count: chnl=%d count=0x%lx\n", chnl, count));
770*0Sstevel@tonic-gate
771*0Sstevel@tonic-gate switch (d37A_chnl_path[chnl]) {
772*0Sstevel@tonic-gate case DMAE_PATH_16:
773*0Sstevel@tonic-gate /*
774*0Sstevel@tonic-gate * Convert byte count to word count
775*0Sstevel@tonic-gate */
776*0Sstevel@tonic-gate count >>= 1;
777*0Sstevel@tonic-gate /* FALLTHROUGH */
778*0Sstevel@tonic-gate case DMAE_PATH_8:
779*0Sstevel@tonic-gate case DMAE_PATH_16B:
780*0Sstevel@tonic-gate case DMAE_PATH_32:
781*0Sstevel@tonic-gate --count;
782*0Sstevel@tonic-gate break;
783*0Sstevel@tonic-gate
784*0Sstevel@tonic-gate default:
785*0Sstevel@tonic-gate return (DDI_FAILURE);
786*0Sstevel@tonic-gate }
787*0Sstevel@tonic-gate
788*0Sstevel@tonic-gate kpreempt_disable(); /* don't preempt thread while using flip-flop */
789*0Sstevel@tonic-gate outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
790*0Sstevel@tonic-gate
791*0Sstevel@tonic-gate count_byte = (uchar_t *)&count;
792*0Sstevel@tonic-gate outb(chan_addr[chnl].cnt_reg, count_byte[0]);
793*0Sstevel@tonic-gate outb(chan_addr[chnl].cnt_reg, count_byte[1]);
794*0Sstevel@tonic-gate #ifdef COUNT_24
795*0Sstevel@tonic-gate outb(chan_addr[chnl].hcnt_reg, count_byte[2]);
796*0Sstevel@tonic-gate #endif /* COUNT_24 */
797*0Sstevel@tonic-gate
798*0Sstevel@tonic-gate kpreempt_enable();
799*0Sstevel@tonic-gate return (DDI_SUCCESS);
800*0Sstevel@tonic-gate }
801*0Sstevel@tonic-gate
802*0Sstevel@tonic-gate
803*0Sstevel@tonic-gate /*
804*0Sstevel@tonic-gate * routine: d37A_read_count()
805*0Sstevel@tonic-gate * purpose: read the 16- or 24-bit count from the Current Count Register for
806*0Sstevel@tonic-gate * the indicated channel
807*0Sstevel@tonic-gate * caller: d37A_get_chan_stat()
808*0Sstevel@tonic-gate * calls: d37A macros
809*0Sstevel@tonic-gate */
810*0Sstevel@tonic-gate
811*0Sstevel@tonic-gate static long
d37A_read_count(int chnl)812*0Sstevel@tonic-gate d37A_read_count(int chnl)
813*0Sstevel@tonic-gate {
814*0Sstevel@tonic-gate long count = 0;
815*0Sstevel@tonic-gate uchar_t *count_byte;
816*0Sstevel@tonic-gate
817*0Sstevel@tonic-gate kpreempt_disable(); /* don't preempt thread while using flip-flop */
818*0Sstevel@tonic-gate count_byte = (uchar_t *)&count;
819*0Sstevel@tonic-gate outb(chan_addr[chnl].ff_reg, 0); /* set flipflop */
820*0Sstevel@tonic-gate
821*0Sstevel@tonic-gate count_byte[0] = inb(chan_addr[chnl].cnt_reg);
822*0Sstevel@tonic-gate count_byte[1] = inb(chan_addr[chnl].cnt_reg);
823*0Sstevel@tonic-gate #ifdef COUNT_24
824*0Sstevel@tonic-gate count_byte[2] = inb(chan_addr[chnl].hcnt_reg);
825*0Sstevel@tonic-gate #endif /* COUNT_24 */
826*0Sstevel@tonic-gate
827*0Sstevel@tonic-gate #ifdef COUNT_24
828*0Sstevel@tonic-gate if ((ulong_t)count == 0xffffff)
829*0Sstevel@tonic-gate #else /* !COUNT_24 */
830*0Sstevel@tonic-gate if ((ulong_t)count == 0xffff)
831*0Sstevel@tonic-gate #endif /* !COUNT_24 */
832*0Sstevel@tonic-gate count = -1;
833*0Sstevel@tonic-gate
834*0Sstevel@tonic-gate kpreempt_enable();
835*0Sstevel@tonic-gate
836*0Sstevel@tonic-gate switch (d37A_chnl_path[chnl]) {
837*0Sstevel@tonic-gate case DMAE_PATH_8:
838*0Sstevel@tonic-gate case DMAE_PATH_16B:
839*0Sstevel@tonic-gate case DMAE_PATH_32:
840*0Sstevel@tonic-gate ++count;
841*0Sstevel@tonic-gate break;
842*0Sstevel@tonic-gate
843*0Sstevel@tonic-gate case DMAE_PATH_16:
844*0Sstevel@tonic-gate /*
845*0Sstevel@tonic-gate * Convert incremented word count to byte count
846*0Sstevel@tonic-gate */
847*0Sstevel@tonic-gate count = (count + 1) << 1;
848*0Sstevel@tonic-gate break;
849*0Sstevel@tonic-gate }
850*0Sstevel@tonic-gate dprintf(("d37A_read_count: chnl=%d count=0x%lx\n", chnl, count));
851*0Sstevel@tonic-gate return (count);
852*0Sstevel@tonic-gate }
853