xref: /onnv-gate/usr/src/uts/common/io/hxge/hxge_common_impl.h (revision 7584:07b5a7770d5b)
16349Sqs148142 /*
26349Sqs148142  * CDDL HEADER START
36349Sqs148142  *
46349Sqs148142  * The contents of this file are subject to the terms of the
56349Sqs148142  * Common Development and Distribution License (the "License").
66349Sqs148142  * You may not use this file except in compliance with the License.
76349Sqs148142  *
86349Sqs148142  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
96349Sqs148142  * or http://www.opensolaris.org/os/licensing.
106349Sqs148142  * See the License for the specific language governing permissions
116349Sqs148142  * and limitations under the License.
126349Sqs148142  *
136349Sqs148142  * When distributing Covered Code, include this CDDL HEADER in each
146349Sqs148142  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
156349Sqs148142  * If applicable, add the following below this CDDL HEADER, with the
166349Sqs148142  * fields enclosed by brackets "[]" replaced with your own identifying
176349Sqs148142  * information: Portions Copyright [yyyy] [name of copyright owner]
186349Sqs148142  *
196349Sqs148142  * CDDL HEADER END
206349Sqs148142  */
216349Sqs148142 /*
226349Sqs148142  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
236349Sqs148142  * Use is subject to license terms.
246349Sqs148142  */
256349Sqs148142 
266349Sqs148142 #ifndef	_SYS_HXGE_HXGE_COMMON_IMPL_H
276349Sqs148142 #define	_SYS_HXGE_HXGE_COMMON_IMPL_H
286349Sqs148142 
296349Sqs148142 #ifdef	__cplusplus
306349Sqs148142 extern "C" {
316349Sqs148142 #endif
326349Sqs148142 
336349Sqs148142 #define	HPI_REGH(hpi_handle)		(hpi_handle.regh)
346349Sqs148142 #define	HPI_REGP(hpi_handle)		(hpi_handle.regp)
356349Sqs148142 
366349Sqs148142 #define		NO_DEBUG	0x0000000000000000ULL
376349Sqs148142 #define		RX_CTL		0x0000000000000001ULL
386349Sqs148142 #define		TX_CTL		0x0000000000000002ULL
396349Sqs148142 #define		OBP_CTL		0x0000000000000004ULL
406349Sqs148142 #define		VPD_CTL		0x0000000000000008ULL
416349Sqs148142 #define		DDI_CTL		0x0000000000000010ULL
426349Sqs148142 #define		MEM_CTL		0x0000000000000020ULL
436349Sqs148142 #define		IOC_CTL		0x0000000000000040ULL
446349Sqs148142 #define		MOD_CTL		0x0000000000000080ULL
456349Sqs148142 #define		DMA_CTL		0x0000000000000100ULL
466349Sqs148142 #define		STR_CTL		0x0000000000000200ULL
476349Sqs148142 #define		INT_CTL		0x0000000000000400ULL
486349Sqs148142 #define		SYSERR_CTL	0x0000000000000800ULL
496349Sqs148142 #define		KST_CTL		0x0000000000001000ULL
506349Sqs148142 #define		FCRAM_CTL	0x0000000000002000ULL
516349Sqs148142 #define		MAC_CTL		0x0000000000004000ULL
526349Sqs148142 #define		DMA2_CTL	0x0000000000008000ULL
536349Sqs148142 #define		RX2_CTL		0x0000000000010000ULL
546349Sqs148142 #define		TX2_CTL		0x0000000000020000ULL
556349Sqs148142 #define		MEM2_CTL	0x0000000000040000ULL
566349Sqs148142 #define		MEM3_CTL	0x0000000000080000ULL
576349Sqs148142 #define		NEMO_CTL	0x0000000000100000ULL
586349Sqs148142 #define		NDD_CTL		0x0000000000200000ULL
596349Sqs148142 #define		NDD2_CTL	0x0000000000400000ULL
606349Sqs148142 #define		PFC_CTL		0x0000000000800000ULL
616349Sqs148142 #define		CFG_CTL		0x0000000001000000ULL
626349Sqs148142 #define		CFG2_CTL	0x0000000002000000ULL
636349Sqs148142 #define		VIR_CTL		0x0000000004000000ULL
646349Sqs148142 #define		VIR2_CTL	0x0000000008000000ULL
656349Sqs148142 #define		HXGE_NOTE	0x0000000010000000ULL
666349Sqs148142 #define		HXGE_ERR_CTL	0x0000000020000000ULL
676349Sqs148142 #define		MAC_INT_CTL	0x0000000040000000ULL
686349Sqs148142 #define		RX_INT_CTL	0x0000000080000000ULL
696349Sqs148142 #define		TX_ERR_CTL	0x0000000100000000ULL
706349Sqs148142 #define		DDI_INT_CTL	0x0000000200000000ULL
71*7584SQiyan.Sun@Sun.COM #define		DLADM_CTL	0x0000000400000000ULL
726349Sqs148142 #define		DUMP_ALWAYS	0x2000000000000000ULL
736349Sqs148142 
746349Sqs148142 /* HPI Debug and Error defines */
756349Sqs148142 #define		HPI_RDC_CTL	0x0000000000000001ULL
766349Sqs148142 #define		HPI_TDC_CTL	0x0000000000000002ULL
776349Sqs148142 #define		HPI_VMAC_CTL	0x0000000000000004ULL
786349Sqs148142 #define		HPI_PFC_CTL	0x0000000000000008ULL
796349Sqs148142 #define		HPI_VIR_CTL	0x0000000000000010ULL
806349Sqs148142 #define		HPI_PIO_CTL	0x0000000000000020ULL
816349Sqs148142 #define		HPI_VIO_CTL	0x0000000000000040ULL
826349Sqs148142 #define		HPI_REG_CTL	0x0000000000000080ULL
836349Sqs148142 #define		HPI_ERR_CTL	0x0000000000000100ULL
846349Sqs148142 
856349Sqs148142 #include <sys/types.h>
866349Sqs148142 #include <sys/ddi.h>
876349Sqs148142 #include <sys/sunddi.h>
886349Sqs148142 #include <sys/dditypes.h>
896349Sqs148142 #include <sys/ethernet.h>
906349Sqs148142 
916349Sqs148142 #ifdef HXGE_DEBUG
926349Sqs148142 #define	HXGE_DEBUG_MSG(params) hxge_debug_msg params
936349Sqs148142 #else
946349Sqs148142 #define	HXGE_DEBUG_MSG(params)
956349Sqs148142 #endif
966349Sqs148142 
976349Sqs148142 #define	HXGE_ERROR_MSG(params)	hxge_debug_msg params
986349Sqs148142 
996349Sqs148142 typedef kmutex_t			hxge_os_mutex_t;
1006349Sqs148142 typedef	krwlock_t			hxge_os_rwlock_t;
1016349Sqs148142 
1026349Sqs148142 typedef	dev_info_t			hxge_dev_info_t;
1036349Sqs148142 typedef	ddi_iblock_cookie_t 		hxge_intr_cookie_t;
1046349Sqs148142 
1056349Sqs148142 typedef ddi_acc_handle_t		hxge_os_acc_handle_t;
1066349Sqs148142 typedef	hxge_os_acc_handle_t		hpi_reg_handle_t;
1076864Sqs148142 #if defined(__i386)
1086864Sqs148142 typedef	uint32_t			hpi_reg_ptr_t;
1096864Sqs148142 #else
1106349Sqs148142 typedef	uint64_t			hpi_reg_ptr_t;
1116864Sqs148142 #endif
1126349Sqs148142 
1136349Sqs148142 typedef ddi_dma_handle_t		hxge_os_dma_handle_t;
1146349Sqs148142 typedef struct _hxge_dma_common_t	hxge_os_dma_common_t;
1156349Sqs148142 typedef struct _hxge_block_mv_t		hxge_os_block_mv_t;
1166349Sqs148142 typedef frtn_t				hxge_os_frtn_t;
1176349Sqs148142 
1186349Sqs148142 #define	HXGE_MUTEX_DRIVER		MUTEX_DRIVER
1196349Sqs148142 #define	MUTEX_INIT(lock, name, type, arg)	\
1206349Sqs148142 					mutex_init(lock, name, type, arg)
1216349Sqs148142 #define	MUTEX_ENTER(lock)		mutex_enter(lock)
1226349Sqs148142 #define	MUTEX_TRY_ENTER(lock)		mutex_tryenter(lock)
1236349Sqs148142 #define	MUTEX_EXIT(lock)		mutex_exit(lock)
1246349Sqs148142 #define	MUTEX_DESTROY(lock)		mutex_destroy(lock)
1256349Sqs148142 
1266349Sqs148142 #define	RW_INIT(lock, name, type, arg)	rw_init(lock, name, type, arg)
1276349Sqs148142 #define	RW_ENTER_WRITER(lock)		rw_enter(lock, RW_WRITER)
1286349Sqs148142 #define	RW_ENTER_READER(lock)		rw_enter(lock, RW_READER)
1296349Sqs148142 #define	RW_TRY_ENTER(lock, type)	rw_tryenter(lock, type)
1306349Sqs148142 #define	RW_EXIT(lock)			rw_exit(lock)
1316349Sqs148142 #define	RW_DESTROY(lock)		rw_destroy(lock)
1326349Sqs148142 #define	KMEM_ALLOC(size, flag)		kmem_alloc(size, flag)
1336349Sqs148142 #define	KMEM_ZALLOC(size, flag)		kmem_zalloc(size, flag)
1346349Sqs148142 #define	KMEM_FREE(buf, size)		kmem_free(buf, size)
1356349Sqs148142 
1366349Sqs148142 #define	HXGE_DELAY(microseconds)	 (drv_usecwait(microseconds))
1376349Sqs148142 
1386864Sqs148142 /*
1396864Sqs148142  * HXGE_HPI_PIO_READ32 and HXGE_HPI_PIO_READ64 should not be called directly
1406864Sqs148142  * on 32 bit platforms
1416864Sqs148142  */
1426349Sqs148142 #define	HXGE_HPI_PIO_READ32(hpi_handle, offset)		\
1436349Sqs148142 	(ddi_get32(HPI_REGH(hpi_handle),		\
1446349Sqs148142 	(uint32_t *)(HPI_REGP(hpi_handle) + offset)))
1456349Sqs148142 
1466864Sqs148142 #if defined(__i386)
1476864Sqs148142 #define	HXGE_HPI_PIO_READ64(hpi_handle, offset)		\
1486864Sqs148142 	(ddi_get64(HPI_REGH(hpi_handle),		\
1496864Sqs148142 	(uint64_t *)(HPI_REGP(hpi_handle) + (uint32_t)offset)))
1506864Sqs148142 #else
1516349Sqs148142 #define	HXGE_HPI_PIO_READ64(hpi_handle, offset)		\
1526349Sqs148142 	(ddi_get64(HPI_REGH(hpi_handle),		\
1536349Sqs148142 	(uint64_t *)(HPI_REGP(hpi_handle) + offset)))
1546864Sqs148142 #endif
1556349Sqs148142 
1566864Sqs148142 #if defined(__i386)
1576349Sqs148142 
1586864Sqs148142 #define	HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) {	\
1596864Sqs148142 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1606864Sqs148142 	ddi_put32(HPI_REGH(hpi_handle),				\
1616864Sqs148142 	    (uint32_t *)(HPI_REGP(hpi_handle) +			\
1626864Sqs148142 	    (uint32_t)offset), data);				\
1636864Sqs148142 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1646864Sqs148142 }
1656864Sqs148142 #define	HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) {	\
1666864Sqs148142 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1676864Sqs148142 	ddi_put64(HPI_REGH(hpi_handle),				\
1686864Sqs148142 	    (uint64_t *)(HPI_REGP(hpi_handle) +			\
1696864Sqs148142 	    (uint32_t)offset), data);				\
1706864Sqs148142 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1716349Sqs148142 }
1726864Sqs148142 #define	HXGE_MEM_PIO_READ64(hpi_handle, val_p) {		\
1736864Sqs148142 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1746864Sqs148142 	*(val_p) = ddi_get64(HPI_REGH(hpi_handle),		\
1756864Sqs148142 	    (uint64_t *)HPI_REGP(hpi_handle));			\
1766864Sqs148142 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1776864Sqs148142 }
1786864Sqs148142 #define	HXGE_MEM_PIO_WRITE64(hpi_handle, data) {		\
1796864Sqs148142 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1806864Sqs148142 	ddi_put64(HPI_REGH(hpi_handle),				\
1816864Sqs148142 	    (uint64_t *)HPI_REGP(hpi_handle), data);		\
1826864Sqs148142 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
1836349Sqs148142 }
1846864Sqs148142 #define	HXGE_REG_RD64(handle, offset, val_p) {			\
1856864Sqs148142 	MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock);	\
1866864Sqs148142 	*(val_p) = HXGE_HPI_PIO_READ64(handle, offset);		\
1876864Sqs148142 	MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock);	\
1886349Sqs148142 }
1896864Sqs148142 #define	HXGE_REG_RD32(handle, offset, val_p) {			\
1906864Sqs148142 	MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock);	\
1916864Sqs148142 	*(val_p) = HXGE_HPI_PIO_READ32(handle, offset);		\
1926864Sqs148142 	MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock);	\
1936349Sqs148142 }
1946864Sqs148142 
1956349Sqs148142 #else
1966349Sqs148142 
1976864Sqs148142 #define	HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data)		\
1986864Sqs148142 	(ddi_put32(HPI_REGH(hpi_handle),			\
1996864Sqs148142 	(uint32_t *)(HPI_REGP(hpi_handle) + offset), data))
2006864Sqs148142 #define	HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data)		\
2016864Sqs148142 	(ddi_put64(HPI_REGH(hpi_handle),			\
2026864Sqs148142 	(uint64_t *)(HPI_REGP(hpi_handle) + offset), data))
2036864Sqs148142 #define	HXGE_MEM_PIO_READ64(hpi_handle, val_p) {		\
2046864Sqs148142 	*(val_p) = ddi_get64(HPI_REGH(hpi_handle),		\
2056864Sqs148142 		(uint64_t *)HPI_REGP(hpi_handle));		\
2066349Sqs148142 }
2076864Sqs148142 #define	HXGE_MEM_PIO_WRITE64(hpi_handle, data)			\
2086864Sqs148142 	(ddi_put64(HPI_REGH(hpi_handle),			\
2096864Sqs148142 		(uint64_t *)HPI_REGP(hpi_handle), data))
2106864Sqs148142 #define	HXGE_REG_RD64(handle, offset, val_p) {			\
2116864Sqs148142 	*(val_p) = HXGE_HPI_PIO_READ64(handle, offset);		\
2126349Sqs148142 }
2136864Sqs148142 #define	HXGE_REG_RD32(handle, offset, val_p) {			\
2146864Sqs148142 	*(val_p) = HXGE_HPI_PIO_READ32(handle, offset);		\
2156864Sqs148142 }
2166864Sqs148142 
2176864Sqs148142 #endif
2186864Sqs148142 
2196864Sqs148142 #define	HXGE_REG_WR64(handle, offset, val) {			\
2206864Sqs148142 	HXGE_HPI_PIO_WRITE64(handle, (offset), (val));		\
2216349Sqs148142 }
2226864Sqs148142 #define	HXGE_REG_WR32(handle, offset, val) {			\
2236864Sqs148142 	HXGE_HPI_PIO_WRITE32(handle, (offset), (val));		\
2246349Sqs148142 }
2256864Sqs148142 
2266864Sqs148142 #define	FM_SERVICE_RESTORED(hxgep)				\
2276864Sqs148142 	if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities))		\
2286864Sqs148142 		ddi_fm_service_impact(hxgep->dip, DDI_SERVICE_RESTORED)
2296864Sqs148142 #define	HXGE_FM_REPORT_ERROR(hxgep, chan, ereport_id)		\
2306864Sqs148142 	if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities))		\
2316864Sqs148142 		hxge_fm_report_error(hxgep, chan, ereport_id)
2326349Sqs148142 
2336349Sqs148142 #ifdef	__cplusplus
2346349Sqs148142 }
2356349Sqs148142 #endif
2366349Sqs148142 
2376349Sqs148142 #endif	/* _SYS_HXGE_HXGE_COMMON_IMPL_H */
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