xref: /onnv-gate/usr/src/uts/common/io/hxge/hpi_vir.c (revision 6864:50c1b31ccb24)
16349Sqs148142 /*
26349Sqs148142  * CDDL HEADER START
36349Sqs148142  *
46349Sqs148142  * The contents of this file are subject to the terms of the
56349Sqs148142  * Common Development and Distribution License (the "License").
66349Sqs148142  * You may not use this file except in compliance with the License.
76349Sqs148142  *
86349Sqs148142  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
96349Sqs148142  * or http://www.opensolaris.org/os/licensing.
106349Sqs148142  * See the License for the specific language governing permissions
116349Sqs148142  * and limitations under the License.
126349Sqs148142  *
136349Sqs148142  * When distributing Covered Code, include this CDDL HEADER in each
146349Sqs148142  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
156349Sqs148142  * If applicable, add the following below this CDDL HEADER, with the
166349Sqs148142  * fields enclosed by brackets "[]" replaced with your own identifying
176349Sqs148142  * information: Portions Copyright [yyyy] [name of copyright owner]
186349Sqs148142  *
196349Sqs148142  * CDDL HEADER END
206349Sqs148142  */
216349Sqs148142 /*
226349Sqs148142  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
236349Sqs148142  * Use is subject to license terms.
246349Sqs148142  */
256349Sqs148142 
266349Sqs148142 #pragma ident	"%Z%%M%	%I%	%E% SMI"
276349Sqs148142 
286349Sqs148142 #include <hpi_vir.h>
296349Sqs148142 #include <hxge_defs.h>
30*6864Sqs148142 #include <hxge_impl.h>
316349Sqs148142 
326349Sqs148142 /*
336349Sqs148142  * Set up a logical group number that a logical device belongs to.
346349Sqs148142  */
356349Sqs148142 hpi_status_t
hpi_fzc_ldg_num_set(hpi_handle_t handle,uint8_t ld,uint8_t ldg)366349Sqs148142 hpi_fzc_ldg_num_set(hpi_handle_t handle, uint8_t ld, uint8_t ldg)
376349Sqs148142 {
386349Sqs148142 	ld_grp_ctrl_t	gnum;
396349Sqs148142 
406349Sqs148142 	if (!LD_VALID(ld)) {
416349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
426349Sqs148142 		    " hpi_fzc_ldg_num_set ld <0x%x>", ld));
436349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld));
446349Sqs148142 	}
456349Sqs148142 
466349Sqs148142 	if (!LDG_VALID(ldg)) {
476349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
486349Sqs148142 		    " hpi_fzc_ldg_num_set ldg <0x%x>", ldg));
496349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ld));
506349Sqs148142 	}
516349Sqs148142 
526349Sqs148142 	gnum.value = 0;
536349Sqs148142 	gnum.bits.num = ldg;
546349Sqs148142 
556349Sqs148142 	HXGE_REG_WR32(handle, LD_GRP_CTRL + LD_NUM_OFFSET(ld), gnum.value);
566349Sqs148142 
576349Sqs148142 	return (HPI_SUCCESS);
586349Sqs148142 }
596349Sqs148142 
606349Sqs148142 /*
616349Sqs148142  * Get device state vectors.
626349Sqs148142  */
636349Sqs148142 hpi_status_t
hpi_ldsv_ldfs_get(hpi_handle_t handle,uint8_t ldg,uint32_t * vector0_p,uint32_t * vector1_p)646349Sqs148142 hpi_ldsv_ldfs_get(hpi_handle_t handle, uint8_t ldg, uint32_t *vector0_p,
656349Sqs148142     uint32_t *vector1_p)
666349Sqs148142 {
676349Sqs148142 	int	status;
686349Sqs148142 
696349Sqs148142 	if ((status = hpi_ldsv_get(handle, ldg, VECTOR0, vector0_p))) {
706349Sqs148142 		return (status);
716349Sqs148142 	}
726349Sqs148142 	if ((status = hpi_ldsv_get(handle, ldg, VECTOR1, vector1_p))) {
736349Sqs148142 		return (status);
746349Sqs148142 	}
756349Sqs148142 
766349Sqs148142 	return (HPI_SUCCESS);
776349Sqs148142 }
786349Sqs148142 
796349Sqs148142 /*
806349Sqs148142  * Get device state vectors.
816349Sqs148142  */
826349Sqs148142 hpi_status_t
hpi_ldsv_get(hpi_handle_t handle,uint8_t ldg,ldsv_type_t vector,uint32_t * ldf_p)836349Sqs148142 hpi_ldsv_get(hpi_handle_t handle, uint8_t ldg, ldsv_type_t vector,
846349Sqs148142     uint32_t *ldf_p)
856349Sqs148142 {
866349Sqs148142 	uint32_t	offset;
876349Sqs148142 
886349Sqs148142 	if (!LDG_VALID(ldg)) {
896349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
906349Sqs148142 		    " hpi_ldsv_get Invalid Input ldg <0x%x>", ldg));
916349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg));
926349Sqs148142 	}
936349Sqs148142 
946349Sqs148142 	switch (vector) {
956349Sqs148142 	case VECTOR0:
966349Sqs148142 		offset = LDSV0 + LDSV_OFFSET(ldg);
976349Sqs148142 		break;
986349Sqs148142 
996349Sqs148142 	case VECTOR1:
1006349Sqs148142 		offset = LDSV1 + LDSV_OFFSET(ldg);
1016349Sqs148142 		break;
1026349Sqs148142 
1036349Sqs148142 	default:
1046349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
1056349Sqs148142 		    " hpi_ldsv_get Invalid Input: ldsv type <0x%x>", vector));
1066349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LDSV_INVALID(vector));
1076349Sqs148142 	}
1086349Sqs148142 
1096349Sqs148142 	HXGE_REG_RD32(handle, offset, ldf_p);
1106349Sqs148142 
1116349Sqs148142 	return (HPI_SUCCESS);
1126349Sqs148142 }
1136349Sqs148142 
1146349Sqs148142 /*
1156349Sqs148142  * Set the mask bits for both ldf0 and ldf1.
1166349Sqs148142  */
1176349Sqs148142 hpi_status_t
hpi_intr_mask_set(hpi_handle_t handle,uint8_t ld,uint8_t ldf_mask)1186349Sqs148142 hpi_intr_mask_set(hpi_handle_t handle, uint8_t ld, uint8_t ldf_mask)
1196349Sqs148142 {
1206349Sqs148142 	uint32_t	offset;
1216349Sqs148142 
1226349Sqs148142 	if (!LD_VALID(ld)) {
1236349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
1246349Sqs148142 		    " hpi_intr_mask_set ld", ld));
1256349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LD_INVALID(ld));
1266349Sqs148142 	}
1276349Sqs148142 
1286349Sqs148142 	ldf_mask &= LD_IM_MASK;
1296349Sqs148142 	offset = LDSV_OFFSET_MASK(ld);
1306349Sqs148142 
1316349Sqs148142 	HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL,
1326349Sqs148142 	    "hpi_intr_mask_set: ld %d offset 0x%0x mask 0x%x",
1336349Sqs148142 	    ld, offset, ldf_mask));
1346349Sqs148142 
1356349Sqs148142 	HXGE_REG_WR32(handle, offset, (uint32_t)ldf_mask);
1366349Sqs148142 
1376349Sqs148142 	return (HPI_SUCCESS);
1386349Sqs148142 }
1396349Sqs148142 
1406349Sqs148142 /*
1416349Sqs148142  * Set interrupt timer and arm bit.
1426349Sqs148142  */
1436349Sqs148142 hpi_status_t
hpi_intr_ldg_mgmt_set(hpi_handle_t handle,uint8_t ldg,boolean_t arm,uint8_t timer)1446349Sqs148142 hpi_intr_ldg_mgmt_set(hpi_handle_t handle, uint8_t ldg, boolean_t arm,
1456349Sqs148142     uint8_t timer)
1466349Sqs148142 {
1476349Sqs148142 	ld_intr_mgmt_t	mgm;
1486349Sqs148142 
1496349Sqs148142 	if (!LDG_VALID(ldg)) {
1506349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
1516349Sqs148142 		    " hpi_intr_ldg_mgmt_set Invalid Input: ldg <0x%x>", ldg));
1526349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LDG_INVALID(ldg));
1536349Sqs148142 	}
1546349Sqs148142 
1556349Sqs148142 	if (!LD_INTTIMER_VALID(timer)) {
1566349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
1576349Sqs148142 		    " hpi_intr_ldg_mgmt_set Invalid Input"
1586349Sqs148142 		    " timer <0x%x>", timer));
1596349Sqs148142 		return (HPI_FAILURE | HPI_VIR_INTM_TM_INVALID(ldg));
1606349Sqs148142 	}
1616349Sqs148142 
1626349Sqs148142 	if (arm) {
1636349Sqs148142 		mgm.bits.arm = 1;
1646349Sqs148142 	} else {
1656349Sqs148142 		HXGE_REG_RD32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg),
1666349Sqs148142 		    &mgm.value);
1676349Sqs148142 	}
1686349Sqs148142 
1696349Sqs148142 	mgm.bits.timer = timer;
1706349Sqs148142 	HXGE_REG_WR32(handle, LD_INTR_MGMT + LDSV_OFFSET(ldg), mgm.value);
1716349Sqs148142 
1726349Sqs148142 	HPI_DEBUG_MSG((handle.function, HPI_VIR_CTL,
1736349Sqs148142 	    " hpi_intr_ldg_mgmt_set: ldg %d reg offset 0x%x",
1746349Sqs148142 	    ldg, LD_INTR_MGMT + LDSV_OFFSET(ldg)));
1756349Sqs148142 
1766349Sqs148142 	return (HPI_SUCCESS);
1776349Sqs148142 }
1786349Sqs148142 
1796349Sqs148142 /*
1806349Sqs148142  * Set the timer resolution.
1816349Sqs148142  */
1826349Sqs148142 hpi_status_t
hpi_fzc_ldg_timer_res_set(hpi_handle_t handle,uint32_t res)1836349Sqs148142 hpi_fzc_ldg_timer_res_set(hpi_handle_t handle, uint32_t res)
1846349Sqs148142 {
1856349Sqs148142 	ld_intr_tim_res_t	tm;
1866349Sqs148142 
1876349Sqs148142 	if (res > LDGTITMRES_RES_MASK) {
1886349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
1896349Sqs148142 		    " hpi_fzc_ldg_timer_res_set Invalid Input: res <0x%x>",
1906349Sqs148142 		    res));
1916349Sqs148142 		return (HPI_FAILURE | HPI_VIR_TM_RES_INVALID);
1926349Sqs148142 	}
1936349Sqs148142 
1946349Sqs148142 	tm.value = 0;
1956349Sqs148142 	tm.bits.res = res;
1966349Sqs148142 
1976349Sqs148142 	HXGE_REG_WR32(handle, LD_INTR_TIM_RES, tm.value);
1986349Sqs148142 
1996349Sqs148142 	return (HPI_SUCCESS);
2006349Sqs148142 }
2016349Sqs148142 
2026349Sqs148142 /*
2036349Sqs148142  * Set the system interrupt data.
2046349Sqs148142  */
2056349Sqs148142 hpi_status_t
hpi_fzc_sid_set(hpi_handle_t handle,fzc_sid_t sid)2066349Sqs148142 hpi_fzc_sid_set(hpi_handle_t handle, fzc_sid_t sid)
2076349Sqs148142 {
2086349Sqs148142 	sid_t	sd;
2096349Sqs148142 
2106349Sqs148142 	if (!LDG_VALID(sid.ldg)) {
2116349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
2126349Sqs148142 		    " hpi_fzc_sid_set Invalid Input: ldg <0x%x>", sid.ldg));
2136349Sqs148142 		return (HPI_FAILURE | HPI_VIR_LDG_INVALID(sid.ldg));
2146349Sqs148142 	}
2156349Sqs148142 
2166349Sqs148142 	if (!SID_VECTOR_VALID(sid.vector)) {
2176349Sqs148142 		HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
2186349Sqs148142 		    " hpi_fzc_sid_set Invalid Input: vector <0x%x>",
2196349Sqs148142 		    sid.vector));
2206349Sqs148142 
2216349Sqs148142 		return (HPI_FAILURE | HPI_VIR_SID_VEC_INVALID(sid.vector));
2226349Sqs148142 	}
2236349Sqs148142 
2246349Sqs148142 	sd.value = 0;
2256349Sqs148142 	sd.bits.data = sid.vector;
2266349Sqs148142 	HXGE_REG_WR32(handle,  SID + LDG_SID_OFFSET(sid.ldg), sd.value);
2276349Sqs148142 
2286349Sqs148142 	return (HPI_SUCCESS);
2296349Sqs148142 }
2306349Sqs148142 
2316349Sqs148142 /*
2326349Sqs148142  * Mask/Unmask the device error mask bits.
2336349Sqs148142  */
2346349Sqs148142 hpi_status_t
hpi_fzc_sys_err_mask_set(hpi_handle_t handle,boolean_t mask)2356349Sqs148142 hpi_fzc_sys_err_mask_set(hpi_handle_t handle, boolean_t mask)
2366349Sqs148142 {
2376349Sqs148142 	dev_err_mask_t	dev_mask;
2386349Sqs148142 
2396349Sqs148142 	dev_mask.value = 0;
2406349Sqs148142 	if (mask) {
2416349Sqs148142 		dev_mask.bits.tdc_mask0 = 1;
2426349Sqs148142 		dev_mask.bits.rdc_mask0 = 1;
2436349Sqs148142 		dev_mask.bits.vnm_pio_mask1 = 1;
2446349Sqs148142 		dev_mask.bits.tdc_mask1 = 1;
2456349Sqs148142 		dev_mask.bits.rdc_mask1 = 1;
2466349Sqs148142 		dev_mask.bits.peu_mask1 = 1;
2476349Sqs148142 	}
2486349Sqs148142 
2496349Sqs148142 	HXGE_REG_WR32(handle, DEV_ERR_MASK, dev_mask.value);
2506349Sqs148142 	return (HPI_SUCCESS);
2516349Sqs148142 }
2526349Sqs148142 
2536349Sqs148142 /*
2546349Sqs148142  * Get the system error stats.
2556349Sqs148142  */
2566349Sqs148142 hpi_status_t
hpi_fzc_sys_err_stat_get(hpi_handle_t handle,dev_err_stat_t * statp)2576349Sqs148142 hpi_fzc_sys_err_stat_get(hpi_handle_t handle, dev_err_stat_t *statp)
2586349Sqs148142 {
2596349Sqs148142 	HXGE_REG_RD32(handle,  DEV_ERR_STAT, &statp->value);
2606349Sqs148142 	return (HPI_SUCCESS);
2616349Sqs148142 }
262