1*6349Sqs148142 /* 2*6349Sqs148142 * CDDL HEADER START 3*6349Sqs148142 * 4*6349Sqs148142 * The contents of this file are subject to the terms of the 5*6349Sqs148142 * Common Development and Distribution License (the "License"). 6*6349Sqs148142 * You may not use this file except in compliance with the License. 7*6349Sqs148142 * 8*6349Sqs148142 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*6349Sqs148142 * or http://www.opensolaris.org/os/licensing. 10*6349Sqs148142 * See the License for the specific language governing permissions 11*6349Sqs148142 * and limitations under the License. 12*6349Sqs148142 * 13*6349Sqs148142 * When distributing Covered Code, include this CDDL HEADER in each 14*6349Sqs148142 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*6349Sqs148142 * If applicable, add the following below this CDDL HEADER, with the 16*6349Sqs148142 * fields enclosed by brackets "[]" replaced with your own identifying 17*6349Sqs148142 * information: Portions Copyright [yyyy] [name of copyright owner] 18*6349Sqs148142 * 19*6349Sqs148142 * CDDL HEADER END 20*6349Sqs148142 */ 21*6349Sqs148142 22*6349Sqs148142 /* 23*6349Sqs148142 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24*6349Sqs148142 * Use is subject to license terms. 25*6349Sqs148142 */ 26*6349Sqs148142 27*6349Sqs148142 #ifndef _HPI_PFC_H 28*6349Sqs148142 #define _HPI_PFC_H 29*6349Sqs148142 30*6349Sqs148142 #pragma ident "%Z%%M% %I% %E% SMI" 31*6349Sqs148142 32*6349Sqs148142 #ifdef __cplusplus 33*6349Sqs148142 extern "C" { 34*6349Sqs148142 #endif 35*6349Sqs148142 36*6349Sqs148142 #include <hpi.h> 37*6349Sqs148142 #include <hxge_common.h> 38*6349Sqs148142 #include <hxge_pfc_hw.h> 39*6349Sqs148142 #include <hxge_pfc.h> 40*6349Sqs148142 41*6349Sqs148142 typedef enum _tcam_op { 42*6349Sqs148142 TCAM_RWC_STAT = 0x1, 43*6349Sqs148142 TCAM_RWC_MATCH = 0x2 44*6349Sqs148142 } tcam_op_t; 45*6349Sqs148142 46*6349Sqs148142 /* 47*6349Sqs148142 * HPI PFC ERROR Codes 48*6349Sqs148142 */ 49*6349Sqs148142 #define HPI_PFC_BLK_CODE PFC_BLK_ID << 8 50*6349Sqs148142 #define HPI_PFC_ERROR (HPI_FAILURE | HPI_PFC_BLK_CODE) 51*6349Sqs148142 #define HPI_TCAM_ERROR 0x10 52*6349Sqs148142 #define HPI_FCRAM_ERROR 0x20 53*6349Sqs148142 #define HPI_GEN_PFC 0x30 54*6349Sqs148142 #define HPI_PFC_SW_PARAM_ERROR 0x40 55*6349Sqs148142 #define HPI_PFC_HW_ERROR 0x80 56*6349Sqs148142 57*6349Sqs148142 #define HPI_PFC_RESET_ERROR (HPI_PFC_ERROR | HPI_GEN_PFC | RESET_FAILED) 58*6349Sqs148142 #define HPI_PFC_TCAM_WR_ERROR \ 59*6349Sqs148142 (HPI_PFC_ERROR | HPI_TCAM_ERROR | WRITE_FAILED) 60*6349Sqs148142 #define HPI_PFC_ASC_RAM_RD_ERROR \ 61*6349Sqs148142 (HPI_PFC_ERROR | HPI_TCAM_ERROR | READ_FAILED) 62*6349Sqs148142 #define HPI_PFC_ASC_RAM_WR_ERROR \ 63*6349Sqs148142 (HPI_PFC_ERROR | HPI_TCAM_ERROR | WRITE_FAILED) 64*6349Sqs148142 65*6349Sqs148142 #define TCAM_CLASS_INVALID \ 66*6349Sqs148142 (HPI_PFC_SW_PARAM_ERROR | 0xb) 67*6349Sqs148142 /* have only 0xc, 0xd, 0xe and 0xf left for sw error codes */ 68*6349Sqs148142 #define HPI_PFC_TCAM_HW_ERROR \ 69*6349Sqs148142 (HPI_PFC_ERROR | HPI_PFC_HW_ERROR | HPI_TCAM_ERROR) 70*6349Sqs148142 71*6349Sqs148142 #define PFC_N_VLAN_MEMBERS 0x20 72*6349Sqs148142 73*6349Sqs148142 #define PFC_N_MAC_ADDRESSES 16 74*6349Sqs148142 #define PFC_MAX_DMA_CHANNELS 4 75*6349Sqs148142 #define PFC_MAC_ADDR_STEP 8 76*6349Sqs148142 77*6349Sqs148142 #define PFC_HASH_STEP 0x08 78*6349Sqs148142 79*6349Sqs148142 #define PFC_L2_CLASS_CONFIG_STEP 0x08 80*6349Sqs148142 81*6349Sqs148142 #define PFC_L3_CLASS_CONFIG_STEP 0x08 82*6349Sqs148142 83*6349Sqs148142 #define PFC_N_TCAM_ENTRIES 42 84*6349Sqs148142 85*6349Sqs148142 #define PFC_VLAN_REG_OFFSET(vlan_id) \ 86*6349Sqs148142 ((((vlan_id_t)(vlan_id / PFC_N_VLAN_MEMBERS)) * 8) + PFC_VLAN_TABLE) 87*6349Sqs148142 #define PFC_VLAN_BIT_OFFSET(vlan_id) \ 88*6349Sqs148142 (vlan_id % PFC_N_VLAN_MEMBERS) 89*6349Sqs148142 #define PFC_MAC_ADDRESS(slot) \ 90*6349Sqs148142 ((slot * PFC_MAC_ADDR_STEP) + PFC_MAC_ADDR) 91*6349Sqs148142 #define PFC_MAC_ADDRESS_MASK(slot) \ 92*6349Sqs148142 ((slot * PFC_MAC_ADDR_STEP) + PFC_MAC_ADDR_MASK) 93*6349Sqs148142 #define PFC_HASH_ADDR(slot) \ 94*6349Sqs148142 ((slot * PFC_HASH_STEP) + PFC_HASH_TABLE) 95*6349Sqs148142 96*6349Sqs148142 #define PFC_L2_CONFIG(slot) \ 97*6349Sqs148142 ((slot * PFC_L2_CLASS_CONFIG_STEP) + PFC_L2_CLASS_CONFIG) 98*6349Sqs148142 #define PFC_L3_CONFIG(slot) \ 99*6349Sqs148142 (((slot - TCAM_CLASS_TCP_IPV4) * PFC_L3_CLASS_CONFIG_STEP) + \ 100*6349Sqs148142 PFC_L3_CLASS_CONFIG) 101*6349Sqs148142 102*6349Sqs148142 typedef uint16_t vlan_id_t; 103*6349Sqs148142 104*6349Sqs148142 /* 105*6349Sqs148142 * PFC Control Register Functions 106*6349Sqs148142 */ 107*6349Sqs148142 hpi_status_t hpi_pfc_set_tcam_enable(hpi_handle_t, boolean_t); 108*6349Sqs148142 hpi_status_t hpi_pfc_set_l2_hash(hpi_handle_t, boolean_t); 109*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_cksum(hpi_handle_t, boolean_t); 110*6349Sqs148142 hpi_status_t hpi_pfc_set_default_dma(hpi_handle_t, uint32_t); 111*6349Sqs148142 hpi_status_t hpi_pfc_mac_addr_enable(hpi_handle_t, uint32_t); 112*6349Sqs148142 hpi_status_t hpi_pfc_mac_addr_disable(hpi_handle_t, uint32_t); 113*6349Sqs148142 hpi_status_t hpi_pfc_set_force_csum(hpi_handle_t, boolean_t); 114*6349Sqs148142 115*6349Sqs148142 /* 116*6349Sqs148142 * PFC vlan Functions 117*6349Sqs148142 */ 118*6349Sqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_clear(hpi_handle_t); 119*6349Sqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_entry_clear(hpi_handle_t, vlan_id_t); 120*6349Sqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_entry_set(hpi_handle_t, vlan_id_t); 121*6349Sqs148142 hpi_status_t hpi_pfc_cfg_vlan_control_set(hpi_handle_t, boolean_t, 122*6349Sqs148142 boolean_t, vlan_id_t); 123*6349Sqs148142 hpi_status_t hpi_pfc_get_vlan_parity_log(hpi_handle_t, 124*6349Sqs148142 pfc_vlan_par_err_log_t *); 125*6349Sqs148142 126*6349Sqs148142 /* 127*6349Sqs148142 * PFC Mac Address Functions 128*6349Sqs148142 */ 129*6349Sqs148142 hpi_status_t hpi_pfc_set_mac_address(hpi_handle_t, uint32_t, uint64_t); 130*6349Sqs148142 hpi_status_t hpi_pfc_clear_mac_address(hpi_handle_t, uint32_t); 131*6349Sqs148142 hpi_status_t hpi_pfc_clear_multicast_hash_table(hpi_handle_t, uint32_t); 132*6349Sqs148142 hpi_status_t hpi_pfc_set_multicast_hash_table(hpi_handle_t, uint32_t, 133*6349Sqs148142 uint64_t); 134*6349Sqs148142 135*6349Sqs148142 /* 136*6349Sqs148142 * PFC L2 and L3 Config Functions. 137*6349Sqs148142 */ 138*6349Sqs148142 hpi_status_t hpi_pfc_set_l2_class_slot(hpi_handle_t, uint16_t, boolean_t, int); 139*6349Sqs148142 hpi_status_t hpi_pfc_get_l3_class_config(hpi_handle_t handle, tcam_class_t slot, 140*6349Sqs148142 tcam_key_cfg_t *cfg); 141*6349Sqs148142 hpi_status_t hpi_pfc_set_l3_class_config(hpi_handle_t handle, tcam_class_t slot, 142*6349Sqs148142 tcam_key_cfg_t cfg); 143*6349Sqs148142 144*6349Sqs148142 /* 145*6349Sqs148142 * PFC TCAM Functions 146*6349Sqs148142 */ 147*6349Sqs148142 hpi_status_t hpi_pfc_tcam_invalidate_all(hpi_handle_t); 148*6349Sqs148142 hpi_status_t hpi_pfc_tcam_entry_invalidate(hpi_handle_t, uint32_t); 149*6349Sqs148142 hpi_status_t hpi_pfc_tcam_entry_write(hpi_handle_t, uint32_t, 150*6349Sqs148142 hxge_tcam_entry_t *); 151*6349Sqs148142 hpi_status_t hpi_pfc_tcam_entry_read(hpi_handle_t, uint32_t, 152*6349Sqs148142 hxge_tcam_entry_t *); 153*6349Sqs148142 hpi_status_t hpi_pfc_tcam_asc_ram_entry_read(hpi_handle_t handle, 154*6349Sqs148142 uint32_t location, uint64_t *ram_data); 155*6349Sqs148142 hpi_status_t hpi_pfc_tcam_asc_ram_entry_write(hpi_handle_t handle, 156*6349Sqs148142 uint32_t location, uint64_t ram_data); 157*6349Sqs148142 hpi_status_t hpi_pfc_get_tcam_parity_log(hpi_handle_t, 158*6349Sqs148142 pfc_tcam_par_err_log_t *); 159*6349Sqs148142 hpi_status_t hpi_pfc_get_tcam_auto_init(hpi_handle_t, 160*6349Sqs148142 pfc_auto_init_t *); 161*6349Sqs148142 162*6349Sqs148142 /* 163*6349Sqs148142 * PFC TCP Control 164*6349Sqs148142 */ 165*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_discard(hpi_handle_t, boolean_t); 166*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_fin(hpi_handle_t, boolean_t); 167*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_syn(hpi_handle_t, boolean_t); 168*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_rst(hpi_handle_t, boolean_t); 169*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_psh(hpi_handle_t, boolean_t); 170*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_ack(hpi_handle_t, boolean_t); 171*6349Sqs148142 hpi_status_t hpi_pfc_set_tcp_control_urg(hpi_handle_t, boolean_t); 172*6349Sqs148142 173*6349Sqs148142 /* 174*6349Sqs148142 * PFC Hash Seed Value 175*6349Sqs148142 */ 176*6349Sqs148142 hpi_status_t hpi_pfc_set_hash_seed_value(hpi_handle_t, uint32_t); 177*6349Sqs148142 178*6349Sqs148142 /* 179*6349Sqs148142 * PFC Interrupt Management Functions 180*6349Sqs148142 */ 181*6349Sqs148142 hpi_status_t hpi_pfc_get_interrupt_status(hpi_handle_t, pfc_int_status_t *); 182*6349Sqs148142 hpi_status_t hpi_pfc_clear_interrupt_status(hpi_handle_t); 183*6349Sqs148142 hpi_status_t hpi_pfc_set_interrupt_mask(hpi_handle_t, boolean_t, 184*6349Sqs148142 boolean_t, boolean_t); 185*6349Sqs148142 186*6349Sqs148142 /* 187*6349Sqs148142 * PFC Packet Logs 188*6349Sqs148142 */ 189*6349Sqs148142 hpi_status_t hpi_pfc_get_drop_log(hpi_handle_t, pfc_drop_log_t *); 190*6349Sqs148142 hpi_status_t hpi_pfc_set_drop_log_mask(hpi_handle_t, boolean_t, 191*6349Sqs148142 boolean_t, boolean_t, boolean_t, boolean_t); 192*6349Sqs148142 hpi_status_t hpi_pfc_get_bad_csum_counter(hpi_handle_t, uint64_t *); 193*6349Sqs148142 hpi_status_t hpi_pfc_get_drop_counter(hpi_handle_t, uint64_t *); 194*6349Sqs148142 195*6349Sqs148142 hpi_status_t hpi_pfc_get_number_mac_addrs(hpi_handle_t handle, 196*6349Sqs148142 uint32_t *n_of_addrs); 197*6349Sqs148142 hpi_status_t hpi_pfc_mac_addr_get_i(hpi_handle_t handle, uint8_t *data, 198*6349Sqs148142 int slot); 199*6349Sqs148142 hpi_status_t hpi_pfc_num_macs_get(hpi_handle_t handle, uint8_t *data); 200*6349Sqs148142 201*6349Sqs148142 #ifdef __cplusplus 202*6349Sqs148142 } 203*6349Sqs148142 #endif 204*6349Sqs148142 205*6349Sqs148142 #endif /* !_HPI_PFC_H */ 206