xref: /onnv-gate/usr/src/uts/common/io/hxge/hpi.h (revision 6349:b4971e04f83d)
1*6349Sqs148142 /*
2*6349Sqs148142  * CDDL HEADER START
3*6349Sqs148142  *
4*6349Sqs148142  * The contents of this file are subject to the terms of the
5*6349Sqs148142  * Common Development and Distribution License (the "License").
6*6349Sqs148142  * You may not use this file except in compliance with the License.
7*6349Sqs148142  *
8*6349Sqs148142  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*6349Sqs148142  * or http://www.opensolaris.org/os/licensing.
10*6349Sqs148142  * See the License for the specific language governing permissions
11*6349Sqs148142  * and limitations under the License.
12*6349Sqs148142  *
13*6349Sqs148142  * When distributing Covered Code, include this CDDL HEADER in each
14*6349Sqs148142  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*6349Sqs148142  * If applicable, add the following below this CDDL HEADER, with the
16*6349Sqs148142  * fields enclosed by brackets "[]" replaced with your own identifying
17*6349Sqs148142  * information: Portions Copyright [yyyy] [name of copyright owner]
18*6349Sqs148142  *
19*6349Sqs148142  * CDDL HEADER END
20*6349Sqs148142  */
21*6349Sqs148142 /*
22*6349Sqs148142  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23*6349Sqs148142  * Use is subject to license terms.
24*6349Sqs148142  */
25*6349Sqs148142 
26*6349Sqs148142 #ifndef _HPI_H
27*6349Sqs148142 #define	_HPI_H
28*6349Sqs148142 
29*6349Sqs148142 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30*6349Sqs148142 
31*6349Sqs148142 #ifdef	__cplusplus
32*6349Sqs148142 extern "C" {
33*6349Sqs148142 #endif
34*6349Sqs148142 
35*6349Sqs148142 #include <sys/types.h>
36*6349Sqs148142 #include <hxge_common_impl.h>
37*6349Sqs148142 #include <hxge_common.h>
38*6349Sqs148142 
39*6349Sqs148142 typedef	uint32_t hpi_status_t;
40*6349Sqs148142 
41*6349Sqs148142 /* Common Block ID */
42*6349Sqs148142 #define	VMAC_BLK_ID			0x1
43*6349Sqs148142 #define	TXDMA_BLK_ID			0x2
44*6349Sqs148142 #define	RXDMA_BLK_ID			0x3
45*6349Sqs148142 #define	PFC_BLK_ID			0x4
46*6349Sqs148142 #define	VIR_BLK_ID			0x5
47*6349Sqs148142 #define	PEU_BLK_ID			0x6
48*6349Sqs148142 
49*6349Sqs148142 /* Common HW error code */
50*6349Sqs148142 /* HW unable to exit from reset state. */
51*6349Sqs148142 #define	RESET_FAILED			0x81
52*6349Sqs148142 
53*6349Sqs148142 /* Write operation failed on indirect write. */
54*6349Sqs148142 #define	WRITE_FAILED			0x82
55*6349Sqs148142 /* Read operation failed on indirect read.	 */
56*6349Sqs148142 #define	READ_FAILED			0x83
57*6349Sqs148142 
58*6349Sqs148142 /* Common SW errors code */
59*6349Sqs148142 
60*6349Sqs148142 #define	PORT_INVALID			0x41	/* Invalid port number */
61*6349Sqs148142 #define	CHANNEL_INVALID			0x42	/* Invalid dma channel number */
62*6349Sqs148142 #define	OPCODE_INVALID			0x43	/* Invalid opcode */
63*6349Sqs148142 #define	REGISTER_INVALID		0x44	/* Invalid register number */
64*6349Sqs148142 #define	COUNTER_INVALID			0x45	/* Invalid counter number */
65*6349Sqs148142 #define	CONFIG_INVALID			0x46	/* Invalid config input */
66*6349Sqs148142 #define	LOGICAL_PAGE_INVALID		0x47	/* Invalid logical page # */
67*6349Sqs148142 #define	VLAN_INVALID			0x48	/* Invalid Vlan ID */
68*6349Sqs148142 #define	RDC_TAB_INVALID			0x49	/* Invalid RDC Group Number */
69*6349Sqs148142 #define	LOCATION_INVALID		0x4a	/* Invalid Entry Location */
70*6349Sqs148142 
71*6349Sqs148142 #define	HPI_SUCCESS			0		/* Operation succeed */
72*6349Sqs148142 #define	HPI_FAILURE			0x80000000	/* Operation failed */
73*6349Sqs148142 
74*6349Sqs148142 /*
75*6349Sqs148142  * Block identifier starts at bit 8.
76*6349Sqs148142  */
77*6349Sqs148142 #define	HPI_BLOCK_ID_SHIFT		8
78*6349Sqs148142 
79*6349Sqs148142 /*
80*6349Sqs148142  * Port, channel and misc. information starts at bit 12.
81*6349Sqs148142  */
82*6349Sqs148142 #define	HPI_PORT_CHAN_SHIFT		12
83*6349Sqs148142 
84*6349Sqs148142 /*
85*6349Sqs148142  * Software Block specific error codes start at 0x50.
86*6349Sqs148142  */
87*6349Sqs148142 #define	HPI_BK_ERROR_START		0x50
88*6349Sqs148142 
89*6349Sqs148142 /*
90*6349Sqs148142  * Hardware block specific error codes start at 0x90.
91*6349Sqs148142  */
92*6349Sqs148142 #define	HPI_BK_HW_ER_START		0x90
93*6349Sqs148142 
94*6349Sqs148142 /* Structures for register tracing */
95*6349Sqs148142 
96*6349Sqs148142 typedef struct _rt_buf {
97*6349Sqs148142 	uint32_t	ctl_addr;
98*6349Sqs148142 	uint32_t	val_l32;
99*6349Sqs148142 	uint32_t	val_h32;
100*6349Sqs148142 } rt_buf_t;
101*6349Sqs148142 
102*6349Sqs148142 /*
103*6349Sqs148142  * Control Address field format
104*6349Sqs148142  *
105*6349Sqs148142  * Bit 0 - 23: Address
106*6349Sqs148142  * Bit 24 - 25: Function Number
107*6349Sqs148142  * Bit 26 - 29: Instance Number
108*6349Sqs148142  * Bit 30: Read/Write Direction bit
109*6349Sqs148142  * Bit 31: Invalid bit
110*6349Sqs148142  */
111*6349Sqs148142 
112*6349Sqs148142 #define	MAX_RTRACE_ENTRIES	1024
113*6349Sqs148142 #define	MAX_RTRACE_IOC_ENTRIES	64
114*6349Sqs148142 #define	TRACE_ADDR_MASK		0x00FFFFFF
115*6349Sqs148142 #define	TRACE_FUNC_MASK		0x03000000
116*6349Sqs148142 #define	TRACE_INST_MASK		0x3C000000
117*6349Sqs148142 #define	TRACE_CTL_WR		0x40000000
118*6349Sqs148142 #define	TRACE_CTL_INVALID	0x80000000
119*6349Sqs148142 #define	TRACE_FUNC_SHIFT	24
120*6349Sqs148142 #define	TRACE_INST_SHIFT	26
121*6349Sqs148142 #define	MSG_BUF_SIZE		1024
122*6349Sqs148142 
123*6349Sqs148142 
124*6349Sqs148142 typedef struct _rtrace {
125*6349Sqs148142 	uint16_t	next_idx;
126*6349Sqs148142 	uint16_t	last_idx;
127*6349Sqs148142 	boolean_t	wrapped;
128*6349Sqs148142 	rt_buf_t	buf[MAX_RTRACE_ENTRIES];
129*6349Sqs148142 } rtrace_t;
130*6349Sqs148142 
131*6349Sqs148142 /* Configuration options */
132*6349Sqs148142 typedef enum config_op {
133*6349Sqs148142 	DISABLE = 0,
134*6349Sqs148142 	ENABLE,
135*6349Sqs148142 	INIT
136*6349Sqs148142 } config_op_t;
137*6349Sqs148142 
138*6349Sqs148142 /* I/O options */
139*6349Sqs148142 typedef enum io_op {
140*6349Sqs148142 	OP_SET = 0,
141*6349Sqs148142 	OP_GET,
142*6349Sqs148142 	OP_UPDATE,
143*6349Sqs148142 	OP_CLEAR
144*6349Sqs148142 } io_op_t;
145*6349Sqs148142 
146*6349Sqs148142 /* HPI Handle */
147*6349Sqs148142 typedef	struct	_hpi_handle_function {
148*6349Sqs148142 	uint16_t		instance;
149*6349Sqs148142 	uint16_t		function;
150*6349Sqs148142 } hpi_handle_function_t;
151*6349Sqs148142 
152*6349Sqs148142 /* HPI Handle */
153*6349Sqs148142 typedef	struct	_hpi_handle {
154*6349Sqs148142 	hpi_reg_handle_t	regh;
155*6349Sqs148142 	hpi_reg_ptr_t		regp;
156*6349Sqs148142 	boolean_t		is_vraddr; /* virtualization region address */
157*6349Sqs148142 	hpi_handle_function_t	function;
158*6349Sqs148142 	void			*hxgep;
159*6349Sqs148142 } hpi_handle_t;
160*6349Sqs148142 
161*6349Sqs148142 extern	rtrace_t hpi_rtracebuf;
162*6349Sqs148142 void hpi_rtrace_update(hpi_handle_t handle, boolean_t wr, rtrace_t *rt,
163*6349Sqs148142     uint32_t addr, uint64_t val);
164*6349Sqs148142 void hpi_rtrace_buf_init(rtrace_t *rt);
165*6349Sqs148142 
166*6349Sqs148142 void hpi_debug_msg(hpi_handle_function_t function, uint64_t level,
167*6349Sqs148142     char *fmt, ...);
168*6349Sqs148142 
169*6349Sqs148142 #ifdef	HPI_DEBUG
170*6349Sqs148142 #define	HPI_DEBUG_MSG(params) hpi_debug_msg params
171*6349Sqs148142 #else
172*6349Sqs148142 #define	HPI_DEBUG_MSG(params)
173*6349Sqs148142 #endif
174*6349Sqs148142 
175*6349Sqs148142 #define	HPI_ERROR_MSG(params) hpi_debug_msg params
176*6349Sqs148142 
177*6349Sqs148142 #ifdef	__cplusplus
178*6349Sqs148142 }
179*6349Sqs148142 #endif
180*6349Sqs148142 
181*6349Sqs148142 #endif	/* _HPI_H */
182