1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * 31*0Sstevel@tonic-gate * IEEE 1284 Parallel Port Device Driver 32*0Sstevel@tonic-gate * 33*0Sstevel@tonic-gate */ 34*0Sstevel@tonic-gate 35*0Sstevel@tonic-gate #include <sys/param.h> 36*0Sstevel@tonic-gate #include <sys/errno.h> 37*0Sstevel@tonic-gate #include <sys/file.h> 38*0Sstevel@tonic-gate #include <sys/cmn_err.h> 39*0Sstevel@tonic-gate #include <sys/stropts.h> 40*0Sstevel@tonic-gate #include <sys/debug.h> 41*0Sstevel@tonic-gate #include <sys/stream.h> 42*0Sstevel@tonic-gate #include <sys/strsun.h> 43*0Sstevel@tonic-gate #include <sys/kmem.h> 44*0Sstevel@tonic-gate #include <sys/ddi.h> 45*0Sstevel@tonic-gate #include <sys/sunddi.h> 46*0Sstevel@tonic-gate #include <sys/conf.h> /* req. by dev_ops flags MTSAFE etc. */ 47*0Sstevel@tonic-gate #include <sys/modctl.h> /* for modldrv */ 48*0Sstevel@tonic-gate #include <sys/stat.h> /* ddi_create_minor_node S_IFCHR */ 49*0Sstevel@tonic-gate #include <sys/open.h> 50*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 51*0Sstevel@tonic-gate #include <sys/kstat.h> 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate #include <sys/prnio.h> 54*0Sstevel@tonic-gate #include <sys/ecppreg.h> /* hw description */ 55*0Sstevel@tonic-gate #include <sys/ecppio.h> /* ioctl description */ 56*0Sstevel@tonic-gate #include <sys/ecppvar.h> /* driver description */ 57*0Sstevel@tonic-gate #include <sys/dma_engine.h> 58*0Sstevel@tonic-gate #include <sys/dma_i8237A.h> 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate /* 61*0Sstevel@tonic-gate * Background 62*0Sstevel@tonic-gate * ========== 63*0Sstevel@tonic-gate * IEEE 1284-1994 standard defines "a signalling method for asynchronous, 64*0Sstevel@tonic-gate * fully interlocked, bidirectional parallel communications between hosts 65*0Sstevel@tonic-gate * and printers or other peripherals." (1.1) The standard defines 5 modes 66*0Sstevel@tonic-gate * of operation - Compatibility, Nibble, Byte, ECP and EPP - which differ 67*0Sstevel@tonic-gate * in direction, bandwidth, pins assignment, DMA capability, etc. 68*0Sstevel@tonic-gate * 69*0Sstevel@tonic-gate * Negotiation is a mechanism for moving between modes. Compatibility mode 70*0Sstevel@tonic-gate * is a default mode, from which negotiations to other modes occur and 71*0Sstevel@tonic-gate * to which both host and peripheral break in case of interface errors. 72*0Sstevel@tonic-gate * Compatibility mode provides a unidirectional (forward) channel for 73*0Sstevel@tonic-gate * communicating with old pre-1284 peripherals. 74*0Sstevel@tonic-gate * 75*0Sstevel@tonic-gate * Each mode has a number of phases. [Mode, phase] pair represents the 76*0Sstevel@tonic-gate * interface state. Host initiates all transfers, though peripheral can 77*0Sstevel@tonic-gate * request backchannel transfer by asserting nErr pin. 78*0Sstevel@tonic-gate * 79*0Sstevel@tonic-gate * Ecpp driver implements an IEEE 1284-compliant host using a combination 80*0Sstevel@tonic-gate * of hardware and software. Hardware part is represented by a controller, 81*0Sstevel@tonic-gate * which is a part of the SuperIO chip. Ecpp supports the following SuperIOs: 82*0Sstevel@tonic-gate * PC82332/PC82336 (U5/U10/U60), PC97317 (U100), M1553 (Grover). 83*0Sstevel@tonic-gate * Struct ecpp_hw describes each SuperIO and is determined in ecpp_attach(). 84*0Sstevel@tonic-gate * 85*0Sstevel@tonic-gate * Negotiation is performed in software. Transfer may be performed either 86*0Sstevel@tonic-gate * in software by driving output pins for each byte (PIO method), or with 87*0Sstevel@tonic-gate * hardware assistance - SuperIO has a 16-byte FIFO, which is filled by 88*0Sstevel@tonic-gate * the driver (normally using DMA), while the chip performs the actual xfer. 89*0Sstevel@tonic-gate * PIO is used for Nibble and Compat, DMA is used for ECP and Compat modes. 90*0Sstevel@tonic-gate * 91*0Sstevel@tonic-gate * Driver currently supports the following modes: 92*0Sstevel@tonic-gate * 93*0Sstevel@tonic-gate * - Compatibility mode: byte-wide forward channel ~50KB/sec; 94*0Sstevel@tonic-gate * pp->io_mode defines PIO or DMA method of transfer; 95*0Sstevel@tonic-gate * - Nibble mode: nibble-wide (4-bit) reverse channel ~30KB/sec; 96*0Sstevel@tonic-gate * - ECP mode: byte-wide bidirectional channel (~1MB/sec); 97*0Sstevel@tonic-gate * 98*0Sstevel@tonic-gate * Theory of operation 99*0Sstevel@tonic-gate * =================== 100*0Sstevel@tonic-gate * The manner in which ecpp drives 1284 interface is that of a state machine. 101*0Sstevel@tonic-gate * State is a combination of 1284 mode {ECPP_*_MODE}, 1284 phase {ECPP_PHASE_*} 102*0Sstevel@tonic-gate * and transfer method {PIO, DMA}. State is a function of application actions 103*0Sstevel@tonic-gate * {write(2), ioctl(2)} and peripheral reaction. 104*0Sstevel@tonic-gate * 105*0Sstevel@tonic-gate * 1284 interface state is described by the following variables: 106*0Sstevel@tonic-gate * pp->current_mode -- 1284 mode used for forward transfers; 107*0Sstevel@tonic-gate * pp->backchannel -- 1284 mode used for backward transfers; 108*0Sstevel@tonic-gate * pp->curent_phase -- 1284 phase; 109*0Sstevel@tonic-gate * 110*0Sstevel@tonic-gate * Bidirectional operation in Compatibility mode is provided by a combination: 111*0Sstevel@tonic-gate * pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE 112*0Sstevel@tonic-gate * ECPP_CENTRONICS means no backchannel 113*0Sstevel@tonic-gate * 114*0Sstevel@tonic-gate * Driver internal state is defined by pp->e_busy as follows: 115*0Sstevel@tonic-gate * ECPP_IDLE -- idle, no active transfers; 116*0Sstevel@tonic-gate * ECPP_BUSY -- transfer is in progress; 117*0Sstevel@tonic-gate * ECPP_ERR -- have data to transfer, but peripheral can`t receive data; 118*0Sstevel@tonic-gate * ECPP_FLUSH -- flushing the queues; 119*0Sstevel@tonic-gate * 120*0Sstevel@tonic-gate * When opened, driver is in ECPP_IDLE state, current mode is ECPP_CENTRONICS 121*0Sstevel@tonic-gate * Default negotiation tries to negotiate to the best mode supported by printer, 122*0Sstevel@tonic-gate * sets pp->current_mode and pp->backchannel accordingly. 123*0Sstevel@tonic-gate * 124*0Sstevel@tonic-gate * When output data arrives in M_DATA mblks ecpp_wput() puts them on the queue 125*0Sstevel@tonic-gate * to let ecpp_wsrv() concatenate small blocks into one big transfer 126*0Sstevel@tonic-gate * by copying them into pp->ioblock. If first the mblk data is bigger than 127*0Sstevel@tonic-gate * pp->ioblock, then it is used instead of i/o block (pointed by pp->msg) 128*0Sstevel@tonic-gate * 129*0Sstevel@tonic-gate * Before starting the transfer the driver will check if peripheral is ready 130*0Sstevel@tonic-gate * by calling ecpp_check_status() and if it is not, driver goes ECPP_ERR state 131*0Sstevel@tonic-gate * and schedules ecpp_wsrv_timer() which would qenable() the wq, effectively 132*0Sstevel@tonic-gate * rechecking the peripheral readiness and restarting itself until it is ready. 133*0Sstevel@tonic-gate * The transfer is then started by calling ecpp_start(), driver goes ECPP_BUSY 134*0Sstevel@tonic-gate * 135*0Sstevel@tonic-gate * While transfer is in progress all arriving messages will be queued up. 136*0Sstevel@tonic-gate * Transfer can end up in either of two ways: 137*0Sstevel@tonic-gate * - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so 138*0Sstevel@tonic-gate * cleanup and go ECPP_IDLE, otherwise putback untransferred and qenable(); 139*0Sstevel@tonic-gate * - ecpp_xfer_timeout() cancels the transfer and puts back untransferred data; 140*0Sstevel@tonic-gate * 141*0Sstevel@tonic-gate * PIO transfer method is very CPU intensive: for each sent byte the peripheral 142*0Sstevel@tonic-gate * state is checked, then the byte is transfered and driver waits for an nAck 143*0Sstevel@tonic-gate * interrupt; ecpp_isr() will then look if there is more data and if so 144*0Sstevel@tonic-gate * triggers the soft interrupt, which transfers the next byte. PIO method 145*0Sstevel@tonic-gate * is needed only for legacy printers which are sensitive to strobe problem 146*0Sstevel@tonic-gate * (Bugid 4192788). 147*0Sstevel@tonic-gate * 148*0Sstevel@tonic-gate * ecpp_wsrv() is responsible for both starting transfers (ecpp_start()) and 149*0Sstevel@tonic-gate * going idle (ecpp_idle_phase()). Many routines qenable() the write queue, 150*0Sstevel@tonic-gate * meaning "check if there are pending requests, process them and go idle". 151*0Sstevel@tonic-gate * 152*0Sstevel@tonic-gate * In it`s idle state the driver will always try to listen to the backchannel 153*0Sstevel@tonic-gate * (as advised by 1284). 154*0Sstevel@tonic-gate * 155*0Sstevel@tonic-gate * The mechanism for handling backchannel requests is as follows: 156*0Sstevel@tonic-gate * - when the peripheral has data to send it asserts nErr pin 157*0Sstevel@tonic-gate * (and also nAck in Nibble Mode) which results in an interrupt on the host; 158*0Sstevel@tonic-gate * - ISR creates M_CTL message containing an ECPP_BACKCHANNEL byte and 159*0Sstevel@tonic-gate * puts it back on the write queue; 160*0Sstevel@tonic-gate * - ecpp_wsrv() gets M_CTL and calls ecpp_peripheral2host(), which kicks off 161*0Sstevel@tonic-gate * the transfer; 162*0Sstevel@tonic-gate * 163*0Sstevel@tonic-gate * This way Nibble and ECP mode backchannel are implemented. 164*0Sstevel@tonic-gate * If the read queue gets full, backchannel request is rejected. 165*0Sstevel@tonic-gate * As the application reads data and queue size falls below the low watermark, 166*0Sstevel@tonic-gate * ecpp_rsrv() gets called and enables the backchannel again. 167*0Sstevel@tonic-gate * 168*0Sstevel@tonic-gate * Future enhancements 169*0Sstevel@tonic-gate * =================== 170*0Sstevel@tonic-gate * 171*0Sstevel@tonic-gate * Support new modes: Byte and EPP. 172*0Sstevel@tonic-gate */ 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate #ifndef ECPP_DEBUG 175*0Sstevel@tonic-gate #define ECPP_DEBUG 0 176*0Sstevel@tonic-gate #endif /* ECPP_DEBUG */ 177*0Sstevel@tonic-gate int ecpp_debug = ECPP_DEBUG; 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate int noecp = 0; /* flag not to use ECP mode */ 180*0Sstevel@tonic-gate 181*0Sstevel@tonic-gate /* driver entry point fn definitions */ 182*0Sstevel@tonic-gate static int ecpp_open(queue_t *, dev_t *, int, int, cred_t *); 183*0Sstevel@tonic-gate static int ecpp_close(queue_t *, int, cred_t *); 184*0Sstevel@tonic-gate static uint_t ecpp_isr(caddr_t); 185*0Sstevel@tonic-gate static uint_t ecpp_softintr(caddr_t); 186*0Sstevel@tonic-gate 187*0Sstevel@tonic-gate /* configuration entry point fn definitions */ 188*0Sstevel@tonic-gate static int ecpp_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 189*0Sstevel@tonic-gate static int ecpp_attach(dev_info_t *, ddi_attach_cmd_t); 190*0Sstevel@tonic-gate static int ecpp_detach(dev_info_t *, ddi_detach_cmd_t); 191*0Sstevel@tonic-gate static struct ecpp_hw_bind *ecpp_determine_sio_type(struct ecppunit *); 192*0Sstevel@tonic-gate 193*0Sstevel@tonic-gate /* isr support routines */ 194*0Sstevel@tonic-gate static uint_t ecpp_nErr_ihdlr(struct ecppunit *); 195*0Sstevel@tonic-gate static uint_t ecpp_pio_ihdlr(struct ecppunit *); 196*0Sstevel@tonic-gate static uint_t ecpp_dma_ihdlr(struct ecppunit *); 197*0Sstevel@tonic-gate static uint_t ecpp_M1553_intr(struct ecppunit *); 198*0Sstevel@tonic-gate 199*0Sstevel@tonic-gate /* configuration support routines */ 200*0Sstevel@tonic-gate static void ecpp_get_props(struct ecppunit *); 201*0Sstevel@tonic-gate 202*0Sstevel@tonic-gate /* Streams Routines */ 203*0Sstevel@tonic-gate static int ecpp_wput(queue_t *, mblk_t *); 204*0Sstevel@tonic-gate static int ecpp_wsrv(queue_t *); 205*0Sstevel@tonic-gate static int ecpp_rsrv(queue_t *); 206*0Sstevel@tonic-gate static void ecpp_flush(struct ecppunit *, int); 207*0Sstevel@tonic-gate static void ecpp_start(struct ecppunit *, caddr_t, size_t); 208*0Sstevel@tonic-gate 209*0Sstevel@tonic-gate /* ioctl handling */ 210*0Sstevel@tonic-gate static void ecpp_putioc(queue_t *, mblk_t *); 211*0Sstevel@tonic-gate static void ecpp_srvioc(queue_t *, mblk_t *); 212*0Sstevel@tonic-gate static void ecpp_wput_iocdata_devid(queue_t *, mblk_t *, uintptr_t); 213*0Sstevel@tonic-gate static void ecpp_putioc_copyout(queue_t *, mblk_t *, void *, int); 214*0Sstevel@tonic-gate static void ecpp_putioc_stateful_copyin(queue_t *, mblk_t *, size_t); 215*0Sstevel@tonic-gate static void ecpp_srvioc_devid(queue_t *, mblk_t *, 216*0Sstevel@tonic-gate struct ecpp_device_id *, int *); 217*0Sstevel@tonic-gate static void ecpp_srvioc_prnif(queue_t *, mblk_t *); 218*0Sstevel@tonic-gate static void ecpp_ack_ioctl(queue_t *, mblk_t *); 219*0Sstevel@tonic-gate static void ecpp_nack_ioctl(queue_t *, mblk_t *, int); 220*0Sstevel@tonic-gate 221*0Sstevel@tonic-gate /* kstat routines */ 222*0Sstevel@tonic-gate static void ecpp_kstat_init(struct ecppunit *); 223*0Sstevel@tonic-gate static int ecpp_kstat_update(kstat_t *, int); 224*0Sstevel@tonic-gate static int ecpp_kstatintr_update(kstat_t *, int); 225*0Sstevel@tonic-gate 226*0Sstevel@tonic-gate /* dma routines */ 227*0Sstevel@tonic-gate static void ecpp_putback_untransfered(struct ecppunit *, void *, uint_t); 228*0Sstevel@tonic-gate static uint8_t ecpp_setup_dma_resources(struct ecppunit *, caddr_t, size_t); 229*0Sstevel@tonic-gate static uint8_t ecpp_init_dma_xfer(struct ecppunit *, caddr_t, size_t); 230*0Sstevel@tonic-gate 231*0Sstevel@tonic-gate /* pio routines */ 232*0Sstevel@tonic-gate static void ecpp_pio_writeb(struct ecppunit *); 233*0Sstevel@tonic-gate static void ecpp_xfer_cleanup(struct ecppunit *); 234*0Sstevel@tonic-gate static uint8_t ecpp_prep_pio_xfer(struct ecppunit *, caddr_t, size_t); 235*0Sstevel@tonic-gate 236*0Sstevel@tonic-gate /* misc */ 237*0Sstevel@tonic-gate static uchar_t ecpp_reset_port_regs(struct ecppunit *); 238*0Sstevel@tonic-gate static void ecpp_xfer_timeout(void *); 239*0Sstevel@tonic-gate static void ecpp_fifo_timer(void *); 240*0Sstevel@tonic-gate static void ecpp_wsrv_timer(void *); 241*0Sstevel@tonic-gate static uchar_t dcr_write(struct ecppunit *, uint8_t); 242*0Sstevel@tonic-gate static uchar_t ecr_write(struct ecppunit *, uint8_t); 243*0Sstevel@tonic-gate static uchar_t ecpp_check_status(struct ecppunit *); 244*0Sstevel@tonic-gate static int ecpp_backchan_req(struct ecppunit *); 245*0Sstevel@tonic-gate static void ecpp_untimeout_unblock(struct ecppunit *, timeout_id_t *); 246*0Sstevel@tonic-gate static uint_t ecpp_get_prn_ifcap(struct ecppunit *); 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate /* stubs */ 249*0Sstevel@tonic-gate static void empty_config_mode(struct ecppunit *); 250*0Sstevel@tonic-gate static void empty_mask_intr(struct ecppunit *); 251*0Sstevel@tonic-gate 252*0Sstevel@tonic-gate /* PC87332 support */ 253*0Sstevel@tonic-gate static int pc87332_map_regs(struct ecppunit *); 254*0Sstevel@tonic-gate static void pc87332_unmap_regs(struct ecppunit *); 255*0Sstevel@tonic-gate static int pc87332_config_chip(struct ecppunit *); 256*0Sstevel@tonic-gate static void pc87332_config_mode(struct ecppunit *); 257*0Sstevel@tonic-gate static uint8_t pc87332_read_config_reg(struct ecppunit *, uint8_t); 258*0Sstevel@tonic-gate static void pc87332_write_config_reg(struct ecppunit *, uint8_t, uint8_t); 259*0Sstevel@tonic-gate static void cheerio_mask_intr(struct ecppunit *); 260*0Sstevel@tonic-gate static void cheerio_unmask_intr(struct ecppunit *); 261*0Sstevel@tonic-gate static int cheerio_dma_start(struct ecppunit *); 262*0Sstevel@tonic-gate static int cheerio_dma_stop(struct ecppunit *, size_t *); 263*0Sstevel@tonic-gate static size_t cheerio_getcnt(struct ecppunit *); 264*0Sstevel@tonic-gate static void cheerio_reset_dcsr(struct ecppunit *); 265*0Sstevel@tonic-gate 266*0Sstevel@tonic-gate /* PC97317 support */ 267*0Sstevel@tonic-gate static int pc97317_map_regs(struct ecppunit *); 268*0Sstevel@tonic-gate static void pc97317_unmap_regs(struct ecppunit *); 269*0Sstevel@tonic-gate static int pc97317_config_chip(struct ecppunit *); 270*0Sstevel@tonic-gate static void pc97317_config_mode(struct ecppunit *); 271*0Sstevel@tonic-gate 272*0Sstevel@tonic-gate /* M1553 Southbridge support */ 273*0Sstevel@tonic-gate static int m1553_map_regs(struct ecppunit *pp); 274*0Sstevel@tonic-gate static void m1553_unmap_regs(struct ecppunit *pp); 275*0Sstevel@tonic-gate static int m1553_config_chip(struct ecppunit *); 276*0Sstevel@tonic-gate static uint8_t m1553_read_config_reg(struct ecppunit *, uint8_t); 277*0Sstevel@tonic-gate static void m1553_write_config_reg(struct ecppunit *, uint8_t, uint8_t); 278*0Sstevel@tonic-gate 279*0Sstevel@tonic-gate /* M1553 Southbridge DMAC 8237 support routines */ 280*0Sstevel@tonic-gate static int dma8237_dma_start(struct ecppunit *); 281*0Sstevel@tonic-gate static int dma8237_dma_stop(struct ecppunit *, size_t *); 282*0Sstevel@tonic-gate static size_t dma8237_getcnt(struct ecppunit *); 283*0Sstevel@tonic-gate static void dma8237_write_addr(struct ecppunit *, uint32_t); 284*0Sstevel@tonic-gate static void dma8237_write_count(struct ecppunit *, uint32_t); 285*0Sstevel@tonic-gate static uint32_t dma8237_read_count(struct ecppunit *); 286*0Sstevel@tonic-gate static void dma8237_write(struct ecppunit *, int, uint8_t); 287*0Sstevel@tonic-gate static uint8_t dma8237_read(struct ecppunit *, int); 288*0Sstevel@tonic-gate #ifdef INCLUDE_DMA8237_READ_ADDR 289*0Sstevel@tonic-gate static uint32_t dma8237_read_addr(struct ecppunit *); 290*0Sstevel@tonic-gate #endif 291*0Sstevel@tonic-gate 292*0Sstevel@tonic-gate /* i86 PC support rountines */ 293*0Sstevel@tonic-gate 294*0Sstevel@tonic-gate #if defined(__x86) 295*0Sstevel@tonic-gate static int x86_dma_start(struct ecppunit *); 296*0Sstevel@tonic-gate static int x86_dma_stop(struct ecppunit *, size_t *); 297*0Sstevel@tonic-gate static int x86_map_regs(struct ecppunit *); 298*0Sstevel@tonic-gate static void x86_unmap_regs(struct ecppunit *); 299*0Sstevel@tonic-gate static int x86_config_chip(struct ecppunit *); 300*0Sstevel@tonic-gate static size_t x86_getcnt(struct ecppunit *); 301*0Sstevel@tonic-gate #endif 302*0Sstevel@tonic-gate 303*0Sstevel@tonic-gate /* IEEE 1284 phase transitions */ 304*0Sstevel@tonic-gate static void ecpp_1284_init_interface(struct ecppunit *); 305*0Sstevel@tonic-gate static int ecpp_1284_termination(struct ecppunit *); 306*0Sstevel@tonic-gate static uchar_t ecpp_idle_phase(struct ecppunit *); 307*0Sstevel@tonic-gate static int ecp_forward2reverse(struct ecppunit *); 308*0Sstevel@tonic-gate static int ecp_reverse2forward(struct ecppunit *); 309*0Sstevel@tonic-gate static int read_nibble_backchan(struct ecppunit *); 310*0Sstevel@tonic-gate 311*0Sstevel@tonic-gate /* reverse transfers */ 312*0Sstevel@tonic-gate static uint_t ecpp_peripheral2host(struct ecppunit *); 313*0Sstevel@tonic-gate static uchar_t ecp_peripheral2host(struct ecppunit *); 314*0Sstevel@tonic-gate static uchar_t nibble_peripheral2host(struct ecppunit *pp, uint8_t *); 315*0Sstevel@tonic-gate static int ecpp_getdevid(struct ecppunit *, uint8_t *, int *, int); 316*0Sstevel@tonic-gate static void ecpp_ecp_read_timeout(void *); 317*0Sstevel@tonic-gate static void ecpp_ecp_read_completion(struct ecppunit *); 318*0Sstevel@tonic-gate 319*0Sstevel@tonic-gate /* IEEE 1284 mode transitions */ 320*0Sstevel@tonic-gate static void ecpp_default_negotiation(struct ecppunit *); 321*0Sstevel@tonic-gate static int ecpp_mode_negotiation(struct ecppunit *, uchar_t); 322*0Sstevel@tonic-gate static int ecpp_1284_negotiation(struct ecppunit *, uint8_t, uint8_t *); 323*0Sstevel@tonic-gate static int ecp_negotiation(struct ecppunit *); 324*0Sstevel@tonic-gate static int nibble_negotiation(struct ecppunit *); 325*0Sstevel@tonic-gate static int devidnib_negotiation(struct ecppunit *); 326*0Sstevel@tonic-gate 327*0Sstevel@tonic-gate /* IEEE 1284 utility routines */ 328*0Sstevel@tonic-gate static int wait_dsr(struct ecppunit *, uint8_t, uint8_t, int); 329*0Sstevel@tonic-gate 330*0Sstevel@tonic-gate /* debugging functions */ 331*0Sstevel@tonic-gate static void ecpp_error(dev_info_t *, char *, ...); 332*0Sstevel@tonic-gate static uchar_t ecpp_get_error_status(uchar_t); 333*0Sstevel@tonic-gate 334*0Sstevel@tonic-gate /* 335*0Sstevel@tonic-gate * Chip-dependent structures 336*0Sstevel@tonic-gate */ 337*0Sstevel@tonic-gate static ddi_dma_attr_t cheerio_dma_attr = { 338*0Sstevel@tonic-gate DMA_ATTR_VERSION, /* version */ 339*0Sstevel@tonic-gate 0x00000000ull, /* dlim_addr_lo */ 340*0Sstevel@tonic-gate 0xfffffffeull, /* dlim_addr_hi */ 341*0Sstevel@tonic-gate 0xffffff, /* DMA counter register */ 342*0Sstevel@tonic-gate 1, /* DMA address alignment */ 343*0Sstevel@tonic-gate 0x74, /* burst sizes */ 344*0Sstevel@tonic-gate 0x0001, /* min effective DMA size */ 345*0Sstevel@tonic-gate 0xffff, /* maximum transfer size */ 346*0Sstevel@tonic-gate 0xffff, /* segment boundary */ 347*0Sstevel@tonic-gate 1, /* s/g list length */ 348*0Sstevel@tonic-gate 1, /* granularity of device */ 349*0Sstevel@tonic-gate 0 /* DMA flags */ 350*0Sstevel@tonic-gate }; 351*0Sstevel@tonic-gate 352*0Sstevel@tonic-gate static struct ecpp_hw pc87332 = { 353*0Sstevel@tonic-gate pc87332_map_regs, 354*0Sstevel@tonic-gate pc87332_unmap_regs, 355*0Sstevel@tonic-gate pc87332_config_chip, 356*0Sstevel@tonic-gate pc87332_config_mode, 357*0Sstevel@tonic-gate cheerio_mask_intr, 358*0Sstevel@tonic-gate cheerio_unmask_intr, 359*0Sstevel@tonic-gate cheerio_dma_start, 360*0Sstevel@tonic-gate cheerio_dma_stop, 361*0Sstevel@tonic-gate cheerio_getcnt, 362*0Sstevel@tonic-gate &cheerio_dma_attr 363*0Sstevel@tonic-gate }; 364*0Sstevel@tonic-gate 365*0Sstevel@tonic-gate static struct ecpp_hw pc97317 = { 366*0Sstevel@tonic-gate pc97317_map_regs, 367*0Sstevel@tonic-gate pc97317_unmap_regs, 368*0Sstevel@tonic-gate pc97317_config_chip, 369*0Sstevel@tonic-gate pc97317_config_mode, 370*0Sstevel@tonic-gate cheerio_mask_intr, 371*0Sstevel@tonic-gate cheerio_unmask_intr, 372*0Sstevel@tonic-gate cheerio_dma_start, 373*0Sstevel@tonic-gate cheerio_dma_stop, 374*0Sstevel@tonic-gate cheerio_getcnt, 375*0Sstevel@tonic-gate &cheerio_dma_attr 376*0Sstevel@tonic-gate }; 377*0Sstevel@tonic-gate 378*0Sstevel@tonic-gate static ddi_dma_attr_t i8237_dma_attr = { 379*0Sstevel@tonic-gate DMA_ATTR_VERSION, /* version */ 380*0Sstevel@tonic-gate 0x00000000ull, /* dlim_addr_lo */ 381*0Sstevel@tonic-gate 0xfffffffeull, /* dlim_addr_hi */ 382*0Sstevel@tonic-gate 0xffff, /* DMA counter register */ 383*0Sstevel@tonic-gate 1, /* DMA address alignment */ 384*0Sstevel@tonic-gate 0x01, /* burst sizes */ 385*0Sstevel@tonic-gate 0x0001, /* min effective DMA size */ 386*0Sstevel@tonic-gate 0xffff, /* maximum transfer size */ 387*0Sstevel@tonic-gate 0x7fff, /* segment boundary */ 388*0Sstevel@tonic-gate 1, /* s/g list length */ 389*0Sstevel@tonic-gate 1, /* granularity of device */ 390*0Sstevel@tonic-gate 0 /* DMA flags */ 391*0Sstevel@tonic-gate }; 392*0Sstevel@tonic-gate 393*0Sstevel@tonic-gate static struct ecpp_hw m1553 = { 394*0Sstevel@tonic-gate m1553_map_regs, 395*0Sstevel@tonic-gate m1553_unmap_regs, 396*0Sstevel@tonic-gate m1553_config_chip, 397*0Sstevel@tonic-gate empty_config_mode, /* no config_mode */ 398*0Sstevel@tonic-gate empty_mask_intr, /* no mask_intr */ 399*0Sstevel@tonic-gate empty_mask_intr, /* no unmask_intr */ 400*0Sstevel@tonic-gate dma8237_dma_start, 401*0Sstevel@tonic-gate dma8237_dma_stop, 402*0Sstevel@tonic-gate dma8237_getcnt, 403*0Sstevel@tonic-gate &i8237_dma_attr 404*0Sstevel@tonic-gate }; 405*0Sstevel@tonic-gate 406*0Sstevel@tonic-gate #if defined(__x86) 407*0Sstevel@tonic-gate static ddi_dma_attr_t sb_dma_attr = { 408*0Sstevel@tonic-gate DMA_ATTR_VERSION, /* version */ 409*0Sstevel@tonic-gate 0x00000000ull, /* dlim_addr_lo */ 410*0Sstevel@tonic-gate 0xffffff, /* dlim_addr_hi */ 411*0Sstevel@tonic-gate 0xffff, /* DMA counter register */ 412*0Sstevel@tonic-gate 1, /* DMA address alignment */ 413*0Sstevel@tonic-gate 0x01, /* burst sizes */ 414*0Sstevel@tonic-gate 0x0001, /* min effective DMA size */ 415*0Sstevel@tonic-gate 0xffffffff, /* maximum transfer size */ 416*0Sstevel@tonic-gate 0xffff, /* segment boundary */ 417*0Sstevel@tonic-gate 1, /* s/g list length */ 418*0Sstevel@tonic-gate 1, /* granularity of device */ 419*0Sstevel@tonic-gate 0 /* DMA flags */ 420*0Sstevel@tonic-gate }; 421*0Sstevel@tonic-gate 422*0Sstevel@tonic-gate static struct ecpp_hw x86 = { 423*0Sstevel@tonic-gate x86_map_regs, 424*0Sstevel@tonic-gate x86_unmap_regs, 425*0Sstevel@tonic-gate x86_config_chip, 426*0Sstevel@tonic-gate empty_config_mode, /* no config_mode */ 427*0Sstevel@tonic-gate empty_mask_intr, /* no mask_intr */ 428*0Sstevel@tonic-gate empty_mask_intr, /* no unmask_intr */ 429*0Sstevel@tonic-gate x86_dma_start, 430*0Sstevel@tonic-gate x86_dma_stop, 431*0Sstevel@tonic-gate x86_getcnt, 432*0Sstevel@tonic-gate &sb_dma_attr 433*0Sstevel@tonic-gate }; 434*0Sstevel@tonic-gate #endif 435*0Sstevel@tonic-gate 436*0Sstevel@tonic-gate /* 437*0Sstevel@tonic-gate * list of supported devices 438*0Sstevel@tonic-gate */ 439*0Sstevel@tonic-gate struct ecpp_hw_bind ecpp_hw_bind[] = { 440*0Sstevel@tonic-gate { "ns87317-ecpp", &pc97317, "PC97317" }, 441*0Sstevel@tonic-gate { "pnpALI,1533,3", &m1553, "M1553" }, 442*0Sstevel@tonic-gate { "ecpp", &pc87332, "PC87332" }, 443*0Sstevel@tonic-gate #if defined(__x86) 444*0Sstevel@tonic-gate { "lp", &x86, "i86pc"}, 445*0Sstevel@tonic-gate #endif 446*0Sstevel@tonic-gate }; 447*0Sstevel@tonic-gate 448*0Sstevel@tonic-gate static ddi_device_acc_attr_t acc_attr = { 449*0Sstevel@tonic-gate DDI_DEVICE_ATTR_V0, 450*0Sstevel@tonic-gate DDI_STRUCTURE_LE_ACC, 451*0Sstevel@tonic-gate DDI_STRICTORDER_ACC 452*0Sstevel@tonic-gate }; 453*0Sstevel@tonic-gate 454*0Sstevel@tonic-gate static struct ecpp_transfer_parms default_xfer_parms = { 455*0Sstevel@tonic-gate FWD_TIMEOUT_DEFAULT, /* write timeout in seconds */ 456*0Sstevel@tonic-gate ECPP_CENTRONICS /* supported mode */ 457*0Sstevel@tonic-gate }; 458*0Sstevel@tonic-gate 459*0Sstevel@tonic-gate /* prnio interface info string */ 460*0Sstevel@tonic-gate static const char prn_ifinfo[] = PRN_PARALLEL; 461*0Sstevel@tonic-gate 462*0Sstevel@tonic-gate /* prnio timeouts */ 463*0Sstevel@tonic-gate static const struct prn_timeouts prn_timeouts_default = { 464*0Sstevel@tonic-gate FWD_TIMEOUT_DEFAULT, /* forward timeout */ 465*0Sstevel@tonic-gate REV_TIMEOUT_DEFAULT /* reverse timeout */ 466*0Sstevel@tonic-gate }; 467*0Sstevel@tonic-gate 468*0Sstevel@tonic-gate static int ecpp_isr_max_delay = ECPP_ISR_MAX_DELAY; 469*0Sstevel@tonic-gate static int ecpp_def_timeout = 90; /* left in for 2.7 compatibility */ 470*0Sstevel@tonic-gate 471*0Sstevel@tonic-gate static void *ecppsoft_statep; 472*0Sstevel@tonic-gate 473*0Sstevel@tonic-gate /* 474*0Sstevel@tonic-gate * STREAMS framework manages locks for these structures 475*0Sstevel@tonic-gate */ 476*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", iocblk)) 477*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", datab)) 478*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", msgb)) 479*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", queue)) 480*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", copyreq)) 481*0Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unique per call", stroptions)) 482*0Sstevel@tonic-gate 483*0Sstevel@tonic-gate struct module_info ecppinfo = { 484*0Sstevel@tonic-gate /* id, name, min pkt siz, max pkt siz, hi water, low water */ 485*0Sstevel@tonic-gate 42, "ecpp", 0, IO_BLOCK_SZ, ECPPHIWAT, ECPPLOWAT 486*0Sstevel@tonic-gate }; 487*0Sstevel@tonic-gate 488*0Sstevel@tonic-gate static struct qinit ecpp_rinit = { 489*0Sstevel@tonic-gate putq, ecpp_rsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL 490*0Sstevel@tonic-gate }; 491*0Sstevel@tonic-gate 492*0Sstevel@tonic-gate static struct qinit ecpp_wint = { 493*0Sstevel@tonic-gate ecpp_wput, ecpp_wsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL 494*0Sstevel@tonic-gate }; 495*0Sstevel@tonic-gate 496*0Sstevel@tonic-gate struct streamtab ecpp_str_info = { 497*0Sstevel@tonic-gate &ecpp_rinit, &ecpp_wint, NULL, NULL 498*0Sstevel@tonic-gate }; 499*0Sstevel@tonic-gate 500*0Sstevel@tonic-gate static struct cb_ops ecpp_cb_ops = { 501*0Sstevel@tonic-gate nodev, /* cb_open */ 502*0Sstevel@tonic-gate nodev, /* cb_close */ 503*0Sstevel@tonic-gate nodev, /* cb_strategy */ 504*0Sstevel@tonic-gate nodev, /* cb_print */ 505*0Sstevel@tonic-gate nodev, /* cb_dump */ 506*0Sstevel@tonic-gate nodev, /* cb_read */ 507*0Sstevel@tonic-gate nodev, /* cb_write */ 508*0Sstevel@tonic-gate nodev, /* cb_ioctl */ 509*0Sstevel@tonic-gate nodev, /* cb_devmap */ 510*0Sstevel@tonic-gate nodev, /* cb_mmap */ 511*0Sstevel@tonic-gate nodev, /* cb_segmap */ 512*0Sstevel@tonic-gate nochpoll, /* cb_chpoll */ 513*0Sstevel@tonic-gate ddi_prop_op, /* cb_prop_op */ 514*0Sstevel@tonic-gate &ecpp_str_info, /* cb_stream */ 515*0Sstevel@tonic-gate (D_NEW | D_MP | D_MTPERQ) /* cb_flag */ 516*0Sstevel@tonic-gate }; 517*0Sstevel@tonic-gate 518*0Sstevel@tonic-gate /* 519*0Sstevel@tonic-gate * Declare ops vectors for auto configuration. 520*0Sstevel@tonic-gate */ 521*0Sstevel@tonic-gate struct dev_ops ecpp_ops = { 522*0Sstevel@tonic-gate DEVO_REV, /* devo_rev */ 523*0Sstevel@tonic-gate 0, /* devo_refcnt */ 524*0Sstevel@tonic-gate ecpp_getinfo, /* devo_getinfo */ 525*0Sstevel@tonic-gate nulldev, /* devo_identify */ 526*0Sstevel@tonic-gate nulldev, /* devo_probe */ 527*0Sstevel@tonic-gate ecpp_attach, /* devo_attach */ 528*0Sstevel@tonic-gate ecpp_detach, /* devo_detach */ 529*0Sstevel@tonic-gate nodev, /* devo_reset */ 530*0Sstevel@tonic-gate &ecpp_cb_ops, /* devo_cb_ops */ 531*0Sstevel@tonic-gate (struct bus_ops *)NULL, /* devo_bus_ops */ 532*0Sstevel@tonic-gate nulldev /* devo_power */ 533*0Sstevel@tonic-gate }; 534*0Sstevel@tonic-gate 535*0Sstevel@tonic-gate extern struct mod_ops mod_driverops; 536*0Sstevel@tonic-gate 537*0Sstevel@tonic-gate static struct modldrv ecppmodldrv = { 538*0Sstevel@tonic-gate &mod_driverops, /* type of module - driver */ 539*0Sstevel@tonic-gate "parallel port driver %I%", 540*0Sstevel@tonic-gate &ecpp_ops, 541*0Sstevel@tonic-gate }; 542*0Sstevel@tonic-gate 543*0Sstevel@tonic-gate static struct modlinkage ecppmodlinkage = { 544*0Sstevel@tonic-gate MODREV_1, 545*0Sstevel@tonic-gate &ecppmodldrv, 546*0Sstevel@tonic-gate 0 547*0Sstevel@tonic-gate }; 548*0Sstevel@tonic-gate 549*0Sstevel@tonic-gate 550*0Sstevel@tonic-gate /* 551*0Sstevel@tonic-gate * 552*0Sstevel@tonic-gate * DDI/DKI entry points and supplementary routines 553*0Sstevel@tonic-gate * 554*0Sstevel@tonic-gate */ 555*0Sstevel@tonic-gate 556*0Sstevel@tonic-gate 557*0Sstevel@tonic-gate int 558*0Sstevel@tonic-gate _init(void) 559*0Sstevel@tonic-gate { 560*0Sstevel@tonic-gate int error; 561*0Sstevel@tonic-gate 562*0Sstevel@tonic-gate if ((error = mod_install(&ecppmodlinkage)) == 0) { 563*0Sstevel@tonic-gate (void) ddi_soft_state_init(&ecppsoft_statep, 564*0Sstevel@tonic-gate sizeof (struct ecppunit), 1); 565*0Sstevel@tonic-gate } 566*0Sstevel@tonic-gate 567*0Sstevel@tonic-gate return (error); 568*0Sstevel@tonic-gate } 569*0Sstevel@tonic-gate 570*0Sstevel@tonic-gate int 571*0Sstevel@tonic-gate _fini(void) 572*0Sstevel@tonic-gate { 573*0Sstevel@tonic-gate int error; 574*0Sstevel@tonic-gate 575*0Sstevel@tonic-gate if ((error = mod_remove(&ecppmodlinkage)) == 0) { 576*0Sstevel@tonic-gate ddi_soft_state_fini(&ecppsoft_statep); 577*0Sstevel@tonic-gate } 578*0Sstevel@tonic-gate 579*0Sstevel@tonic-gate return (error); 580*0Sstevel@tonic-gate } 581*0Sstevel@tonic-gate 582*0Sstevel@tonic-gate int 583*0Sstevel@tonic-gate _info(struct modinfo *modinfop) 584*0Sstevel@tonic-gate { 585*0Sstevel@tonic-gate return (mod_info(&ecppmodlinkage, modinfop)); 586*0Sstevel@tonic-gate } 587*0Sstevel@tonic-gate 588*0Sstevel@tonic-gate static int 589*0Sstevel@tonic-gate ecpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 590*0Sstevel@tonic-gate { 591*0Sstevel@tonic-gate int instance; 592*0Sstevel@tonic-gate char name[16]; 593*0Sstevel@tonic-gate struct ecppunit *pp; 594*0Sstevel@tonic-gate struct ecpp_hw_bind *hw_bind; 595*0Sstevel@tonic-gate 596*0Sstevel@tonic-gate instance = ddi_get_instance(dip); 597*0Sstevel@tonic-gate 598*0Sstevel@tonic-gate switch (cmd) { 599*0Sstevel@tonic-gate case DDI_ATTACH: 600*0Sstevel@tonic-gate break; 601*0Sstevel@tonic-gate 602*0Sstevel@tonic-gate case DDI_RESUME: 603*0Sstevel@tonic-gate if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) { 604*0Sstevel@tonic-gate return (DDI_FAILURE); 605*0Sstevel@tonic-gate } 606*0Sstevel@tonic-gate 607*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 608*0Sstevel@tonic-gate 609*0Sstevel@tonic-gate pp->suspended = FALSE; 610*0Sstevel@tonic-gate 611*0Sstevel@tonic-gate /* 612*0Sstevel@tonic-gate * Initialize the chip and restore current mode if needed 613*0Sstevel@tonic-gate */ 614*0Sstevel@tonic-gate (void) ECPP_CONFIG_CHIP(pp); 615*0Sstevel@tonic-gate (void) ecpp_reset_port_regs(pp); 616*0Sstevel@tonic-gate 617*0Sstevel@tonic-gate if (pp->oflag == TRUE) { 618*0Sstevel@tonic-gate int current_mode = pp->current_mode; 619*0Sstevel@tonic-gate 620*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 621*0Sstevel@tonic-gate (void) ecpp_mode_negotiation(pp, current_mode); 622*0Sstevel@tonic-gate } 623*0Sstevel@tonic-gate 624*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 625*0Sstevel@tonic-gate 626*0Sstevel@tonic-gate return (DDI_SUCCESS); 627*0Sstevel@tonic-gate 628*0Sstevel@tonic-gate default: 629*0Sstevel@tonic-gate return (DDI_FAILURE); 630*0Sstevel@tonic-gate } 631*0Sstevel@tonic-gate 632*0Sstevel@tonic-gate if (ddi_soft_state_zalloc(ecppsoft_statep, instance) != 0) { 633*0Sstevel@tonic-gate ecpp_error(dip, "ddi_soft_state_zalloc failed\n"); 634*0Sstevel@tonic-gate goto fail; 635*0Sstevel@tonic-gate } 636*0Sstevel@tonic-gate 637*0Sstevel@tonic-gate pp = ddi_get_soft_state(ecppsoft_statep, instance); 638*0Sstevel@tonic-gate 639*0Sstevel@tonic-gate pp->dip = dip; 640*0Sstevel@tonic-gate pp->suspended = FALSE; 641*0Sstevel@tonic-gate 642*0Sstevel@tonic-gate /* 643*0Sstevel@tonic-gate * Determine SuperIO type and set chip-dependent variables 644*0Sstevel@tonic-gate */ 645*0Sstevel@tonic-gate hw_bind = ecpp_determine_sio_type(pp); 646*0Sstevel@tonic-gate 647*0Sstevel@tonic-gate if (hw_bind == NULL) { 648*0Sstevel@tonic-gate cmn_err(CE_NOTE, "parallel port controller not supported"); 649*0Sstevel@tonic-gate goto fail_sio; 650*0Sstevel@tonic-gate } else { 651*0Sstevel@tonic-gate pp->hw = hw_bind->hw; 652*0Sstevel@tonic-gate ecpp_error(pp->dip, "SuperIO type: %s\n", hw_bind->info); 653*0Sstevel@tonic-gate } 654*0Sstevel@tonic-gate 655*0Sstevel@tonic-gate /* 656*0Sstevel@tonic-gate * Map registers 657*0Sstevel@tonic-gate */ 658*0Sstevel@tonic-gate if (ECPP_MAP_REGS(pp) != SUCCESS) { 659*0Sstevel@tonic-gate goto fail_map; 660*0Sstevel@tonic-gate } 661*0Sstevel@tonic-gate 662*0Sstevel@tonic-gate if (ddi_dma_alloc_handle(dip, pp->hw->attr, DDI_DMA_DONTWAIT, 663*0Sstevel@tonic-gate NULL, &pp->dma_handle) != DDI_SUCCESS) { 664*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: failed ddi_dma_alloc_handle\n"); 665*0Sstevel@tonic-gate goto fail_dma; 666*0Sstevel@tonic-gate } 667*0Sstevel@tonic-gate 668*0Sstevel@tonic-gate if (ddi_get_iblock_cookie(dip, 0, 669*0Sstevel@tonic-gate &pp->ecpp_trap_cookie) != DDI_SUCCESS) { 670*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: failed ddi_get_iblock_cookie\n"); 671*0Sstevel@tonic-gate goto fail_ibc; 672*0Sstevel@tonic-gate } 673*0Sstevel@tonic-gate 674*0Sstevel@tonic-gate mutex_init(&pp->umutex, NULL, MUTEX_DRIVER, 675*0Sstevel@tonic-gate (void *)pp->ecpp_trap_cookie); 676*0Sstevel@tonic-gate 677*0Sstevel@tonic-gate cv_init(&pp->pport_cv, NULL, CV_DRIVER, NULL); 678*0Sstevel@tonic-gate 679*0Sstevel@tonic-gate if (ddi_add_intr(dip, 0, &pp->ecpp_trap_cookie, NULL, ecpp_isr, 680*0Sstevel@tonic-gate (caddr_t)pp) != DDI_SUCCESS) { 681*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: failed to add hard intr\n"); 682*0Sstevel@tonic-gate goto fail_intr; 683*0Sstevel@tonic-gate } 684*0Sstevel@tonic-gate 685*0Sstevel@tonic-gate if (ddi_add_softintr(dip, DDI_SOFTINT_LOW, 686*0Sstevel@tonic-gate &pp->softintr_id, 0, 0, ecpp_softintr, 687*0Sstevel@tonic-gate (caddr_t)pp) != DDI_SUCCESS) { 688*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: failed to add soft intr\n"); 689*0Sstevel@tonic-gate goto fail_softintr; 690*0Sstevel@tonic-gate } 691*0Sstevel@tonic-gate 692*0Sstevel@tonic-gate (void) sprintf(name, "ecpp%d", instance); 693*0Sstevel@tonic-gate 694*0Sstevel@tonic-gate if (ddi_create_minor_node(dip, name, S_IFCHR, instance, 695*0Sstevel@tonic-gate DDI_NT_PRINTER, NULL) == DDI_FAILURE) { 696*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: create_minor_node failed\n"); 697*0Sstevel@tonic-gate goto fail_minor; 698*0Sstevel@tonic-gate } 699*0Sstevel@tonic-gate 700*0Sstevel@tonic-gate pp->ioblock = (caddr_t)kmem_alloc(IO_BLOCK_SZ, KM_SLEEP); 701*0Sstevel@tonic-gate if (pp->ioblock == NULL) { 702*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: kmem_alloc failed\n"); 703*0Sstevel@tonic-gate goto fail_iob; 704*0Sstevel@tonic-gate } else { 705*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_attach: ioblock=0x%x\n", pp->ioblock); 706*0Sstevel@tonic-gate } 707*0Sstevel@tonic-gate 708*0Sstevel@tonic-gate ecpp_get_props(pp); 709*0Sstevel@tonic-gate #if defined(__x86) 710*0Sstevel@tonic-gate if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) { 711*0Sstevel@tonic-gate if (ddi_dmae_alloc(dip, pp->uh.x86.chn, 712*0Sstevel@tonic-gate DDI_DMA_DONTWAIT, NULL) == DDI_SUCCESS) 713*0Sstevel@tonic-gate ecpp_error(pp->dip, "dmae_alloc success!\n"); 714*0Sstevel@tonic-gate } 715*0Sstevel@tonic-gate #endif 716*0Sstevel@tonic-gate if (ECPP_CONFIG_CHIP(pp) == FAILURE) { 717*0Sstevel@tonic-gate ecpp_error(pp->dip, "config_chip failed.\n"); 718*0Sstevel@tonic-gate goto fail_config; 719*0Sstevel@tonic-gate } 720*0Sstevel@tonic-gate 721*0Sstevel@tonic-gate ecpp_kstat_init(pp); 722*0Sstevel@tonic-gate 723*0Sstevel@tonic-gate ddi_report_dev(dip); 724*0Sstevel@tonic-gate 725*0Sstevel@tonic-gate return (DDI_SUCCESS); 726*0Sstevel@tonic-gate 727*0Sstevel@tonic-gate fail_config: 728*0Sstevel@tonic-gate ddi_prop_remove_all(dip); 729*0Sstevel@tonic-gate kmem_free(pp->ioblock, IO_BLOCK_SZ); 730*0Sstevel@tonic-gate fail_iob: 731*0Sstevel@tonic-gate ddi_remove_minor_node(dip, NULL); 732*0Sstevel@tonic-gate fail_minor: 733*0Sstevel@tonic-gate ddi_remove_softintr(pp->softintr_id); 734*0Sstevel@tonic-gate fail_softintr: 735*0Sstevel@tonic-gate ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie); 736*0Sstevel@tonic-gate fail_intr: 737*0Sstevel@tonic-gate mutex_destroy(&pp->umutex); 738*0Sstevel@tonic-gate cv_destroy(&pp->pport_cv); 739*0Sstevel@tonic-gate fail_ibc: 740*0Sstevel@tonic-gate ddi_dma_free_handle(&pp->dma_handle); 741*0Sstevel@tonic-gate fail_dma: 742*0Sstevel@tonic-gate ECPP_UNMAP_REGS(pp); 743*0Sstevel@tonic-gate fail_map: 744*0Sstevel@tonic-gate fail_sio: 745*0Sstevel@tonic-gate ddi_soft_state_free(ecppsoft_statep, instance); 746*0Sstevel@tonic-gate fail: 747*0Sstevel@tonic-gate ecpp_error(dip, "ecpp_attach: failed.\n"); 748*0Sstevel@tonic-gate 749*0Sstevel@tonic-gate return (DDI_FAILURE); 750*0Sstevel@tonic-gate } 751*0Sstevel@tonic-gate 752*0Sstevel@tonic-gate static int 753*0Sstevel@tonic-gate ecpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 754*0Sstevel@tonic-gate { 755*0Sstevel@tonic-gate int instance; 756*0Sstevel@tonic-gate struct ecppunit *pp; 757*0Sstevel@tonic-gate 758*0Sstevel@tonic-gate instance = ddi_get_instance(dip); 759*0Sstevel@tonic-gate 760*0Sstevel@tonic-gate switch (cmd) { 761*0Sstevel@tonic-gate case DDI_DETACH: 762*0Sstevel@tonic-gate break; 763*0Sstevel@tonic-gate 764*0Sstevel@tonic-gate case DDI_SUSPEND: 765*0Sstevel@tonic-gate if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) { 766*0Sstevel@tonic-gate return (DDI_FAILURE); 767*0Sstevel@tonic-gate } 768*0Sstevel@tonic-gate 769*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 770*0Sstevel@tonic-gate ASSERT(pp->suspended == FALSE); 771*0Sstevel@tonic-gate 772*0Sstevel@tonic-gate pp->suspended = TRUE; /* prevent new transfers */ 773*0Sstevel@tonic-gate 774*0Sstevel@tonic-gate /* 775*0Sstevel@tonic-gate * Wait if there's any activity on the port 776*0Sstevel@tonic-gate */ 777*0Sstevel@tonic-gate if ((pp->e_busy == ECPP_BUSY) || (pp->e_busy == ECPP_FLUSH)) { 778*0Sstevel@tonic-gate (void) cv_timedwait(&pp->pport_cv, &pp->umutex, 779*0Sstevel@tonic-gate ddi_get_lbolt() + 780*0Sstevel@tonic-gate SUSPEND_TOUT * drv_usectohz(1000000)); 781*0Sstevel@tonic-gate if ((pp->e_busy == ECPP_BUSY) || 782*0Sstevel@tonic-gate (pp->e_busy == ECPP_FLUSH)) { 783*0Sstevel@tonic-gate pp->suspended = FALSE; 784*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 785*0Sstevel@tonic-gate ecpp_error(pp->dip, 786*0Sstevel@tonic-gate "ecpp_detach: suspend timeout\n"); 787*0Sstevel@tonic-gate return (DDI_FAILURE); 788*0Sstevel@tonic-gate } 789*0Sstevel@tonic-gate } 790*0Sstevel@tonic-gate 791*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 792*0Sstevel@tonic-gate return (DDI_SUCCESS); 793*0Sstevel@tonic-gate 794*0Sstevel@tonic-gate default: 795*0Sstevel@tonic-gate return (DDI_FAILURE); 796*0Sstevel@tonic-gate } 797*0Sstevel@tonic-gate 798*0Sstevel@tonic-gate pp = ddi_get_soft_state(ecppsoft_statep, instance); 799*0Sstevel@tonic-gate #if defined(__x86) 800*0Sstevel@tonic-gate if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) 801*0Sstevel@tonic-gate (void) ddi_dmae_release(pp->dip, pp->uh.x86.chn); 802*0Sstevel@tonic-gate #endif 803*0Sstevel@tonic-gate if (pp->dma_handle != NULL) 804*0Sstevel@tonic-gate ddi_dma_free_handle(&pp->dma_handle); 805*0Sstevel@tonic-gate 806*0Sstevel@tonic-gate ddi_remove_minor_node(dip, NULL); 807*0Sstevel@tonic-gate 808*0Sstevel@tonic-gate ddi_remove_softintr(pp->softintr_id); 809*0Sstevel@tonic-gate 810*0Sstevel@tonic-gate ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie); 811*0Sstevel@tonic-gate 812*0Sstevel@tonic-gate if (pp->ksp) { 813*0Sstevel@tonic-gate kstat_delete(pp->ksp); 814*0Sstevel@tonic-gate } 815*0Sstevel@tonic-gate if (pp->intrstats) { 816*0Sstevel@tonic-gate kstat_delete(pp->intrstats); 817*0Sstevel@tonic-gate } 818*0Sstevel@tonic-gate 819*0Sstevel@tonic-gate cv_destroy(&pp->pport_cv); 820*0Sstevel@tonic-gate 821*0Sstevel@tonic-gate mutex_destroy(&pp->umutex); 822*0Sstevel@tonic-gate 823*0Sstevel@tonic-gate ECPP_UNMAP_REGS(pp); 824*0Sstevel@tonic-gate 825*0Sstevel@tonic-gate kmem_free(pp->ioblock, IO_BLOCK_SZ); 826*0Sstevel@tonic-gate 827*0Sstevel@tonic-gate ddi_prop_remove_all(dip); 828*0Sstevel@tonic-gate 829*0Sstevel@tonic-gate ddi_soft_state_free(ecppsoft_statep, instance); 830*0Sstevel@tonic-gate 831*0Sstevel@tonic-gate return (DDI_SUCCESS); 832*0Sstevel@tonic-gate 833*0Sstevel@tonic-gate } 834*0Sstevel@tonic-gate 835*0Sstevel@tonic-gate /* 836*0Sstevel@tonic-gate * ecpp_get_props() reads ecpp.conf for user defineable tuneables. 837*0Sstevel@tonic-gate * If the file or a particular variable is not there, a default value 838*0Sstevel@tonic-gate * is assigned. 839*0Sstevel@tonic-gate */ 840*0Sstevel@tonic-gate 841*0Sstevel@tonic-gate static void 842*0Sstevel@tonic-gate ecpp_get_props(struct ecppunit *pp) 843*0Sstevel@tonic-gate { 844*0Sstevel@tonic-gate char *prop; 845*0Sstevel@tonic-gate #if defined(__x86) 846*0Sstevel@tonic-gate int len; 847*0Sstevel@tonic-gate int value; 848*0Sstevel@tonic-gate #endif 849*0Sstevel@tonic-gate /* 850*0Sstevel@tonic-gate * If fast_centronics is TRUE, non-compliant IEEE 1284 851*0Sstevel@tonic-gate * peripherals ( Centronics peripherals) will operate in DMA mode. 852*0Sstevel@tonic-gate * Transfers betwee main memory and the device will be via DMA; 853*0Sstevel@tonic-gate * peripheral handshaking will be conducted by superio logic. 854*0Sstevel@tonic-gate * If ecpp can not read the variable correctly fast_centronics will 855*0Sstevel@tonic-gate * be set to FALSE. In this case, transfers and handshaking 856*0Sstevel@tonic-gate * will be conducted by PIO for Centronics devices. 857*0Sstevel@tonic-gate */ 858*0Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 859*0Sstevel@tonic-gate "fast-centronics", &prop) == DDI_PROP_SUCCESS) { 860*0Sstevel@tonic-gate pp->fast_centronics = 861*0Sstevel@tonic-gate (strcmp(prop, "true") == 0) ? TRUE : FALSE; 862*0Sstevel@tonic-gate ddi_prop_free(prop); 863*0Sstevel@tonic-gate } else { 864*0Sstevel@tonic-gate pp->fast_centronics = FALSE; 865*0Sstevel@tonic-gate } 866*0Sstevel@tonic-gate 867*0Sstevel@tonic-gate /* 868*0Sstevel@tonic-gate * If fast-1284-compatible is set to TRUE, when ecpp communicates 869*0Sstevel@tonic-gate * with IEEE 1284 compliant peripherals, data transfers between 870*0Sstevel@tonic-gate * main memory and the parallel port will be conducted by DMA. 871*0Sstevel@tonic-gate * Handshaking between the port and peripheral will be conducted 872*0Sstevel@tonic-gate * by superio logic. This is the default characteristic. If 873*0Sstevel@tonic-gate * fast-1284-compatible is set to FALSE, transfers and handshaking 874*0Sstevel@tonic-gate * will be conducted by PIO. 875*0Sstevel@tonic-gate */ 876*0Sstevel@tonic-gate 877*0Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 878*0Sstevel@tonic-gate "fast-1284-compatible", &prop) == DDI_PROP_SUCCESS) { 879*0Sstevel@tonic-gate pp->fast_compat = (strcmp(prop, "true") == 0) ? TRUE : FALSE; 880*0Sstevel@tonic-gate ddi_prop_free(prop); 881*0Sstevel@tonic-gate } else { 882*0Sstevel@tonic-gate pp->fast_compat = TRUE; 883*0Sstevel@tonic-gate } 884*0Sstevel@tonic-gate 885*0Sstevel@tonic-gate /* 886*0Sstevel@tonic-gate * Some centronics peripherals require the nInit signal to be 887*0Sstevel@tonic-gate * toggled to reset the device. If centronics_init_seq is set 888*0Sstevel@tonic-gate * to TRUE, ecpp will toggle the nInit signal upon every ecpp_open(). 889*0Sstevel@tonic-gate * Applications have the opportunity to toggle the nInit signal 890*0Sstevel@tonic-gate * with ioctl(2) calls as well. The default is to set it to FALSE. 891*0Sstevel@tonic-gate */ 892*0Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0, 893*0Sstevel@tonic-gate "centronics-init-seq", &prop) == DDI_PROP_SUCCESS) { 894*0Sstevel@tonic-gate pp->init_seq = (strcmp(prop, "true") == 0) ? TRUE : FALSE; 895*0Sstevel@tonic-gate ddi_prop_free(prop); 896*0Sstevel@tonic-gate } else { 897*0Sstevel@tonic-gate pp->init_seq = FALSE; 898*0Sstevel@tonic-gate } 899*0Sstevel@tonic-gate 900*0Sstevel@tonic-gate /* 901*0Sstevel@tonic-gate * If one of the centronics status signals are in an erroneous 902*0Sstevel@tonic-gate * state, ecpp_wsrv() will be reinvoked centronics-retry ms to 903*0Sstevel@tonic-gate * check if the status is ok to transfer. If the property is not 904*0Sstevel@tonic-gate * found, wsrv_retry will be set to CENTRONICS_RETRY ms. 905*0Sstevel@tonic-gate */ 906*0Sstevel@tonic-gate pp->wsrv_retry = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 907*0Sstevel@tonic-gate "centronics-retry", CENTRONICS_RETRY); 908*0Sstevel@tonic-gate 909*0Sstevel@tonic-gate /* 910*0Sstevel@tonic-gate * In PIO mode, ecpp_isr() will loop for wait for the busy signal 911*0Sstevel@tonic-gate * to be deasserted before transferring the next byte. wait_for_busy 912*0Sstevel@tonic-gate * is specificied in microseconds. If the property is not found 913*0Sstevel@tonic-gate * ecpp_isr() will wait for a maximum of WAIT_FOR_BUSY us. 914*0Sstevel@tonic-gate */ 915*0Sstevel@tonic-gate pp->wait_for_busy = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 916*0Sstevel@tonic-gate "centronics-wait-for-busy", WAIT_FOR_BUSY); 917*0Sstevel@tonic-gate 918*0Sstevel@tonic-gate /* 919*0Sstevel@tonic-gate * In PIO mode, centronics transfers must hold the data signals 920*0Sstevel@tonic-gate * for a data_setup_time milliseconds before the strobe is asserted. 921*0Sstevel@tonic-gate */ 922*0Sstevel@tonic-gate pp->data_setup_time = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 923*0Sstevel@tonic-gate "centronics-data-setup-time", DATA_SETUP_TIME); 924*0Sstevel@tonic-gate 925*0Sstevel@tonic-gate /* 926*0Sstevel@tonic-gate * In PIO mode, centronics transfers asserts the strobe signal 927*0Sstevel@tonic-gate * for a period of strobe_pulse_width milliseconds. 928*0Sstevel@tonic-gate */ 929*0Sstevel@tonic-gate pp->strobe_pulse_width = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 930*0Sstevel@tonic-gate "centronics-strobe-pulse-width", STROBE_PULSE_WIDTH); 931*0Sstevel@tonic-gate 932*0Sstevel@tonic-gate /* 933*0Sstevel@tonic-gate * Upon a transfer the peripheral, ecpp waits write_timeout seconds 934*0Sstevel@tonic-gate * for the transmission to complete. 935*0Sstevel@tonic-gate */ 936*0Sstevel@tonic-gate default_xfer_parms.write_timeout = ddi_prop_get_int(DDI_DEV_T_ANY, 937*0Sstevel@tonic-gate pp->dip, 0, "ecpp-transfer-timeout", ecpp_def_timeout); 938*0Sstevel@tonic-gate 939*0Sstevel@tonic-gate pp->xfer_parms = default_xfer_parms; 940*0Sstevel@tonic-gate 941*0Sstevel@tonic-gate /* 942*0Sstevel@tonic-gate * Get dma channel for M1553 943*0Sstevel@tonic-gate */ 944*0Sstevel@tonic-gate if (pp->hw == &m1553) { 945*0Sstevel@tonic-gate pp->uh.m1553.chn = ddi_prop_get_int(DDI_DEV_T_ANY, 946*0Sstevel@tonic-gate pp->dip, 0, "dma-channel", 0x1); 947*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_get_prop:chn=%x\n", pp->uh.m1553.chn); 948*0Sstevel@tonic-gate } 949*0Sstevel@tonic-gate #if defined(__x86) 950*0Sstevel@tonic-gate len = sizeof (value); 951*0Sstevel@tonic-gate /* Get dma channel for i86 pc */ 952*0Sstevel@tonic-gate if (pp->hw == &x86) { 953*0Sstevel@tonic-gate if (ddi_prop_op(DDI_DEV_T_ANY, pp->dip, PROP_LEN_AND_VAL_BUF, 954*0Sstevel@tonic-gate DDI_PROP_DONTPASS, "dma-channels", (caddr_t)&value, &len) 955*0Sstevel@tonic-gate != DDI_PROP_SUCCESS) { 956*0Sstevel@tonic-gate ecpp_error(pp->dip, "No dma channel found\n"); 957*0Sstevel@tonic-gate pp->uh.x86.chn = 0xff; 958*0Sstevel@tonic-gate pp->fast_compat = FALSE; 959*0Sstevel@tonic-gate pp->noecpregs = TRUE; 960*0Sstevel@tonic-gate } else 961*0Sstevel@tonic-gate pp->uh.x86.chn = (uint8_t)value; 962*0Sstevel@tonic-gate } 963*0Sstevel@tonic-gate #endif 964*0Sstevel@tonic-gate /* 965*0Sstevel@tonic-gate * these properties are not yet public 966*0Sstevel@tonic-gate */ 967*0Sstevel@tonic-gate pp->ecp_rev_speed = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 968*0Sstevel@tonic-gate "ecp-rev-speed", ECP_REV_SPEED); 969*0Sstevel@tonic-gate 970*0Sstevel@tonic-gate pp->rev_watchdog = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0, 971*0Sstevel@tonic-gate "rev-watchdog", REV_WATCHDOG); 972*0Sstevel@tonic-gate 973*0Sstevel@tonic-gate ecpp_error(pp->dip, 974*0Sstevel@tonic-gate "ecpp_get_prop: fast_centronics=%x, fast-1284=%x\n" 975*0Sstevel@tonic-gate "ecpp_get_prop: wsrv_retry=%d, wait_for_busy=%d\n" 976*0Sstevel@tonic-gate "ecpp_get_prop: data_setup=%d, strobe_pulse=%d\n" 977*0Sstevel@tonic-gate "ecpp_get_prop: transfer-timeout=%d\n", 978*0Sstevel@tonic-gate pp->fast_centronics, pp->fast_compat, 979*0Sstevel@tonic-gate pp->wsrv_retry, pp->wait_for_busy, 980*0Sstevel@tonic-gate pp->data_setup_time, pp->strobe_pulse_width, 981*0Sstevel@tonic-gate pp->xfer_parms.write_timeout); 982*0Sstevel@tonic-gate } 983*0Sstevel@tonic-gate 984*0Sstevel@tonic-gate /*ARGSUSED*/ 985*0Sstevel@tonic-gate int 986*0Sstevel@tonic-gate ecpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 987*0Sstevel@tonic-gate { 988*0Sstevel@tonic-gate dev_t dev = (dev_t)arg; 989*0Sstevel@tonic-gate struct ecppunit *pp; 990*0Sstevel@tonic-gate int instance, ret; 991*0Sstevel@tonic-gate 992*0Sstevel@tonic-gate instance = getminor(dev); 993*0Sstevel@tonic-gate 994*0Sstevel@tonic-gate switch (infocmd) { 995*0Sstevel@tonic-gate case DDI_INFO_DEVT2DEVINFO: 996*0Sstevel@tonic-gate pp = ddi_get_soft_state(ecppsoft_statep, instance); 997*0Sstevel@tonic-gate if (pp != NULL) { 998*0Sstevel@tonic-gate *result = pp->dip; 999*0Sstevel@tonic-gate ret = DDI_SUCCESS; 1000*0Sstevel@tonic-gate } else { 1001*0Sstevel@tonic-gate ret = DDI_FAILURE; 1002*0Sstevel@tonic-gate } 1003*0Sstevel@tonic-gate break; 1004*0Sstevel@tonic-gate 1005*0Sstevel@tonic-gate case DDI_INFO_DEVT2INSTANCE: 1006*0Sstevel@tonic-gate *result = (void *)(uintptr_t)instance; 1007*0Sstevel@tonic-gate ret = DDI_SUCCESS; 1008*0Sstevel@tonic-gate break; 1009*0Sstevel@tonic-gate 1010*0Sstevel@tonic-gate default: 1011*0Sstevel@tonic-gate ret = DDI_FAILURE; 1012*0Sstevel@tonic-gate break; 1013*0Sstevel@tonic-gate } 1014*0Sstevel@tonic-gate 1015*0Sstevel@tonic-gate return (ret); 1016*0Sstevel@tonic-gate } 1017*0Sstevel@tonic-gate 1018*0Sstevel@tonic-gate /*ARGSUSED2*/ 1019*0Sstevel@tonic-gate static int 1020*0Sstevel@tonic-gate ecpp_open(queue_t *q, dev_t *dev, int flag, int sflag, cred_t *credp) 1021*0Sstevel@tonic-gate { 1022*0Sstevel@tonic-gate struct ecppunit *pp; 1023*0Sstevel@tonic-gate int instance; 1024*0Sstevel@tonic-gate struct stroptions *sop; 1025*0Sstevel@tonic-gate mblk_t *mop; 1026*0Sstevel@tonic-gate 1027*0Sstevel@tonic-gate instance = getminor(*dev); 1028*0Sstevel@tonic-gate 1029*0Sstevel@tonic-gate if (instance < 0) { 1030*0Sstevel@tonic-gate return (ENXIO); 1031*0Sstevel@tonic-gate } 1032*0Sstevel@tonic-gate 1033*0Sstevel@tonic-gate pp = (struct ecppunit *)ddi_get_soft_state(ecppsoft_statep, instance); 1034*0Sstevel@tonic-gate 1035*0Sstevel@tonic-gate if (pp == NULL) { 1036*0Sstevel@tonic-gate return (ENXIO); 1037*0Sstevel@tonic-gate } 1038*0Sstevel@tonic-gate 1039*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1040*0Sstevel@tonic-gate 1041*0Sstevel@tonic-gate /* 1042*0Sstevel@tonic-gate * Parallel port is an exclusive-use device 1043*0Sstevel@tonic-gate * thus providing print job integrity 1044*0Sstevel@tonic-gate */ 1045*0Sstevel@tonic-gate if (pp->oflag == TRUE) { 1046*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp open failed"); 1047*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1048*0Sstevel@tonic-gate return (EBUSY); 1049*0Sstevel@tonic-gate } 1050*0Sstevel@tonic-gate 1051*0Sstevel@tonic-gate pp->oflag = TRUE; 1052*0Sstevel@tonic-gate 1053*0Sstevel@tonic-gate /* initialize state variables */ 1054*0Sstevel@tonic-gate pp->prn_timeouts = prn_timeouts_default; 1055*0Sstevel@tonic-gate pp->xfer_parms = default_xfer_parms; 1056*0Sstevel@tonic-gate pp->current_mode = ECPP_CENTRONICS; 1057*0Sstevel@tonic-gate pp->backchannel = ECPP_CENTRONICS; 1058*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_PO; 1059*0Sstevel@tonic-gate pp->port = ECPP_PORT_DMA; 1060*0Sstevel@tonic-gate pp->instance = instance; 1061*0Sstevel@tonic-gate pp->timeout_error = 0; 1062*0Sstevel@tonic-gate pp->saved_dsr = DSR_READ(pp); 1063*0Sstevel@tonic-gate pp->ecpp_drain_counter = 0; 1064*0Sstevel@tonic-gate pp->dma_cancelled = FALSE; 1065*0Sstevel@tonic-gate pp->io_mode = ECPP_DMA; 1066*0Sstevel@tonic-gate pp->joblen = 0; 1067*0Sstevel@tonic-gate pp->tfifo_intr = 0; 1068*0Sstevel@tonic-gate pp->softintr_pending = 0; 1069*0Sstevel@tonic-gate pp->nread = 0; 1070*0Sstevel@tonic-gate 1071*0Sstevel@tonic-gate /* clear the state flag */ 1072*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 1073*0Sstevel@tonic-gate 1074*0Sstevel@tonic-gate pp->readq = RD(q); 1075*0Sstevel@tonic-gate pp->writeq = WR(q); 1076*0Sstevel@tonic-gate pp->msg = NULL; 1077*0Sstevel@tonic-gate 1078*0Sstevel@tonic-gate RD(q)->q_ptr = WR(q)->q_ptr = (caddr_t)pp; 1079*0Sstevel@tonic-gate 1080*0Sstevel@tonic-gate /* 1081*0Sstevel@tonic-gate * Get ready: check host/peripheral, negotiate into default mode 1082*0Sstevel@tonic-gate */ 1083*0Sstevel@tonic-gate if (ecpp_reset_port_regs(pp) == FAILURE) { 1084*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1085*0Sstevel@tonic-gate return (EIO); 1086*0Sstevel@tonic-gate } 1087*0Sstevel@tonic-gate 1088*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1089*0Sstevel@tonic-gate 1090*0Sstevel@tonic-gate /* 1091*0Sstevel@tonic-gate * Configure the Stream head and enable the Stream 1092*0Sstevel@tonic-gate */ 1093*0Sstevel@tonic-gate if (!(mop = allocb(sizeof (struct stroptions), BPRI_MED))) { 1094*0Sstevel@tonic-gate return (EAGAIN); 1095*0Sstevel@tonic-gate } 1096*0Sstevel@tonic-gate 1097*0Sstevel@tonic-gate mop->b_datap->db_type = M_SETOPTS; 1098*0Sstevel@tonic-gate mop->b_wptr += sizeof (struct stroptions); 1099*0Sstevel@tonic-gate 1100*0Sstevel@tonic-gate /* 1101*0Sstevel@tonic-gate * if device is open with O_NONBLOCK flag set, let read(2) return 0 1102*0Sstevel@tonic-gate * if no data waiting to be read. Writes will block on flow control. 1103*0Sstevel@tonic-gate */ 1104*0Sstevel@tonic-gate sop = (struct stroptions *)mop->b_rptr; 1105*0Sstevel@tonic-gate sop->so_flags = SO_HIWAT | SO_LOWAT | SO_NDELON | SO_MREADON; 1106*0Sstevel@tonic-gate sop->so_hiwat = ECPPHIWAT; 1107*0Sstevel@tonic-gate sop->so_lowat = ECPPLOWAT; 1108*0Sstevel@tonic-gate 1109*0Sstevel@tonic-gate /* enable the stream */ 1110*0Sstevel@tonic-gate qprocson(q); 1111*0Sstevel@tonic-gate 1112*0Sstevel@tonic-gate putnext(q, mop); 1113*0Sstevel@tonic-gate 1114*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1115*0Sstevel@tonic-gate 1116*0Sstevel@tonic-gate ecpp_default_negotiation(pp); 1117*0Sstevel@tonic-gate 1118*0Sstevel@tonic-gate /* go revidle */ 1119*0Sstevel@tonic-gate (void) ecpp_idle_phase(pp); 1120*0Sstevel@tonic-gate 1121*0Sstevel@tonic-gate ecpp_error(pp->dip, 1122*0Sstevel@tonic-gate "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n", 1123*0Sstevel@tonic-gate pp->current_mode, pp->current_phase, 1124*0Sstevel@tonic-gate ECR_READ(pp), DSR_READ(pp), DCR_READ(pp)); 1125*0Sstevel@tonic-gate 1126*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1127*0Sstevel@tonic-gate 1128*0Sstevel@tonic-gate return (0); 1129*0Sstevel@tonic-gate } 1130*0Sstevel@tonic-gate 1131*0Sstevel@tonic-gate /*ARGSUSED1*/ 1132*0Sstevel@tonic-gate static int 1133*0Sstevel@tonic-gate ecpp_close(queue_t *q, int flag, cred_t *cred_p) 1134*0Sstevel@tonic-gate { 1135*0Sstevel@tonic-gate struct ecppunit *pp; 1136*0Sstevel@tonic-gate timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id; 1137*0Sstevel@tonic-gate 1138*0Sstevel@tonic-gate pp = (struct ecppunit *)q->q_ptr; 1139*0Sstevel@tonic-gate 1140*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_close: entering ...\n"); 1141*0Sstevel@tonic-gate 1142*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1143*0Sstevel@tonic-gate 1144*0Sstevel@tonic-gate /* 1145*0Sstevel@tonic-gate * ecpp_close() will continue to loop until the 1146*0Sstevel@tonic-gate * queue has been drained or if the thread 1147*0Sstevel@tonic-gate * has received a SIG. Typically, when the queue 1148*0Sstevel@tonic-gate * has data, the port will be ECPP_BUSY. However, 1149*0Sstevel@tonic-gate * after a dma completes and before the wsrv 1150*0Sstevel@tonic-gate * starts the next transfer, the port may be IDLE. 1151*0Sstevel@tonic-gate * In this case, ecpp_close() will loop within this 1152*0Sstevel@tonic-gate * while(qsize) segment. Since, ecpp_wsrv() runs 1153*0Sstevel@tonic-gate * at software interupt level, this shouldn't loop 1154*0Sstevel@tonic-gate * very long. 1155*0Sstevel@tonic-gate */ 1156*0Sstevel@tonic-gate while (pp->e_busy != ECPP_IDLE || qsize(WR(q))) { 1157*0Sstevel@tonic-gate if (!cv_wait_sig(&pp->pport_cv, &pp->umutex)) { 1158*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_close:B: received SIG\n"); 1159*0Sstevel@tonic-gate /* 1160*0Sstevel@tonic-gate * Returning from a signal such as 1161*0Sstevel@tonic-gate * SIGTERM or SIGKILL 1162*0Sstevel@tonic-gate */ 1163*0Sstevel@tonic-gate ecpp_flush(pp, FWRITE); 1164*0Sstevel@tonic-gate break; 1165*0Sstevel@tonic-gate } else { 1166*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_close:rcvd cv-sig\n"); 1167*0Sstevel@tonic-gate } 1168*0Sstevel@tonic-gate } 1169*0Sstevel@tonic-gate 1170*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_close: joblen=%d, ctx_cf=%d, " 1171*0Sstevel@tonic-gate "qsize(WR(q))=%d, qsize(RD(q))=%d\n", 1172*0Sstevel@tonic-gate pp->joblen, pp->ctx_cf, qsize(pp->writeq), qsize(q)); 1173*0Sstevel@tonic-gate 1174*0Sstevel@tonic-gate /* 1175*0Sstevel@tonic-gate * Cancel all timeouts, disable interrupts 1176*0Sstevel@tonic-gate * 1177*0Sstevel@tonic-gate * Note that we can`t call untimeout(9F) with mutex held: 1178*0Sstevel@tonic-gate * callout may be blocked on the same mutex, and untimeout() will 1179*0Sstevel@tonic-gate * cv_wait() while callout is executing, thus creating a deadlock 1180*0Sstevel@tonic-gate * So we zero the timeout id's inside mutex and call untimeout later 1181*0Sstevel@tonic-gate */ 1182*0Sstevel@tonic-gate timeout_id = pp->timeout_id; 1183*0Sstevel@tonic-gate fifo_timer_id = pp->fifo_timer_id; 1184*0Sstevel@tonic-gate wsrv_timer_id = pp->wsrv_timer_id; 1185*0Sstevel@tonic-gate 1186*0Sstevel@tonic-gate pp->timeout_id = pp->fifo_timer_id = pp->wsrv_timer_id = 0; 1187*0Sstevel@tonic-gate 1188*0Sstevel@tonic-gate pp->softintr_pending = 0; 1189*0Sstevel@tonic-gate pp->dma_cancelled = TRUE; 1190*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 1191*0Sstevel@tonic-gate 1192*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1193*0Sstevel@tonic-gate 1194*0Sstevel@tonic-gate qprocsoff(q); 1195*0Sstevel@tonic-gate 1196*0Sstevel@tonic-gate if (timeout_id) { 1197*0Sstevel@tonic-gate (void) untimeout(timeout_id); 1198*0Sstevel@tonic-gate } 1199*0Sstevel@tonic-gate if (fifo_timer_id) { 1200*0Sstevel@tonic-gate (void) untimeout(fifo_timer_id); 1201*0Sstevel@tonic-gate } 1202*0Sstevel@tonic-gate if (wsrv_timer_id) { 1203*0Sstevel@tonic-gate (void) untimeout(wsrv_timer_id); 1204*0Sstevel@tonic-gate } 1205*0Sstevel@tonic-gate 1206*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1207*0Sstevel@tonic-gate 1208*0Sstevel@tonic-gate /* set link to Compatible mode */ 1209*0Sstevel@tonic-gate if ((pp->current_mode == ECPP_ECP_MODE) && 1210*0Sstevel@tonic-gate (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) { 1211*0Sstevel@tonic-gate (void) ecp_reverse2forward(pp); 1212*0Sstevel@tonic-gate } 1213*0Sstevel@tonic-gate 1214*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 1215*0Sstevel@tonic-gate 1216*0Sstevel@tonic-gate pp->oflag = FALSE; 1217*0Sstevel@tonic-gate q->q_ptr = WR(q)->q_ptr = NULL; 1218*0Sstevel@tonic-gate pp->readq = pp->writeq = NULL; 1219*0Sstevel@tonic-gate pp->msg = NULL; 1220*0Sstevel@tonic-gate 1221*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n", 1222*0Sstevel@tonic-gate ECR_READ(pp), DSR_READ(pp), DCR_READ(pp)); 1223*0Sstevel@tonic-gate 1224*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1225*0Sstevel@tonic-gate 1226*0Sstevel@tonic-gate return (0); 1227*0Sstevel@tonic-gate } 1228*0Sstevel@tonic-gate 1229*0Sstevel@tonic-gate /* 1230*0Sstevel@tonic-gate * standard put procedure for ecpp 1231*0Sstevel@tonic-gate */ 1232*0Sstevel@tonic-gate static int 1233*0Sstevel@tonic-gate ecpp_wput(queue_t *q, mblk_t *mp) 1234*0Sstevel@tonic-gate { 1235*0Sstevel@tonic-gate struct msgb *nmp; 1236*0Sstevel@tonic-gate struct ecppunit *pp; 1237*0Sstevel@tonic-gate 1238*0Sstevel@tonic-gate pp = (struct ecppunit *)q->q_ptr; 1239*0Sstevel@tonic-gate 1240*0Sstevel@tonic-gate if (!mp) { 1241*0Sstevel@tonic-gate return (0); 1242*0Sstevel@tonic-gate } 1243*0Sstevel@tonic-gate 1244*0Sstevel@tonic-gate if ((mp->b_wptr - mp->b_rptr) <= 0) { 1245*0Sstevel@tonic-gate ecpp_error(pp->dip, 1246*0Sstevel@tonic-gate "ecpp_wput:bogus packet recieved mp=%x\n", mp); 1247*0Sstevel@tonic-gate freemsg(mp); 1248*0Sstevel@tonic-gate return (0); 1249*0Sstevel@tonic-gate } 1250*0Sstevel@tonic-gate 1251*0Sstevel@tonic-gate switch (DB_TYPE(mp)) { 1252*0Sstevel@tonic-gate case M_DATA: 1253*0Sstevel@tonic-gate /* 1254*0Sstevel@tonic-gate * This is a quick fix for multiple message block problem, 1255*0Sstevel@tonic-gate * it will be changed later with better performance code. 1256*0Sstevel@tonic-gate */ 1257*0Sstevel@tonic-gate if (mp->b_cont) { 1258*0Sstevel@tonic-gate /* 1259*0Sstevel@tonic-gate * mblk has scattered data ... do msgpullup 1260*0Sstevel@tonic-gate * if it fails, continue with the current mblk 1261*0Sstevel@tonic-gate */ 1262*0Sstevel@tonic-gate if ((nmp = msgpullup(mp, -1)) != NULL) { 1263*0Sstevel@tonic-gate freemsg(mp); 1264*0Sstevel@tonic-gate mp = nmp; 1265*0Sstevel@tonic-gate ecpp_error(pp->dip, 1266*0Sstevel@tonic-gate "ecpp_wput:msgpullup: mp=%p len=%d\n", 1267*0Sstevel@tonic-gate mp, mp->b_wptr - mp->b_rptr); 1268*0Sstevel@tonic-gate } 1269*0Sstevel@tonic-gate } 1270*0Sstevel@tonic-gate 1271*0Sstevel@tonic-gate /* let ecpp_wsrv() concatenate small blocks */ 1272*0Sstevel@tonic-gate (void) putq(q, mp); 1273*0Sstevel@tonic-gate 1274*0Sstevel@tonic-gate break; 1275*0Sstevel@tonic-gate 1276*0Sstevel@tonic-gate case M_CTL: 1277*0Sstevel@tonic-gate (void) putq(q, mp); 1278*0Sstevel@tonic-gate 1279*0Sstevel@tonic-gate break; 1280*0Sstevel@tonic-gate 1281*0Sstevel@tonic-gate case M_IOCTL: { 1282*0Sstevel@tonic-gate struct iocblk *iocbp; 1283*0Sstevel@tonic-gate 1284*0Sstevel@tonic-gate iocbp = (struct iocblk *)mp->b_rptr; 1285*0Sstevel@tonic-gate 1286*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput:M_IOCTL %x\n", iocbp->ioc_cmd); 1287*0Sstevel@tonic-gate 1288*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1289*0Sstevel@tonic-gate 1290*0Sstevel@tonic-gate /* TESTIO and GET_STATUS can be used during transfer */ 1291*0Sstevel@tonic-gate if ((pp->e_busy == ECPP_BUSY) && 1292*0Sstevel@tonic-gate (iocbp->ioc_cmd != BPPIOC_TESTIO) && 1293*0Sstevel@tonic-gate (iocbp->ioc_cmd != PRNIOC_GET_STATUS)) { 1294*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1295*0Sstevel@tonic-gate (void) putq(q, mp); 1296*0Sstevel@tonic-gate } else { 1297*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1298*0Sstevel@tonic-gate ecpp_putioc(q, mp); 1299*0Sstevel@tonic-gate } 1300*0Sstevel@tonic-gate 1301*0Sstevel@tonic-gate break; 1302*0Sstevel@tonic-gate } 1303*0Sstevel@tonic-gate 1304*0Sstevel@tonic-gate case M_IOCDATA: { 1305*0Sstevel@tonic-gate struct copyresp *csp; 1306*0Sstevel@tonic-gate 1307*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput:M_IOCDATA\n"); 1308*0Sstevel@tonic-gate 1309*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 1310*0Sstevel@tonic-gate 1311*0Sstevel@tonic-gate /* 1312*0Sstevel@tonic-gate * If copy request failed, quit now 1313*0Sstevel@tonic-gate */ 1314*0Sstevel@tonic-gate if (csp->cp_rval != 0) { 1315*0Sstevel@tonic-gate freemsg(mp); 1316*0Sstevel@tonic-gate return (0); 1317*0Sstevel@tonic-gate } 1318*0Sstevel@tonic-gate 1319*0Sstevel@tonic-gate switch (csp->cp_cmd) { 1320*0Sstevel@tonic-gate case ECPPIOC_SETPARMS: 1321*0Sstevel@tonic-gate case ECPPIOC_SETREGS: 1322*0Sstevel@tonic-gate case ECPPIOC_SETPORT: 1323*0Sstevel@tonic-gate case ECPPIOC_SETDATA: 1324*0Sstevel@tonic-gate case PRNIOC_SET_IFCAP: 1325*0Sstevel@tonic-gate case PRNIOC_SET_TIMEOUTS: 1326*0Sstevel@tonic-gate /* 1327*0Sstevel@tonic-gate * need to retrieve and use the data, but if the 1328*0Sstevel@tonic-gate * device is busy, wait. 1329*0Sstevel@tonic-gate */ 1330*0Sstevel@tonic-gate (void) putq(q, mp); 1331*0Sstevel@tonic-gate break; 1332*0Sstevel@tonic-gate 1333*0Sstevel@tonic-gate case ECPPIOC_GETPARMS: 1334*0Sstevel@tonic-gate case ECPPIOC_GETREGS: 1335*0Sstevel@tonic-gate case ECPPIOC_GETPORT: 1336*0Sstevel@tonic-gate case ECPPIOC_GETDATA: 1337*0Sstevel@tonic-gate case BPPIOC_GETERR: 1338*0Sstevel@tonic-gate case BPPIOC_TESTIO: 1339*0Sstevel@tonic-gate case PRNIOC_GET_IFCAP: 1340*0Sstevel@tonic-gate case PRNIOC_GET_STATUS: 1341*0Sstevel@tonic-gate case PRNIOC_GET_1284_STATUS: 1342*0Sstevel@tonic-gate case PRNIOC_GET_TIMEOUTS: 1343*0Sstevel@tonic-gate /* data transfered to user space okay */ 1344*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 1345*0Sstevel@tonic-gate break; 1346*0Sstevel@tonic-gate 1347*0Sstevel@tonic-gate case ECPPIOC_GETDEVID: 1348*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(q, mp, 1349*0Sstevel@tonic-gate offsetof(struct ecpp_device_id, rlen)); 1350*0Sstevel@tonic-gate break; 1351*0Sstevel@tonic-gate 1352*0Sstevel@tonic-gate case PRNIOC_GET_1284_DEVID: 1353*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(q, mp, 1354*0Sstevel@tonic-gate offsetof(struct prn_1284_device_id, id_rlen)); 1355*0Sstevel@tonic-gate break; 1356*0Sstevel@tonic-gate 1357*0Sstevel@tonic-gate case PRNIOC_GET_IFINFO: 1358*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(q, mp, 1359*0Sstevel@tonic-gate offsetof(struct prn_interface_info, if_rlen)); 1360*0Sstevel@tonic-gate break; 1361*0Sstevel@tonic-gate 1362*0Sstevel@tonic-gate default: 1363*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1364*0Sstevel@tonic-gate break; 1365*0Sstevel@tonic-gate } 1366*0Sstevel@tonic-gate 1367*0Sstevel@tonic-gate break; 1368*0Sstevel@tonic-gate } 1369*0Sstevel@tonic-gate 1370*0Sstevel@tonic-gate case M_FLUSH: 1371*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput:M_FLUSH\n"); 1372*0Sstevel@tonic-gate 1373*0Sstevel@tonic-gate if (*mp->b_rptr & FLUSHW) { 1374*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1375*0Sstevel@tonic-gate ecpp_flush(pp, FWRITE); 1376*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1377*0Sstevel@tonic-gate } 1378*0Sstevel@tonic-gate 1379*0Sstevel@tonic-gate if (*mp->b_rptr & FLUSHR) { 1380*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1381*0Sstevel@tonic-gate ecpp_flush(pp, FREAD); 1382*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1383*0Sstevel@tonic-gate qreply(q, mp); 1384*0Sstevel@tonic-gate } else { 1385*0Sstevel@tonic-gate freemsg(mp); 1386*0Sstevel@tonic-gate } 1387*0Sstevel@tonic-gate 1388*0Sstevel@tonic-gate break; 1389*0Sstevel@tonic-gate 1390*0Sstevel@tonic-gate case M_READ: 1391*0Sstevel@tonic-gate /* 1392*0Sstevel@tonic-gate * When the user calls read(2), M_READ message is sent to us, 1393*0Sstevel@tonic-gate * first byte of which is the number of requested bytes 1394*0Sstevel@tonic-gate * We add up user requests and use resulting number 1395*0Sstevel@tonic-gate * to calculate the reverse transfer block size 1396*0Sstevel@tonic-gate */ 1397*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1398*0Sstevel@tonic-gate if (pp->e_busy == ECPP_IDLE) { 1399*0Sstevel@tonic-gate pp->nread += *(size_t *)mp->b_rptr; 1400*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput: M_READ %d", pp->nread); 1401*0Sstevel@tonic-gate freemsg(mp); 1402*0Sstevel@tonic-gate } else { 1403*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput: M_READ queueing"); 1404*0Sstevel@tonic-gate (void) putq(q, mp); 1405*0Sstevel@tonic-gate } 1406*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1407*0Sstevel@tonic-gate break; 1408*0Sstevel@tonic-gate 1409*0Sstevel@tonic-gate default: 1410*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wput: bad messagetype 0x%x\n", 1411*0Sstevel@tonic-gate DB_TYPE(mp)); 1412*0Sstevel@tonic-gate freemsg(mp); 1413*0Sstevel@tonic-gate break; 1414*0Sstevel@tonic-gate } 1415*0Sstevel@tonic-gate 1416*0Sstevel@tonic-gate return (0); 1417*0Sstevel@tonic-gate } 1418*0Sstevel@tonic-gate 1419*0Sstevel@tonic-gate /* 1420*0Sstevel@tonic-gate * Process ECPPIOC_GETDEVID-like ioctls 1421*0Sstevel@tonic-gate */ 1422*0Sstevel@tonic-gate static void 1423*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(queue_t *q, mblk_t *mp, uintptr_t rlen_offset) 1424*0Sstevel@tonic-gate { 1425*0Sstevel@tonic-gate struct copyresp *csp; 1426*0Sstevel@tonic-gate struct ecpp_copystate *stp; 1427*0Sstevel@tonic-gate mblk_t *datamp; 1428*0Sstevel@tonic-gate 1429*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 1430*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)csp->cp_private->b_rptr; 1431*0Sstevel@tonic-gate 1432*0Sstevel@tonic-gate /* determine the state of copyin/copyout process */ 1433*0Sstevel@tonic-gate switch (stp->state) { 1434*0Sstevel@tonic-gate case ECPP_STRUCTIN: 1435*0Sstevel@tonic-gate /* user structure has arrived */ 1436*0Sstevel@tonic-gate (void) putq(q, mp); 1437*0Sstevel@tonic-gate break; 1438*0Sstevel@tonic-gate 1439*0Sstevel@tonic-gate case ECPP_ADDROUT: 1440*0Sstevel@tonic-gate /* 1441*0Sstevel@tonic-gate * data transfered to user space okay 1442*0Sstevel@tonic-gate * now update user structure 1443*0Sstevel@tonic-gate */ 1444*0Sstevel@tonic-gate datamp = allocb(sizeof (int), BPRI_MED); 1445*0Sstevel@tonic-gate if (datamp == NULL) { 1446*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, ENOSR); 1447*0Sstevel@tonic-gate break; 1448*0Sstevel@tonic-gate } 1449*0Sstevel@tonic-gate 1450*0Sstevel@tonic-gate *(int *)datamp->b_rptr = 1451*0Sstevel@tonic-gate *(int *)((char *)&stp->un + rlen_offset); 1452*0Sstevel@tonic-gate stp->state = ECPP_STRUCTOUT; 1453*0Sstevel@tonic-gate 1454*0Sstevel@tonic-gate mcopyout(mp, csp->cp_private, sizeof (int), 1455*0Sstevel@tonic-gate (char *)stp->uaddr + rlen_offset, datamp); 1456*0Sstevel@tonic-gate qreply(q, mp); 1457*0Sstevel@tonic-gate break; 1458*0Sstevel@tonic-gate 1459*0Sstevel@tonic-gate case ECPP_STRUCTOUT: 1460*0Sstevel@tonic-gate /* user structure was updated okay */ 1461*0Sstevel@tonic-gate freemsg(csp->cp_private); 1462*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 1463*0Sstevel@tonic-gate break; 1464*0Sstevel@tonic-gate 1465*0Sstevel@tonic-gate default: 1466*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1467*0Sstevel@tonic-gate break; 1468*0Sstevel@tonic-gate } 1469*0Sstevel@tonic-gate } 1470*0Sstevel@tonic-gate 1471*0Sstevel@tonic-gate static uchar_t 1472*0Sstevel@tonic-gate ecpp_get_error_status(uchar_t status) 1473*0Sstevel@tonic-gate { 1474*0Sstevel@tonic-gate uchar_t pin_status = 0; 1475*0Sstevel@tonic-gate 1476*0Sstevel@tonic-gate if (!(status & ECPP_nERR)) { 1477*0Sstevel@tonic-gate pin_status |= BPP_ERR_ERR; 1478*0Sstevel@tonic-gate } 1479*0Sstevel@tonic-gate 1480*0Sstevel@tonic-gate if (status & ECPP_PE) { 1481*0Sstevel@tonic-gate pin_status |= BPP_PE_ERR; 1482*0Sstevel@tonic-gate } 1483*0Sstevel@tonic-gate 1484*0Sstevel@tonic-gate if (!(status & ECPP_SLCT)) { 1485*0Sstevel@tonic-gate pin_status |= BPP_SLCT_ERR; 1486*0Sstevel@tonic-gate } 1487*0Sstevel@tonic-gate 1488*0Sstevel@tonic-gate if (!(status & ECPP_nBUSY)) { 1489*0Sstevel@tonic-gate pin_status |= BPP_SLCT_ERR; 1490*0Sstevel@tonic-gate } 1491*0Sstevel@tonic-gate 1492*0Sstevel@tonic-gate return (pin_status); 1493*0Sstevel@tonic-gate } 1494*0Sstevel@tonic-gate 1495*0Sstevel@tonic-gate /* 1496*0Sstevel@tonic-gate * ioctl handler for output PUT procedure. 1497*0Sstevel@tonic-gate */ 1498*0Sstevel@tonic-gate static void 1499*0Sstevel@tonic-gate ecpp_putioc(queue_t *q, mblk_t *mp) 1500*0Sstevel@tonic-gate { 1501*0Sstevel@tonic-gate struct iocblk *iocbp; 1502*0Sstevel@tonic-gate struct ecppunit *pp; 1503*0Sstevel@tonic-gate 1504*0Sstevel@tonic-gate pp = (struct ecppunit *)q->q_ptr; 1505*0Sstevel@tonic-gate 1506*0Sstevel@tonic-gate iocbp = (struct iocblk *)mp->b_rptr; 1507*0Sstevel@tonic-gate 1508*0Sstevel@tonic-gate /* I_STR ioctls are invalid */ 1509*0Sstevel@tonic-gate if (iocbp->ioc_count != TRANSPARENT) { 1510*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1511*0Sstevel@tonic-gate return; 1512*0Sstevel@tonic-gate } 1513*0Sstevel@tonic-gate 1514*0Sstevel@tonic-gate switch (iocbp->ioc_cmd) { 1515*0Sstevel@tonic-gate case ECPPIOC_SETPARMS: { 1516*0Sstevel@tonic-gate mcopyin(mp, NULL, sizeof (struct ecpp_transfer_parms), NULL); 1517*0Sstevel@tonic-gate qreply(q, mp); 1518*0Sstevel@tonic-gate break; 1519*0Sstevel@tonic-gate } 1520*0Sstevel@tonic-gate 1521*0Sstevel@tonic-gate case ECPPIOC_GETPARMS: { 1522*0Sstevel@tonic-gate struct ecpp_transfer_parms xfer_parms; 1523*0Sstevel@tonic-gate 1524*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1525*0Sstevel@tonic-gate 1526*0Sstevel@tonic-gate pp->xfer_parms.mode = pp->current_mode; 1527*0Sstevel@tonic-gate xfer_parms = pp->xfer_parms; 1528*0Sstevel@tonic-gate 1529*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1530*0Sstevel@tonic-gate 1531*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &xfer_parms, sizeof (xfer_parms)); 1532*0Sstevel@tonic-gate break; 1533*0Sstevel@tonic-gate } 1534*0Sstevel@tonic-gate 1535*0Sstevel@tonic-gate case ECPPIOC_SETREGS: { 1536*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1537*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 1538*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1539*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1540*0Sstevel@tonic-gate break; 1541*0Sstevel@tonic-gate } 1542*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1543*0Sstevel@tonic-gate 1544*0Sstevel@tonic-gate mcopyin(mp, NULL, sizeof (struct ecpp_regs), NULL); 1545*0Sstevel@tonic-gate qreply(q, mp); 1546*0Sstevel@tonic-gate break; 1547*0Sstevel@tonic-gate } 1548*0Sstevel@tonic-gate 1549*0Sstevel@tonic-gate case ECPPIOC_GETREGS: { 1550*0Sstevel@tonic-gate struct ecpp_regs rg; 1551*0Sstevel@tonic-gate 1552*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1553*0Sstevel@tonic-gate 1554*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 1555*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1556*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1557*0Sstevel@tonic-gate break; 1558*0Sstevel@tonic-gate } 1559*0Sstevel@tonic-gate 1560*0Sstevel@tonic-gate rg.dsr = DSR_READ(pp); 1561*0Sstevel@tonic-gate rg.dcr = DCR_READ(pp); 1562*0Sstevel@tonic-gate 1563*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1564*0Sstevel@tonic-gate 1565*0Sstevel@tonic-gate ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n", 1566*0Sstevel@tonic-gate rg.dsr, rg.dcr); 1567*0Sstevel@tonic-gate 1568*0Sstevel@tonic-gate /* these bits must be 1 */ 1569*0Sstevel@tonic-gate rg.dsr |= ECPP_SETREGS_DSR_MASK; 1570*0Sstevel@tonic-gate rg.dcr |= ECPP_SETREGS_DCR_MASK; 1571*0Sstevel@tonic-gate 1572*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &rg, sizeof (rg)); 1573*0Sstevel@tonic-gate break; 1574*0Sstevel@tonic-gate } 1575*0Sstevel@tonic-gate 1576*0Sstevel@tonic-gate case ECPPIOC_SETPORT: 1577*0Sstevel@tonic-gate case ECPPIOC_SETDATA: { 1578*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1579*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 1580*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1581*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1582*0Sstevel@tonic-gate break; 1583*0Sstevel@tonic-gate } 1584*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1585*0Sstevel@tonic-gate 1586*0Sstevel@tonic-gate /* 1587*0Sstevel@tonic-gate * each of the commands fetches a byte quantity. 1588*0Sstevel@tonic-gate */ 1589*0Sstevel@tonic-gate mcopyin(mp, NULL, sizeof (uchar_t), NULL); 1590*0Sstevel@tonic-gate qreply(q, mp); 1591*0Sstevel@tonic-gate break; 1592*0Sstevel@tonic-gate } 1593*0Sstevel@tonic-gate 1594*0Sstevel@tonic-gate case ECPPIOC_GETDATA: 1595*0Sstevel@tonic-gate case ECPPIOC_GETPORT: { 1596*0Sstevel@tonic-gate uchar_t byte; 1597*0Sstevel@tonic-gate 1598*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1599*0Sstevel@tonic-gate 1600*0Sstevel@tonic-gate /* must be in diagnostic mode for these commands to work */ 1601*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 1602*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1603*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1604*0Sstevel@tonic-gate break; 1605*0Sstevel@tonic-gate } 1606*0Sstevel@tonic-gate 1607*0Sstevel@tonic-gate if (iocbp->ioc_cmd == ECPPIOC_GETPORT) { 1608*0Sstevel@tonic-gate byte = pp->port; 1609*0Sstevel@tonic-gate } else if (iocbp->ioc_cmd == ECPPIOC_GETDATA) { 1610*0Sstevel@tonic-gate switch (pp->port) { 1611*0Sstevel@tonic-gate case ECPP_PORT_PIO: 1612*0Sstevel@tonic-gate byte = DATAR_READ(pp); 1613*0Sstevel@tonic-gate break; 1614*0Sstevel@tonic-gate case ECPP_PORT_TDMA: 1615*0Sstevel@tonic-gate byte = TFIFO_READ(pp); 1616*0Sstevel@tonic-gate ecpp_error(pp->dip, "GETDATA=0x%x\n", byte); 1617*0Sstevel@tonic-gate break; 1618*0Sstevel@tonic-gate default: 1619*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1620*0Sstevel@tonic-gate break; 1621*0Sstevel@tonic-gate } 1622*0Sstevel@tonic-gate } else { 1623*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1624*0Sstevel@tonic-gate ecpp_error(pp->dip, "weird command"); 1625*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1626*0Sstevel@tonic-gate break; 1627*0Sstevel@tonic-gate } 1628*0Sstevel@tonic-gate 1629*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1630*0Sstevel@tonic-gate 1631*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &byte, sizeof (byte)); 1632*0Sstevel@tonic-gate 1633*0Sstevel@tonic-gate break; 1634*0Sstevel@tonic-gate } 1635*0Sstevel@tonic-gate 1636*0Sstevel@tonic-gate case BPPIOC_GETERR: { 1637*0Sstevel@tonic-gate struct bpp_error_status bpp_status; 1638*0Sstevel@tonic-gate 1639*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1640*0Sstevel@tonic-gate 1641*0Sstevel@tonic-gate bpp_status.timeout_occurred = pp->timeout_error; 1642*0Sstevel@tonic-gate bpp_status.bus_error = 0; /* not used */ 1643*0Sstevel@tonic-gate bpp_status.pin_status = ecpp_get_error_status(pp->saved_dsr); 1644*0Sstevel@tonic-gate 1645*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1646*0Sstevel@tonic-gate 1647*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &bpp_status, sizeof (bpp_status)); 1648*0Sstevel@tonic-gate 1649*0Sstevel@tonic-gate break; 1650*0Sstevel@tonic-gate } 1651*0Sstevel@tonic-gate 1652*0Sstevel@tonic-gate case BPPIOC_TESTIO: { 1653*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1654*0Sstevel@tonic-gate 1655*0Sstevel@tonic-gate if (!((pp->current_mode == ECPP_CENTRONICS) || 1656*0Sstevel@tonic-gate (pp->current_mode == ECPP_COMPAT_MODE))) { 1657*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1658*0Sstevel@tonic-gate } else { 1659*0Sstevel@tonic-gate pp->saved_dsr = DSR_READ(pp); 1660*0Sstevel@tonic-gate 1661*0Sstevel@tonic-gate if ((pp->saved_dsr & ECPP_PE) || 1662*0Sstevel@tonic-gate !(pp->saved_dsr & ECPP_SLCT) || 1663*0Sstevel@tonic-gate !(pp->saved_dsr & ECPP_nERR)) { 1664*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EIO); 1665*0Sstevel@tonic-gate } else { 1666*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 1667*0Sstevel@tonic-gate } 1668*0Sstevel@tonic-gate } 1669*0Sstevel@tonic-gate 1670*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1671*0Sstevel@tonic-gate 1672*0Sstevel@tonic-gate break; 1673*0Sstevel@tonic-gate } 1674*0Sstevel@tonic-gate 1675*0Sstevel@tonic-gate case PRNIOC_RESET: 1676*0Sstevel@tonic-gate /* 1677*0Sstevel@tonic-gate * Initialize interface only if no transfer is in progress 1678*0Sstevel@tonic-gate */ 1679*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1680*0Sstevel@tonic-gate if (pp->e_busy == ECPP_BUSY) { 1681*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1682*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EIO); 1683*0Sstevel@tonic-gate } else { 1684*0Sstevel@tonic-gate (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS); 1685*0Sstevel@tonic-gate 1686*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN); 1687*0Sstevel@tonic-gate drv_usecwait(2); 1688*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT); 1689*0Sstevel@tonic-gate 1690*0Sstevel@tonic-gate ecpp_default_negotiation(pp); 1691*0Sstevel@tonic-gate 1692*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1693*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 1694*0Sstevel@tonic-gate } 1695*0Sstevel@tonic-gate break; 1696*0Sstevel@tonic-gate 1697*0Sstevel@tonic-gate case PRNIOC_GET_IFCAP: { 1698*0Sstevel@tonic-gate uint_t ifcap; 1699*0Sstevel@tonic-gate 1700*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1701*0Sstevel@tonic-gate 1702*0Sstevel@tonic-gate ifcap = ecpp_get_prn_ifcap(pp); 1703*0Sstevel@tonic-gate 1704*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1705*0Sstevel@tonic-gate 1706*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &ifcap, sizeof (ifcap)); 1707*0Sstevel@tonic-gate break; 1708*0Sstevel@tonic-gate } 1709*0Sstevel@tonic-gate 1710*0Sstevel@tonic-gate case PRNIOC_SET_IFCAP: { 1711*0Sstevel@tonic-gate mcopyin(mp, NULL, sizeof (uint_t), NULL); 1712*0Sstevel@tonic-gate qreply(q, mp); 1713*0Sstevel@tonic-gate break; 1714*0Sstevel@tonic-gate } 1715*0Sstevel@tonic-gate 1716*0Sstevel@tonic-gate case PRNIOC_GET_TIMEOUTS: { 1717*0Sstevel@tonic-gate struct prn_timeouts timeouts; 1718*0Sstevel@tonic-gate 1719*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1720*0Sstevel@tonic-gate timeouts = pp->prn_timeouts; 1721*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1722*0Sstevel@tonic-gate 1723*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &timeouts, sizeof (timeouts)); 1724*0Sstevel@tonic-gate 1725*0Sstevel@tonic-gate break; 1726*0Sstevel@tonic-gate } 1727*0Sstevel@tonic-gate 1728*0Sstevel@tonic-gate case PRNIOC_SET_TIMEOUTS: 1729*0Sstevel@tonic-gate mcopyin(mp, NULL, sizeof (struct prn_timeouts), 1730*0Sstevel@tonic-gate *(caddr_t *)(void *)mp->b_cont->b_rptr); 1731*0Sstevel@tonic-gate qreply(q, mp); 1732*0Sstevel@tonic-gate break; 1733*0Sstevel@tonic-gate 1734*0Sstevel@tonic-gate case PRNIOC_GET_STATUS: { 1735*0Sstevel@tonic-gate uint8_t dsr; 1736*0Sstevel@tonic-gate uint_t status; 1737*0Sstevel@tonic-gate 1738*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1739*0Sstevel@tonic-gate 1740*0Sstevel@tonic-gate /* DSR only makes sense in Centronics & Compat mode */ 1741*0Sstevel@tonic-gate if (pp->current_mode == ECPP_CENTRONICS || 1742*0Sstevel@tonic-gate pp->current_mode == ECPP_COMPAT_MODE) { 1743*0Sstevel@tonic-gate dsr = DSR_READ(pp); 1744*0Sstevel@tonic-gate if ((dsr & ECPP_PE) || 1745*0Sstevel@tonic-gate !(dsr & ECPP_SLCT) || !(dsr & ECPP_nERR)) { 1746*0Sstevel@tonic-gate status = PRN_ONLINE; 1747*0Sstevel@tonic-gate } else { 1748*0Sstevel@tonic-gate status = PRN_ONLINE | PRN_READY; 1749*0Sstevel@tonic-gate } 1750*0Sstevel@tonic-gate } else { 1751*0Sstevel@tonic-gate status = PRN_ONLINE | PRN_READY; 1752*0Sstevel@tonic-gate } 1753*0Sstevel@tonic-gate 1754*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1755*0Sstevel@tonic-gate 1756*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &status, sizeof (status)); 1757*0Sstevel@tonic-gate break; 1758*0Sstevel@tonic-gate } 1759*0Sstevel@tonic-gate 1760*0Sstevel@tonic-gate case PRNIOC_GET_1284_STATUS: { 1761*0Sstevel@tonic-gate uint8_t dsr; 1762*0Sstevel@tonic-gate uchar_t status; 1763*0Sstevel@tonic-gate 1764*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1765*0Sstevel@tonic-gate 1766*0Sstevel@tonic-gate /* status only makes sense in Centronics & Compat mode */ 1767*0Sstevel@tonic-gate if (pp->current_mode != ECPP_COMPAT_MODE && 1768*0Sstevel@tonic-gate pp->current_mode != ECPP_CENTRONICS) { 1769*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1770*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1771*0Sstevel@tonic-gate break; 1772*0Sstevel@tonic-gate } 1773*0Sstevel@tonic-gate 1774*0Sstevel@tonic-gate dsr = DSR_READ(pp); /* read status */ 1775*0Sstevel@tonic-gate 1776*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1777*0Sstevel@tonic-gate 1778*0Sstevel@tonic-gate ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr); 1779*0Sstevel@tonic-gate 1780*0Sstevel@tonic-gate status = (dsr & (ECPP_SLCT | ECPP_PE | ECPP_nERR)) | 1781*0Sstevel@tonic-gate (~dsr & ECPP_nBUSY); 1782*0Sstevel@tonic-gate 1783*0Sstevel@tonic-gate ecpp_putioc_copyout(q, mp, &status, sizeof (status)); 1784*0Sstevel@tonic-gate break; 1785*0Sstevel@tonic-gate } 1786*0Sstevel@tonic-gate 1787*0Sstevel@tonic-gate case ECPPIOC_GETDEVID: 1788*0Sstevel@tonic-gate ecpp_putioc_stateful_copyin(q, mp, 1789*0Sstevel@tonic-gate sizeof (struct ecpp_device_id)); 1790*0Sstevel@tonic-gate break; 1791*0Sstevel@tonic-gate 1792*0Sstevel@tonic-gate case PRNIOC_GET_1284_DEVID: 1793*0Sstevel@tonic-gate ecpp_putioc_stateful_copyin(q, mp, 1794*0Sstevel@tonic-gate sizeof (struct prn_1284_device_id)); 1795*0Sstevel@tonic-gate break; 1796*0Sstevel@tonic-gate 1797*0Sstevel@tonic-gate case PRNIOC_GET_IFINFO: 1798*0Sstevel@tonic-gate ecpp_putioc_stateful_copyin(q, mp, 1799*0Sstevel@tonic-gate sizeof (struct prn_interface_info)); 1800*0Sstevel@tonic-gate break; 1801*0Sstevel@tonic-gate 1802*0Sstevel@tonic-gate default: 1803*0Sstevel@tonic-gate ecpp_error(pp->dip, "putioc: unknown IOCTL: %x\n", 1804*0Sstevel@tonic-gate iocbp->ioc_cmd); 1805*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 1806*0Sstevel@tonic-gate break; 1807*0Sstevel@tonic-gate } 1808*0Sstevel@tonic-gate } 1809*0Sstevel@tonic-gate 1810*0Sstevel@tonic-gate /* 1811*0Sstevel@tonic-gate * allocate mblk and copyout the requested number of bytes 1812*0Sstevel@tonic-gate */ 1813*0Sstevel@tonic-gate static void 1814*0Sstevel@tonic-gate ecpp_putioc_copyout(queue_t *q, mblk_t *mp, void *buf, int len) 1815*0Sstevel@tonic-gate { 1816*0Sstevel@tonic-gate mblk_t *tmp; 1817*0Sstevel@tonic-gate 1818*0Sstevel@tonic-gate if ((tmp = allocb(len, BPRI_MED)) == NULL) { 1819*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, ENOSR); 1820*0Sstevel@tonic-gate return; 1821*0Sstevel@tonic-gate } 1822*0Sstevel@tonic-gate 1823*0Sstevel@tonic-gate bcopy(buf, tmp->b_wptr, len); 1824*0Sstevel@tonic-gate 1825*0Sstevel@tonic-gate mcopyout(mp, NULL, len, NULL, tmp); 1826*0Sstevel@tonic-gate qreply(q, mp); 1827*0Sstevel@tonic-gate } 1828*0Sstevel@tonic-gate 1829*0Sstevel@tonic-gate /* 1830*0Sstevel@tonic-gate * copyin the structure using struct ecpp_copystate 1831*0Sstevel@tonic-gate */ 1832*0Sstevel@tonic-gate static void 1833*0Sstevel@tonic-gate ecpp_putioc_stateful_copyin(queue_t *q, mblk_t *mp, size_t size) 1834*0Sstevel@tonic-gate { 1835*0Sstevel@tonic-gate mblk_t *tmp; 1836*0Sstevel@tonic-gate struct ecpp_copystate *stp; 1837*0Sstevel@tonic-gate 1838*0Sstevel@tonic-gate if ((tmp = allocb(sizeof (struct ecpp_copystate), BPRI_MED)) == NULL) { 1839*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EAGAIN); 1840*0Sstevel@tonic-gate return; 1841*0Sstevel@tonic-gate } 1842*0Sstevel@tonic-gate 1843*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)tmp->b_rptr; 1844*0Sstevel@tonic-gate stp->state = ECPP_STRUCTIN; 1845*0Sstevel@tonic-gate stp->uaddr = *(caddr_t *)mp->b_cont->b_rptr; 1846*0Sstevel@tonic-gate 1847*0Sstevel@tonic-gate tmp->b_wptr += sizeof (struct ecpp_copystate); 1848*0Sstevel@tonic-gate 1849*0Sstevel@tonic-gate mcopyin(mp, tmp, size, stp->uaddr); 1850*0Sstevel@tonic-gate qreply(q, mp); 1851*0Sstevel@tonic-gate } 1852*0Sstevel@tonic-gate 1853*0Sstevel@tonic-gate /* 1854*0Sstevel@tonic-gate * read queue is only used when the peripheral sends data faster, 1855*0Sstevel@tonic-gate * then the application consumes it; 1856*0Sstevel@tonic-gate * once the low water mark is reached, this routine will be scheduled 1857*0Sstevel@tonic-gate */ 1858*0Sstevel@tonic-gate static int 1859*0Sstevel@tonic-gate ecpp_rsrv(queue_t *q) 1860*0Sstevel@tonic-gate { 1861*0Sstevel@tonic-gate struct msgb *mp; 1862*0Sstevel@tonic-gate 1863*0Sstevel@tonic-gate /* 1864*0Sstevel@tonic-gate * send data upstream until next queue is full or the queue is empty 1865*0Sstevel@tonic-gate */ 1866*0Sstevel@tonic-gate while (canputnext(q) && (mp = getq(q))) { 1867*0Sstevel@tonic-gate putnext(q, mp); 1868*0Sstevel@tonic-gate } 1869*0Sstevel@tonic-gate 1870*0Sstevel@tonic-gate /* 1871*0Sstevel@tonic-gate * if there is still space on the queue, enable backchannel 1872*0Sstevel@tonic-gate */ 1873*0Sstevel@tonic-gate if (canputnext(q)) { 1874*0Sstevel@tonic-gate struct ecppunit *pp = (struct ecppunit *)q->q_ptr; 1875*0Sstevel@tonic-gate 1876*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1877*0Sstevel@tonic-gate 1878*0Sstevel@tonic-gate if (pp->e_busy == ECPP_IDLE) { 1879*0Sstevel@tonic-gate (void) ecpp_idle_phase(pp); 1880*0Sstevel@tonic-gate cv_signal(&pp->pport_cv); /* signal ecpp_close() */ 1881*0Sstevel@tonic-gate } 1882*0Sstevel@tonic-gate 1883*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1884*0Sstevel@tonic-gate } 1885*0Sstevel@tonic-gate 1886*0Sstevel@tonic-gate return (0); 1887*0Sstevel@tonic-gate } 1888*0Sstevel@tonic-gate 1889*0Sstevel@tonic-gate static int 1890*0Sstevel@tonic-gate ecpp_wsrv(queue_t *q) 1891*0Sstevel@tonic-gate { 1892*0Sstevel@tonic-gate struct ecppunit *pp = (struct ecppunit *)q->q_ptr; 1893*0Sstevel@tonic-gate struct msgb *mp; 1894*0Sstevel@tonic-gate size_t len, total_len; 1895*0Sstevel@tonic-gate size_t my_ioblock_sz; 1896*0Sstevel@tonic-gate caddr_t my_ioblock; 1897*0Sstevel@tonic-gate caddr_t start_addr; 1898*0Sstevel@tonic-gate 1899*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 1900*0Sstevel@tonic-gate 1901*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wsrv: e_busy=%x\n", pp->e_busy); 1902*0Sstevel@tonic-gate 1903*0Sstevel@tonic-gate /* if channel is actively doing work, wait till completed */ 1904*0Sstevel@tonic-gate if (pp->e_busy == ECPP_BUSY || pp->e_busy == ECPP_FLUSH) { 1905*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1906*0Sstevel@tonic-gate return (0); 1907*0Sstevel@tonic-gate } else if (pp->suspended == TRUE) { 1908*0Sstevel@tonic-gate /* 1909*0Sstevel@tonic-gate * if the system is about to suspend and ecpp_detach() 1910*0Sstevel@tonic-gate * is blocked due to active transfers, wake it up and exit 1911*0Sstevel@tonic-gate */ 1912*0Sstevel@tonic-gate cv_signal(&pp->pport_cv); 1913*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1914*0Sstevel@tonic-gate return (0); 1915*0Sstevel@tonic-gate } 1916*0Sstevel@tonic-gate 1917*0Sstevel@tonic-gate /* peripheral status should be okay before starting transfer */ 1918*0Sstevel@tonic-gate if (pp->e_busy == ECPP_ERR) { 1919*0Sstevel@tonic-gate if (ecpp_check_status(pp) == FAILURE) { 1920*0Sstevel@tonic-gate if (pp->wsrv_timer_id == 0) { 1921*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: start wrsv_timer\n"); 1922*0Sstevel@tonic-gate pp->wsrv_timer_id = timeout(ecpp_wsrv_timer, 1923*0Sstevel@tonic-gate (caddr_t)pp, 1924*0Sstevel@tonic-gate drv_usectohz(pp->wsrv_retry * 1000)); 1925*0Sstevel@tonic-gate } else { 1926*0Sstevel@tonic-gate ecpp_error(pp->dip, 1927*0Sstevel@tonic-gate "ecpp_wsrv: wrsv_timer is active\n"); 1928*0Sstevel@tonic-gate } 1929*0Sstevel@tonic-gate 1930*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 1931*0Sstevel@tonic-gate return (0); 1932*0Sstevel@tonic-gate } else { 1933*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 1934*0Sstevel@tonic-gate } 1935*0Sstevel@tonic-gate } 1936*0Sstevel@tonic-gate 1937*0Sstevel@tonic-gate my_ioblock = pp->ioblock; 1938*0Sstevel@tonic-gate my_ioblock_sz = IO_BLOCK_SZ; 1939*0Sstevel@tonic-gate 1940*0Sstevel@tonic-gate /* 1941*0Sstevel@tonic-gate * it`s important to null pp->msg here, 1942*0Sstevel@tonic-gate * cleaning up from the previous transfer attempts 1943*0Sstevel@tonic-gate */ 1944*0Sstevel@tonic-gate pp->msg = NULL; 1945*0Sstevel@tonic-gate 1946*0Sstevel@tonic-gate start_addr = NULL; 1947*0Sstevel@tonic-gate len = total_len = 0; 1948*0Sstevel@tonic-gate /* 1949*0Sstevel@tonic-gate * The following loop is implemented to gather the 1950*0Sstevel@tonic-gate * many small writes that the lp subsystem makes and 1951*0Sstevel@tonic-gate * compile them into one large dma transfer. The len and 1952*0Sstevel@tonic-gate * total_len variables are a running count of the number of 1953*0Sstevel@tonic-gate * bytes that have been gathered. They are bcopied to the 1954*0Sstevel@tonic-gate * ioblock buffer. The pp->e_busy is set to E_BUSY as soon as 1955*0Sstevel@tonic-gate * we start gathering packets to indicate the following transfer. 1956*0Sstevel@tonic-gate */ 1957*0Sstevel@tonic-gate while (mp = getq(q)) { 1958*0Sstevel@tonic-gate switch (DB_TYPE(mp)) { 1959*0Sstevel@tonic-gate case M_DATA: 1960*0Sstevel@tonic-gate pp->e_busy = ECPP_BUSY; 1961*0Sstevel@tonic-gate len = mp->b_wptr - mp->b_rptr; 1962*0Sstevel@tonic-gate 1963*0Sstevel@tonic-gate if ((total_len == 0) && (len >= my_ioblock_sz)) { 1964*0Sstevel@tonic-gate /* 1965*0Sstevel@tonic-gate * if the first M_DATA is bigger than ioblock, 1966*0Sstevel@tonic-gate * just use this mblk and start the transfer 1967*0Sstevel@tonic-gate */ 1968*0Sstevel@tonic-gate total_len = len; 1969*0Sstevel@tonic-gate start_addr = (caddr_t)mp->b_rptr; 1970*0Sstevel@tonic-gate pp->msg = mp; 1971*0Sstevel@tonic-gate goto breakout; 1972*0Sstevel@tonic-gate } else if (total_len + len > my_ioblock_sz) { 1973*0Sstevel@tonic-gate /* 1974*0Sstevel@tonic-gate * current M_DATA does not fit in ioblock, 1975*0Sstevel@tonic-gate * put it back and start the transfer 1976*0Sstevel@tonic-gate */ 1977*0Sstevel@tonic-gate (void) putbq(q, mp); 1978*0Sstevel@tonic-gate goto breakout; 1979*0Sstevel@tonic-gate } else { 1980*0Sstevel@tonic-gate /* 1981*0Sstevel@tonic-gate * otherwise add data to ioblock and free mblk 1982*0Sstevel@tonic-gate */ 1983*0Sstevel@tonic-gate bcopy(mp->b_rptr, my_ioblock, len); 1984*0Sstevel@tonic-gate my_ioblock += len; 1985*0Sstevel@tonic-gate total_len += len; 1986*0Sstevel@tonic-gate start_addr = (caddr_t)pp->ioblock; 1987*0Sstevel@tonic-gate freemsg(mp); 1988*0Sstevel@tonic-gate } 1989*0Sstevel@tonic-gate break; 1990*0Sstevel@tonic-gate 1991*0Sstevel@tonic-gate case M_IOCTL: 1992*0Sstevel@tonic-gate /* 1993*0Sstevel@tonic-gate * Assume a simple loopback test: an application 1994*0Sstevel@tonic-gate * writes data into the TFIFO, reads it using 1995*0Sstevel@tonic-gate * ECPPIOC_GETDATA and compares. If the transfer 1996*0Sstevel@tonic-gate * times out (which is only possible on Grover), 1997*0Sstevel@tonic-gate * the ioctl might be processed before the data 1998*0Sstevel@tonic-gate * got to the TFIFO, which leads to miscompare. 1999*0Sstevel@tonic-gate * So if we met ioctl, postpone it until after xfer. 2000*0Sstevel@tonic-gate */ 2001*0Sstevel@tonic-gate if (total_len > 0) { 2002*0Sstevel@tonic-gate (void) putbq(q, mp); 2003*0Sstevel@tonic-gate goto breakout; 2004*0Sstevel@tonic-gate } 2005*0Sstevel@tonic-gate 2006*0Sstevel@tonic-gate ecpp_error(pp->dip, "M_IOCTL.\n"); 2007*0Sstevel@tonic-gate 2008*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 2009*0Sstevel@tonic-gate 2010*0Sstevel@tonic-gate ecpp_putioc(q, mp); 2011*0Sstevel@tonic-gate 2012*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 2013*0Sstevel@tonic-gate 2014*0Sstevel@tonic-gate break; 2015*0Sstevel@tonic-gate 2016*0Sstevel@tonic-gate case M_IOCDATA: { 2017*0Sstevel@tonic-gate struct copyresp *csp = (struct copyresp *)mp->b_rptr; 2018*0Sstevel@tonic-gate 2019*0Sstevel@tonic-gate ecpp_error(pp->dip, "M_IOCDATA\n"); 2020*0Sstevel@tonic-gate 2021*0Sstevel@tonic-gate /* 2022*0Sstevel@tonic-gate * If copy request failed, quit now 2023*0Sstevel@tonic-gate */ 2024*0Sstevel@tonic-gate if (csp->cp_rval != 0) { 2025*0Sstevel@tonic-gate freemsg(mp); 2026*0Sstevel@tonic-gate break; 2027*0Sstevel@tonic-gate } 2028*0Sstevel@tonic-gate 2029*0Sstevel@tonic-gate switch (csp->cp_cmd) { 2030*0Sstevel@tonic-gate case ECPPIOC_SETPARMS: 2031*0Sstevel@tonic-gate case ECPPIOC_SETREGS: 2032*0Sstevel@tonic-gate case ECPPIOC_SETPORT: 2033*0Sstevel@tonic-gate case ECPPIOC_SETDATA: 2034*0Sstevel@tonic-gate case ECPPIOC_GETDEVID: 2035*0Sstevel@tonic-gate case PRNIOC_SET_IFCAP: 2036*0Sstevel@tonic-gate case PRNIOC_GET_1284_DEVID: 2037*0Sstevel@tonic-gate case PRNIOC_SET_TIMEOUTS: 2038*0Sstevel@tonic-gate case PRNIOC_GET_IFINFO: 2039*0Sstevel@tonic-gate ecpp_srvioc(q, mp); 2040*0Sstevel@tonic-gate break; 2041*0Sstevel@tonic-gate 2042*0Sstevel@tonic-gate default: 2043*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2044*0Sstevel@tonic-gate break; 2045*0Sstevel@tonic-gate } 2046*0Sstevel@tonic-gate 2047*0Sstevel@tonic-gate break; 2048*0Sstevel@tonic-gate } 2049*0Sstevel@tonic-gate 2050*0Sstevel@tonic-gate case M_CTL: 2051*0Sstevel@tonic-gate if (pp->e_busy != ECPP_IDLE) { 2052*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: M_CTL postponed\n"); 2053*0Sstevel@tonic-gate (void) putbq(q, mp); 2054*0Sstevel@tonic-gate goto breakout; 2055*0Sstevel@tonic-gate } else { 2056*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: M_CTL\n"); 2057*0Sstevel@tonic-gate } 2058*0Sstevel@tonic-gate 2059*0Sstevel@tonic-gate /* sanity check */ 2060*0Sstevel@tonic-gate if ((mp->b_wptr - mp->b_rptr != sizeof (int)) || 2061*0Sstevel@tonic-gate (*(int *)mp->b_rptr != ECPP_BACKCHANNEL)) { 2062*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: bogus M_CTL"); 2063*0Sstevel@tonic-gate freemsg(mp); 2064*0Sstevel@tonic-gate break; 2065*0Sstevel@tonic-gate } else { 2066*0Sstevel@tonic-gate freemsg(mp); 2067*0Sstevel@tonic-gate } 2068*0Sstevel@tonic-gate 2069*0Sstevel@tonic-gate /* This was a backchannel request */ 2070*0Sstevel@tonic-gate (void) ecpp_peripheral2host(pp); 2071*0Sstevel@tonic-gate 2072*0Sstevel@tonic-gate /* exit if transfer have been initiated */ 2073*0Sstevel@tonic-gate if (pp->e_busy == ECPP_BUSY) { 2074*0Sstevel@tonic-gate goto breakout; 2075*0Sstevel@tonic-gate } 2076*0Sstevel@tonic-gate break; 2077*0Sstevel@tonic-gate 2078*0Sstevel@tonic-gate case M_READ: 2079*0Sstevel@tonic-gate pp->nread += *(size_t *)mp->b_rptr; 2080*0Sstevel@tonic-gate freemsg(mp); 2081*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: M_READ %d", pp->nread); 2082*0Sstevel@tonic-gate break; 2083*0Sstevel@tonic-gate 2084*0Sstevel@tonic-gate default: 2085*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv: should never get here\n"); 2086*0Sstevel@tonic-gate freemsg(mp); 2087*0Sstevel@tonic-gate break; 2088*0Sstevel@tonic-gate } 2089*0Sstevel@tonic-gate } 2090*0Sstevel@tonic-gate breakout: 2091*0Sstevel@tonic-gate /* 2092*0Sstevel@tonic-gate * If total_len > 0 then start the transfer, otherwise goto idle state 2093*0Sstevel@tonic-gate */ 2094*0Sstevel@tonic-gate if (total_len > 0) { 2095*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv:starting: total_len=%d\n", total_len); 2096*0Sstevel@tonic-gate pp->e_busy = ECPP_BUSY; 2097*0Sstevel@tonic-gate ecpp_start(pp, start_addr, total_len); 2098*0Sstevel@tonic-gate } else { 2099*0Sstevel@tonic-gate ecpp_error(pp->dip, "wsrv:finishing: ebusy=%x\n", pp->e_busy); 2100*0Sstevel@tonic-gate 2101*0Sstevel@tonic-gate /* IDLE if xfer_timeout, or FIFO_EMPTY */ 2102*0Sstevel@tonic-gate if (pp->e_busy == ECPP_IDLE) { 2103*0Sstevel@tonic-gate (void) ecpp_idle_phase(pp); 2104*0Sstevel@tonic-gate cv_signal(&pp->pport_cv); /* signal ecpp_close() */ 2105*0Sstevel@tonic-gate } 2106*0Sstevel@tonic-gate } 2107*0Sstevel@tonic-gate 2108*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 2109*0Sstevel@tonic-gate return (1); 2110*0Sstevel@tonic-gate } 2111*0Sstevel@tonic-gate 2112*0Sstevel@tonic-gate /* 2113*0Sstevel@tonic-gate * Ioctl processor for queued ioctl data transfer messages. 2114*0Sstevel@tonic-gate */ 2115*0Sstevel@tonic-gate static void 2116*0Sstevel@tonic-gate ecpp_srvioc(queue_t *q, mblk_t *mp) 2117*0Sstevel@tonic-gate { 2118*0Sstevel@tonic-gate struct iocblk *iocbp; 2119*0Sstevel@tonic-gate struct ecppunit *pp; 2120*0Sstevel@tonic-gate 2121*0Sstevel@tonic-gate iocbp = (struct iocblk *)mp->b_rptr; 2122*0Sstevel@tonic-gate pp = (struct ecppunit *)q->q_ptr; 2123*0Sstevel@tonic-gate 2124*0Sstevel@tonic-gate switch (iocbp->ioc_cmd) { 2125*0Sstevel@tonic-gate case ECPPIOC_SETPARMS: { 2126*0Sstevel@tonic-gate struct ecpp_transfer_parms *xferp; 2127*0Sstevel@tonic-gate 2128*0Sstevel@tonic-gate xferp = (struct ecpp_transfer_parms *)mp->b_cont->b_rptr; 2129*0Sstevel@tonic-gate 2130*0Sstevel@tonic-gate if (xferp->write_timeout <= 0 || 2131*0Sstevel@tonic-gate xferp->write_timeout >= ECPP_MAX_TIMEOUT) { 2132*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2133*0Sstevel@tonic-gate break; 2134*0Sstevel@tonic-gate } 2135*0Sstevel@tonic-gate 2136*0Sstevel@tonic-gate if (!((xferp->mode == ECPP_CENTRONICS) || 2137*0Sstevel@tonic-gate (xferp->mode == ECPP_COMPAT_MODE) || 2138*0Sstevel@tonic-gate (xferp->mode == ECPP_NIBBLE_MODE) || 2139*0Sstevel@tonic-gate (xferp->mode == ECPP_ECP_MODE) || 2140*0Sstevel@tonic-gate (xferp->mode == ECPP_DIAG_MODE))) { 2141*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2142*0Sstevel@tonic-gate break; 2143*0Sstevel@tonic-gate } 2144*0Sstevel@tonic-gate 2145*0Sstevel@tonic-gate pp->xfer_parms = *xferp; 2146*0Sstevel@tonic-gate pp->prn_timeouts.tmo_forward = pp->xfer_parms.write_timeout; 2147*0Sstevel@tonic-gate 2148*0Sstevel@tonic-gate ecpp_error(pp->dip, "srvioc: current_mode =%x new mode=%x\n", 2149*0Sstevel@tonic-gate pp->current_mode, pp->xfer_parms.mode); 2150*0Sstevel@tonic-gate 2151*0Sstevel@tonic-gate if (ecpp_mode_negotiation(pp, pp->xfer_parms.mode) == FAILURE) { 2152*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT); 2153*0Sstevel@tonic-gate } else { 2154*0Sstevel@tonic-gate /* 2155*0Sstevel@tonic-gate * mode nego was a success. If nibble mode check 2156*0Sstevel@tonic-gate * back channel and set into REVIDLE. 2157*0Sstevel@tonic-gate */ 2158*0Sstevel@tonic-gate if ((pp->current_mode == ECPP_NIBBLE_MODE) && 2159*0Sstevel@tonic-gate (read_nibble_backchan(pp) == FAILURE)) { 2160*0Sstevel@tonic-gate /* 2161*0Sstevel@tonic-gate * problems reading the backchannel 2162*0Sstevel@tonic-gate * returned to centronics; 2163*0Sstevel@tonic-gate * ioctl fails. 2164*0Sstevel@tonic-gate */ 2165*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT); 2166*0Sstevel@tonic-gate break; 2167*0Sstevel@tonic-gate } 2168*0Sstevel@tonic-gate 2169*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2170*0Sstevel@tonic-gate } 2171*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 2172*0Sstevel@tonic-gate pp->port = ECPP_PORT_DMA; 2173*0Sstevel@tonic-gate } else { 2174*0Sstevel@tonic-gate pp->port = ECPP_PORT_PIO; 2175*0Sstevel@tonic-gate } 2176*0Sstevel@tonic-gate 2177*0Sstevel@tonic-gate pp->xfer_parms.mode = pp->current_mode; 2178*0Sstevel@tonic-gate 2179*0Sstevel@tonic-gate break; 2180*0Sstevel@tonic-gate } 2181*0Sstevel@tonic-gate 2182*0Sstevel@tonic-gate case ECPPIOC_SETREGS: { 2183*0Sstevel@tonic-gate struct ecpp_regs *rg; 2184*0Sstevel@tonic-gate uint8_t dcr; 2185*0Sstevel@tonic-gate 2186*0Sstevel@tonic-gate rg = (struct ecpp_regs *)mp->b_cont->b_rptr; 2187*0Sstevel@tonic-gate 2188*0Sstevel@tonic-gate /* must be in diagnostic mode for these commands to work */ 2189*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 2190*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2191*0Sstevel@tonic-gate break; 2192*0Sstevel@tonic-gate } 2193*0Sstevel@tonic-gate 2194*0Sstevel@tonic-gate /* bits 4-7 must be 1 or return EINVAL */ 2195*0Sstevel@tonic-gate if ((rg->dcr & ECPP_SETREGS_DCR_MASK) != 2196*0Sstevel@tonic-gate ECPP_SETREGS_DCR_MASK) { 2197*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2198*0Sstevel@tonic-gate break; 2199*0Sstevel@tonic-gate } 2200*0Sstevel@tonic-gate 2201*0Sstevel@tonic-gate /* get the old dcr */ 2202*0Sstevel@tonic-gate dcr = DCR_READ(pp) & ~ECPP_REV_DIR; 2203*0Sstevel@tonic-gate /* get the new dcr */ 2204*0Sstevel@tonic-gate dcr = (dcr & ECPP_SETREGS_DCR_MASK) | 2205*0Sstevel@tonic-gate (rg->dcr & ~ECPP_SETREGS_DCR_MASK); 2206*0Sstevel@tonic-gate DCR_WRITE(pp, dcr); 2207*0Sstevel@tonic-gate ecpp_error(pp->dip, "ECPPIOC_SETREGS:dcr=%x\n", dcr); 2208*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2209*0Sstevel@tonic-gate break; 2210*0Sstevel@tonic-gate } 2211*0Sstevel@tonic-gate 2212*0Sstevel@tonic-gate case ECPPIOC_SETPORT: { 2213*0Sstevel@tonic-gate uchar_t *port; 2214*0Sstevel@tonic-gate 2215*0Sstevel@tonic-gate port = (uchar_t *)mp->b_cont->b_rptr; 2216*0Sstevel@tonic-gate 2217*0Sstevel@tonic-gate /* must be in diagnostic mode for these commands to work */ 2218*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 2219*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2220*0Sstevel@tonic-gate break; 2221*0Sstevel@tonic-gate } 2222*0Sstevel@tonic-gate 2223*0Sstevel@tonic-gate switch (*port) { 2224*0Sstevel@tonic-gate case ECPP_PORT_PIO: 2225*0Sstevel@tonic-gate /* put superio into PIO mode */ 2226*0Sstevel@tonic-gate ECR_WRITE(pp, 2227*0Sstevel@tonic-gate ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV); 2228*0Sstevel@tonic-gate pp->port = *port; 2229*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2230*0Sstevel@tonic-gate break; 2231*0Sstevel@tonic-gate 2232*0Sstevel@tonic-gate case ECPP_PORT_TDMA: 2233*0Sstevel@tonic-gate ecpp_error(pp->dip, "SETPORT: to TDMA\n"); 2234*0Sstevel@tonic-gate pp->tfifo_intr = 1; 2235*0Sstevel@tonic-gate /* change to mode 110 */ 2236*0Sstevel@tonic-gate ECR_WRITE(pp, 2237*0Sstevel@tonic-gate ECR_mode_110 | ECPP_INTR_MASK | ECPP_INTR_SRV); 2238*0Sstevel@tonic-gate pp->port = *port; 2239*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2240*0Sstevel@tonic-gate break; 2241*0Sstevel@tonic-gate 2242*0Sstevel@tonic-gate default: 2243*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2244*0Sstevel@tonic-gate } 2245*0Sstevel@tonic-gate 2246*0Sstevel@tonic-gate break; 2247*0Sstevel@tonic-gate } 2248*0Sstevel@tonic-gate 2249*0Sstevel@tonic-gate case ECPPIOC_SETDATA: { 2250*0Sstevel@tonic-gate uchar_t *data; 2251*0Sstevel@tonic-gate 2252*0Sstevel@tonic-gate data = (uchar_t *)mp->b_cont->b_rptr; 2253*0Sstevel@tonic-gate 2254*0Sstevel@tonic-gate /* must be in diagnostic mode for these commands to work */ 2255*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 2256*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2257*0Sstevel@tonic-gate break; 2258*0Sstevel@tonic-gate } 2259*0Sstevel@tonic-gate 2260*0Sstevel@tonic-gate switch (pp->port) { 2261*0Sstevel@tonic-gate case ECPP_PORT_PIO: 2262*0Sstevel@tonic-gate DATAR_WRITE(pp, *data); 2263*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2264*0Sstevel@tonic-gate break; 2265*0Sstevel@tonic-gate 2266*0Sstevel@tonic-gate case ECPP_PORT_TDMA: 2267*0Sstevel@tonic-gate TFIFO_WRITE(pp, *data); 2268*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2269*0Sstevel@tonic-gate break; 2270*0Sstevel@tonic-gate 2271*0Sstevel@tonic-gate default: 2272*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2273*0Sstevel@tonic-gate } 2274*0Sstevel@tonic-gate 2275*0Sstevel@tonic-gate break; 2276*0Sstevel@tonic-gate } 2277*0Sstevel@tonic-gate 2278*0Sstevel@tonic-gate case ECPPIOC_GETDEVID: { 2279*0Sstevel@tonic-gate struct copyresp *csp; 2280*0Sstevel@tonic-gate struct ecpp_copystate *stp; 2281*0Sstevel@tonic-gate struct ecpp_device_id *dp; 2282*0Sstevel@tonic-gate struct ecpp_device_id id; 2283*0Sstevel@tonic-gate 2284*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 2285*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)csp->cp_private->b_rptr; 2286*0Sstevel@tonic-gate dp = (struct ecpp_device_id *)mp->b_cont->b_rptr; 2287*0Sstevel@tonic-gate 2288*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2289*0Sstevel@tonic-gate if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) { 2290*0Sstevel@tonic-gate struct ecpp_device_id32 *dp32; 2291*0Sstevel@tonic-gate 2292*0Sstevel@tonic-gate dp32 = (struct ecpp_device_id32 *)dp; 2293*0Sstevel@tonic-gate id.mode = dp32->mode; 2294*0Sstevel@tonic-gate id.len = dp32->len; 2295*0Sstevel@tonic-gate id.addr = (char *)(uintptr_t)dp32->addr; 2296*0Sstevel@tonic-gate } else { 2297*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2298*0Sstevel@tonic-gate id = *dp; 2299*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2300*0Sstevel@tonic-gate } 2301*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2302*0Sstevel@tonic-gate 2303*0Sstevel@tonic-gate ecpp_srvioc_devid(q, mp, &id, &stp->un.devid.rlen); 2304*0Sstevel@tonic-gate break; 2305*0Sstevel@tonic-gate } 2306*0Sstevel@tonic-gate 2307*0Sstevel@tonic-gate case PRNIOC_GET_1284_DEVID: { 2308*0Sstevel@tonic-gate struct copyresp *csp; 2309*0Sstevel@tonic-gate struct ecpp_copystate *stp; 2310*0Sstevel@tonic-gate struct prn_1284_device_id *dp; 2311*0Sstevel@tonic-gate struct ecpp_device_id id; 2312*0Sstevel@tonic-gate 2313*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 2314*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)csp->cp_private->b_rptr; 2315*0Sstevel@tonic-gate dp = (struct prn_1284_device_id *)mp->b_cont->b_rptr; 2316*0Sstevel@tonic-gate 2317*0Sstevel@tonic-gate /* imitate struct ecpp_device_id */ 2318*0Sstevel@tonic-gate id.mode = ECPP_NIBBLE_MODE; 2319*0Sstevel@tonic-gate 2320*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2321*0Sstevel@tonic-gate if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) { 2322*0Sstevel@tonic-gate struct prn_1284_device_id32 *dp32; 2323*0Sstevel@tonic-gate 2324*0Sstevel@tonic-gate dp32 = (struct prn_1284_device_id32 *)dp; 2325*0Sstevel@tonic-gate id.len = dp32->id_len; 2326*0Sstevel@tonic-gate id.addr = (char *)(uintptr_t)dp32->id_data; 2327*0Sstevel@tonic-gate } else { 2328*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2329*0Sstevel@tonic-gate id.len = dp->id_len; 2330*0Sstevel@tonic-gate id.addr = (char *)dp->id_data; 2331*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2332*0Sstevel@tonic-gate } 2333*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2334*0Sstevel@tonic-gate 2335*0Sstevel@tonic-gate ecpp_srvioc_devid(q, mp, &id, 2336*0Sstevel@tonic-gate (int *)&stp->un.prn_devid.id_rlen); 2337*0Sstevel@tonic-gate break; 2338*0Sstevel@tonic-gate } 2339*0Sstevel@tonic-gate 2340*0Sstevel@tonic-gate case PRNIOC_SET_IFCAP: { 2341*0Sstevel@tonic-gate uint_t ifcap, new_ifcap; 2342*0Sstevel@tonic-gate 2343*0Sstevel@tonic-gate ifcap = ecpp_get_prn_ifcap(pp); 2344*0Sstevel@tonic-gate new_ifcap = *(uint_t *)mp->b_cont->b_rptr; 2345*0Sstevel@tonic-gate 2346*0Sstevel@tonic-gate if (ifcap == new_ifcap) { 2347*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2348*0Sstevel@tonic-gate break; 2349*0Sstevel@tonic-gate } 2350*0Sstevel@tonic-gate 2351*0Sstevel@tonic-gate /* only changing PRN_BIDI is supported */ 2352*0Sstevel@tonic-gate if ((ifcap ^ new_ifcap) & ~PRN_BIDI) { 2353*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2354*0Sstevel@tonic-gate break; 2355*0Sstevel@tonic-gate } 2356*0Sstevel@tonic-gate 2357*0Sstevel@tonic-gate if (new_ifcap & PRN_BIDI) { /* go bidirectional */ 2358*0Sstevel@tonic-gate ecpp_default_negotiation(pp); 2359*0Sstevel@tonic-gate } else { /* go unidirectional */ 2360*0Sstevel@tonic-gate (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS); 2361*0Sstevel@tonic-gate } 2362*0Sstevel@tonic-gate 2363*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2364*0Sstevel@tonic-gate break; 2365*0Sstevel@tonic-gate } 2366*0Sstevel@tonic-gate 2367*0Sstevel@tonic-gate case PRNIOC_SET_TIMEOUTS: { 2368*0Sstevel@tonic-gate struct prn_timeouts *prn_timeouts; 2369*0Sstevel@tonic-gate 2370*0Sstevel@tonic-gate prn_timeouts = (struct prn_timeouts *)mp->b_cont->b_rptr; 2371*0Sstevel@tonic-gate 2372*0Sstevel@tonic-gate if (prn_timeouts->tmo_forward > ECPP_MAX_TIMEOUT) { 2373*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2374*0Sstevel@tonic-gate break; 2375*0Sstevel@tonic-gate } 2376*0Sstevel@tonic-gate 2377*0Sstevel@tonic-gate pp->prn_timeouts = *prn_timeouts; 2378*0Sstevel@tonic-gate pp->xfer_parms.write_timeout = (int)prn_timeouts->tmo_forward; 2379*0Sstevel@tonic-gate 2380*0Sstevel@tonic-gate ecpp_ack_ioctl(q, mp); 2381*0Sstevel@tonic-gate break; 2382*0Sstevel@tonic-gate } 2383*0Sstevel@tonic-gate 2384*0Sstevel@tonic-gate case PRNIOC_GET_IFINFO: 2385*0Sstevel@tonic-gate ecpp_srvioc_prnif(q, mp); 2386*0Sstevel@tonic-gate break; 2387*0Sstevel@tonic-gate 2388*0Sstevel@tonic-gate default: /* unexpected ioctl type */ 2389*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2390*0Sstevel@tonic-gate break; 2391*0Sstevel@tonic-gate } 2392*0Sstevel@tonic-gate } 2393*0Sstevel@tonic-gate 2394*0Sstevel@tonic-gate static void 2395*0Sstevel@tonic-gate ecpp_srvioc_devid(queue_t *q, mblk_t *mp, struct ecpp_device_id *id, int *rlen) 2396*0Sstevel@tonic-gate { 2397*0Sstevel@tonic-gate struct ecppunit *pp; 2398*0Sstevel@tonic-gate struct copyresp *csp; 2399*0Sstevel@tonic-gate struct ecpp_copystate *stp; 2400*0Sstevel@tonic-gate int error; 2401*0Sstevel@tonic-gate int len; 2402*0Sstevel@tonic-gate int mode; 2403*0Sstevel@tonic-gate mblk_t *datamp; 2404*0Sstevel@tonic-gate 2405*0Sstevel@tonic-gate pp = (struct ecppunit *)q->q_ptr; 2406*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 2407*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)csp->cp_private->b_rptr; 2408*0Sstevel@tonic-gate mode = id->mode; 2409*0Sstevel@tonic-gate 2410*0Sstevel@tonic-gate /* check arguments */ 2411*0Sstevel@tonic-gate if ((mode < ECPP_CENTRONICS) || (mode > ECPP_ECP_MODE)) { 2412*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_srvioc_devid: mode=%x, len=%x\n", 2413*0Sstevel@tonic-gate mode, id->len); 2414*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EINVAL); 2415*0Sstevel@tonic-gate return; 2416*0Sstevel@tonic-gate } 2417*0Sstevel@tonic-gate 2418*0Sstevel@tonic-gate /* Currently only Nibble mode is supported */ 2419*0Sstevel@tonic-gate if (mode != ECPP_NIBBLE_MODE) { 2420*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT); 2421*0Sstevel@tonic-gate return; 2422*0Sstevel@tonic-gate } 2423*0Sstevel@tonic-gate 2424*0Sstevel@tonic-gate if ((id->addr == NULL) && (id->len != 0)) { 2425*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EFAULT); 2426*0Sstevel@tonic-gate return; 2427*0Sstevel@tonic-gate } 2428*0Sstevel@tonic-gate 2429*0Sstevel@tonic-gate /* read device ID length */ 2430*0Sstevel@tonic-gate if (error = ecpp_getdevid(pp, NULL, &len, mode)) { 2431*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, error); 2432*0Sstevel@tonic-gate goto breakout; 2433*0Sstevel@tonic-gate } 2434*0Sstevel@tonic-gate 2435*0Sstevel@tonic-gate /* don't take into account two length bytes */ 2436*0Sstevel@tonic-gate len -= 2; 2437*0Sstevel@tonic-gate *rlen = len; 2438*0Sstevel@tonic-gate 2439*0Sstevel@tonic-gate /* limit transfer to user buffer length */ 2440*0Sstevel@tonic-gate if (id->len < len) { 2441*0Sstevel@tonic-gate len = id->len; 2442*0Sstevel@tonic-gate } 2443*0Sstevel@tonic-gate 2444*0Sstevel@tonic-gate if (len == 0) { 2445*0Sstevel@tonic-gate /* just return rlen */ 2446*0Sstevel@tonic-gate stp->state = ECPP_ADDROUT; 2447*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(q, mp, 2448*0Sstevel@tonic-gate (uintptr_t)rlen - (uintptr_t)&stp->un); 2449*0Sstevel@tonic-gate goto breakout; 2450*0Sstevel@tonic-gate } 2451*0Sstevel@tonic-gate 2452*0Sstevel@tonic-gate if ((datamp = allocb(len, BPRI_MED)) == NULL) { 2453*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, ENOSR); 2454*0Sstevel@tonic-gate goto breakout; 2455*0Sstevel@tonic-gate } 2456*0Sstevel@tonic-gate 2457*0Sstevel@tonic-gate /* read ID string */ 2458*0Sstevel@tonic-gate error = ecpp_getdevid(pp, datamp->b_rptr, &len, mode); 2459*0Sstevel@tonic-gate if (error) { 2460*0Sstevel@tonic-gate freemsg(datamp); 2461*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, error); 2462*0Sstevel@tonic-gate goto breakout; 2463*0Sstevel@tonic-gate } else { 2464*0Sstevel@tonic-gate datamp->b_wptr += len; 2465*0Sstevel@tonic-gate 2466*0Sstevel@tonic-gate stp->state = ECPP_ADDROUT; 2467*0Sstevel@tonic-gate mcopyout(mp, csp->cp_private, len, id->addr, datamp); 2468*0Sstevel@tonic-gate qreply(q, mp); 2469*0Sstevel@tonic-gate } 2470*0Sstevel@tonic-gate 2471*0Sstevel@tonic-gate return; 2472*0Sstevel@tonic-gate 2473*0Sstevel@tonic-gate breakout: 2474*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 2475*0Sstevel@tonic-gate } 2476*0Sstevel@tonic-gate 2477*0Sstevel@tonic-gate /* 2478*0Sstevel@tonic-gate * PRNIOC_GET_IFINFO: return prnio interface info string 2479*0Sstevel@tonic-gate */ 2480*0Sstevel@tonic-gate static void 2481*0Sstevel@tonic-gate ecpp_srvioc_prnif(queue_t *q, mblk_t *mp) 2482*0Sstevel@tonic-gate { 2483*0Sstevel@tonic-gate struct copyresp *csp; 2484*0Sstevel@tonic-gate struct ecpp_copystate *stp; 2485*0Sstevel@tonic-gate uint_t len; 2486*0Sstevel@tonic-gate struct prn_interface_info *ip; 2487*0Sstevel@tonic-gate struct prn_interface_info info; 2488*0Sstevel@tonic-gate mblk_t *datamp; 2489*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2490*0Sstevel@tonic-gate struct iocblk *iocbp = (struct iocblk *)mp->b_rptr; 2491*0Sstevel@tonic-gate #endif 2492*0Sstevel@tonic-gate 2493*0Sstevel@tonic-gate csp = (struct copyresp *)mp->b_rptr; 2494*0Sstevel@tonic-gate stp = (struct ecpp_copystate *)csp->cp_private->b_rptr; 2495*0Sstevel@tonic-gate ip = (struct prn_interface_info *)mp->b_cont->b_rptr; 2496*0Sstevel@tonic-gate 2497*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2498*0Sstevel@tonic-gate if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) { 2499*0Sstevel@tonic-gate struct prn_interface_info32 *ip32; 2500*0Sstevel@tonic-gate 2501*0Sstevel@tonic-gate ip32 = (struct prn_interface_info32 *)ip; 2502*0Sstevel@tonic-gate info.if_len = ip32->if_len; 2503*0Sstevel@tonic-gate info.if_data = (char *)(uintptr_t)ip32->if_data; 2504*0Sstevel@tonic-gate } else { 2505*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2506*0Sstevel@tonic-gate info = *ip; 2507*0Sstevel@tonic-gate #ifdef _MULTI_DATAMODEL 2508*0Sstevel@tonic-gate } 2509*0Sstevel@tonic-gate #endif /* _MULTI_DATAMODEL */ 2510*0Sstevel@tonic-gate 2511*0Sstevel@tonic-gate len = strlen(prn_ifinfo); 2512*0Sstevel@tonic-gate stp->un.prn_if.if_rlen = len; 2513*0Sstevel@tonic-gate stp->state = ECPP_ADDROUT; 2514*0Sstevel@tonic-gate 2515*0Sstevel@tonic-gate /* check arguments */ 2516*0Sstevel@tonic-gate if ((info.if_data == NULL) && (info.if_len != 0)) { 2517*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, EFAULT); 2518*0Sstevel@tonic-gate return; 2519*0Sstevel@tonic-gate } 2520*0Sstevel@tonic-gate 2521*0Sstevel@tonic-gate if (info.if_len == 0) { 2522*0Sstevel@tonic-gate /* just copyout rlen */ 2523*0Sstevel@tonic-gate ecpp_wput_iocdata_devid(q, mp, 2524*0Sstevel@tonic-gate offsetof(struct prn_interface_info, if_rlen)); 2525*0Sstevel@tonic-gate return; 2526*0Sstevel@tonic-gate } 2527*0Sstevel@tonic-gate 2528*0Sstevel@tonic-gate /* if needed, trim to the buffer size */ 2529*0Sstevel@tonic-gate if (len > info.if_len) { 2530*0Sstevel@tonic-gate len = info.if_len; 2531*0Sstevel@tonic-gate } 2532*0Sstevel@tonic-gate 2533*0Sstevel@tonic-gate if ((datamp = allocb(len, BPRI_MED)) == NULL) { 2534*0Sstevel@tonic-gate ecpp_nack_ioctl(q, mp, ENOSR); 2535*0Sstevel@tonic-gate return; 2536*0Sstevel@tonic-gate } 2537*0Sstevel@tonic-gate 2538*0Sstevel@tonic-gate bcopy(&prn_ifinfo[0], datamp->b_wptr, len); 2539*0Sstevel@tonic-gate datamp->b_wptr += len; 2540*0Sstevel@tonic-gate 2541*0Sstevel@tonic-gate mcopyout(mp, csp->cp_private, len, info.if_data, datamp); 2542*0Sstevel@tonic-gate qreply(q, mp); 2543*0Sstevel@tonic-gate } 2544*0Sstevel@tonic-gate 2545*0Sstevel@tonic-gate static void 2546*0Sstevel@tonic-gate ecpp_flush(struct ecppunit *pp, int cmd) 2547*0Sstevel@tonic-gate { 2548*0Sstevel@tonic-gate queue_t *q; 2549*0Sstevel@tonic-gate uint8_t ecr, dcr; 2550*0Sstevel@tonic-gate timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id; 2551*0Sstevel@tonic-gate 2552*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 2553*0Sstevel@tonic-gate 2554*0Sstevel@tonic-gate if (!(cmd & FWRITE)) { 2555*0Sstevel@tonic-gate return; 2556*0Sstevel@tonic-gate } 2557*0Sstevel@tonic-gate 2558*0Sstevel@tonic-gate q = pp->writeq; 2559*0Sstevel@tonic-gate timeout_id = fifo_timer_id = wsrv_timer_id = 0; 2560*0Sstevel@tonic-gate 2561*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_flush e_busy=%x\n", pp->e_busy); 2562*0Sstevel@tonic-gate 2563*0Sstevel@tonic-gate /* if there is an ongoing DMA, it needs to be turned off. */ 2564*0Sstevel@tonic-gate switch (pp->e_busy) { 2565*0Sstevel@tonic-gate case ECPP_BUSY: 2566*0Sstevel@tonic-gate /* 2567*0Sstevel@tonic-gate * Change the port status to ECPP_FLUSH to 2568*0Sstevel@tonic-gate * indicate to ecpp_wsrv that the wq is being flushed. 2569*0Sstevel@tonic-gate */ 2570*0Sstevel@tonic-gate pp->e_busy = ECPP_FLUSH; 2571*0Sstevel@tonic-gate 2572*0Sstevel@tonic-gate /* 2573*0Sstevel@tonic-gate * dma_cancelled indicates to ecpp_isr() that we have 2574*0Sstevel@tonic-gate * turned off the DMA. Since the mutex is held, ecpp_isr() 2575*0Sstevel@tonic-gate * may be blocked. Once ecpp_flush() finishes and ecpp_isr() 2576*0Sstevel@tonic-gate * gains the mutex, ecpp_isr() will have a _reset_ DMAC. Most 2577*0Sstevel@tonic-gate * significantly, the DMAC will be reset after ecpp_isr() was 2578*0Sstevel@tonic-gate * invoked. Therefore we need to have a flag "dma_cancelled" 2579*0Sstevel@tonic-gate * to signify when the described condition has occured. If 2580*0Sstevel@tonic-gate * ecpp_isr() notes a dma_cancelled, it will ignore the DMAC csr 2581*0Sstevel@tonic-gate * and simply claim the interupt. 2582*0Sstevel@tonic-gate */ 2583*0Sstevel@tonic-gate 2584*0Sstevel@tonic-gate pp->dma_cancelled = TRUE; 2585*0Sstevel@tonic-gate 2586*0Sstevel@tonic-gate /* either DMA or PIO transfer */ 2587*0Sstevel@tonic-gate if (COMPAT_DMA(pp) || 2588*0Sstevel@tonic-gate (pp->current_mode == ECPP_ECP_MODE) || 2589*0Sstevel@tonic-gate (pp->current_mode == ECPP_DIAG_MODE)) { 2590*0Sstevel@tonic-gate /* 2591*0Sstevel@tonic-gate * if the bcr is zero, then DMA is complete and 2592*0Sstevel@tonic-gate * we are waiting for the fifo to drain. Therefore, 2593*0Sstevel@tonic-gate * turn off dma. 2594*0Sstevel@tonic-gate */ 2595*0Sstevel@tonic-gate if (ECPP_DMA_STOP(pp, NULL) == FAILURE) { 2596*0Sstevel@tonic-gate ecpp_error(pp->dip, 2597*0Sstevel@tonic-gate "ecpp_flush: dma_stop failed.\n"); 2598*0Sstevel@tonic-gate } 2599*0Sstevel@tonic-gate 2600*0Sstevel@tonic-gate /* 2601*0Sstevel@tonic-gate * If the status of the port is ECPP_BUSY, 2602*0Sstevel@tonic-gate * the DMA is stopped by either explicitly above, or by 2603*0Sstevel@tonic-gate * ecpp_isr() but the FIFO hasn't drained yet. In either 2604*0Sstevel@tonic-gate * case, we need to unbind the dma mappings. 2605*0Sstevel@tonic-gate */ 2606*0Sstevel@tonic-gate if (ddi_dma_unbind_handle( 2607*0Sstevel@tonic-gate pp->dma_handle) != DDI_SUCCESS) 2608*0Sstevel@tonic-gate ecpp_error(pp->dip, 2609*0Sstevel@tonic-gate "ecpp_flush: unbind failed.\n"); 2610*0Sstevel@tonic-gate 2611*0Sstevel@tonic-gate if (pp->msg != NULL) { 2612*0Sstevel@tonic-gate freemsg(pp->msg); 2613*0Sstevel@tonic-gate pp->msg = NULL; 2614*0Sstevel@tonic-gate } 2615*0Sstevel@tonic-gate } else { 2616*0Sstevel@tonic-gate /* 2617*0Sstevel@tonic-gate * PIO transfer: disable nAck interrups 2618*0Sstevel@tonic-gate */ 2619*0Sstevel@tonic-gate dcr = DCR_READ(pp); 2620*0Sstevel@tonic-gate dcr &= ~(ECPP_REV_DIR | ECPP_INTR_EN); 2621*0Sstevel@tonic-gate DCR_WRITE(pp, dcr); 2622*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 2623*0Sstevel@tonic-gate } 2624*0Sstevel@tonic-gate 2625*0Sstevel@tonic-gate /* 2626*0Sstevel@tonic-gate * The transfer is cleaned up. There may or may not be data 2627*0Sstevel@tonic-gate * in the fifo. We don't care at this point. Ie. SuperIO may 2628*0Sstevel@tonic-gate * transfer the remaining bytes in the fifo or not. it doesn't 2629*0Sstevel@tonic-gate * matter. All that is important at this stage is that no more 2630*0Sstevel@tonic-gate * fifo timers are started. 2631*0Sstevel@tonic-gate */ 2632*0Sstevel@tonic-gate 2633*0Sstevel@tonic-gate timeout_id = pp->timeout_id; 2634*0Sstevel@tonic-gate fifo_timer_id = pp->fifo_timer_id; 2635*0Sstevel@tonic-gate pp->timeout_id = pp->fifo_timer_id = 0; 2636*0Sstevel@tonic-gate pp->softintr_pending = 0; 2637*0Sstevel@tonic-gate 2638*0Sstevel@tonic-gate break; 2639*0Sstevel@tonic-gate 2640*0Sstevel@tonic-gate case ECPP_ERR: 2641*0Sstevel@tonic-gate /* 2642*0Sstevel@tonic-gate * Change the port status to ECPP_FLUSH to 2643*0Sstevel@tonic-gate * indicate to ecpp_wsrv that the wq is being flushed. 2644*0Sstevel@tonic-gate */ 2645*0Sstevel@tonic-gate pp->e_busy = ECPP_FLUSH; 2646*0Sstevel@tonic-gate 2647*0Sstevel@tonic-gate /* 2648*0Sstevel@tonic-gate * Most likely there are mblks in the queue, 2649*0Sstevel@tonic-gate * but the driver can not transmit because 2650*0Sstevel@tonic-gate * of the bad port status. In this case, 2651*0Sstevel@tonic-gate * ecpp_flush() should make sure ecpp_wsrv_timer() 2652*0Sstevel@tonic-gate * is turned off. 2653*0Sstevel@tonic-gate */ 2654*0Sstevel@tonic-gate wsrv_timer_id = pp->wsrv_timer_id; 2655*0Sstevel@tonic-gate pp->wsrv_timer_id = 0; 2656*0Sstevel@tonic-gate 2657*0Sstevel@tonic-gate break; 2658*0Sstevel@tonic-gate 2659*0Sstevel@tonic-gate case ECPP_IDLE: 2660*0Sstevel@tonic-gate /* No work to do. Ready to flush */ 2661*0Sstevel@tonic-gate break; 2662*0Sstevel@tonic-gate 2663*0Sstevel@tonic-gate default: 2664*0Sstevel@tonic-gate ecpp_error(pp->dip, 2665*0Sstevel@tonic-gate "ecpp_flush: illegal state %x\n", pp->e_busy); 2666*0Sstevel@tonic-gate } 2667*0Sstevel@tonic-gate 2668*0Sstevel@tonic-gate /* in DIAG mode clear TFIFO if needed */ 2669*0Sstevel@tonic-gate if (pp->current_mode == ECPP_DIAG_MODE) { 2670*0Sstevel@tonic-gate ecr = ECR_READ(pp); 2671*0Sstevel@tonic-gate if (!(ecr & ECPP_FIFO_EMPTY)) { 2672*0Sstevel@tonic-gate ECR_WRITE(pp, 2673*0Sstevel@tonic-gate ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001); 2674*0Sstevel@tonic-gate ECR_WRITE(pp, ecr); 2675*0Sstevel@tonic-gate } 2676*0Sstevel@tonic-gate } 2677*0Sstevel@tonic-gate 2678*0Sstevel@tonic-gate /* Discard all messages on the output queue. */ 2679*0Sstevel@tonic-gate flushq(q, FLUSHDATA); 2680*0Sstevel@tonic-gate 2681*0Sstevel@tonic-gate /* The port is no longer flushing or dma'ing for that matter. */ 2682*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 2683*0Sstevel@tonic-gate 2684*0Sstevel@tonic-gate /* Set the right phase */ 2685*0Sstevel@tonic-gate if (pp->current_mode == ECPP_ECP_MODE) { 2686*0Sstevel@tonic-gate if (pp->current_phase == ECPP_PHASE_ECP_REV_XFER) { 2687*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_REV_IDLE; 2688*0Sstevel@tonic-gate } else { 2689*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE; 2690*0Sstevel@tonic-gate } 2691*0Sstevel@tonic-gate } 2692*0Sstevel@tonic-gate 2693*0Sstevel@tonic-gate /* cancel timeouts if any */ 2694*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 2695*0Sstevel@tonic-gate 2696*0Sstevel@tonic-gate if (timeout_id) { 2697*0Sstevel@tonic-gate (void) untimeout(timeout_id); 2698*0Sstevel@tonic-gate } 2699*0Sstevel@tonic-gate if (fifo_timer_id) { 2700*0Sstevel@tonic-gate (void) untimeout(fifo_timer_id); 2701*0Sstevel@tonic-gate } 2702*0Sstevel@tonic-gate if (wsrv_timer_id) { 2703*0Sstevel@tonic-gate (void) untimeout(wsrv_timer_id); 2704*0Sstevel@tonic-gate } 2705*0Sstevel@tonic-gate 2706*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 2707*0Sstevel@tonic-gate 2708*0Sstevel@tonic-gate cv_signal(&pp->pport_cv); /* wake up ecpp_close() */ 2709*0Sstevel@tonic-gate } 2710*0Sstevel@tonic-gate 2711*0Sstevel@tonic-gate static void 2712*0Sstevel@tonic-gate ecpp_start(struct ecppunit *pp, caddr_t addr, size_t len) 2713*0Sstevel@tonic-gate { 2714*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 2715*0Sstevel@tonic-gate ASSERT(pp->e_busy == ECPP_BUSY); 2716*0Sstevel@tonic-gate 2717*0Sstevel@tonic-gate ecpp_error(pp->dip, 2718*0Sstevel@tonic-gate "ecpp_start:current_mode=%x,current_phase=%x,ecr=%x,len=%d\n", 2719*0Sstevel@tonic-gate pp->current_mode, pp->current_phase, ECR_READ(pp), len); 2720*0Sstevel@tonic-gate 2721*0Sstevel@tonic-gate pp->dma_dir = DDI_DMA_WRITE; /* this is a forward transfer */ 2722*0Sstevel@tonic-gate 2723*0Sstevel@tonic-gate switch (pp->current_mode) { 2724*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 2725*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 2726*0Sstevel@tonic-gate 2727*0Sstevel@tonic-gate /* After termination we are either Compatible or Centronics */ 2728*0Sstevel@tonic-gate 2729*0Sstevel@tonic-gate /* FALLTHRU */ 2730*0Sstevel@tonic-gate 2731*0Sstevel@tonic-gate case ECPP_CENTRONICS: 2732*0Sstevel@tonic-gate case ECPP_COMPAT_MODE: 2733*0Sstevel@tonic-gate if (pp->io_mode == ECPP_DMA) { 2734*0Sstevel@tonic-gate if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) { 2735*0Sstevel@tonic-gate return; 2736*0Sstevel@tonic-gate } 2737*0Sstevel@tonic-gate } else { 2738*0Sstevel@tonic-gate /* PIO mode */ 2739*0Sstevel@tonic-gate if (ecpp_prep_pio_xfer(pp, addr, len) == FAILURE) { 2740*0Sstevel@tonic-gate return; 2741*0Sstevel@tonic-gate } 2742*0Sstevel@tonic-gate (void) ecpp_pio_writeb(pp); 2743*0Sstevel@tonic-gate } 2744*0Sstevel@tonic-gate break; 2745*0Sstevel@tonic-gate 2746*0Sstevel@tonic-gate case ECPP_DIAG_MODE: { 2747*0Sstevel@tonic-gate int oldlen; 2748*0Sstevel@tonic-gate 2749*0Sstevel@tonic-gate /* put superio into TFIFO mode, if not already */ 2750*0Sstevel@tonic-gate ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110); 2751*0Sstevel@tonic-gate /* 2752*0Sstevel@tonic-gate * DMA would block if the TFIFO is not empty 2753*0Sstevel@tonic-gate * if by this moment nobody read these bytes, they`re gone 2754*0Sstevel@tonic-gate */ 2755*0Sstevel@tonic-gate drv_usecwait(1); 2756*0Sstevel@tonic-gate if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) { 2757*0Sstevel@tonic-gate ecpp_error(pp->dip, 2758*0Sstevel@tonic-gate "ecpp_start: TFIFO not empty, clearing\n"); 2759*0Sstevel@tonic-gate ECR_WRITE(pp, 2760*0Sstevel@tonic-gate ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001); 2761*0Sstevel@tonic-gate ECR_WRITE(pp, 2762*0Sstevel@tonic-gate ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110); 2763*0Sstevel@tonic-gate } 2764*0Sstevel@tonic-gate 2765*0Sstevel@tonic-gate /* we can DMA at most 16 bytes into TFIFO */ 2766*0Sstevel@tonic-gate oldlen = len; 2767*0Sstevel@tonic-gate if (len > ECPP_FIFO_SZ) { 2768*0Sstevel@tonic-gate len = ECPP_FIFO_SZ; 2769*0Sstevel@tonic-gate } 2770*0Sstevel@tonic-gate 2771*0Sstevel@tonic-gate if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) { 2772*0Sstevel@tonic-gate return; 2773*0Sstevel@tonic-gate } 2774*0Sstevel@tonic-gate 2775*0Sstevel@tonic-gate /* put the rest of data back on the queue */ 2776*0Sstevel@tonic-gate if (oldlen > len) { 2777*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, addr + len, oldlen - len); 2778*0Sstevel@tonic-gate } 2779*0Sstevel@tonic-gate 2780*0Sstevel@tonic-gate break; 2781*0Sstevel@tonic-gate } 2782*0Sstevel@tonic-gate 2783*0Sstevel@tonic-gate case ECPP_ECP_MODE: 2784*0Sstevel@tonic-gate ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE || 2785*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_IDLE); 2786*0Sstevel@tonic-gate 2787*0Sstevel@tonic-gate /* if in Reverse Phase negotiate to Forward */ 2788*0Sstevel@tonic-gate if (pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) { 2789*0Sstevel@tonic-gate if (ecp_reverse2forward(pp) == FAILURE) { 2790*0Sstevel@tonic-gate if (pp->msg) { 2791*0Sstevel@tonic-gate (void) putbq(pp->writeq, pp->msg); 2792*0Sstevel@tonic-gate } else { 2793*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, 2794*0Sstevel@tonic-gate addr, len); 2795*0Sstevel@tonic-gate } 2796*0Sstevel@tonic-gate } 2797*0Sstevel@tonic-gate } 2798*0Sstevel@tonic-gate 2799*0Sstevel@tonic-gate if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) { 2800*0Sstevel@tonic-gate return; 2801*0Sstevel@tonic-gate } 2802*0Sstevel@tonic-gate 2803*0Sstevel@tonic-gate break; 2804*0Sstevel@tonic-gate } 2805*0Sstevel@tonic-gate 2806*0Sstevel@tonic-gate /* schedule transfer timeout */ 2807*0Sstevel@tonic-gate pp->timeout_id = timeout(ecpp_xfer_timeout, (caddr_t)pp, 2808*0Sstevel@tonic-gate pp->xfer_parms.write_timeout * drv_usectohz(1000000)); 2809*0Sstevel@tonic-gate } 2810*0Sstevel@tonic-gate 2811*0Sstevel@tonic-gate /* 2812*0Sstevel@tonic-gate * Transfer a PIO "block" a byte at a time. 2813*0Sstevel@tonic-gate * The block is starts at addr and ends at pp->last_byte 2814*0Sstevel@tonic-gate */ 2815*0Sstevel@tonic-gate static uint8_t 2816*0Sstevel@tonic-gate ecpp_prep_pio_xfer(struct ecppunit *pp, caddr_t addr, size_t len) 2817*0Sstevel@tonic-gate { 2818*0Sstevel@tonic-gate pp->next_byte = addr; 2819*0Sstevel@tonic-gate pp->last_byte = (caddr_t)((ulong_t)addr + len); 2820*0Sstevel@tonic-gate 2821*0Sstevel@tonic-gate if (ecpp_check_status(pp) == FAILURE) { 2822*0Sstevel@tonic-gate /* 2823*0Sstevel@tonic-gate * if status signals are bad, do not start PIO, 2824*0Sstevel@tonic-gate * put everything back on the queue. 2825*0Sstevel@tonic-gate */ 2826*0Sstevel@tonic-gate ecpp_error(pp->dip, 2827*0Sstevel@tonic-gate "ecpp_prep_pio_xfer:suspend PIO len=%d\n", len); 2828*0Sstevel@tonic-gate 2829*0Sstevel@tonic-gate if (pp->msg != NULL) { 2830*0Sstevel@tonic-gate /* 2831*0Sstevel@tonic-gate * this circumstance we want to copy the 2832*0Sstevel@tonic-gate * untransfered section of msg to a new mblk, 2833*0Sstevel@tonic-gate * then free the orignal one. 2834*0Sstevel@tonic-gate */ 2835*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, 2836*0Sstevel@tonic-gate (void *)pp->msg->b_rptr, len); 2837*0Sstevel@tonic-gate ecpp_error(pp->dip, 2838*0Sstevel@tonic-gate "ecpp_prep_pio_xfer: len1=%d\n", len); 2839*0Sstevel@tonic-gate 2840*0Sstevel@tonic-gate freemsg(pp->msg); 2841*0Sstevel@tonic-gate pp->msg = NULL; 2842*0Sstevel@tonic-gate } else { 2843*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, pp->ioblock, len); 2844*0Sstevel@tonic-gate ecpp_error(pp->dip, 2845*0Sstevel@tonic-gate "ecpp_prep_pio_xfer: len2=%d\n", len); 2846*0Sstevel@tonic-gate } 2847*0Sstevel@tonic-gate qenable(pp->writeq); 2848*0Sstevel@tonic-gate 2849*0Sstevel@tonic-gate return (FAILURE); 2850*0Sstevel@tonic-gate } 2851*0Sstevel@tonic-gate 2852*0Sstevel@tonic-gate pp->dma_cancelled = FALSE; 2853*0Sstevel@tonic-gate 2854*0Sstevel@tonic-gate /* pport must be in PIO mode */ 2855*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_001 | 2856*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) != SUCCESS) { 2857*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_prep_pio_xfer: failed w/ECR.\n"); 2858*0Sstevel@tonic-gate } 2859*0Sstevel@tonic-gate 2860*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n", 2861*0Sstevel@tonic-gate DCR_READ(pp), ECR_READ(pp)); 2862*0Sstevel@tonic-gate 2863*0Sstevel@tonic-gate return (SUCCESS); 2864*0Sstevel@tonic-gate } 2865*0Sstevel@tonic-gate 2866*0Sstevel@tonic-gate static uint8_t 2867*0Sstevel@tonic-gate ecpp_init_dma_xfer(struct ecppunit *pp, caddr_t addr, size_t len) 2868*0Sstevel@tonic-gate { 2869*0Sstevel@tonic-gate uint8_t ecr_mode[] = { 2870*0Sstevel@tonic-gate 0, 2871*0Sstevel@tonic-gate ECR_mode_010, /* Centronix */ 2872*0Sstevel@tonic-gate ECR_mode_010, /* Compat */ 2873*0Sstevel@tonic-gate 0, /* Byte */ 2874*0Sstevel@tonic-gate 0, /* Nibble */ 2875*0Sstevel@tonic-gate ECR_mode_011, /* ECP */ 2876*0Sstevel@tonic-gate 0, /* Failure */ 2877*0Sstevel@tonic-gate ECR_mode_110, /* Diag */ 2878*0Sstevel@tonic-gate }; 2879*0Sstevel@tonic-gate uint8_t ecr; 2880*0Sstevel@tonic-gate 2881*0Sstevel@tonic-gate ASSERT((pp->current_mode <= ECPP_DIAG_MODE) && 2882*0Sstevel@tonic-gate (ecr_mode[pp->current_mode] != 0)); 2883*0Sstevel@tonic-gate 2884*0Sstevel@tonic-gate if (ecpp_setup_dma_resources(pp, addr, len) == FAILURE) { 2885*0Sstevel@tonic-gate qenable(pp->writeq); 2886*0Sstevel@tonic-gate return (FAILURE); 2887*0Sstevel@tonic-gate } 2888*0Sstevel@tonic-gate 2889*0Sstevel@tonic-gate if (ecpp_check_status(pp) == FAILURE) { 2890*0Sstevel@tonic-gate /* 2891*0Sstevel@tonic-gate * if status signals are bad, do not start DMA, but 2892*0Sstevel@tonic-gate * rather put everything back on the queue. 2893*0Sstevel@tonic-gate */ 2894*0Sstevel@tonic-gate ecpp_error(pp->dip, 2895*0Sstevel@tonic-gate "ecpp_init_dma_xfer: suspending DMA len=%d\n", 2896*0Sstevel@tonic-gate pp->dma_cookie.dmac_size); 2897*0Sstevel@tonic-gate 2898*0Sstevel@tonic-gate if (pp->msg != NULL) { 2899*0Sstevel@tonic-gate /* 2900*0Sstevel@tonic-gate * this circumstance we want to copy the 2901*0Sstevel@tonic-gate * untransfered section of msg to a new mblk, 2902*0Sstevel@tonic-gate * then free the orignal one. 2903*0Sstevel@tonic-gate */ 2904*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, 2905*0Sstevel@tonic-gate (void *)pp->msg->b_rptr, len); 2906*0Sstevel@tonic-gate ecpp_error(pp->dip, 2907*0Sstevel@tonic-gate "ecpp_init_dma_xfer:a:len=%d\n", len); 2908*0Sstevel@tonic-gate 2909*0Sstevel@tonic-gate freemsg(pp->msg); 2910*0Sstevel@tonic-gate pp->msg = NULL; 2911*0Sstevel@tonic-gate } else { 2912*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, pp->ioblock, len); 2913*0Sstevel@tonic-gate ecpp_error(pp->dip, 2914*0Sstevel@tonic-gate "ecpp_init_dma_xfer:b:len=%d\n", len); 2915*0Sstevel@tonic-gate } 2916*0Sstevel@tonic-gate 2917*0Sstevel@tonic-gate if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) { 2918*0Sstevel@tonic-gate ecpp_error(pp->dip, 2919*0Sstevel@tonic-gate "ecpp_init_dma_xfer: unbind FAILURE.\n"); 2920*0Sstevel@tonic-gate } 2921*0Sstevel@tonic-gate qenable(pp->writeq); 2922*0Sstevel@tonic-gate return (FAILURE); 2923*0Sstevel@tonic-gate } 2924*0Sstevel@tonic-gate 2925*0Sstevel@tonic-gate pp->xfercnt = pp->resid = len; 2926*0Sstevel@tonic-gate pp->dma_cancelled = FALSE; 2927*0Sstevel@tonic-gate pp->tfifo_intr = 0; 2928*0Sstevel@tonic-gate 2929*0Sstevel@tonic-gate /* set the right ECR mode and disable DMA */ 2930*0Sstevel@tonic-gate ecr = ecr_mode[pp->current_mode]; 2931*0Sstevel@tonic-gate (void) ecr_write(pp, ecr | ECPP_INTR_SRV | ECPP_INTR_MASK); 2932*0Sstevel@tonic-gate 2933*0Sstevel@tonic-gate /* prepare DMAC for a transfer */ 2934*0Sstevel@tonic-gate if (ECPP_DMA_START(pp) == FAILURE) { 2935*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_init_dma_xfer: dma_start FAILED.\n"); 2936*0Sstevel@tonic-gate return (FAILURE); 2937*0Sstevel@tonic-gate } 2938*0Sstevel@tonic-gate 2939*0Sstevel@tonic-gate /* GO! */ 2940*0Sstevel@tonic-gate (void) ecr_write(pp, ecr | ECPP_DMA_ENABLE | ECPP_INTR_MASK); 2941*0Sstevel@tonic-gate 2942*0Sstevel@tonic-gate return (SUCCESS); 2943*0Sstevel@tonic-gate } 2944*0Sstevel@tonic-gate 2945*0Sstevel@tonic-gate static uint8_t 2946*0Sstevel@tonic-gate ecpp_setup_dma_resources(struct ecppunit *pp, caddr_t addr, size_t len) 2947*0Sstevel@tonic-gate { 2948*0Sstevel@tonic-gate int err; 2949*0Sstevel@tonic-gate off_t woff; 2950*0Sstevel@tonic-gate size_t wlen; 2951*0Sstevel@tonic-gate 2952*0Sstevel@tonic-gate ASSERT(pp->dma_dir == DDI_DMA_READ || pp->dma_dir == DDI_DMA_WRITE); 2953*0Sstevel@tonic-gate 2954*0Sstevel@tonic-gate err = ddi_dma_addr_bind_handle(pp->dma_handle, NULL, 2955*0Sstevel@tonic-gate addr, len, pp->dma_dir | DDI_DMA_PARTIAL, 2956*0Sstevel@tonic-gate DDI_DMA_DONTWAIT, NULL, 2957*0Sstevel@tonic-gate &pp->dma_cookie, &pp->dma_cookie_count); 2958*0Sstevel@tonic-gate 2959*0Sstevel@tonic-gate switch (err) { 2960*0Sstevel@tonic-gate case DDI_DMA_MAPPED: 2961*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_setup_dma: DMA_MAPPED\n"); 2962*0Sstevel@tonic-gate 2963*0Sstevel@tonic-gate pp->dma_nwin = 1; 2964*0Sstevel@tonic-gate pp->dma_curwin = 1; 2965*0Sstevel@tonic-gate break; 2966*0Sstevel@tonic-gate 2967*0Sstevel@tonic-gate case DDI_DMA_PARTIAL_MAP: { 2968*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_setup_dma: DMA_PARTIAL_MAP\n"); 2969*0Sstevel@tonic-gate 2970*0Sstevel@tonic-gate if (ddi_dma_numwin(pp->dma_handle, 2971*0Sstevel@tonic-gate &pp->dma_nwin) != DDI_SUCCESS) { 2972*0Sstevel@tonic-gate (void) ddi_dma_unbind_handle(pp->dma_handle); 2973*0Sstevel@tonic-gate return (FAILURE); 2974*0Sstevel@tonic-gate } 2975*0Sstevel@tonic-gate pp->dma_curwin = 1; 2976*0Sstevel@tonic-gate 2977*0Sstevel@tonic-gate /* 2978*0Sstevel@tonic-gate * The very first window is returned by bind_handle, 2979*0Sstevel@tonic-gate * but we must do this explicitly here, otherwise 2980*0Sstevel@tonic-gate * next getwin would return wrong cookie dmac_size 2981*0Sstevel@tonic-gate */ 2982*0Sstevel@tonic-gate if (ddi_dma_getwin(pp->dma_handle, 0, &woff, &wlen, 2983*0Sstevel@tonic-gate &pp->dma_cookie, &pp->dma_cookie_count) != DDI_SUCCESS) { 2984*0Sstevel@tonic-gate ecpp_error(pp->dip, 2985*0Sstevel@tonic-gate "ecpp_setup_dma: ddi_dma_getwin failed!"); 2986*0Sstevel@tonic-gate (void) ddi_dma_unbind_handle(pp->dma_handle); 2987*0Sstevel@tonic-gate return (FAILURE); 2988*0Sstevel@tonic-gate } 2989*0Sstevel@tonic-gate 2990*0Sstevel@tonic-gate ecpp_error(pp->dip, 2991*0Sstevel@tonic-gate "ecpp_setup_dma: cookies=%d, windows=%d" 2992*0Sstevel@tonic-gate " addr=%lx len=%d\n", 2993*0Sstevel@tonic-gate pp->dma_cookie_count, pp->dma_nwin, 2994*0Sstevel@tonic-gate pp->dma_cookie.dmac_address, pp->dma_cookie.dmac_size); 2995*0Sstevel@tonic-gate 2996*0Sstevel@tonic-gate break; 2997*0Sstevel@tonic-gate } 2998*0Sstevel@tonic-gate 2999*0Sstevel@tonic-gate default: 3000*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_setup_dma: err=%x\n", err); 3001*0Sstevel@tonic-gate return (FAILURE); 3002*0Sstevel@tonic-gate } 3003*0Sstevel@tonic-gate 3004*0Sstevel@tonic-gate return (SUCCESS); 3005*0Sstevel@tonic-gate } 3006*0Sstevel@tonic-gate 3007*0Sstevel@tonic-gate static void 3008*0Sstevel@tonic-gate ecpp_ack_ioctl(queue_t *q, mblk_t *mp) 3009*0Sstevel@tonic-gate { 3010*0Sstevel@tonic-gate struct iocblk *iocbp; 3011*0Sstevel@tonic-gate 3012*0Sstevel@tonic-gate mp->b_datap->db_type = M_IOCACK; 3013*0Sstevel@tonic-gate mp->b_wptr = mp->b_rptr + sizeof (struct iocblk); 3014*0Sstevel@tonic-gate 3015*0Sstevel@tonic-gate if (mp->b_cont) { 3016*0Sstevel@tonic-gate freemsg(mp->b_cont); 3017*0Sstevel@tonic-gate mp->b_cont = NULL; 3018*0Sstevel@tonic-gate } 3019*0Sstevel@tonic-gate 3020*0Sstevel@tonic-gate iocbp = (struct iocblk *)mp->b_rptr; 3021*0Sstevel@tonic-gate iocbp->ioc_error = 0; 3022*0Sstevel@tonic-gate iocbp->ioc_count = 0; 3023*0Sstevel@tonic-gate iocbp->ioc_rval = 0; 3024*0Sstevel@tonic-gate 3025*0Sstevel@tonic-gate qreply(q, mp); 3026*0Sstevel@tonic-gate } 3027*0Sstevel@tonic-gate 3028*0Sstevel@tonic-gate static void 3029*0Sstevel@tonic-gate ecpp_nack_ioctl(queue_t *q, mblk_t *mp, int err) 3030*0Sstevel@tonic-gate { 3031*0Sstevel@tonic-gate struct iocblk *iocbp; 3032*0Sstevel@tonic-gate 3033*0Sstevel@tonic-gate mp->b_datap->db_type = M_IOCNAK; 3034*0Sstevel@tonic-gate mp->b_wptr = mp->b_rptr + sizeof (struct iocblk); 3035*0Sstevel@tonic-gate iocbp = (struct iocblk *)mp->b_rptr; 3036*0Sstevel@tonic-gate iocbp->ioc_error = err; 3037*0Sstevel@tonic-gate 3038*0Sstevel@tonic-gate if (mp->b_cont) { 3039*0Sstevel@tonic-gate freemsg(mp->b_cont); 3040*0Sstevel@tonic-gate mp->b_cont = NULL; 3041*0Sstevel@tonic-gate } 3042*0Sstevel@tonic-gate 3043*0Sstevel@tonic-gate qreply(q, mp); 3044*0Sstevel@tonic-gate } 3045*0Sstevel@tonic-gate 3046*0Sstevel@tonic-gate uint_t 3047*0Sstevel@tonic-gate ecpp_isr(caddr_t arg) 3048*0Sstevel@tonic-gate { 3049*0Sstevel@tonic-gate struct ecppunit *pp = (struct ecppunit *)(void *)arg; 3050*0Sstevel@tonic-gate uint32_t dcsr; 3051*0Sstevel@tonic-gate uint8_t dsr; 3052*0Sstevel@tonic-gate int cheerio_pend_counter; 3053*0Sstevel@tonic-gate int retval = DDI_INTR_UNCLAIMED; 3054*0Sstevel@tonic-gate hrtime_t now; 3055*0Sstevel@tonic-gate 3056*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 3057*0Sstevel@tonic-gate /* 3058*0Sstevel@tonic-gate * interrupt may occur while other thread is holding the lock 3059*0Sstevel@tonic-gate * and cancels DMA transfer (e.g. ecpp_flush()) 3060*0Sstevel@tonic-gate * since it cannot cancel the interrupt thread, 3061*0Sstevel@tonic-gate * it just sets dma_cancelled to TRUE, 3062*0Sstevel@tonic-gate * telling interrupt handler to exit immediately 3063*0Sstevel@tonic-gate */ 3064*0Sstevel@tonic-gate if (pp->dma_cancelled == TRUE) { 3065*0Sstevel@tonic-gate ecpp_error(pp->dip, "dma-cancel isr\n"); 3066*0Sstevel@tonic-gate 3067*0Sstevel@tonic-gate pp->intr_hard++; 3068*0Sstevel@tonic-gate pp->dma_cancelled = FALSE; 3069*0Sstevel@tonic-gate 3070*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3071*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3072*0Sstevel@tonic-gate } 3073*0Sstevel@tonic-gate 3074*0Sstevel@tonic-gate /* Southbridge interrupts are handled separately */ 3075*0Sstevel@tonic-gate #if defined(__x86) 3076*0Sstevel@tonic-gate if (pp->hw == &x86) 3077*0Sstevel@tonic-gate #else 3078*0Sstevel@tonic-gate if (pp->hw == &m1553) 3079*0Sstevel@tonic-gate #endif 3080*0Sstevel@tonic-gate { 3081*0Sstevel@tonic-gate retval = ecpp_M1553_intr(pp); 3082*0Sstevel@tonic-gate if (retval == DDI_INTR_UNCLAIMED) { 3083*0Sstevel@tonic-gate goto unexpected; 3084*0Sstevel@tonic-gate } 3085*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3086*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3087*0Sstevel@tonic-gate } 3088*0Sstevel@tonic-gate 3089*0Sstevel@tonic-gate /* 3090*0Sstevel@tonic-gate * the intr is through the motherboard. it is faster than PCI route. 3091*0Sstevel@tonic-gate * sometimes ecpp_isr() is invoked before cheerio csr is updated. 3092*0Sstevel@tonic-gate */ 3093*0Sstevel@tonic-gate cheerio_pend_counter = ecpp_isr_max_delay; 3094*0Sstevel@tonic-gate dcsr = GET_DMAC_CSR(pp); 3095*0Sstevel@tonic-gate 3096*0Sstevel@tonic-gate while (!(dcsr & DCSR_INT_PEND) && cheerio_pend_counter-- > 0) { 3097*0Sstevel@tonic-gate drv_usecwait(1); 3098*0Sstevel@tonic-gate dcsr = GET_DMAC_CSR(pp); 3099*0Sstevel@tonic-gate } 3100*0Sstevel@tonic-gate 3101*0Sstevel@tonic-gate /* 3102*0Sstevel@tonic-gate * This is a workaround for what seems to be a timing problem 3103*0Sstevel@tonic-gate * with the delivery of interrupts and CSR updating with the 3104*0Sstevel@tonic-gate * ebus2 csr, superio and the n_ERR pin from the peripheral. 3105*0Sstevel@tonic-gate * 3106*0Sstevel@tonic-gate * delay is not needed for PIO mode 3107*0Sstevel@tonic-gate */ 3108*0Sstevel@tonic-gate if (!COMPAT_PIO(pp)) { 3109*0Sstevel@tonic-gate drv_usecwait(100); 3110*0Sstevel@tonic-gate dcsr = GET_DMAC_CSR(pp); 3111*0Sstevel@tonic-gate } 3112*0Sstevel@tonic-gate 3113*0Sstevel@tonic-gate /* on 97317 in Extended mode IRQ_ST of DSR is deasserted when read */ 3114*0Sstevel@tonic-gate dsr = DSR_READ(pp); 3115*0Sstevel@tonic-gate 3116*0Sstevel@tonic-gate /* 3117*0Sstevel@tonic-gate * check if interrupt is for this device: 3118*0Sstevel@tonic-gate * it should be reflected either in cheerio DCSR register 3119*0Sstevel@tonic-gate * or in IRQ_ST bit of DSR on 97317 3120*0Sstevel@tonic-gate */ 3121*0Sstevel@tonic-gate if ((dcsr & DCSR_INT_PEND) == 0) { 3122*0Sstevel@tonic-gate if (pp->hw != &pc97317) { 3123*0Sstevel@tonic-gate goto unclaimed; 3124*0Sstevel@tonic-gate } 3125*0Sstevel@tonic-gate /* 3126*0Sstevel@tonic-gate * on Excalibur, reading DSR will deassert SuperIO IRQx line 3127*0Sstevel@tonic-gate * RIO's DCSR_INT_PEND seems to follow IRQx transitions, 3128*0Sstevel@tonic-gate * so if DSR is read after interrupt occured, but before 3129*0Sstevel@tonic-gate * we get here, IRQx and hence INT_PEND will be deasserted 3130*0Sstevel@tonic-gate * as a result, we can miss a service interrupt in PIO mode 3131*0Sstevel@tonic-gate * 3132*0Sstevel@tonic-gate * malicious DSR reader is BPPIOC_TESTIO, which is called 3133*0Sstevel@tonic-gate * by LP in between data blocks to check printer status 3134*0Sstevel@tonic-gate * this workaround lets us not to miss an interrupt 3135*0Sstevel@tonic-gate * 3136*0Sstevel@tonic-gate * also, nErr interrupt (ECP mode) not always reflected in DCSR 3137*0Sstevel@tonic-gate */ 3138*0Sstevel@tonic-gate if (((dsr & ECPP_IRQ_ST) == 0) || 3139*0Sstevel@tonic-gate ((COMPAT_PIO(pp)) && (pp->e_busy == ECPP_BUSY)) || 3140*0Sstevel@tonic-gate (((dsr & ECPP_nERR) == 0) && 3141*0Sstevel@tonic-gate (pp->current_mode == ECPP_ECP_MODE))) { 3142*0Sstevel@tonic-gate dcsr = 0; 3143*0Sstevel@tonic-gate } else { 3144*0Sstevel@tonic-gate goto unclaimed; 3145*0Sstevel@tonic-gate } 3146*0Sstevel@tonic-gate } 3147*0Sstevel@tonic-gate 3148*0Sstevel@tonic-gate pp->intr_hard++; 3149*0Sstevel@tonic-gate 3150*0Sstevel@tonic-gate /* the intr is for us - check all possible interrupt sources */ 3151*0Sstevel@tonic-gate if (dcsr & DCSR_ERR_PEND) { 3152*0Sstevel@tonic-gate size_t bcr; 3153*0Sstevel@tonic-gate 3154*0Sstevel@tonic-gate /* we are expecting a data transfer interrupt */ 3155*0Sstevel@tonic-gate ASSERT(pp->e_busy == ECPP_BUSY); 3156*0Sstevel@tonic-gate 3157*0Sstevel@tonic-gate /* 3158*0Sstevel@tonic-gate * some kind of DMA error 3159*0Sstevel@tonic-gate */ 3160*0Sstevel@tonic-gate if (ECPP_DMA_STOP(pp, &bcr) == FAILURE) { 3161*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_isr: dma_stop failed\n"); 3162*0Sstevel@tonic-gate } 3163*0Sstevel@tonic-gate 3164*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_isr: DMAC ERROR bcr=%d\n", bcr); 3165*0Sstevel@tonic-gate 3166*0Sstevel@tonic-gate ecpp_xfer_cleanup(pp); 3167*0Sstevel@tonic-gate 3168*0Sstevel@tonic-gate if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) { 3169*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_isr(e): unbind failed\n"); 3170*0Sstevel@tonic-gate } 3171*0Sstevel@tonic-gate 3172*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3173*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3174*0Sstevel@tonic-gate } 3175*0Sstevel@tonic-gate 3176*0Sstevel@tonic-gate if (dcsr & DCSR_TC) { 3177*0Sstevel@tonic-gate retval = ecpp_dma_ihdlr(pp); 3178*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3179*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3180*0Sstevel@tonic-gate } 3181*0Sstevel@tonic-gate 3182*0Sstevel@tonic-gate if (COMPAT_PIO(pp)) { 3183*0Sstevel@tonic-gate retval = ecpp_pio_ihdlr(pp); 3184*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3185*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3186*0Sstevel@tonic-gate } 3187*0Sstevel@tonic-gate 3188*0Sstevel@tonic-gate /* does peripheral need attention? */ 3189*0Sstevel@tonic-gate if ((dsr & ECPP_nERR) == 0) { 3190*0Sstevel@tonic-gate retval = ecpp_nErr_ihdlr(pp); 3191*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3192*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3193*0Sstevel@tonic-gate } 3194*0Sstevel@tonic-gate 3195*0Sstevel@tonic-gate pp->intr_hard--; 3196*0Sstevel@tonic-gate 3197*0Sstevel@tonic-gate unexpected: 3198*0Sstevel@tonic-gate 3199*0Sstevel@tonic-gate pp->intr_spurious++; 3200*0Sstevel@tonic-gate 3201*0Sstevel@tonic-gate /* 3202*0Sstevel@tonic-gate * The following procedure tries to prevent soft hangs 3203*0Sstevel@tonic-gate * in event of peripheral/superio misbehaviour: 3204*0Sstevel@tonic-gate * if number of unexpected interrupts in the last SPUR_PERIOD ns 3205*0Sstevel@tonic-gate * exceeded SPUR_CRITICAL, then shut up interrupts 3206*0Sstevel@tonic-gate */ 3207*0Sstevel@tonic-gate now = gethrtime(); 3208*0Sstevel@tonic-gate if (pp->lastspur == 0 || now - pp->lastspur > SPUR_PERIOD) { 3209*0Sstevel@tonic-gate /* last unexpected interrupt was long ago */ 3210*0Sstevel@tonic-gate pp->lastspur = now; 3211*0Sstevel@tonic-gate pp->nspur = 1; 3212*0Sstevel@tonic-gate } else { 3213*0Sstevel@tonic-gate /* last unexpected interrupt was recently */ 3214*0Sstevel@tonic-gate pp->nspur++; 3215*0Sstevel@tonic-gate } 3216*0Sstevel@tonic-gate 3217*0Sstevel@tonic-gate if (pp->nspur >= SPUR_CRITICAL) { 3218*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 3219*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK | ECPP_INTR_SRV); 3220*0Sstevel@tonic-gate pp->nspur = 0; 3221*0Sstevel@tonic-gate cmn_err(CE_NOTE, "%s%d: too many interrupt requests", 3222*0Sstevel@tonic-gate ddi_get_name(pp->dip), ddi_get_instance(pp->dip)); 3223*0Sstevel@tonic-gate } else { 3224*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_SRV | ECPP_INTR_MASK); 3225*0Sstevel@tonic-gate } 3226*0Sstevel@tonic-gate 3227*0Sstevel@tonic-gate ecpp_error(pp->dip, 3228*0Sstevel@tonic-gate "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n", 3229*0Sstevel@tonic-gate dcsr, ECR_READ(pp), dsr, DCR_READ(pp), 3230*0Sstevel@tonic-gate pp->current_mode, pp->current_phase); 3231*0Sstevel@tonic-gate 3232*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3233*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3234*0Sstevel@tonic-gate 3235*0Sstevel@tonic-gate unclaimed: 3236*0Sstevel@tonic-gate 3237*0Sstevel@tonic-gate pp->intr_spurious++; 3238*0Sstevel@tonic-gate 3239*0Sstevel@tonic-gate ecpp_error(pp->dip, 3240*0Sstevel@tonic-gate "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n", 3241*0Sstevel@tonic-gate dcsr, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp), 3242*0Sstevel@tonic-gate pp->current_mode, pp->current_phase); 3243*0Sstevel@tonic-gate 3244*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3245*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 3246*0Sstevel@tonic-gate } 3247*0Sstevel@tonic-gate 3248*0Sstevel@tonic-gate /* 3249*0Sstevel@tonic-gate * M1553 intr handler 3250*0Sstevel@tonic-gate */ 3251*0Sstevel@tonic-gate static uint_t 3252*0Sstevel@tonic-gate ecpp_M1553_intr(struct ecppunit *pp) 3253*0Sstevel@tonic-gate { 3254*0Sstevel@tonic-gate int retval = DDI_INTR_UNCLAIMED; 3255*0Sstevel@tonic-gate 3256*0Sstevel@tonic-gate pp->intr_hard++; 3257*0Sstevel@tonic-gate 3258*0Sstevel@tonic-gate if (pp->e_busy == ECPP_BUSY) { 3259*0Sstevel@tonic-gate /* Centronics or Compat PIO transfer */ 3260*0Sstevel@tonic-gate if (COMPAT_PIO(pp)) { 3261*0Sstevel@tonic-gate return (ecpp_pio_ihdlr(pp)); 3262*0Sstevel@tonic-gate } 3263*0Sstevel@tonic-gate 3264*0Sstevel@tonic-gate /* Centronics or Compat DMA transfer */ 3265*0Sstevel@tonic-gate if (COMPAT_DMA(pp) || 3266*0Sstevel@tonic-gate (pp->current_mode == ECPP_ECP_MODE) || 3267*0Sstevel@tonic-gate (pp->current_mode == ECPP_DIAG_MODE)) { 3268*0Sstevel@tonic-gate return (ecpp_dma_ihdlr(pp)); 3269*0Sstevel@tonic-gate } 3270*0Sstevel@tonic-gate } 3271*0Sstevel@tonic-gate 3272*0Sstevel@tonic-gate /* Nibble or ECP backchannel request? */ 3273*0Sstevel@tonic-gate if ((DSR_READ(pp) & ECPP_nERR) == 0) { 3274*0Sstevel@tonic-gate return (ecpp_nErr_ihdlr(pp)); 3275*0Sstevel@tonic-gate } 3276*0Sstevel@tonic-gate 3277*0Sstevel@tonic-gate return (retval); 3278*0Sstevel@tonic-gate } 3279*0Sstevel@tonic-gate 3280*0Sstevel@tonic-gate /* 3281*0Sstevel@tonic-gate * DMA completion interrupt handler 3282*0Sstevel@tonic-gate */ 3283*0Sstevel@tonic-gate static uint_t 3284*0Sstevel@tonic-gate ecpp_dma_ihdlr(struct ecppunit *pp) 3285*0Sstevel@tonic-gate { 3286*0Sstevel@tonic-gate clock_t tm; 3287*0Sstevel@tonic-gate 3288*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n", 3289*0Sstevel@tonic-gate pp->current_mode, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp)); 3290*0Sstevel@tonic-gate 3291*0Sstevel@tonic-gate /* we are expecting a data transfer interrupt */ 3292*0Sstevel@tonic-gate ASSERT(pp->e_busy == ECPP_BUSY); 3293*0Sstevel@tonic-gate 3294*0Sstevel@tonic-gate /* Intr generated while invoking TFIFO mode. Exit */ 3295*0Sstevel@tonic-gate if (pp->tfifo_intr == 1) { 3296*0Sstevel@tonic-gate pp->tfifo_intr = 0; 3297*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_dma_ihdlr: tfifo_intr is 1\n"); 3298*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3299*0Sstevel@tonic-gate } 3300*0Sstevel@tonic-gate 3301*0Sstevel@tonic-gate if (ECPP_DMA_STOP(pp, NULL) == FAILURE) { 3302*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_dma_ihdlr: dma_stop failed\n"); 3303*0Sstevel@tonic-gate } 3304*0Sstevel@tonic-gate 3305*0Sstevel@tonic-gate if (pp->current_mode == ECPP_ECP_MODE && 3306*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_XFER) { 3307*0Sstevel@tonic-gate ecpp_ecp_read_completion(pp); 3308*0Sstevel@tonic-gate } else { 3309*0Sstevel@tonic-gate /* 3310*0Sstevel@tonic-gate * fifo_timer() will do the cleanup when the FIFO drains 3311*0Sstevel@tonic-gate */ 3312*0Sstevel@tonic-gate if ((ECR_READ(pp) & ECPP_FIFO_EMPTY) || 3313*0Sstevel@tonic-gate (pp->current_mode == ECPP_DIAG_MODE)) { 3314*0Sstevel@tonic-gate tm = 0; /* no use in waiting if FIFO is already empty */ 3315*0Sstevel@tonic-gate } else { 3316*0Sstevel@tonic-gate tm = drv_usectohz(FIFO_DRAIN_PERIOD); 3317*0Sstevel@tonic-gate } 3318*0Sstevel@tonic-gate pp->fifo_timer_id = timeout(ecpp_fifo_timer, (caddr_t)pp, tm); 3319*0Sstevel@tonic-gate } 3320*0Sstevel@tonic-gate 3321*0Sstevel@tonic-gate /* 3322*0Sstevel@tonic-gate * Stop the DMA transfer timeout timer 3323*0Sstevel@tonic-gate * this operation will temporarily give up the mutex, 3324*0Sstevel@tonic-gate * so we do it in the end of the handler to avoid races 3325*0Sstevel@tonic-gate */ 3326*0Sstevel@tonic-gate ecpp_untimeout_unblock(pp, &pp->timeout_id); 3327*0Sstevel@tonic-gate 3328*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3329*0Sstevel@tonic-gate } 3330*0Sstevel@tonic-gate 3331*0Sstevel@tonic-gate /* 3332*0Sstevel@tonic-gate * ecpp_pio_ihdlr() is a PIO interrupt processing routine 3333*0Sstevel@tonic-gate * It masks interrupts, updates statistics and initiates next byte transfer 3334*0Sstevel@tonic-gate */ 3335*0Sstevel@tonic-gate static uint_t 3336*0Sstevel@tonic-gate ecpp_pio_ihdlr(struct ecppunit *pp) 3337*0Sstevel@tonic-gate { 3338*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 3339*0Sstevel@tonic-gate ASSERT(pp->e_busy == ECPP_BUSY); 3340*0Sstevel@tonic-gate 3341*0Sstevel@tonic-gate /* update statistics */ 3342*0Sstevel@tonic-gate pp->joblen++; 3343*0Sstevel@tonic-gate pp->ctxpio_obytes++; 3344*0Sstevel@tonic-gate 3345*0Sstevel@tonic-gate /* disable nAck interrups */ 3346*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 3347*0Sstevel@tonic-gate DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_REV_DIR | ECPP_INTR_EN)); 3348*0Sstevel@tonic-gate 3349*0Sstevel@tonic-gate /* 3350*0Sstevel@tonic-gate * If it was the last byte of the data block cleanup, 3351*0Sstevel@tonic-gate * otherwise trigger a soft interrupt to send the next byte 3352*0Sstevel@tonic-gate */ 3353*0Sstevel@tonic-gate if (pp->next_byte >= pp->last_byte) { 3354*0Sstevel@tonic-gate ecpp_xfer_cleanup(pp); 3355*0Sstevel@tonic-gate ecpp_error(pp->dip, 3356*0Sstevel@tonic-gate "ecpp_pio_ihdlr: pp->joblen=%d,pp->ctx_cf=%d,\n", 3357*0Sstevel@tonic-gate pp->joblen, pp->ctx_cf); 3358*0Sstevel@tonic-gate } else { 3359*0Sstevel@tonic-gate if (pp->softintr_pending) { 3360*0Sstevel@tonic-gate ecpp_error(pp->dip, 3361*0Sstevel@tonic-gate "ecpp_pio_ihdlr:E: next byte in progress\n"); 3362*0Sstevel@tonic-gate } else { 3363*0Sstevel@tonic-gate pp->softintr_flags = ECPP_SOFTINTR_PIONEXT; 3364*0Sstevel@tonic-gate pp->softintr_pending = 1; 3365*0Sstevel@tonic-gate ddi_trigger_softintr(pp->softintr_id); 3366*0Sstevel@tonic-gate } 3367*0Sstevel@tonic-gate } 3368*0Sstevel@tonic-gate 3369*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3370*0Sstevel@tonic-gate } 3371*0Sstevel@tonic-gate 3372*0Sstevel@tonic-gate /* 3373*0Sstevel@tonic-gate * ecpp_pio_writeb() sends a byte using Centronics handshake 3374*0Sstevel@tonic-gate */ 3375*0Sstevel@tonic-gate static void 3376*0Sstevel@tonic-gate ecpp_pio_writeb(struct ecppunit *pp) 3377*0Sstevel@tonic-gate { 3378*0Sstevel@tonic-gate uint8_t dcr; 3379*0Sstevel@tonic-gate 3380*0Sstevel@tonic-gate dcr = DCR_READ(pp) & ~ECPP_REV_DIR; 3381*0Sstevel@tonic-gate dcr |= ECPP_INTR_EN; 3382*0Sstevel@tonic-gate 3383*0Sstevel@tonic-gate /* send the next byte */ 3384*0Sstevel@tonic-gate DATAR_WRITE(pp, *(pp->next_byte++)); 3385*0Sstevel@tonic-gate 3386*0Sstevel@tonic-gate drv_usecwait(pp->data_setup_time); 3387*0Sstevel@tonic-gate 3388*0Sstevel@tonic-gate /* Now Assert (neg logic) nStrobe */ 3389*0Sstevel@tonic-gate if (dcr_write(pp, dcr | ECPP_STB) == FAILURE) { 3390*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_pio_writeb:1: failed w/DCR\n"); 3391*0Sstevel@tonic-gate } 3392*0Sstevel@tonic-gate 3393*0Sstevel@tonic-gate /* Enable nAck interrupts */ 3394*0Sstevel@tonic-gate (void) DSR_READ(pp); /* ensure IRQ_ST is armed */ 3395*0Sstevel@tonic-gate ECPP_UNMASK_INTR(pp); 3396*0Sstevel@tonic-gate 3397*0Sstevel@tonic-gate drv_usecwait(pp->strobe_pulse_width); 3398*0Sstevel@tonic-gate 3399*0Sstevel@tonic-gate if (dcr_write(pp, dcr & ~ECPP_STB) == FAILURE) { 3400*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_pio_writeb:2: failed w/DCR\n"); 3401*0Sstevel@tonic-gate } 3402*0Sstevel@tonic-gate } 3403*0Sstevel@tonic-gate 3404*0Sstevel@tonic-gate /* 3405*0Sstevel@tonic-gate * Backchannel request interrupt handler 3406*0Sstevel@tonic-gate */ 3407*0Sstevel@tonic-gate static uint_t 3408*0Sstevel@tonic-gate ecpp_nErr_ihdlr(struct ecppunit *pp) 3409*0Sstevel@tonic-gate { 3410*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_nErr_ihdlr: mode=%x, phase=%x\n", 3411*0Sstevel@tonic-gate pp->current_mode, pp->current_phase); 3412*0Sstevel@tonic-gate 3413*0Sstevel@tonic-gate if (pp->oflag != TRUE) { 3414*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_nErr_ihdlr: not open!\n"); 3415*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 3416*0Sstevel@tonic-gate } 3417*0Sstevel@tonic-gate 3418*0Sstevel@tonic-gate if (pp->e_busy == ECPP_BUSY) { 3419*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_nErr_ihdlr: busy\n"); 3420*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK); 3421*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3422*0Sstevel@tonic-gate } 3423*0Sstevel@tonic-gate 3424*0Sstevel@tonic-gate /* mask nErr & nAck interrupts */ 3425*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 3426*0Sstevel@tonic-gate DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_INTR_EN | ECPP_REV_DIR)); 3427*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK); 3428*0Sstevel@tonic-gate 3429*0Sstevel@tonic-gate /* going reverse */ 3430*0Sstevel@tonic-gate switch (pp->current_mode) { 3431*0Sstevel@tonic-gate case ECPP_ECP_MODE: 3432*0Sstevel@tonic-gate /* 3433*0Sstevel@tonic-gate * Peripheral asserts nPeriphRequest (nFault) 3434*0Sstevel@tonic-gate */ 3435*0Sstevel@tonic-gate break; 3436*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 3437*0Sstevel@tonic-gate /* 3438*0Sstevel@tonic-gate * Event 18: Periph asserts nErr to indicate data avail 3439*0Sstevel@tonic-gate * Event 19: After waiting minimum pulse width, 3440*0Sstevel@tonic-gate * periph sets nAck high to generate an interrupt 3441*0Sstevel@tonic-gate * 3442*0Sstevel@tonic-gate * Interface is in Interrupt Phase 3443*0Sstevel@tonic-gate */ 3444*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_REVINTR; 3445*0Sstevel@tonic-gate 3446*0Sstevel@tonic-gate break; 3447*0Sstevel@tonic-gate default: 3448*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_nErr_ihdlr: wrong mode!\n"); 3449*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 3450*0Sstevel@tonic-gate } 3451*0Sstevel@tonic-gate 3452*0Sstevel@tonic-gate (void) ecpp_backchan_req(pp); /* put backchannel request on the wq */ 3453*0Sstevel@tonic-gate 3454*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3455*0Sstevel@tonic-gate } 3456*0Sstevel@tonic-gate 3457*0Sstevel@tonic-gate /* 3458*0Sstevel@tonic-gate * Softintr handler does work according to softintr_flags: 3459*0Sstevel@tonic-gate * in case of ECPP_SOFTINTR_PIONEXT it sends next byte of PIO transfer 3460*0Sstevel@tonic-gate */ 3461*0Sstevel@tonic-gate static uint_t 3462*0Sstevel@tonic-gate ecpp_softintr(caddr_t arg) 3463*0Sstevel@tonic-gate { 3464*0Sstevel@tonic-gate struct ecppunit *pp = (struct ecppunit *)arg; 3465*0Sstevel@tonic-gate uint32_t unx_len, ecpp_reattempts = 0; 3466*0Sstevel@tonic-gate 3467*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 3468*0Sstevel@tonic-gate 3469*0Sstevel@tonic-gate pp->intr_soft++; 3470*0Sstevel@tonic-gate 3471*0Sstevel@tonic-gate if (!pp->softintr_pending) { 3472*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3473*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3474*0Sstevel@tonic-gate } else { 3475*0Sstevel@tonic-gate pp->softintr_pending = 0; 3476*0Sstevel@tonic-gate } 3477*0Sstevel@tonic-gate 3478*0Sstevel@tonic-gate if (pp->softintr_flags & ECPP_SOFTINTR_PIONEXT) { 3479*0Sstevel@tonic-gate pp->softintr_flags &= ~ECPP_SOFTINTR_PIONEXT; 3480*0Sstevel@tonic-gate /* 3481*0Sstevel@tonic-gate * Sent next byte in PIO mode 3482*0Sstevel@tonic-gate */ 3483*0Sstevel@tonic-gate ecpp_reattempts = 0; 3484*0Sstevel@tonic-gate do { 3485*0Sstevel@tonic-gate if (ecpp_check_status(pp) == SUCCESS) { 3486*0Sstevel@tonic-gate pp->e_busy = ECPP_BUSY; 3487*0Sstevel@tonic-gate break; 3488*0Sstevel@tonic-gate } 3489*0Sstevel@tonic-gate drv_usecwait(1); 3490*0Sstevel@tonic-gate if (pp->isr_reattempt_high < ecpp_reattempts) { 3491*0Sstevel@tonic-gate pp->isr_reattempt_high = ecpp_reattempts; 3492*0Sstevel@tonic-gate } 3493*0Sstevel@tonic-gate } while (++ecpp_reattempts < pp->wait_for_busy); 3494*0Sstevel@tonic-gate 3495*0Sstevel@tonic-gate /* if the peripheral still not recovered suspend the transfer */ 3496*0Sstevel@tonic-gate if (pp->e_busy == ECPP_ERR) { 3497*0Sstevel@tonic-gate ++pp->ctx_cf; /* check status fail */ 3498*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_softintr:check_status:F: " 3499*0Sstevel@tonic-gate "dsr=%x jl=%d cf_isr=%d\n", 3500*0Sstevel@tonic-gate DSR_READ(pp), pp->joblen, pp->ctx_cf); 3501*0Sstevel@tonic-gate 3502*0Sstevel@tonic-gate /* 3503*0Sstevel@tonic-gate * if status signals are bad, 3504*0Sstevel@tonic-gate * put everything back on the wq. 3505*0Sstevel@tonic-gate */ 3506*0Sstevel@tonic-gate unx_len = pp->last_byte - pp->next_byte; 3507*0Sstevel@tonic-gate if (pp->msg != NULL) { 3508*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, 3509*0Sstevel@tonic-gate (void *)pp->msg->b_rptr, unx_len); 3510*0Sstevel@tonic-gate ecpp_error(pp->dip, 3511*0Sstevel@tonic-gate "ecpp_softintr:e1:unx_len=%d\n", unx_len); 3512*0Sstevel@tonic-gate 3513*0Sstevel@tonic-gate freemsg(pp->msg); 3514*0Sstevel@tonic-gate pp->msg = NULL; 3515*0Sstevel@tonic-gate } else { 3516*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, 3517*0Sstevel@tonic-gate pp->next_byte, unx_len); 3518*0Sstevel@tonic-gate ecpp_error(pp->dip, 3519*0Sstevel@tonic-gate "ecpp_softintr:e2:unx_len=%d\n", unx_len); 3520*0Sstevel@tonic-gate } 3521*0Sstevel@tonic-gate 3522*0Sstevel@tonic-gate ecpp_xfer_cleanup(pp); 3523*0Sstevel@tonic-gate pp->e_busy = ECPP_ERR; 3524*0Sstevel@tonic-gate qenable(pp->writeq); 3525*0Sstevel@tonic-gate } else { 3526*0Sstevel@tonic-gate /* send the next one */ 3527*0Sstevel@tonic-gate pp->e_busy = ECPP_BUSY; 3528*0Sstevel@tonic-gate (void) ecpp_pio_writeb(pp); 3529*0Sstevel@tonic-gate } 3530*0Sstevel@tonic-gate } 3531*0Sstevel@tonic-gate 3532*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3533*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3534*0Sstevel@tonic-gate } 3535*0Sstevel@tonic-gate 3536*0Sstevel@tonic-gate 3537*0Sstevel@tonic-gate /* 3538*0Sstevel@tonic-gate * Transfer clean-up: 3539*0Sstevel@tonic-gate * shut down the DMAC 3540*0Sstevel@tonic-gate * stop the transfer timer 3541*0Sstevel@tonic-gate * enable write queue 3542*0Sstevel@tonic-gate */ 3543*0Sstevel@tonic-gate static void 3544*0Sstevel@tonic-gate ecpp_xfer_cleanup(struct ecppunit *pp) 3545*0Sstevel@tonic-gate { 3546*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 3547*0Sstevel@tonic-gate 3548*0Sstevel@tonic-gate /* 3549*0Sstevel@tonic-gate * if we did not use the ioblock, the mblk that 3550*0Sstevel@tonic-gate * was used should be freed. 3551*0Sstevel@tonic-gate */ 3552*0Sstevel@tonic-gate if (pp->msg != NULL) { 3553*0Sstevel@tonic-gate freemsg(pp->msg); 3554*0Sstevel@tonic-gate pp->msg = NULL; 3555*0Sstevel@tonic-gate } 3556*0Sstevel@tonic-gate 3557*0Sstevel@tonic-gate /* The port is no longer active */ 3558*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 3559*0Sstevel@tonic-gate 3560*0Sstevel@tonic-gate /* Stop the transfer timeout timer */ 3561*0Sstevel@tonic-gate ecpp_untimeout_unblock(pp, &pp->timeout_id); 3562*0Sstevel@tonic-gate 3563*0Sstevel@tonic-gate qenable(pp->writeq); 3564*0Sstevel@tonic-gate } 3565*0Sstevel@tonic-gate 3566*0Sstevel@tonic-gate /*VARARGS*/ 3567*0Sstevel@tonic-gate static void 3568*0Sstevel@tonic-gate ecpp_error(dev_info_t *dip, char *fmt, ...) 3569*0Sstevel@tonic-gate { 3570*0Sstevel@tonic-gate static long last; 3571*0Sstevel@tonic-gate static char *lastfmt; 3572*0Sstevel@tonic-gate char msg_buffer[255]; 3573*0Sstevel@tonic-gate va_list ap; 3574*0Sstevel@tonic-gate time_t now; 3575*0Sstevel@tonic-gate 3576*0Sstevel@tonic-gate if (!ecpp_debug) { 3577*0Sstevel@tonic-gate return; 3578*0Sstevel@tonic-gate } 3579*0Sstevel@tonic-gate 3580*0Sstevel@tonic-gate /* 3581*0Sstevel@tonic-gate * This function is supposed to be a quick non-blockable 3582*0Sstevel@tonic-gate * wrapper for cmn_err(9F), which provides a sensible degree 3583*0Sstevel@tonic-gate * of debug message throttling. Not using any type of lock 3584*0Sstevel@tonic-gate * is a requirement, but this also leaves two static variables 3585*0Sstevel@tonic-gate * - last and lastfmt - unprotected. However, this will not do 3586*0Sstevel@tonic-gate * any harm to driver functionality, it can only weaken throttling. 3587*0Sstevel@tonic-gate * The following directive asks warlock to not worry about these 3588*0Sstevel@tonic-gate * variables. 3589*0Sstevel@tonic-gate */ 3590*0Sstevel@tonic-gate _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(last, lastfmt)) 3591*0Sstevel@tonic-gate 3592*0Sstevel@tonic-gate /* 3593*0Sstevel@tonic-gate * Don't print same error message too often. 3594*0Sstevel@tonic-gate */ 3595*0Sstevel@tonic-gate now = gethrestime_sec(); 3596*0Sstevel@tonic-gate if ((last == (now & ~1)) && (lastfmt == fmt)) 3597*0Sstevel@tonic-gate return; 3598*0Sstevel@tonic-gate 3599*0Sstevel@tonic-gate last = now & ~1; 3600*0Sstevel@tonic-gate lastfmt = fmt; 3601*0Sstevel@tonic-gate 3602*0Sstevel@tonic-gate va_start(ap, fmt); 3603*0Sstevel@tonic-gate (void) vsprintf(msg_buffer, fmt, ap); 3604*0Sstevel@tonic-gate cmn_err(CE_CONT, "%s%d: %s", ddi_get_name(dip), 3605*0Sstevel@tonic-gate ddi_get_instance(dip), msg_buffer); 3606*0Sstevel@tonic-gate va_end(ap); 3607*0Sstevel@tonic-gate } 3608*0Sstevel@tonic-gate 3609*0Sstevel@tonic-gate /* 3610*0Sstevel@tonic-gate * Forward transfer timeout 3611*0Sstevel@tonic-gate */ 3612*0Sstevel@tonic-gate static void 3613*0Sstevel@tonic-gate ecpp_xfer_timeout(void *arg) 3614*0Sstevel@tonic-gate { 3615*0Sstevel@tonic-gate struct ecppunit *pp = arg; 3616*0Sstevel@tonic-gate void *unx_addr; 3617*0Sstevel@tonic-gate size_t unx_len, xferd; 3618*0Sstevel@tonic-gate uint8_t dcr; 3619*0Sstevel@tonic-gate timeout_id_t fifo_timer_id; 3620*0Sstevel@tonic-gate 3621*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 3622*0Sstevel@tonic-gate 3623*0Sstevel@tonic-gate if (pp->timeout_id == 0) { 3624*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3625*0Sstevel@tonic-gate return; 3626*0Sstevel@tonic-gate } else { 3627*0Sstevel@tonic-gate pp->timeout_id = 0; 3628*0Sstevel@tonic-gate } 3629*0Sstevel@tonic-gate 3630*0Sstevel@tonic-gate pp->xfer_tout++; 3631*0Sstevel@tonic-gate 3632*0Sstevel@tonic-gate pp->dma_cancelled = TRUE; /* prevent race with isr() */ 3633*0Sstevel@tonic-gate 3634*0Sstevel@tonic-gate if (COMPAT_PIO(pp)) { 3635*0Sstevel@tonic-gate /* 3636*0Sstevel@tonic-gate * PIO mode timeout 3637*0Sstevel@tonic-gate */ 3638*0Sstevel@tonic-gate 3639*0Sstevel@tonic-gate /* turn off nAck interrupts */ 3640*0Sstevel@tonic-gate dcr = DCR_READ(pp); 3641*0Sstevel@tonic-gate (void) dcr_write(pp, dcr & ~(ECPP_REV_DIR | ECPP_INTR_EN)); 3642*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 3643*0Sstevel@tonic-gate 3644*0Sstevel@tonic-gate pp->softintr_pending = 0; 3645*0Sstevel@tonic-gate unx_len = pp->last_byte - pp->next_byte; 3646*0Sstevel@tonic-gate ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len); 3647*0Sstevel@tonic-gate 3648*0Sstevel@tonic-gate if (unx_len > 0) { 3649*0Sstevel@tonic-gate unx_addr = pp->next_byte; 3650*0Sstevel@tonic-gate } else { 3651*0Sstevel@tonic-gate ecpp_xfer_cleanup(pp); 3652*0Sstevel@tonic-gate qenable(pp->writeq); 3653*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3654*0Sstevel@tonic-gate return; 3655*0Sstevel@tonic-gate } 3656*0Sstevel@tonic-gate } else { 3657*0Sstevel@tonic-gate /* 3658*0Sstevel@tonic-gate * DMA mode timeout 3659*0Sstevel@tonic-gate * 3660*0Sstevel@tonic-gate * If DMAC fails to shut off, continue anyways and attempt 3661*0Sstevel@tonic-gate * to put untransfered data back on queue. 3662*0Sstevel@tonic-gate */ 3663*0Sstevel@tonic-gate if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) { 3664*0Sstevel@tonic-gate ecpp_error(pp->dip, 3665*0Sstevel@tonic-gate "ecpp_xfer_timeout: failed dma_stop\n"); 3666*0Sstevel@tonic-gate } 3667*0Sstevel@tonic-gate 3668*0Sstevel@tonic-gate ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len); 3669*0Sstevel@tonic-gate 3670*0Sstevel@tonic-gate if (ddi_dma_unbind_handle(pp->dma_handle) == DDI_FAILURE) { 3671*0Sstevel@tonic-gate ecpp_error(pp->dip, 3672*0Sstevel@tonic-gate "ecpp_xfer_timeout: failed unbind\n"); 3673*0Sstevel@tonic-gate } 3674*0Sstevel@tonic-gate 3675*0Sstevel@tonic-gate /* 3676*0Sstevel@tonic-gate * if the bcr is zero, then DMA is complete and 3677*0Sstevel@tonic-gate * we are waiting for the fifo to drain. So let 3678*0Sstevel@tonic-gate * ecpp_fifo_timer() look after the clean up. 3679*0Sstevel@tonic-gate */ 3680*0Sstevel@tonic-gate if (unx_len == 0) { 3681*0Sstevel@tonic-gate qenable(pp->writeq); 3682*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3683*0Sstevel@tonic-gate return; 3684*0Sstevel@tonic-gate } else { 3685*0Sstevel@tonic-gate xferd = pp->dma_cookie.dmac_size - unx_len; 3686*0Sstevel@tonic-gate pp->resid -= xferd; 3687*0Sstevel@tonic-gate unx_len = pp->resid; 3688*0Sstevel@tonic-gate 3689*0Sstevel@tonic-gate /* update statistics */ 3690*0Sstevel@tonic-gate pp->obytes[pp->current_mode] += xferd; 3691*0Sstevel@tonic-gate pp->joblen += xferd; 3692*0Sstevel@tonic-gate 3693*0Sstevel@tonic-gate if (pp->msg != NULL) { 3694*0Sstevel@tonic-gate unx_addr = (caddr_t)pp->msg->b_wptr - unx_len; 3695*0Sstevel@tonic-gate } else { 3696*0Sstevel@tonic-gate unx_addr = pp->ioblock + 3697*0Sstevel@tonic-gate (pp->xfercnt - unx_len); 3698*0Sstevel@tonic-gate } 3699*0Sstevel@tonic-gate } 3700*0Sstevel@tonic-gate } 3701*0Sstevel@tonic-gate 3702*0Sstevel@tonic-gate /* Following code is common for PIO and DMA modes */ 3703*0Sstevel@tonic-gate 3704*0Sstevel@tonic-gate ecpp_putback_untransfered(pp, (caddr_t)unx_addr, unx_len); 3705*0Sstevel@tonic-gate 3706*0Sstevel@tonic-gate if (pp->msg != NULL) { 3707*0Sstevel@tonic-gate freemsg(pp->msg); 3708*0Sstevel@tonic-gate pp->msg = NULL; 3709*0Sstevel@tonic-gate } 3710*0Sstevel@tonic-gate 3711*0Sstevel@tonic-gate /* mark the error status structure */ 3712*0Sstevel@tonic-gate pp->timeout_error = 1; 3713*0Sstevel@tonic-gate pp->e_busy = ECPP_ERR; 3714*0Sstevel@tonic-gate fifo_timer_id = pp->fifo_timer_id; 3715*0Sstevel@tonic-gate pp->fifo_timer_id = 0; 3716*0Sstevel@tonic-gate 3717*0Sstevel@tonic-gate qenable(pp->writeq); 3718*0Sstevel@tonic-gate 3719*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3720*0Sstevel@tonic-gate 3721*0Sstevel@tonic-gate if (fifo_timer_id) { 3722*0Sstevel@tonic-gate (void) untimeout(fifo_timer_id); 3723*0Sstevel@tonic-gate } 3724*0Sstevel@tonic-gate } 3725*0Sstevel@tonic-gate 3726*0Sstevel@tonic-gate static void 3727*0Sstevel@tonic-gate ecpp_putback_untransfered(struct ecppunit *pp, void *startp, uint_t len) 3728*0Sstevel@tonic-gate { 3729*0Sstevel@tonic-gate mblk_t *new_mp; 3730*0Sstevel@tonic-gate 3731*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_putback_untrans=%d\n", len); 3732*0Sstevel@tonic-gate 3733*0Sstevel@tonic-gate if (len == 0) { 3734*0Sstevel@tonic-gate return; 3735*0Sstevel@tonic-gate } 3736*0Sstevel@tonic-gate 3737*0Sstevel@tonic-gate new_mp = allocb(len, BPRI_MED); 3738*0Sstevel@tonic-gate if (new_mp == NULL) { 3739*0Sstevel@tonic-gate ecpp_error(pp->dip, 3740*0Sstevel@tonic-gate "ecpp_putback_untransfered: allocb FAILURE.\n"); 3741*0Sstevel@tonic-gate return; 3742*0Sstevel@tonic-gate } 3743*0Sstevel@tonic-gate 3744*0Sstevel@tonic-gate bcopy(startp, new_mp->b_rptr, len); 3745*0Sstevel@tonic-gate new_mp->b_wptr = new_mp->b_rptr + len; 3746*0Sstevel@tonic-gate 3747*0Sstevel@tonic-gate if (!putbq(pp->writeq, new_mp)) { 3748*0Sstevel@tonic-gate freemsg(new_mp); 3749*0Sstevel@tonic-gate } 3750*0Sstevel@tonic-gate } 3751*0Sstevel@tonic-gate 3752*0Sstevel@tonic-gate static uchar_t 3753*0Sstevel@tonic-gate ecr_write(struct ecppunit *pp, uint8_t ecr_byte) 3754*0Sstevel@tonic-gate { 3755*0Sstevel@tonic-gate int i, current_ecr; 3756*0Sstevel@tonic-gate 3757*0Sstevel@tonic-gate for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) { 3758*0Sstevel@tonic-gate ECR_WRITE(pp, ecr_byte); 3759*0Sstevel@tonic-gate 3760*0Sstevel@tonic-gate current_ecr = ECR_READ(pp); 3761*0Sstevel@tonic-gate 3762*0Sstevel@tonic-gate /* mask off the lower two read-only bits */ 3763*0Sstevel@tonic-gate if ((ecr_byte & 0xFC) == (current_ecr & 0xFC)) 3764*0Sstevel@tonic-gate return (SUCCESS); 3765*0Sstevel@tonic-gate } 3766*0Sstevel@tonic-gate return (FAILURE); 3767*0Sstevel@tonic-gate } 3768*0Sstevel@tonic-gate 3769*0Sstevel@tonic-gate static uchar_t 3770*0Sstevel@tonic-gate dcr_write(struct ecppunit *pp, uint8_t dcr_byte) 3771*0Sstevel@tonic-gate { 3772*0Sstevel@tonic-gate uint8_t current_dcr; 3773*0Sstevel@tonic-gate int i; 3774*0Sstevel@tonic-gate 3775*0Sstevel@tonic-gate for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) { 3776*0Sstevel@tonic-gate DCR_WRITE(pp, dcr_byte); 3777*0Sstevel@tonic-gate 3778*0Sstevel@tonic-gate current_dcr = DCR_READ(pp); 3779*0Sstevel@tonic-gate 3780*0Sstevel@tonic-gate /* compare only bits 0-4 (direction bit return 1) */ 3781*0Sstevel@tonic-gate if ((dcr_byte & 0x1F) == (current_dcr & 0x1F)) 3782*0Sstevel@tonic-gate return (SUCCESS); 3783*0Sstevel@tonic-gate } 3784*0Sstevel@tonic-gate ecpp_error(pp->dip, 3785*0Sstevel@tonic-gate "(%d)dcr_write: dcr written =%x, dcr readback =%x\n", 3786*0Sstevel@tonic-gate i, dcr_byte, current_dcr); 3787*0Sstevel@tonic-gate 3788*0Sstevel@tonic-gate return (FAILURE); 3789*0Sstevel@tonic-gate } 3790*0Sstevel@tonic-gate 3791*0Sstevel@tonic-gate static uchar_t 3792*0Sstevel@tonic-gate ecpp_reset_port_regs(struct ecppunit *pp) 3793*0Sstevel@tonic-gate { 3794*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT); 3795*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV); 3796*0Sstevel@tonic-gate return (SUCCESS); 3797*0Sstevel@tonic-gate } 3798*0Sstevel@tonic-gate 3799*0Sstevel@tonic-gate /* 3800*0Sstevel@tonic-gate * The data transferred by the DMA engine goes through the FIFO, 3801*0Sstevel@tonic-gate * so that when the DMA counter reaches zero (and an interrupt occurs) 3802*0Sstevel@tonic-gate * the FIFO can still contain data. If this is the case, the ISR will 3803*0Sstevel@tonic-gate * schedule this callback to wait until the FIFO drains or a timeout occurs. 3804*0Sstevel@tonic-gate */ 3805*0Sstevel@tonic-gate static void 3806*0Sstevel@tonic-gate ecpp_fifo_timer(void *arg) 3807*0Sstevel@tonic-gate { 3808*0Sstevel@tonic-gate struct ecppunit *pp = arg; 3809*0Sstevel@tonic-gate uint8_t ecr; 3810*0Sstevel@tonic-gate timeout_id_t timeout_id; 3811*0Sstevel@tonic-gate 3812*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 3813*0Sstevel@tonic-gate 3814*0Sstevel@tonic-gate /* 3815*0Sstevel@tonic-gate * If the FIFO timer has been turned off, exit. 3816*0Sstevel@tonic-gate */ 3817*0Sstevel@tonic-gate if (pp->fifo_timer_id == 0) { 3818*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_fifo_timer: untimedout\n"); 3819*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3820*0Sstevel@tonic-gate return; 3821*0Sstevel@tonic-gate } else { 3822*0Sstevel@tonic-gate pp->fifo_timer_id = 0; 3823*0Sstevel@tonic-gate } 3824*0Sstevel@tonic-gate 3825*0Sstevel@tonic-gate /* 3826*0Sstevel@tonic-gate * If the FIFO is not empty restart timer. Wait FIFO_DRAIN_PERIOD 3827*0Sstevel@tonic-gate * (250 ms) and check FIFO_EMPTY bit again. Repeat until FIFO is 3828*0Sstevel@tonic-gate * empty or until 10 * FIFO_DRAIN_PERIOD expires. 3829*0Sstevel@tonic-gate */ 3830*0Sstevel@tonic-gate ecr = ECR_READ(pp); 3831*0Sstevel@tonic-gate 3832*0Sstevel@tonic-gate if ((pp->current_mode != ECPP_DIAG_MODE) && 3833*0Sstevel@tonic-gate (((ecr & ECPP_FIFO_EMPTY) == 0) && 3834*0Sstevel@tonic-gate (pp->ecpp_drain_counter < 10))) { 3835*0Sstevel@tonic-gate 3836*0Sstevel@tonic-gate ecpp_error(pp->dip, 3837*0Sstevel@tonic-gate "ecpp_fifo_timer(%d):FIFO not empty:ecr=%x\n", 3838*0Sstevel@tonic-gate pp->ecpp_drain_counter, ecr); 3839*0Sstevel@tonic-gate 3840*0Sstevel@tonic-gate pp->fifo_timer_id = timeout(ecpp_fifo_timer, 3841*0Sstevel@tonic-gate (caddr_t)pp, drv_usectohz(FIFO_DRAIN_PERIOD)); 3842*0Sstevel@tonic-gate ++pp->ecpp_drain_counter; 3843*0Sstevel@tonic-gate 3844*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3845*0Sstevel@tonic-gate return; 3846*0Sstevel@tonic-gate } 3847*0Sstevel@tonic-gate 3848*0Sstevel@tonic-gate if (pp->current_mode != ECPP_DIAG_MODE) { 3849*0Sstevel@tonic-gate /* 3850*0Sstevel@tonic-gate * If the FIFO won't drain after 10 FIFO_DRAIN_PERIODs 3851*0Sstevel@tonic-gate * then don't wait any longer. Simply clean up the transfer. 3852*0Sstevel@tonic-gate */ 3853*0Sstevel@tonic-gate if (pp->ecpp_drain_counter >= 10) { 3854*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_fifo_timer(%d):" 3855*0Sstevel@tonic-gate " clearing FIFO,can't wait:ecr=%x\n", 3856*0Sstevel@tonic-gate pp->ecpp_drain_counter, ecr); 3857*0Sstevel@tonic-gate } else { 3858*0Sstevel@tonic-gate ecpp_error(pp->dip, 3859*0Sstevel@tonic-gate "ecpp_fifo_timer(%d):FIFO empty:ecr=%x\n", 3860*0Sstevel@tonic-gate pp->ecpp_drain_counter, ecr); 3861*0Sstevel@tonic-gate } 3862*0Sstevel@tonic-gate 3863*0Sstevel@tonic-gate pp->ecpp_drain_counter = 0; 3864*0Sstevel@tonic-gate } 3865*0Sstevel@tonic-gate 3866*0Sstevel@tonic-gate /* 3867*0Sstevel@tonic-gate * Main section of routine: 3868*0Sstevel@tonic-gate * - stop the DMA transfer timer 3869*0Sstevel@tonic-gate * - program DMA with next cookie/window or unbind the DMA mapping 3870*0Sstevel@tonic-gate * - update stats 3871*0Sstevel@tonic-gate * - if last mblk in queue, signal to close() & return to idle state 3872*0Sstevel@tonic-gate */ 3873*0Sstevel@tonic-gate 3874*0Sstevel@tonic-gate /* Stop the DMA transfer timeout timer */ 3875*0Sstevel@tonic-gate timeout_id = pp->timeout_id; 3876*0Sstevel@tonic-gate pp->timeout_id = 0; 3877*0Sstevel@tonic-gate 3878*0Sstevel@tonic-gate /* data has drained from fifo, it is ok to free dma resource */ 3879*0Sstevel@tonic-gate if (pp->current_mode == ECPP_ECP_MODE || 3880*0Sstevel@tonic-gate pp->current_mode == ECPP_DIAG_MODE || 3881*0Sstevel@tonic-gate COMPAT_DMA(pp)) { 3882*0Sstevel@tonic-gate off_t off; 3883*0Sstevel@tonic-gate size_t len; 3884*0Sstevel@tonic-gate 3885*0Sstevel@tonic-gate /* update residual */ 3886*0Sstevel@tonic-gate pp->resid -= pp->dma_cookie.dmac_size; 3887*0Sstevel@tonic-gate 3888*0Sstevel@tonic-gate /* update statistics */ 3889*0Sstevel@tonic-gate pp->joblen += pp->dma_cookie.dmac_size; 3890*0Sstevel@tonic-gate if (pp->dma_dir == DDI_DMA_WRITE) { 3891*0Sstevel@tonic-gate pp->obytes[pp->current_mode] += 3892*0Sstevel@tonic-gate pp->dma_cookie.dmac_size; 3893*0Sstevel@tonic-gate } else { 3894*0Sstevel@tonic-gate pp->ibytes[pp->current_mode] += 3895*0Sstevel@tonic-gate pp->dma_cookie.dmac_size; 3896*0Sstevel@tonic-gate } 3897*0Sstevel@tonic-gate 3898*0Sstevel@tonic-gate /* 3899*0Sstevel@tonic-gate * Look if any cookies/windows left 3900*0Sstevel@tonic-gate */ 3901*0Sstevel@tonic-gate if (--pp->dma_cookie_count > 0) { 3902*0Sstevel@tonic-gate /* process the next cookie */ 3903*0Sstevel@tonic-gate ddi_dma_nextcookie(pp->dma_handle, 3904*0Sstevel@tonic-gate &pp->dma_cookie); 3905*0Sstevel@tonic-gate } else if (pp->dma_curwin < pp->dma_nwin) { 3906*0Sstevel@tonic-gate /* process the next window */ 3907*0Sstevel@tonic-gate if (ddi_dma_getwin(pp->dma_handle, 3908*0Sstevel@tonic-gate pp->dma_curwin, &off, &len, 3909*0Sstevel@tonic-gate &pp->dma_cookie, 3910*0Sstevel@tonic-gate &pp->dma_cookie_count) != DDI_SUCCESS) { 3911*0Sstevel@tonic-gate ecpp_error(pp->dip, 3912*0Sstevel@tonic-gate "ecpp_fifo_timer: ddi_dma_getwin failed\n"); 3913*0Sstevel@tonic-gate goto dma_done; 3914*0Sstevel@tonic-gate } 3915*0Sstevel@tonic-gate 3916*0Sstevel@tonic-gate pp->dma_curwin++; 3917*0Sstevel@tonic-gate } else { 3918*0Sstevel@tonic-gate goto dma_done; 3919*0Sstevel@tonic-gate } 3920*0Sstevel@tonic-gate 3921*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_fifo_timer: next addr=%llx len=%d\n", 3922*0Sstevel@tonic-gate pp->dma_cookie.dmac_address, 3923*0Sstevel@tonic-gate pp->dma_cookie.dmac_size); 3924*0Sstevel@tonic-gate 3925*0Sstevel@tonic-gate /* kick off new transfer */ 3926*0Sstevel@tonic-gate if (ECPP_DMA_START(pp) != SUCCESS) { 3927*0Sstevel@tonic-gate ecpp_error(pp->dip, 3928*0Sstevel@tonic-gate "ecpp_fifo_timer: dma_start failed\n"); 3929*0Sstevel@tonic-gate goto dma_done; 3930*0Sstevel@tonic-gate } 3931*0Sstevel@tonic-gate 3932*0Sstevel@tonic-gate (void) ecr_write(pp, (ecr & 0xe0) | 3933*0Sstevel@tonic-gate ECPP_DMA_ENABLE | ECPP_INTR_MASK); 3934*0Sstevel@tonic-gate 3935*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3936*0Sstevel@tonic-gate 3937*0Sstevel@tonic-gate if (timeout_id) { 3938*0Sstevel@tonic-gate (void) untimeout(timeout_id); 3939*0Sstevel@tonic-gate } 3940*0Sstevel@tonic-gate return; 3941*0Sstevel@tonic-gate 3942*0Sstevel@tonic-gate dma_done: 3943*0Sstevel@tonic-gate if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) { 3944*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_fifo_timer: unbind failed\n"); 3945*0Sstevel@tonic-gate } else { 3946*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_fifo_timer: unbind ok\n"); 3947*0Sstevel@tonic-gate } 3948*0Sstevel@tonic-gate } 3949*0Sstevel@tonic-gate 3950*0Sstevel@tonic-gate /* 3951*0Sstevel@tonic-gate * if we did not use the dmablock, the mblk that 3952*0Sstevel@tonic-gate * was used should be freed. 3953*0Sstevel@tonic-gate */ 3954*0Sstevel@tonic-gate if (pp->msg != NULL) { 3955*0Sstevel@tonic-gate freemsg(pp->msg); 3956*0Sstevel@tonic-gate pp->msg = NULL; 3957*0Sstevel@tonic-gate } 3958*0Sstevel@tonic-gate 3959*0Sstevel@tonic-gate /* The port is no longer active */ 3960*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 3961*0Sstevel@tonic-gate 3962*0Sstevel@tonic-gate qenable(pp->writeq); 3963*0Sstevel@tonic-gate 3964*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 3965*0Sstevel@tonic-gate 3966*0Sstevel@tonic-gate if (timeout_id) { 3967*0Sstevel@tonic-gate (void) untimeout(timeout_id); 3968*0Sstevel@tonic-gate } 3969*0Sstevel@tonic-gate } 3970*0Sstevel@tonic-gate 3971*0Sstevel@tonic-gate /* 3972*0Sstevel@tonic-gate * In Compatibility mode, check if the peripheral is ready to accept data 3973*0Sstevel@tonic-gate */ 3974*0Sstevel@tonic-gate static uint8_t 3975*0Sstevel@tonic-gate ecpp_check_status(struct ecppunit *pp) 3976*0Sstevel@tonic-gate { 3977*0Sstevel@tonic-gate uint8_t dsr; 3978*0Sstevel@tonic-gate uint8_t statmask; 3979*0Sstevel@tonic-gate 3980*0Sstevel@tonic-gate if (pp->current_mode == ECPP_ECP_MODE || 3981*0Sstevel@tonic-gate pp->current_mode == ECPP_DIAG_MODE) 3982*0Sstevel@tonic-gate return (SUCCESS); 3983*0Sstevel@tonic-gate 3984*0Sstevel@tonic-gate statmask = ECPP_nERR | ECPP_SLCT | ECPP_nBUSY | ECPP_nACK; 3985*0Sstevel@tonic-gate 3986*0Sstevel@tonic-gate dsr = DSR_READ(pp); 3987*0Sstevel@tonic-gate if ((dsr & ECPP_PE) || ((dsr & statmask) != statmask)) { 3988*0Sstevel@tonic-gate pp->e_busy = ECPP_ERR; 3989*0Sstevel@tonic-gate return (FAILURE); 3990*0Sstevel@tonic-gate } else { 3991*0Sstevel@tonic-gate return (SUCCESS); 3992*0Sstevel@tonic-gate } 3993*0Sstevel@tonic-gate } 3994*0Sstevel@tonic-gate 3995*0Sstevel@tonic-gate /* 3996*0Sstevel@tonic-gate * if the peripheral is not ready to accept data, write service routine 3997*0Sstevel@tonic-gate * periodically reschedules itself to recheck peripheral status 3998*0Sstevel@tonic-gate * and start data transfer as soon as possible 3999*0Sstevel@tonic-gate */ 4000*0Sstevel@tonic-gate static void 4001*0Sstevel@tonic-gate ecpp_wsrv_timer(void *arg) 4002*0Sstevel@tonic-gate { 4003*0Sstevel@tonic-gate struct ecppunit *pp = arg; 4004*0Sstevel@tonic-gate 4005*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wsrv_timer: starting\n"); 4006*0Sstevel@tonic-gate 4007*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 4008*0Sstevel@tonic-gate 4009*0Sstevel@tonic-gate if (pp->wsrv_timer_id == 0) { 4010*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4011*0Sstevel@tonic-gate return; 4012*0Sstevel@tonic-gate } else { 4013*0Sstevel@tonic-gate pp->wsrv_timer_id = 0; 4014*0Sstevel@tonic-gate } 4015*0Sstevel@tonic-gate 4016*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_wsrv_timer: qenabling...\n"); 4017*0Sstevel@tonic-gate 4018*0Sstevel@tonic-gate qenable(pp->writeq); 4019*0Sstevel@tonic-gate 4020*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4021*0Sstevel@tonic-gate } 4022*0Sstevel@tonic-gate 4023*0Sstevel@tonic-gate /* 4024*0Sstevel@tonic-gate * Allocate a message indicating a backchannel request 4025*0Sstevel@tonic-gate * and put it on the write queue 4026*0Sstevel@tonic-gate */ 4027*0Sstevel@tonic-gate static int 4028*0Sstevel@tonic-gate ecpp_backchan_req(struct ecppunit *pp) 4029*0Sstevel@tonic-gate { 4030*0Sstevel@tonic-gate mblk_t *mp; 4031*0Sstevel@tonic-gate 4032*0Sstevel@tonic-gate if ((mp = allocb(sizeof (int), BPRI_MED)) == NULL) { 4033*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_backchan_req: allocb failed\n"); 4034*0Sstevel@tonic-gate return (FAILURE); 4035*0Sstevel@tonic-gate } else { 4036*0Sstevel@tonic-gate mp->b_datap->db_type = M_CTL; 4037*0Sstevel@tonic-gate *(int *)mp->b_rptr = ECPP_BACKCHANNEL; 4038*0Sstevel@tonic-gate mp->b_wptr = mp->b_rptr + sizeof (int); 4039*0Sstevel@tonic-gate if (!putbq(pp->writeq, mp)) { 4040*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_backchan_req:putbq failed\n"); 4041*0Sstevel@tonic-gate freemsg(mp); 4042*0Sstevel@tonic-gate return (FAILURE); 4043*0Sstevel@tonic-gate } 4044*0Sstevel@tonic-gate return (SUCCESS); 4045*0Sstevel@tonic-gate } 4046*0Sstevel@tonic-gate } 4047*0Sstevel@tonic-gate 4048*0Sstevel@tonic-gate /* 4049*0Sstevel@tonic-gate * Cancel the function scheduled with timeout(9F) 4050*0Sstevel@tonic-gate * This function is to be called with the mutex held 4051*0Sstevel@tonic-gate */ 4052*0Sstevel@tonic-gate static void 4053*0Sstevel@tonic-gate ecpp_untimeout_unblock(struct ecppunit *pp, timeout_id_t *id) 4054*0Sstevel@tonic-gate { 4055*0Sstevel@tonic-gate timeout_id_t saved_id; 4056*0Sstevel@tonic-gate 4057*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 4058*0Sstevel@tonic-gate 4059*0Sstevel@tonic-gate if (*id) { 4060*0Sstevel@tonic-gate saved_id = *id; 4061*0Sstevel@tonic-gate *id = 0; 4062*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4063*0Sstevel@tonic-gate (void) untimeout(saved_id); 4064*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 4065*0Sstevel@tonic-gate } 4066*0Sstevel@tonic-gate } 4067*0Sstevel@tonic-gate 4068*0Sstevel@tonic-gate /* 4069*0Sstevel@tonic-gate * get prnio interface capabilities 4070*0Sstevel@tonic-gate */ 4071*0Sstevel@tonic-gate static uint_t 4072*0Sstevel@tonic-gate ecpp_get_prn_ifcap(struct ecppunit *pp) 4073*0Sstevel@tonic-gate { 4074*0Sstevel@tonic-gate uint_t ifcap; 4075*0Sstevel@tonic-gate 4076*0Sstevel@tonic-gate ifcap = PRN_1284_DEVID | PRN_TIMEOUTS | PRN_STREAMS; 4077*0Sstevel@tonic-gate 4078*0Sstevel@tonic-gate /* status (DSR) only makes sense in Centronics & Compat modes */ 4079*0Sstevel@tonic-gate if (pp->current_mode == ECPP_CENTRONICS || 4080*0Sstevel@tonic-gate pp->current_mode == ECPP_COMPAT_MODE) { 4081*0Sstevel@tonic-gate ifcap |= PRN_1284_STATUS; 4082*0Sstevel@tonic-gate } else if (pp->current_mode == ECPP_NIBBLE_MODE || 4083*0Sstevel@tonic-gate pp->current_mode == ECPP_ECP_MODE) { 4084*0Sstevel@tonic-gate ifcap |= PRN_BIDI; 4085*0Sstevel@tonic-gate } 4086*0Sstevel@tonic-gate 4087*0Sstevel@tonic-gate return (ifcap); 4088*0Sstevel@tonic-gate } 4089*0Sstevel@tonic-gate 4090*0Sstevel@tonic-gate /* 4091*0Sstevel@tonic-gate * Determine SuperI/O type 4092*0Sstevel@tonic-gate */ 4093*0Sstevel@tonic-gate static struct ecpp_hw_bind * 4094*0Sstevel@tonic-gate ecpp_determine_sio_type(struct ecppunit *pp) 4095*0Sstevel@tonic-gate { 4096*0Sstevel@tonic-gate struct ecpp_hw_bind *hw_bind; 4097*0Sstevel@tonic-gate char *name; 4098*0Sstevel@tonic-gate int i; 4099*0Sstevel@tonic-gate 4100*0Sstevel@tonic-gate name = ddi_binding_name(pp->dip); 4101*0Sstevel@tonic-gate 4102*0Sstevel@tonic-gate for (hw_bind = NULL, i = 0; i < NELEM(ecpp_hw_bind); i++) { 4103*0Sstevel@tonic-gate if (strcmp(name, ecpp_hw_bind[i].name) == 0) { 4104*0Sstevel@tonic-gate hw_bind = &ecpp_hw_bind[i]; 4105*0Sstevel@tonic-gate break; 4106*0Sstevel@tonic-gate } 4107*0Sstevel@tonic-gate } 4108*0Sstevel@tonic-gate 4109*0Sstevel@tonic-gate return (hw_bind); 4110*0Sstevel@tonic-gate } 4111*0Sstevel@tonic-gate 4112*0Sstevel@tonic-gate 4113*0Sstevel@tonic-gate /* 4114*0Sstevel@tonic-gate * 4115*0Sstevel@tonic-gate * IEEE 1284 support routines: 4116*0Sstevel@tonic-gate * negotiation and termination; 4117*0Sstevel@tonic-gate * phase transitions; 4118*0Sstevel@tonic-gate * device ID; 4119*0Sstevel@tonic-gate * 4120*0Sstevel@tonic-gate */ 4121*0Sstevel@tonic-gate 4122*0Sstevel@tonic-gate /* 4123*0Sstevel@tonic-gate * Interface initialization, abnormal termination into Compatibility mode 4124*0Sstevel@tonic-gate * 4125*0Sstevel@tonic-gate * Peripheral may be non-1284, so we set current mode to ECPP_CENTRONICS 4126*0Sstevel@tonic-gate */ 4127*0Sstevel@tonic-gate static void 4128*0Sstevel@tonic-gate ecpp_1284_init_interface(struct ecppunit *pp) 4129*0Sstevel@tonic-gate { 4130*0Sstevel@tonic-gate ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001); 4131*0Sstevel@tonic-gate 4132*0Sstevel@tonic-gate /* 4133*0Sstevel@tonic-gate * Toggle the nInit signal if configured in ecpp.conf 4134*0Sstevel@tonic-gate * for most peripherals it is not needed 4135*0Sstevel@tonic-gate */ 4136*0Sstevel@tonic-gate if (pp->init_seq == TRUE) { 4137*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN); 4138*0Sstevel@tonic-gate drv_usecwait(50); /* T(ER) = 50us */ 4139*0Sstevel@tonic-gate } 4140*0Sstevel@tonic-gate 4141*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN); 4142*0Sstevel@tonic-gate 4143*0Sstevel@tonic-gate pp->current_mode = pp->backchannel = ECPP_CENTRONICS; 4144*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_C_IDLE; 4145*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4146*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 4147*0Sstevel@tonic-gate 4148*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_1284_init_interface: ok\n"); 4149*0Sstevel@tonic-gate } 4150*0Sstevel@tonic-gate 4151*0Sstevel@tonic-gate /* 4152*0Sstevel@tonic-gate * ECP mode negotiation 4153*0Sstevel@tonic-gate */ 4154*0Sstevel@tonic-gate static int 4155*0Sstevel@tonic-gate ecp_negotiation(struct ecppunit *pp) 4156*0Sstevel@tonic-gate { 4157*0Sstevel@tonic-gate uint8_t dsr; 4158*0Sstevel@tonic-gate 4159*0Sstevel@tonic-gate /* ECP mode negotiation */ 4160*0Sstevel@tonic-gate 4161*0Sstevel@tonic-gate if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE) 4162*0Sstevel@tonic-gate return (FAILURE); 4163*0Sstevel@tonic-gate 4164*0Sstevel@tonic-gate /* Event 5: peripheral deasserts PError and Busy, asserts Select */ 4165*0Sstevel@tonic-gate if ((dsr & (ECPP_PE | ECPP_nBUSY | ECPP_SLCT)) != 4166*0Sstevel@tonic-gate (ECPP_nBUSY | ECPP_SLCT)) { 4167*0Sstevel@tonic-gate ecpp_error(pp->dip, 4168*0Sstevel@tonic-gate "ecp_negotiation: failed event 5 %x\n", DSR_READ(pp)); 4169*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4170*0Sstevel@tonic-gate return (FAILURE); 4171*0Sstevel@tonic-gate } 4172*0Sstevel@tonic-gate 4173*0Sstevel@tonic-gate /* entered Setup Phase */ 4174*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_SETUP; 4175*0Sstevel@tonic-gate 4176*0Sstevel@tonic-gate /* Event 30: host asserts nAutoFd */ 4177*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX); 4178*0Sstevel@tonic-gate 4179*0Sstevel@tonic-gate /* Event 31: peripheral asserts PError */ 4180*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) { 4181*0Sstevel@tonic-gate ecpp_error(pp->dip, 4182*0Sstevel@tonic-gate "ecp_negotiation: failed event 31 %x\n", DSR_READ(pp)); 4183*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4184*0Sstevel@tonic-gate return (FAILURE); 4185*0Sstevel@tonic-gate } 4186*0Sstevel@tonic-gate 4187*0Sstevel@tonic-gate /* entered Forward Idle Phase */ 4188*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE; 4189*0Sstevel@tonic-gate 4190*0Sstevel@tonic-gate /* successful negotiation into ECP mode */ 4191*0Sstevel@tonic-gate pp->current_mode = ECPP_ECP_MODE; 4192*0Sstevel@tonic-gate pp->backchannel = ECPP_ECP_MODE; 4193*0Sstevel@tonic-gate 4194*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_negotiation: ok\n"); 4195*0Sstevel@tonic-gate 4196*0Sstevel@tonic-gate return (SUCCESS); 4197*0Sstevel@tonic-gate } 4198*0Sstevel@tonic-gate 4199*0Sstevel@tonic-gate /* 4200*0Sstevel@tonic-gate * Nibble mode negotiation 4201*0Sstevel@tonic-gate */ 4202*0Sstevel@tonic-gate static int 4203*0Sstevel@tonic-gate nibble_negotiation(struct ecppunit *pp) 4204*0Sstevel@tonic-gate { 4205*0Sstevel@tonic-gate uint8_t dsr; 4206*0Sstevel@tonic-gate 4207*0Sstevel@tonic-gate if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) { 4208*0Sstevel@tonic-gate return (FAILURE); 4209*0Sstevel@tonic-gate } 4210*0Sstevel@tonic-gate 4211*0Sstevel@tonic-gate /* 4212*0Sstevel@tonic-gate * If peripheral has data available, PE and nErr will 4213*0Sstevel@tonic-gate * be set low at Event 5 & 6. 4214*0Sstevel@tonic-gate */ 4215*0Sstevel@tonic-gate if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) { 4216*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_AVAIL; 4217*0Sstevel@tonic-gate } else { 4218*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_NAVAIL; 4219*0Sstevel@tonic-gate } 4220*0Sstevel@tonic-gate 4221*0Sstevel@tonic-gate /* successful negotiation into Nibble mode */ 4222*0Sstevel@tonic-gate pp->current_mode = ECPP_NIBBLE_MODE; 4223*0Sstevel@tonic-gate pp->backchannel = ECPP_NIBBLE_MODE; 4224*0Sstevel@tonic-gate 4225*0Sstevel@tonic-gate ecpp_error(pp->dip, "nibble_negotiation: ok (phase=%x)\n", 4226*0Sstevel@tonic-gate pp->current_phase); 4227*0Sstevel@tonic-gate 4228*0Sstevel@tonic-gate return (SUCCESS); 4229*0Sstevel@tonic-gate 4230*0Sstevel@tonic-gate } 4231*0Sstevel@tonic-gate 4232*0Sstevel@tonic-gate /* 4233*0Sstevel@tonic-gate * Wait ptimeout usec for periph to set 'mask' bits to 'val' state 4234*0Sstevel@tonic-gate * 4235*0Sstevel@tonic-gate * return value < 0 indicates timeout 4236*0Sstevel@tonic-gate */ 4237*0Sstevel@tonic-gate static int 4238*0Sstevel@tonic-gate wait_dsr(struct ecppunit *pp, uint8_t mask, uint8_t val, int ptimeout) 4239*0Sstevel@tonic-gate { 4240*0Sstevel@tonic-gate while (((DSR_READ(pp) & mask) != val) && ptimeout--) { 4241*0Sstevel@tonic-gate drv_usecwait(1); 4242*0Sstevel@tonic-gate } 4243*0Sstevel@tonic-gate 4244*0Sstevel@tonic-gate return (ptimeout); 4245*0Sstevel@tonic-gate } 4246*0Sstevel@tonic-gate 4247*0Sstevel@tonic-gate /* 4248*0Sstevel@tonic-gate * 1284 negotiation Events 0..6 4249*0Sstevel@tonic-gate * required mode is indicated by extensibility request value 4250*0Sstevel@tonic-gate * 4251*0Sstevel@tonic-gate * After successful negotiation SUCCESS is returned and 4252*0Sstevel@tonic-gate * current mode is set according to xreq, 4253*0Sstevel@tonic-gate * otherwise FAILURE is returned and current mode is set to 4254*0Sstevel@tonic-gate * either COMPAT (1284 periph) or CENTRONICS (non-1284 periph) 4255*0Sstevel@tonic-gate * 4256*0Sstevel@tonic-gate * Current phase must be set by the caller (mode-specific negotiation) 4257*0Sstevel@tonic-gate * 4258*0Sstevel@tonic-gate * If rdsr is not NULL, DSR value after Event 6 is stored here 4259*0Sstevel@tonic-gate */ 4260*0Sstevel@tonic-gate static int 4261*0Sstevel@tonic-gate ecpp_1284_negotiation(struct ecppunit *pp, uint8_t xreq, uint8_t *rdsr) 4262*0Sstevel@tonic-gate { 4263*0Sstevel@tonic-gate int xflag; 4264*0Sstevel@tonic-gate 4265*0Sstevel@tonic-gate ecpp_error(pp->dip, "nego(%x): entering...\n", xreq); 4266*0Sstevel@tonic-gate 4267*0Sstevel@tonic-gate /* negotiation should start in Compatibility mode */ 4268*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4269*0Sstevel@tonic-gate 4270*0Sstevel@tonic-gate /* Set host into Compat mode */ 4271*0Sstevel@tonic-gate ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001); 4272*0Sstevel@tonic-gate 4273*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NEGO; 4274*0Sstevel@tonic-gate 4275*0Sstevel@tonic-gate /* Event 0: host sets extensibility request on data lines */ 4276*0Sstevel@tonic-gate DATAR_WRITE(pp, xreq); 4277*0Sstevel@tonic-gate 4278*0Sstevel@tonic-gate /* Event 1: host deassert nSelectin and assert nAutoFd */ 4279*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX); 4280*0Sstevel@tonic-gate 4281*0Sstevel@tonic-gate drv_usecwait(1); /* Tp(ecp) == 0.5us */ 4282*0Sstevel@tonic-gate 4283*0Sstevel@tonic-gate /* 4284*0Sstevel@tonic-gate * Event 2: peripheral asserts nAck, deasserts nFault, 4285*0Sstevel@tonic-gate * asserts Select, asserts PError 4286*0Sstevel@tonic-gate */ 4287*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nERR | ECPP_SLCT | ECPP_PE | ECPP_nACK, 4288*0Sstevel@tonic-gate ECPP_nERR | ECPP_SLCT | ECPP_PE, 35000) < 0) { 4289*0Sstevel@tonic-gate /* peripheral is not 1284-compliant */ 4290*0Sstevel@tonic-gate ecpp_error(pp->dip, 4291*0Sstevel@tonic-gate "nego(%x): failed event 2 %x\n", xreq, DSR_READ(pp)); 4292*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4293*0Sstevel@tonic-gate return (FAILURE); 4294*0Sstevel@tonic-gate } 4295*0Sstevel@tonic-gate 4296*0Sstevel@tonic-gate /* 4297*0Sstevel@tonic-gate * Event 3: host asserts nStrobe, latching extensibility value into 4298*0Sstevel@tonic-gate * peripherals input latch. 4299*0Sstevel@tonic-gate */ 4300*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_STB); 4301*0Sstevel@tonic-gate 4302*0Sstevel@tonic-gate drv_usecwait(2); /* Tp(ecp) = 0.5us */ 4303*0Sstevel@tonic-gate 4304*0Sstevel@tonic-gate /* 4305*0Sstevel@tonic-gate * Event 4: hosts deasserts nStrobe and nAutoFD to acknowledge that 4306*0Sstevel@tonic-gate * it has recognized an 1284 compatible peripheral 4307*0Sstevel@tonic-gate */ 4308*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT); 4309*0Sstevel@tonic-gate 4310*0Sstevel@tonic-gate /* 4311*0Sstevel@tonic-gate * Event 5: Peripheral confirms it supports requested extension 4312*0Sstevel@tonic-gate * For Nibble mode Xflag must be low, otherwise it must be high 4313*0Sstevel@tonic-gate */ 4314*0Sstevel@tonic-gate xflag = (xreq == ECPP_XREQ_NIBBLE) ? 0 : ECPP_SLCT; 4315*0Sstevel@tonic-gate 4316*0Sstevel@tonic-gate /* 4317*0Sstevel@tonic-gate * Event 6: Peripheral sets nAck high 4318*0Sstevel@tonic-gate * indicating that status lines are valid 4319*0Sstevel@tonic-gate */ 4320*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) { 4321*0Sstevel@tonic-gate /* Something wrong with peripheral */ 4322*0Sstevel@tonic-gate ecpp_error(pp->dip, 4323*0Sstevel@tonic-gate "nego(%x): failed event 6 %x\n", xreq, DSR_READ(pp)); 4324*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4325*0Sstevel@tonic-gate return (FAILURE); 4326*0Sstevel@tonic-gate } 4327*0Sstevel@tonic-gate 4328*0Sstevel@tonic-gate if ((DSR_READ(pp) & ECPP_SLCT) != xflag) { 4329*0Sstevel@tonic-gate /* Extensibility value is not supported */ 4330*0Sstevel@tonic-gate ecpp_error(pp->dip, 4331*0Sstevel@tonic-gate "nego(%x): failed event 5 %x\n", xreq, DSR_READ(pp)); 4332*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4333*0Sstevel@tonic-gate return (FAILURE); 4334*0Sstevel@tonic-gate } 4335*0Sstevel@tonic-gate 4336*0Sstevel@tonic-gate if (rdsr) { 4337*0Sstevel@tonic-gate *rdsr = DSR_READ(pp); 4338*0Sstevel@tonic-gate } 4339*0Sstevel@tonic-gate 4340*0Sstevel@tonic-gate return (SUCCESS); 4341*0Sstevel@tonic-gate } 4342*0Sstevel@tonic-gate 4343*0Sstevel@tonic-gate /* 4344*0Sstevel@tonic-gate * 1284 Termination: Events 22..28 - set link to Compatibility mode 4345*0Sstevel@tonic-gate * 4346*0Sstevel@tonic-gate * This routine is not designed for Immediate termination, 4347*0Sstevel@tonic-gate * caller must take care of waiting for a valid state, 4348*0Sstevel@tonic-gate * (in particular, in ECP mode current phase must be Forward Idle) 4349*0Sstevel@tonic-gate * otherwise interface will be reinitialized 4350*0Sstevel@tonic-gate * 4351*0Sstevel@tonic-gate * In case of Valid state termination SUCCESS is returned and 4352*0Sstevel@tonic-gate * current_mode is ECPP_COMPAT_MODE, current phase is ECPP_PHASE_C_IDLE 4353*0Sstevel@tonic-gate * Otherwise interface is reinitialized, FAILURE is returned and 4354*0Sstevel@tonic-gate * current mode is ECPP_CENTRONICS, current phase is ECPP_PHASE_C_IDLE 4355*0Sstevel@tonic-gate */ 4356*0Sstevel@tonic-gate static int 4357*0Sstevel@tonic-gate ecpp_1284_termination(struct ecppunit *pp) 4358*0Sstevel@tonic-gate { 4359*0Sstevel@tonic-gate int previous_mode = pp->current_mode; 4360*0Sstevel@tonic-gate 4361*0Sstevel@tonic-gate if (((pp->current_mode == ECPP_COMPAT_MODE || 4362*0Sstevel@tonic-gate pp->current_mode == ECPP_CENTRONICS) && 4363*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_C_IDLE) || 4364*0Sstevel@tonic-gate pp->current_mode == ECPP_DIAG_MODE) { 4365*0Sstevel@tonic-gate ecpp_error(pp->dip, "termination: not needed\n"); 4366*0Sstevel@tonic-gate return (SUCCESS); 4367*0Sstevel@tonic-gate } 4368*0Sstevel@tonic-gate 4369*0Sstevel@tonic-gate /* Set host into Compat mode, interrupts disabled */ 4370*0Sstevel@tonic-gate ECPP_MASK_INTR(pp); 4371*0Sstevel@tonic-gate ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001); 4372*0Sstevel@tonic-gate 4373*0Sstevel@tonic-gate pp->current_mode = ECPP_COMPAT_MODE; /* needed by next function */ 4374*0Sstevel@tonic-gate 4375*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4376*0Sstevel@tonic-gate 4377*0Sstevel@tonic-gate /* 4378*0Sstevel@tonic-gate * EPP mode uses simple nInit pulse for termination 4379*0Sstevel@tonic-gate */ 4380*0Sstevel@tonic-gate if (previous_mode == ECPP_EPP_MODE) { 4381*0Sstevel@tonic-gate /* Event 68: host sets nInit low */ 4382*0Sstevel@tonic-gate DCR_WRITE(pp, 0); 4383*0Sstevel@tonic-gate 4384*0Sstevel@tonic-gate drv_usecwait(55); /* T(ER) = 50us */ 4385*0Sstevel@tonic-gate 4386*0Sstevel@tonic-gate /* Event 69: host sets nInit high */ 4387*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN); 4388*0Sstevel@tonic-gate 4389*0Sstevel@tonic-gate goto endterm; 4390*0Sstevel@tonic-gate } 4391*0Sstevel@tonic-gate 4392*0Sstevel@tonic-gate /* terminate peripheral to Compat mode */ 4393*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_TERM; 4394*0Sstevel@tonic-gate 4395*0Sstevel@tonic-gate /* Event 22: hosts sets nSelectIn low and nAutoFd high */ 4396*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN); 4397*0Sstevel@tonic-gate 4398*0Sstevel@tonic-gate /* Event 23: peripheral deasserts nFault and nBusy */ 4399*0Sstevel@tonic-gate /* Event 24: peripheral asserts nAck */ 4400*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nERR | ECPP_nBUSY | ECPP_nACK, 4401*0Sstevel@tonic-gate ECPP_nERR, 35000) < 0) { 4402*0Sstevel@tonic-gate ecpp_error(pp->dip, 4403*0Sstevel@tonic-gate "termination: failed events 23,24 %x\n", DSR_READ(pp)); 4404*0Sstevel@tonic-gate ecpp_1284_init_interface(pp); 4405*0Sstevel@tonic-gate return (FAILURE); 4406*0Sstevel@tonic-gate } 4407*0Sstevel@tonic-gate 4408*0Sstevel@tonic-gate drv_usecwait(1); /* Tp = 0.5us */ 4409*0Sstevel@tonic-gate 4410*0Sstevel@tonic-gate /* Event 25: hosts sets nAutoFd low */ 4411*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN | ECPP_AFX); 4412*0Sstevel@tonic-gate 4413*0Sstevel@tonic-gate /* Event 26: the peripheral puts itself in Compatible mode */ 4414*0Sstevel@tonic-gate 4415*0Sstevel@tonic-gate /* Event 27: peripheral deasserts nAck */ 4416*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) { 4417*0Sstevel@tonic-gate ecpp_error(pp->dip, 4418*0Sstevel@tonic-gate "termination: failed event 27 %x\n", DSR_READ(pp)); 4419*0Sstevel@tonic-gate ecpp_1284_init_interface(pp); 4420*0Sstevel@tonic-gate return (FAILURE); 4421*0Sstevel@tonic-gate } 4422*0Sstevel@tonic-gate 4423*0Sstevel@tonic-gate drv_usecwait(1); /* Tp = 0.5us */ 4424*0Sstevel@tonic-gate 4425*0Sstevel@tonic-gate /* Event 28: hosts deasserts nAutoFd */ 4426*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN); 4427*0Sstevel@tonic-gate 4428*0Sstevel@tonic-gate drv_usecwait(1); /* Tp = 0.5us */ 4429*0Sstevel@tonic-gate 4430*0Sstevel@tonic-gate endterm: 4431*0Sstevel@tonic-gate /* Compatible mode Idle Phase */ 4432*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_C_IDLE; 4433*0Sstevel@tonic-gate 4434*0Sstevel@tonic-gate ecpp_error(pp->dip, "termination: completed %x %x\n", 4435*0Sstevel@tonic-gate DSR_READ(pp), DCR_READ(pp)); 4436*0Sstevel@tonic-gate 4437*0Sstevel@tonic-gate return (SUCCESS); 4438*0Sstevel@tonic-gate } 4439*0Sstevel@tonic-gate 4440*0Sstevel@tonic-gate /* 4441*0Sstevel@tonic-gate * Initiate ECP backchannel DMA transfer 4442*0Sstevel@tonic-gate */ 4443*0Sstevel@tonic-gate static uchar_t 4444*0Sstevel@tonic-gate ecp_peripheral2host(struct ecppunit *pp) 4445*0Sstevel@tonic-gate { 4446*0Sstevel@tonic-gate mblk_t *mp = NULL; 4447*0Sstevel@tonic-gate size_t len; 4448*0Sstevel@tonic-gate uint32_t xfer_time; 4449*0Sstevel@tonic-gate 4450*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_ECP_MODE && 4451*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_IDLE); 4452*0Sstevel@tonic-gate 4453*0Sstevel@tonic-gate /* 4454*0Sstevel@tonic-gate * hardware generates cycles to receive data from the peripheral 4455*0Sstevel@tonic-gate * we only need to read from FIFO 4456*0Sstevel@tonic-gate */ 4457*0Sstevel@tonic-gate 4458*0Sstevel@tonic-gate /* 4459*0Sstevel@tonic-gate * If user issued read(2) of rev_resid bytes, xfer exactly this amount 4460*0Sstevel@tonic-gate * unless it exceeds ECP_REV_BLKSZ_MAX; otherwise try to read 4461*0Sstevel@tonic-gate * ECP_REV_BLKSZ_MAX or at least ECP_REV_BLKSZ bytes 4462*0Sstevel@tonic-gate */ 4463*0Sstevel@tonic-gate if (pp->nread > 0) { 4464*0Sstevel@tonic-gate len = min(pp->nread, ECP_REV_BLKSZ_MAX); 4465*0Sstevel@tonic-gate } else { 4466*0Sstevel@tonic-gate len = ECP_REV_BLKSZ_MAX; 4467*0Sstevel@tonic-gate } 4468*0Sstevel@tonic-gate 4469*0Sstevel@tonic-gate pp->nread = 0; /* clear after use */ 4470*0Sstevel@tonic-gate 4471*0Sstevel@tonic-gate /* 4472*0Sstevel@tonic-gate * Allocate mblk for data, make max 2 attepmts: 4473*0Sstevel@tonic-gate * if len bytes block fails, try our block size 4474*0Sstevel@tonic-gate */ 4475*0Sstevel@tonic-gate while ((mp = allocb(len, BPRI_MED)) == NULL) { 4476*0Sstevel@tonic-gate ecpp_error(pp->dip, 4477*0Sstevel@tonic-gate "ecp_periph2host: failed allocb(%d)\n", len); 4478*0Sstevel@tonic-gate if (len > ECP_REV_BLKSZ) { 4479*0Sstevel@tonic-gate len = ECP_REV_BLKSZ; 4480*0Sstevel@tonic-gate } else { 4481*0Sstevel@tonic-gate break; 4482*0Sstevel@tonic-gate } 4483*0Sstevel@tonic-gate } 4484*0Sstevel@tonic-gate 4485*0Sstevel@tonic-gate if (mp == NULL) { 4486*0Sstevel@tonic-gate goto fail; 4487*0Sstevel@tonic-gate } 4488*0Sstevel@tonic-gate 4489*0Sstevel@tonic-gate pp->msg = mp; 4490*0Sstevel@tonic-gate pp->e_busy = ECPP_BUSY; 4491*0Sstevel@tonic-gate pp->dma_dir = DDI_DMA_READ; 4492*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_REV_XFER; 4493*0Sstevel@tonic-gate 4494*0Sstevel@tonic-gate if (ecpp_init_dma_xfer(pp, (caddr_t)mp->b_rptr, len) == FAILURE) { 4495*0Sstevel@tonic-gate goto fail; 4496*0Sstevel@tonic-gate } 4497*0Sstevel@tonic-gate 4498*0Sstevel@tonic-gate /* 4499*0Sstevel@tonic-gate * there are two problems with defining ECP backchannel xfer timeout 4500*0Sstevel@tonic-gate * 4501*0Sstevel@tonic-gate * a) IEEE 1284 allows infinite time between backchannel bytes, 4502*0Sstevel@tonic-gate * but we must stop at some point to send the data upstream, 4503*0Sstevel@tonic-gate * look if any forward transfer requests are pending, etc; 4504*0Sstevel@tonic-gate * all that done, we can continue with backchannel data; 4505*0Sstevel@tonic-gate * 4506*0Sstevel@tonic-gate * b) we don`t know how much data peripheral has; 4507*0Sstevel@tonic-gate * DMA counter is set to our buffer size, which can be bigger 4508*0Sstevel@tonic-gate * than needed - in this case a timeout must detect this; 4509*0Sstevel@tonic-gate * 4510*0Sstevel@tonic-gate * The timeout we schedule here serves as both the transfer timeout 4511*0Sstevel@tonic-gate * and a means of detecting backchannel stalls; in fact, there are 4512*0Sstevel@tonic-gate * two timeouts in one: 4513*0Sstevel@tonic-gate * 4514*0Sstevel@tonic-gate * - transfer timeout is based on the ECP bandwidth of ~1MB/sec and 4515*0Sstevel@tonic-gate * equals the time needed to transfer the whole buffer 4516*0Sstevel@tonic-gate * (but not less than ECP_REV_MINTOUT ms); if it occurs, 4517*0Sstevel@tonic-gate * DMA is stopped and the data is sent upstream; 4518*0Sstevel@tonic-gate * 4519*0Sstevel@tonic-gate * - backchannel watchdog, which would look at DMA counter 4520*0Sstevel@tonic-gate * every rev_watchdog ms and stop the transfer only 4521*0Sstevel@tonic-gate * if the counter hasn`t changed since the last time; 4522*0Sstevel@tonic-gate * otherwise it would save DMA counter value and restart itself; 4523*0Sstevel@tonic-gate * 4524*0Sstevel@tonic-gate * transfer timeout is a multiple of rev_watchdog 4525*0Sstevel@tonic-gate * and implemented as a downward counter 4526*0Sstevel@tonic-gate * 4527*0Sstevel@tonic-gate * on Grover, we can`t access DMAC registers while DMA is in flight, 4528*0Sstevel@tonic-gate * so we can`t have watchdog on Grover, only timeout 4529*0Sstevel@tonic-gate */ 4530*0Sstevel@tonic-gate 4531*0Sstevel@tonic-gate /* calculate number of watchdog invocations equal to the xfer timeout */ 4532*0Sstevel@tonic-gate xfer_time = max((1000 * len) / pp->ecp_rev_speed, ECP_REV_MINTOUT); 4533*0Sstevel@tonic-gate #if defined(__x86) 4534*0Sstevel@tonic-gate pp->rev_timeout_cnt = (pp->hw == &x86) ? 1 : 4535*0Sstevel@tonic-gate #else 4536*0Sstevel@tonic-gate pp->rev_timeout_cnt = (pp->hw == &m1553) ? 1 : 4537*0Sstevel@tonic-gate #endif 4538*0Sstevel@tonic-gate max(xfer_time / pp->rev_watchdog, 1); 4539*0Sstevel@tonic-gate 4540*0Sstevel@tonic-gate pp->last_dmacnt = len; /* nothing xferred yet */ 4541*0Sstevel@tonic-gate 4542*0Sstevel@tonic-gate pp->timeout_id = timeout(ecpp_ecp_read_timeout, (caddr_t)pp, 4543*0Sstevel@tonic-gate drv_usectohz(pp->rev_watchdog * 1000)); 4544*0Sstevel@tonic-gate 4545*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_periph2host: DMA started len=%d\n" 4546*0Sstevel@tonic-gate "xfer_time=%d wdog=%d cnt=%d\n", 4547*0Sstevel@tonic-gate len, xfer_time, pp->rev_watchdog, pp->rev_timeout_cnt); 4548*0Sstevel@tonic-gate 4549*0Sstevel@tonic-gate return (SUCCESS); 4550*0Sstevel@tonic-gate 4551*0Sstevel@tonic-gate fail: 4552*0Sstevel@tonic-gate if (mp) { 4553*0Sstevel@tonic-gate freemsg(mp); 4554*0Sstevel@tonic-gate } 4555*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 4556*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_REV_IDLE; 4557*0Sstevel@tonic-gate 4558*0Sstevel@tonic-gate return (FAILURE); 4559*0Sstevel@tonic-gate } 4560*0Sstevel@tonic-gate 4561*0Sstevel@tonic-gate /* 4562*0Sstevel@tonic-gate * ECP backchannel read timeout 4563*0Sstevel@tonic-gate * implements both backchannel watchdog and transfer timeout in ECP mode 4564*0Sstevel@tonic-gate * if the transfer is still in progress, reschedule itself, 4565*0Sstevel@tonic-gate * otherwise call completion routine 4566*0Sstevel@tonic-gate */ 4567*0Sstevel@tonic-gate static void 4568*0Sstevel@tonic-gate ecpp_ecp_read_timeout(void *arg) 4569*0Sstevel@tonic-gate { 4570*0Sstevel@tonic-gate struct ecppunit *pp = arg; 4571*0Sstevel@tonic-gate size_t dmacnt; 4572*0Sstevel@tonic-gate 4573*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 4574*0Sstevel@tonic-gate 4575*0Sstevel@tonic-gate if (pp->timeout_id == 0) { 4576*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4577*0Sstevel@tonic-gate return; 4578*0Sstevel@tonic-gate } else { 4579*0Sstevel@tonic-gate pp->timeout_id = 0; 4580*0Sstevel@tonic-gate } 4581*0Sstevel@tonic-gate 4582*0Sstevel@tonic-gate if (--pp->rev_timeout_cnt == 0) { 4583*0Sstevel@tonic-gate /* 4584*0Sstevel@tonic-gate * Transfer timed out 4585*0Sstevel@tonic-gate */ 4586*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_timeout: timeout\n"); 4587*0Sstevel@tonic-gate pp->xfer_tout++; 4588*0Sstevel@tonic-gate ecpp_ecp_read_completion(pp); 4589*0Sstevel@tonic-gate } else { 4590*0Sstevel@tonic-gate /* 4591*0Sstevel@tonic-gate * Backchannel watchdog: 4592*0Sstevel@tonic-gate * look if DMA made any progress from the last time 4593*0Sstevel@tonic-gate */ 4594*0Sstevel@tonic-gate dmacnt = ECPP_DMA_GETCNT(pp); 4595*0Sstevel@tonic-gate if (dmacnt - pp->last_dmacnt == 0) { 4596*0Sstevel@tonic-gate /* 4597*0Sstevel@tonic-gate * No progress - stop the transfer and send 4598*0Sstevel@tonic-gate * whatever has been read so far up the stream 4599*0Sstevel@tonic-gate */ 4600*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_timeout: no progress\n"); 4601*0Sstevel@tonic-gate pp->xfer_tout++; 4602*0Sstevel@tonic-gate ecpp_ecp_read_completion(pp); 4603*0Sstevel@tonic-gate } else { 4604*0Sstevel@tonic-gate /* 4605*0Sstevel@tonic-gate * Something was transferred - restart ourselves 4606*0Sstevel@tonic-gate */ 4607*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_timeout: restarting\n"); 4608*0Sstevel@tonic-gate pp->last_dmacnt = dmacnt; 4609*0Sstevel@tonic-gate pp->timeout_id = timeout(ecpp_ecp_read_timeout, 4610*0Sstevel@tonic-gate (caddr_t)pp, 4611*0Sstevel@tonic-gate drv_usectohz(pp->rev_watchdog * 1000)); 4612*0Sstevel@tonic-gate } 4613*0Sstevel@tonic-gate } 4614*0Sstevel@tonic-gate 4615*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4616*0Sstevel@tonic-gate } 4617*0Sstevel@tonic-gate 4618*0Sstevel@tonic-gate /* 4619*0Sstevel@tonic-gate * ECP backchannel read completion: 4620*0Sstevel@tonic-gate * stop the DMA, free DMA resources and send read data upstream 4621*0Sstevel@tonic-gate */ 4622*0Sstevel@tonic-gate static void 4623*0Sstevel@tonic-gate ecpp_ecp_read_completion(struct ecppunit *pp) 4624*0Sstevel@tonic-gate { 4625*0Sstevel@tonic-gate size_t xfer_len, unx_len; 4626*0Sstevel@tonic-gate mblk_t *mp; 4627*0Sstevel@tonic-gate 4628*0Sstevel@tonic-gate ASSERT(mutex_owned(&pp->umutex)); 4629*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_ECP_MODE && 4630*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_XFER); 4631*0Sstevel@tonic-gate ASSERT(pp->msg != NULL); 4632*0Sstevel@tonic-gate 4633*0Sstevel@tonic-gate /* 4634*0Sstevel@tonic-gate * Stop the transfer and unbind DMA handle 4635*0Sstevel@tonic-gate */ 4636*0Sstevel@tonic-gate if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) { 4637*0Sstevel@tonic-gate unx_len = pp->resid; 4638*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_completion: failed dma_stop\n"); 4639*0Sstevel@tonic-gate } 4640*0Sstevel@tonic-gate 4641*0Sstevel@tonic-gate mp = pp->msg; 4642*0Sstevel@tonic-gate xfer_len = pp->resid - unx_len; /* how much data was transferred */ 4643*0Sstevel@tonic-gate 4644*0Sstevel@tonic-gate if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) { 4645*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_completion: unbind failed.\n"); 4646*0Sstevel@tonic-gate } 4647*0Sstevel@tonic-gate 4648*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_completion: xfered %d bytes of %d\n", 4649*0Sstevel@tonic-gate xfer_len, pp->resid); 4650*0Sstevel@tonic-gate 4651*0Sstevel@tonic-gate /* clean up and update statistics */ 4652*0Sstevel@tonic-gate pp->msg = NULL; 4653*0Sstevel@tonic-gate pp->resid -= xfer_len; 4654*0Sstevel@tonic-gate pp->ibytes[pp->current_mode] += xfer_len; 4655*0Sstevel@tonic-gate pp->e_busy = ECPP_IDLE; 4656*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_REV_IDLE; 4657*0Sstevel@tonic-gate 4658*0Sstevel@tonic-gate /* 4659*0Sstevel@tonic-gate * Send the read data up the stream 4660*0Sstevel@tonic-gate */ 4661*0Sstevel@tonic-gate mp->b_wptr += xfer_len; 4662*0Sstevel@tonic-gate if (canputnext(pp->readq)) { 4663*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4664*0Sstevel@tonic-gate putnext(pp->readq, mp); 4665*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 4666*0Sstevel@tonic-gate } else { 4667*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_read_completion: fail canputnext\n"); 4668*0Sstevel@tonic-gate if (!putq(pp->readq, mp)) { 4669*0Sstevel@tonic-gate freemsg(mp); 4670*0Sstevel@tonic-gate } 4671*0Sstevel@tonic-gate } 4672*0Sstevel@tonic-gate 4673*0Sstevel@tonic-gate /* if bytes left in the FIFO another transfer is needed */ 4674*0Sstevel@tonic-gate if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) { 4675*0Sstevel@tonic-gate (void) ecpp_backchan_req(pp); 4676*0Sstevel@tonic-gate } 4677*0Sstevel@tonic-gate 4678*0Sstevel@tonic-gate qenable(pp->writeq); 4679*0Sstevel@tonic-gate } 4680*0Sstevel@tonic-gate 4681*0Sstevel@tonic-gate /* 4682*0Sstevel@tonic-gate * Read one byte in the Nibble mode 4683*0Sstevel@tonic-gate */ 4684*0Sstevel@tonic-gate static uchar_t 4685*0Sstevel@tonic-gate nibble_peripheral2host(struct ecppunit *pp, uint8_t *byte) 4686*0Sstevel@tonic-gate { 4687*0Sstevel@tonic-gate uint8_t n[2]; /* two nibbles */ 4688*0Sstevel@tonic-gate int i; 4689*0Sstevel@tonic-gate 4690*0Sstevel@tonic-gate /* 4691*0Sstevel@tonic-gate * One byte is made of two nibbles 4692*0Sstevel@tonic-gate */ 4693*0Sstevel@tonic-gate for (i = 0; i < 2; i++) { 4694*0Sstevel@tonic-gate /* Event 7, 12: host asserts nAutoFd to move to read a nibble */ 4695*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX); 4696*0Sstevel@tonic-gate 4697*0Sstevel@tonic-gate /* Event 8: peripheral puts data on the status lines */ 4698*0Sstevel@tonic-gate 4699*0Sstevel@tonic-gate /* Event 9: peripheral asserts nAck, data available */ 4700*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nACK, 0, 35000) < 0) { 4701*0Sstevel@tonic-gate ecpp_error(pp->dip, 4702*0Sstevel@tonic-gate "nibble_periph2host(%d): failed event 9 %x\n", 4703*0Sstevel@tonic-gate i + 1, DSR_READ(pp)); 4704*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4705*0Sstevel@tonic-gate return (FAILURE); 4706*0Sstevel@tonic-gate } 4707*0Sstevel@tonic-gate 4708*0Sstevel@tonic-gate n[i] = DSR_READ(pp); /* get a nibble */ 4709*0Sstevel@tonic-gate 4710*0Sstevel@tonic-gate /* Event 10: host deasserts nAutoFd to say it grabbed data */ 4711*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT); 4712*0Sstevel@tonic-gate 4713*0Sstevel@tonic-gate /* (2) Event 13: peripheral asserts PE - end of data phase */ 4714*0Sstevel@tonic-gate 4715*0Sstevel@tonic-gate /* Event 11: peripheral deasserts nAck to finish handshake */ 4716*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) { 4717*0Sstevel@tonic-gate ecpp_error(pp->dip, 4718*0Sstevel@tonic-gate "nibble_periph2host(%d): failed event 11 %x\n", 4719*0Sstevel@tonic-gate i + 1, DSR_READ(pp)); 4720*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4721*0Sstevel@tonic-gate return (FAILURE); 4722*0Sstevel@tonic-gate } 4723*0Sstevel@tonic-gate } 4724*0Sstevel@tonic-gate 4725*0Sstevel@tonic-gate /* extract data byte from two nibbles - optimized formula */ 4726*0Sstevel@tonic-gate *byte = ((((n[1] & ~ECPP_nACK) << 1) | (~n[1] & ECPP_nBUSY)) & 0xf0) | 4727*0Sstevel@tonic-gate ((((n[0] & ~ECPP_nACK) >> 3) | ((~n[0] & ECPP_nBUSY) >> 4)) & 0x0f); 4728*0Sstevel@tonic-gate 4729*0Sstevel@tonic-gate pp->ibytes[ECPP_NIBBLE_MODE]++; 4730*0Sstevel@tonic-gate return (SUCCESS); 4731*0Sstevel@tonic-gate } 4732*0Sstevel@tonic-gate 4733*0Sstevel@tonic-gate /* 4734*0Sstevel@tonic-gate * process data transfers requested by the peripheral 4735*0Sstevel@tonic-gate */ 4736*0Sstevel@tonic-gate static uint_t 4737*0Sstevel@tonic-gate ecpp_peripheral2host(struct ecppunit *pp) 4738*0Sstevel@tonic-gate { 4739*0Sstevel@tonic-gate if (!canputnext(pp->readq)) { 4740*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_peripheral2host: readq full\n"); 4741*0Sstevel@tonic-gate return (SUCCESS); 4742*0Sstevel@tonic-gate } 4743*0Sstevel@tonic-gate 4744*0Sstevel@tonic-gate switch (pp->backchannel) { 4745*0Sstevel@tonic-gate case ECPP_CENTRONICS: 4746*0Sstevel@tonic-gate /* no backchannel */ 4747*0Sstevel@tonic-gate return (SUCCESS); 4748*0Sstevel@tonic-gate 4749*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 4750*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_NIBBLE_MODE); 4751*0Sstevel@tonic-gate 4752*0Sstevel@tonic-gate /* 4753*0Sstevel@tonic-gate * Event 20: Host sets nAutoFd high to ack request 4754*0Sstevel@tonic-gate */ 4755*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT); 4756*0Sstevel@tonic-gate 4757*0Sstevel@tonic-gate /* Event 21: Periph sets PError low to ack host */ 4758*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_PE, 0, 35000) < 0) { 4759*0Sstevel@tonic-gate ecpp_error(pp->dip, 4760*0Sstevel@tonic-gate "ecpp_periph2host: failed event 21 %x\n", 4761*0Sstevel@tonic-gate DSR_READ(pp)); 4762*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4763*0Sstevel@tonic-gate return (FAILURE); 4764*0Sstevel@tonic-gate } 4765*0Sstevel@tonic-gate 4766*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_AVAIL; 4767*0Sstevel@tonic-gate 4768*0Sstevel@tonic-gate /* this routine will read the data in Nibble mode */ 4769*0Sstevel@tonic-gate return (ecpp_idle_phase(pp)); 4770*0Sstevel@tonic-gate 4771*0Sstevel@tonic-gate case ECPP_ECP_MODE: 4772*0Sstevel@tonic-gate if ((pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE) && 4773*0Sstevel@tonic-gate (ecp_forward2reverse(pp) == FAILURE)) { 4774*0Sstevel@tonic-gate return (FAILURE); 4775*0Sstevel@tonic-gate } 4776*0Sstevel@tonic-gate 4777*0Sstevel@tonic-gate return (ecp_peripheral2host(pp)); /* start the transfer */ 4778*0Sstevel@tonic-gate 4779*0Sstevel@tonic-gate case ECPP_DIAG_MODE: { 4780*0Sstevel@tonic-gate mblk_t *mp; 4781*0Sstevel@tonic-gate int i; 4782*0Sstevel@tonic-gate 4783*0Sstevel@tonic-gate if (ECR_READ(pp) & ECPP_FIFO_EMPTY) { 4784*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_periph2host: fifo empty\n"); 4785*0Sstevel@tonic-gate return (SUCCESS); 4786*0Sstevel@tonic-gate } 4787*0Sstevel@tonic-gate 4788*0Sstevel@tonic-gate /* allocate the FIFO size */ 4789*0Sstevel@tonic-gate if ((mp = allocb(ECPP_FIFO_SZ, BPRI_MED)) == NULL) { 4790*0Sstevel@tonic-gate ecpp_error(pp->dip, 4791*0Sstevel@tonic-gate "ecpp_periph2host: allocb FAILURE.\n"); 4792*0Sstevel@tonic-gate return (FAILURE); 4793*0Sstevel@tonic-gate } 4794*0Sstevel@tonic-gate 4795*0Sstevel@tonic-gate /* 4796*0Sstevel@tonic-gate * For the time being just read it byte by byte 4797*0Sstevel@tonic-gate */ 4798*0Sstevel@tonic-gate i = ECPP_FIFO_SZ; 4799*0Sstevel@tonic-gate while (i-- && (!(ECR_READ(pp) & ECPP_FIFO_EMPTY))) { 4800*0Sstevel@tonic-gate *mp->b_wptr++ = TFIFO_READ(pp); 4801*0Sstevel@tonic-gate drv_usecwait(1); /* ECR is sometimes slow to update */ 4802*0Sstevel@tonic-gate } 4803*0Sstevel@tonic-gate 4804*0Sstevel@tonic-gate if (canputnext(pp->readq)) { 4805*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 4806*0Sstevel@tonic-gate mp->b_datap->db_type = M_DATA; 4807*0Sstevel@tonic-gate ecpp_error(pp->dip, 4808*0Sstevel@tonic-gate "ecpp_periph2host: sending %d bytes\n", 4809*0Sstevel@tonic-gate mp->b_wptr - mp->b_rptr); 4810*0Sstevel@tonic-gate putnext(pp->readq, mp); 4811*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 4812*0Sstevel@tonic-gate return (SUCCESS); 4813*0Sstevel@tonic-gate } else { 4814*0Sstevel@tonic-gate ecpp_error(pp->dip, 4815*0Sstevel@tonic-gate "ecpp_periph2host: !canputnext data lost\n"); 4816*0Sstevel@tonic-gate freemsg(mp); 4817*0Sstevel@tonic-gate return (FAILURE); 4818*0Sstevel@tonic-gate } 4819*0Sstevel@tonic-gate } 4820*0Sstevel@tonic-gate 4821*0Sstevel@tonic-gate default: 4822*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_peripheraltohost: illegal back"); 4823*0Sstevel@tonic-gate return (FAILURE); 4824*0Sstevel@tonic-gate } 4825*0Sstevel@tonic-gate } 4826*0Sstevel@tonic-gate 4827*0Sstevel@tonic-gate /* 4828*0Sstevel@tonic-gate * Negotiate from ECP Forward Idle to Reverse Idle Phase 4829*0Sstevel@tonic-gate * 4830*0Sstevel@tonic-gate * (manipulations with dcr/ecr are according to ECP Specification) 4831*0Sstevel@tonic-gate */ 4832*0Sstevel@tonic-gate static int 4833*0Sstevel@tonic-gate ecp_forward2reverse(struct ecppunit *pp) 4834*0Sstevel@tonic-gate { 4835*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_ECP_MODE && 4836*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE); 4837*0Sstevel@tonic-gate 4838*0Sstevel@tonic-gate /* place port into PS2 mode */ 4839*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK); 4840*0Sstevel@tonic-gate 4841*0Sstevel@tonic-gate /* set direction bit (DCR3-0 must be 0100 - National) */ 4842*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT); 4843*0Sstevel@tonic-gate 4844*0Sstevel@tonic-gate /* enable hardware assist */ 4845*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK); 4846*0Sstevel@tonic-gate 4847*0Sstevel@tonic-gate drv_usecwait(1); /* Tp(ecp) = 0.5us */ 4848*0Sstevel@tonic-gate 4849*0Sstevel@tonic-gate /* Event 39: host sets nInit low */ 4850*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_REV_DIR); 4851*0Sstevel@tonic-gate 4852*0Sstevel@tonic-gate /* Event 40: peripheral sets PError low */ 4853*0Sstevel@tonic-gate 4854*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_REV_IDLE; 4855*0Sstevel@tonic-gate 4856*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_forward2reverse ok\n"); 4857*0Sstevel@tonic-gate 4858*0Sstevel@tonic-gate return (SUCCESS); 4859*0Sstevel@tonic-gate } 4860*0Sstevel@tonic-gate 4861*0Sstevel@tonic-gate /* 4862*0Sstevel@tonic-gate * Negotiate from ECP Reverse Idle to Forward Idle Phase 4863*0Sstevel@tonic-gate * 4864*0Sstevel@tonic-gate * (manipulations with dcr/ecr are according to ECP Specification) 4865*0Sstevel@tonic-gate */ 4866*0Sstevel@tonic-gate static int 4867*0Sstevel@tonic-gate ecp_reverse2forward(struct ecppunit *pp) 4868*0Sstevel@tonic-gate { 4869*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_ECP_MODE && 4870*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_IDLE); 4871*0Sstevel@tonic-gate 4872*0Sstevel@tonic-gate /* Event 47: host deasserts nInit */ 4873*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT); 4874*0Sstevel@tonic-gate 4875*0Sstevel@tonic-gate /* 4876*0Sstevel@tonic-gate * Event 48: peripheral deasserts nAck 4877*0Sstevel@tonic-gate * Event 49: peripheral asserts PError 4878*0Sstevel@tonic-gate */ 4879*0Sstevel@tonic-gate if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) { 4880*0Sstevel@tonic-gate ecpp_error(pp->dip, 4881*0Sstevel@tonic-gate "ecp_reverse2forward: failed event 49 %x\n", DSR_READ(pp)); 4882*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4883*0Sstevel@tonic-gate return (FAILURE); 4884*0Sstevel@tonic-gate } 4885*0Sstevel@tonic-gate 4886*0Sstevel@tonic-gate /* place port into PS2 mode */ 4887*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK); 4888*0Sstevel@tonic-gate 4889*0Sstevel@tonic-gate /* clear direction bit */ 4890*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT); 4891*0Sstevel@tonic-gate 4892*0Sstevel@tonic-gate /* reenable hardware assist */ 4893*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK); 4894*0Sstevel@tonic-gate 4895*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE; 4896*0Sstevel@tonic-gate 4897*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecp_reverse2forward ok\n"); 4898*0Sstevel@tonic-gate 4899*0Sstevel@tonic-gate return (SUCCESS); 4900*0Sstevel@tonic-gate } 4901*0Sstevel@tonic-gate 4902*0Sstevel@tonic-gate /* 4903*0Sstevel@tonic-gate * Default negotiation chooses the best mode supported by peripheral 4904*0Sstevel@tonic-gate * Note that backchannel mode may be different from forward mode 4905*0Sstevel@tonic-gate */ 4906*0Sstevel@tonic-gate static void 4907*0Sstevel@tonic-gate ecpp_default_negotiation(struct ecppunit *pp) 4908*0Sstevel@tonic-gate { 4909*0Sstevel@tonic-gate if (!noecp && (ecpp_mode_negotiation(pp, ECPP_ECP_MODE) == SUCCESS)) { 4910*0Sstevel@tonic-gate /* 1284 compatible device */ 4911*0Sstevel@tonic-gate pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO; 4912*0Sstevel@tonic-gate return; 4913*0Sstevel@tonic-gate } else if (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == SUCCESS) { 4914*0Sstevel@tonic-gate /* 1284 compatible device */ 4915*0Sstevel@tonic-gate pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO; 4916*0Sstevel@tonic-gate } else { 4917*0Sstevel@tonic-gate /* Centronics device */ 4918*0Sstevel@tonic-gate pp->io_mode = 4919*0Sstevel@tonic-gate (pp->fast_centronics == TRUE) ? ECPP_DMA : ECPP_PIO; 4920*0Sstevel@tonic-gate } 4921*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4922*0Sstevel@tonic-gate } 4923*0Sstevel@tonic-gate 4924*0Sstevel@tonic-gate /* 4925*0Sstevel@tonic-gate * Negotiate to the mode indicated by newmode 4926*0Sstevel@tonic-gate */ 4927*0Sstevel@tonic-gate static int 4928*0Sstevel@tonic-gate ecpp_mode_negotiation(struct ecppunit *pp, uchar_t newmode) 4929*0Sstevel@tonic-gate { 4930*0Sstevel@tonic-gate /* any other mode is impossible */ 4931*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_CENTRONICS || 4932*0Sstevel@tonic-gate pp->current_mode == ECPP_COMPAT_MODE || 4933*0Sstevel@tonic-gate pp->current_mode == ECPP_NIBBLE_MODE || 4934*0Sstevel@tonic-gate pp->current_mode == ECPP_ECP_MODE || 4935*0Sstevel@tonic-gate pp->current_mode == ECPP_DIAG_MODE); 4936*0Sstevel@tonic-gate 4937*0Sstevel@tonic-gate if (pp->current_mode == newmode) { 4938*0Sstevel@tonic-gate return (SUCCESS); 4939*0Sstevel@tonic-gate } 4940*0Sstevel@tonic-gate 4941*0Sstevel@tonic-gate /* termination from ECP is only allowed from the Forward Idle Phase */ 4942*0Sstevel@tonic-gate if ((pp->current_mode == ECPP_ECP_MODE) && 4943*0Sstevel@tonic-gate (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) { 4944*0Sstevel@tonic-gate /* this may break into Centronics */ 4945*0Sstevel@tonic-gate (void) ecp_reverse2forward(pp); 4946*0Sstevel@tonic-gate } 4947*0Sstevel@tonic-gate 4948*0Sstevel@tonic-gate switch (newmode) { 4949*0Sstevel@tonic-gate case ECPP_CENTRONICS: 4950*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 4951*0Sstevel@tonic-gate 4952*0Sstevel@tonic-gate /* put superio into PIO mode */ 4953*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV); 4954*0Sstevel@tonic-gate 4955*0Sstevel@tonic-gate pp->current_mode = ECPP_CENTRONICS; 4956*0Sstevel@tonic-gate pp->backchannel = ECPP_CENTRONICS; 4957*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4958*0Sstevel@tonic-gate 4959*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 4960*0Sstevel@tonic-gate return (SUCCESS); 4961*0Sstevel@tonic-gate 4962*0Sstevel@tonic-gate case ECPP_COMPAT_MODE: 4963*0Sstevel@tonic-gate /* ECPP_COMPAT_MODE should support Nibble as a backchannel */ 4964*0Sstevel@tonic-gate if (pp->current_mode == ECPP_NIBBLE_MODE) { 4965*0Sstevel@tonic-gate if (ecpp_1284_termination(pp) == SUCCESS) { 4966*0Sstevel@tonic-gate pp->current_mode = ECPP_COMPAT_MODE; 4967*0Sstevel@tonic-gate pp->backchannel = ECPP_NIBBLE_MODE; 4968*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4969*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 4970*0Sstevel@tonic-gate return (SUCCESS); 4971*0Sstevel@tonic-gate } else { 4972*0Sstevel@tonic-gate return (FAILURE); 4973*0Sstevel@tonic-gate } 4974*0Sstevel@tonic-gate } 4975*0Sstevel@tonic-gate 4976*0Sstevel@tonic-gate if ((nibble_negotiation(pp) == SUCCESS) && 4977*0Sstevel@tonic-gate (ecpp_1284_termination(pp) == SUCCESS)) { 4978*0Sstevel@tonic-gate pp->backchannel = ECPP_NIBBLE_MODE; 4979*0Sstevel@tonic-gate pp->current_mode = ECPP_COMPAT_MODE; 4980*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4981*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 4982*0Sstevel@tonic-gate return (SUCCESS); 4983*0Sstevel@tonic-gate } else { 4984*0Sstevel@tonic-gate return (FAILURE); 4985*0Sstevel@tonic-gate } 4986*0Sstevel@tonic-gate 4987*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 4988*0Sstevel@tonic-gate if (nibble_negotiation(pp) == FAILURE) { 4989*0Sstevel@tonic-gate return (FAILURE); 4990*0Sstevel@tonic-gate } 4991*0Sstevel@tonic-gate 4992*0Sstevel@tonic-gate pp->backchannel = ECPP_NIBBLE_MODE; 4993*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 4994*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 4995*0Sstevel@tonic-gate 4996*0Sstevel@tonic-gate return (SUCCESS); 4997*0Sstevel@tonic-gate 4998*0Sstevel@tonic-gate case ECPP_ECP_MODE: 4999*0Sstevel@tonic-gate if (pp->noecpregs) 5000*0Sstevel@tonic-gate return (FAILURE); 5001*0Sstevel@tonic-gate if (ecp_negotiation(pp) == FAILURE) { 5002*0Sstevel@tonic-gate return (FAILURE); 5003*0Sstevel@tonic-gate } 5004*0Sstevel@tonic-gate 5005*0Sstevel@tonic-gate /* 5006*0Sstevel@tonic-gate * National says CTR[3:0] should be 0100b before moving to 011 5007*0Sstevel@tonic-gate */ 5008*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT); 5009*0Sstevel@tonic-gate 5010*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_011 | 5011*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) { 5012*0Sstevel@tonic-gate ecpp_error(pp->dip, "mode_nego:ECP: failed w/ecr\n"); 5013*0Sstevel@tonic-gate return (FAILURE); 5014*0Sstevel@tonic-gate } 5015*0Sstevel@tonic-gate 5016*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 5017*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 5018*0Sstevel@tonic-gate 5019*0Sstevel@tonic-gate return (SUCCESS); 5020*0Sstevel@tonic-gate 5021*0Sstevel@tonic-gate case ECPP_DIAG_MODE: 5022*0Sstevel@tonic-gate /* 5023*0Sstevel@tonic-gate * In DIAG mode application can do nasty things(e.g drive pins) 5024*0Sstevel@tonic-gate * To keep peripheral sane, terminate to Compatibility mode 5025*0Sstevel@tonic-gate */ 5026*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 5027*0Sstevel@tonic-gate 5028*0Sstevel@tonic-gate /* put superio into TFIFO mode */ 5029*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_001 | 5030*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) { 5031*0Sstevel@tonic-gate ecpp_error(pp->dip, "put to TFIFO: failed w/ecr\n"); 5032*0Sstevel@tonic-gate return (FAILURE); 5033*0Sstevel@tonic-gate } 5034*0Sstevel@tonic-gate 5035*0Sstevel@tonic-gate pp->current_mode = ECPP_DIAG_MODE; 5036*0Sstevel@tonic-gate pp->backchannel = ECPP_DIAG_MODE; 5037*0Sstevel@tonic-gate ECPP_CONFIG_MODE(pp); 5038*0Sstevel@tonic-gate pp->to_mode[pp->current_mode]++; 5039*0Sstevel@tonic-gate 5040*0Sstevel@tonic-gate return (SUCCESS); 5041*0Sstevel@tonic-gate 5042*0Sstevel@tonic-gate default: 5043*0Sstevel@tonic-gate ecpp_error(pp->dip, 5044*0Sstevel@tonic-gate "ecpp_mode_negotiation: mode %d not supported\n", newmode); 5045*0Sstevel@tonic-gate return (FAILURE); 5046*0Sstevel@tonic-gate } 5047*0Sstevel@tonic-gate } 5048*0Sstevel@tonic-gate 5049*0Sstevel@tonic-gate /* 5050*0Sstevel@tonic-gate * Standard (9.1): Peripheral data is available only when the host places 5051*0Sstevel@tonic-gate * the interface in a mode capable of peripheral-to-host data transfer. 5052*0Sstevel@tonic-gate * This requires the host periodically to place the interface in such a mode. 5053*0Sstevel@tonic-gate * Polling can be eliminated by leaving the interface in an 1284 idle phase. 5054*0Sstevel@tonic-gate */ 5055*0Sstevel@tonic-gate static uchar_t 5056*0Sstevel@tonic-gate ecpp_idle_phase(struct ecppunit *pp) 5057*0Sstevel@tonic-gate { 5058*0Sstevel@tonic-gate uchar_t rval = FAILURE; 5059*0Sstevel@tonic-gate 5060*0Sstevel@tonic-gate /* 5061*0Sstevel@tonic-gate * If there is no space on the read queue, do not reverse channel 5062*0Sstevel@tonic-gate */ 5063*0Sstevel@tonic-gate if (!canputnext(pp->readq)) { 5064*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: readq full\n"); 5065*0Sstevel@tonic-gate return (SUCCESS); 5066*0Sstevel@tonic-gate } 5067*0Sstevel@tonic-gate 5068*0Sstevel@tonic-gate switch (pp->backchannel) { 5069*0Sstevel@tonic-gate case ECPP_CENTRONICS: 5070*0Sstevel@tonic-gate case ECPP_COMPAT_MODE: 5071*0Sstevel@tonic-gate case ECPP_DIAG_MODE: 5072*0Sstevel@tonic-gate /* nothing */ 5073*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: compat idle\n"); 5074*0Sstevel@tonic-gate return (SUCCESS); 5075*0Sstevel@tonic-gate 5076*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 5077*0Sstevel@tonic-gate /* 5078*0Sstevel@tonic-gate * read as much data as possible, ending up in either 5079*0Sstevel@tonic-gate * Reverse Idle or Host Busy Data Available phase 5080*0Sstevel@tonic-gate */ 5081*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: nibble backchannel\n"); 5082*0Sstevel@tonic-gate if ((pp->current_mode != ECPP_NIBBLE_MODE) && 5083*0Sstevel@tonic-gate (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == FAILURE)) { 5084*0Sstevel@tonic-gate break; 5085*0Sstevel@tonic-gate } 5086*0Sstevel@tonic-gate 5087*0Sstevel@tonic-gate rval = read_nibble_backchan(pp); 5088*0Sstevel@tonic-gate 5089*0Sstevel@tonic-gate /* put interface into Reverse Idle phase */ 5090*0Sstevel@tonic-gate if (pp->current_phase == ECPP_PHASE_NIBT_NAVAIL && 5091*0Sstevel@tonic-gate canputnext(pp->readq)) { 5092*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: going revidle\n"); 5093*0Sstevel@tonic-gate 5094*0Sstevel@tonic-gate /* 5095*0Sstevel@tonic-gate * Event 7: host asserts nAutoFd 5096*0Sstevel@tonic-gate * enable nAck interrupt to get a backchannel request 5097*0Sstevel@tonic-gate */ 5098*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_INTR_EN); 5099*0Sstevel@tonic-gate 5100*0Sstevel@tonic-gate ECPP_UNMASK_INTR(pp); 5101*0Sstevel@tonic-gate } 5102*0Sstevel@tonic-gate 5103*0Sstevel@tonic-gate break; 5104*0Sstevel@tonic-gate 5105*0Sstevel@tonic-gate case ECPP_ECP_MODE: 5106*0Sstevel@tonic-gate /* 5107*0Sstevel@tonic-gate * if data is already available, request the backchannel xfer 5108*0Sstevel@tonic-gate * otherwise stay in Forward Idle and enable nErr interrupts 5109*0Sstevel@tonic-gate */ 5110*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: ECP forward\n"); 5111*0Sstevel@tonic-gate 5112*0Sstevel@tonic-gate ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE || 5113*0Sstevel@tonic-gate pp->current_phase == ECPP_PHASE_ECP_REV_IDLE); 5114*0Sstevel@tonic-gate 5115*0Sstevel@tonic-gate /* put interface into Forward Idle phase */ 5116*0Sstevel@tonic-gate if ((pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) && 5117*0Sstevel@tonic-gate (ecp_reverse2forward(pp) == FAILURE)) { 5118*0Sstevel@tonic-gate return (FAILURE); 5119*0Sstevel@tonic-gate } 5120*0Sstevel@tonic-gate 5121*0Sstevel@tonic-gate /* 5122*0Sstevel@tonic-gate * if data already available, put backchannel request on the wq 5123*0Sstevel@tonic-gate * otherwise enable nErr interrupts 5124*0Sstevel@tonic-gate */ 5125*0Sstevel@tonic-gate if ((DSR_READ(pp) & ECPP_nERR) == 0) { 5126*0Sstevel@tonic-gate (void) ecpp_backchan_req(pp); 5127*0Sstevel@tonic-gate } else { 5128*0Sstevel@tonic-gate ECR_WRITE(pp, 5129*0Sstevel@tonic-gate ECR_READ(pp) & ~ECPP_INTR_MASK | ECPP_INTR_SRV); 5130*0Sstevel@tonic-gate 5131*0Sstevel@tonic-gate ECPP_UNMASK_INTR(pp); 5132*0Sstevel@tonic-gate } 5133*0Sstevel@tonic-gate 5134*0Sstevel@tonic-gate return (SUCCESS); 5135*0Sstevel@tonic-gate 5136*0Sstevel@tonic-gate default: 5137*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_idle_phase: illegal backchannel"); 5138*0Sstevel@tonic-gate } 5139*0Sstevel@tonic-gate 5140*0Sstevel@tonic-gate return (rval); 5141*0Sstevel@tonic-gate } 5142*0Sstevel@tonic-gate 5143*0Sstevel@tonic-gate /* 5144*0Sstevel@tonic-gate * This routine will leave the port in ECPP_PHASE_NIBT_REVIDLE 5145*0Sstevel@tonic-gate * Due to flow control, though, it may stop at ECPP_PHASE_NIBT_AVAIL, 5146*0Sstevel@tonic-gate * and continue later as the user consumes data from the read queue 5147*0Sstevel@tonic-gate * 5148*0Sstevel@tonic-gate * The current phase should be NIBT_AVAIL or NIBT_NAVAIL 5149*0Sstevel@tonic-gate * If some events fail during transfer, termination puts link 5150*0Sstevel@tonic-gate * to Compatibility mode and FAILURE is returned 5151*0Sstevel@tonic-gate */ 5152*0Sstevel@tonic-gate static int 5153*0Sstevel@tonic-gate read_nibble_backchan(struct ecppunit *pp) 5154*0Sstevel@tonic-gate { 5155*0Sstevel@tonic-gate mblk_t *mp; 5156*0Sstevel@tonic-gate int i; 5157*0Sstevel@tonic-gate int rval = SUCCESS; 5158*0Sstevel@tonic-gate 5159*0Sstevel@tonic-gate ASSERT(pp->current_mode == ECPP_NIBBLE_MODE); 5160*0Sstevel@tonic-gate 5161*0Sstevel@tonic-gate pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE)) 5162*0Sstevel@tonic-gate ? ECPP_PHASE_NIBT_NAVAIL 5163*0Sstevel@tonic-gate : ECPP_PHASE_NIBT_AVAIL; 5164*0Sstevel@tonic-gate 5165*0Sstevel@tonic-gate ecpp_error(pp->dip, "read_nibble_backchan: %x\n", DSR_READ(pp)); 5166*0Sstevel@tonic-gate 5167*0Sstevel@tonic-gate /* 5168*0Sstevel@tonic-gate * While data is available, read it in NIBBLE_REV_BLKSZ byte chunks 5169*0Sstevel@tonic-gate * and send up the stream 5170*0Sstevel@tonic-gate */ 5171*0Sstevel@tonic-gate while (pp->current_phase == ECPP_PHASE_NIBT_AVAIL && rval == SUCCESS) { 5172*0Sstevel@tonic-gate /* see if there's space on the queue */ 5173*0Sstevel@tonic-gate if (!canputnext(pp->readq)) { 5174*0Sstevel@tonic-gate ecpp_error(pp->dip, 5175*0Sstevel@tonic-gate "read_nibble_backchan: canputnext failed\n"); 5176*0Sstevel@tonic-gate return (SUCCESS); 5177*0Sstevel@tonic-gate } 5178*0Sstevel@tonic-gate 5179*0Sstevel@tonic-gate if ((mp = allocb(NIBBLE_REV_BLKSZ, BPRI_MED)) == NULL) { 5180*0Sstevel@tonic-gate ecpp_error(pp->dip, 5181*0Sstevel@tonic-gate "read_nibble_backchan: allocb failed\n"); 5182*0Sstevel@tonic-gate return (SUCCESS); 5183*0Sstevel@tonic-gate } 5184*0Sstevel@tonic-gate 5185*0Sstevel@tonic-gate /* read a chunk of data from the peripheral byte by byte */ 5186*0Sstevel@tonic-gate i = NIBBLE_REV_BLKSZ; 5187*0Sstevel@tonic-gate while (i-- && !(DSR_READ(pp) & ECPP_nERR)) { 5188*0Sstevel@tonic-gate if (nibble_peripheral2host(pp, mp->b_wptr) != SUCCESS) { 5189*0Sstevel@tonic-gate rval = FAILURE; 5190*0Sstevel@tonic-gate break; 5191*0Sstevel@tonic-gate } 5192*0Sstevel@tonic-gate mp->b_wptr++; 5193*0Sstevel@tonic-gate } 5194*0Sstevel@tonic-gate 5195*0Sstevel@tonic-gate pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE)) 5196*0Sstevel@tonic-gate ? ECPP_PHASE_NIBT_NAVAIL 5197*0Sstevel@tonic-gate : ECPP_PHASE_NIBT_AVAIL; 5198*0Sstevel@tonic-gate 5199*0Sstevel@tonic-gate if (mp->b_wptr - mp->b_rptr > 0) { 5200*0Sstevel@tonic-gate ecpp_error(pp->dip, 5201*0Sstevel@tonic-gate "read_nibble_backchan: sending %d bytes\n", 5202*0Sstevel@tonic-gate mp->b_wptr - mp->b_rptr); 5203*0Sstevel@tonic-gate pp->nread = 0; 5204*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 5205*0Sstevel@tonic-gate putnext(pp->readq, mp); 5206*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 5207*0Sstevel@tonic-gate } else { 5208*0Sstevel@tonic-gate freemsg(mp); 5209*0Sstevel@tonic-gate } 5210*0Sstevel@tonic-gate } 5211*0Sstevel@tonic-gate 5212*0Sstevel@tonic-gate return (rval); 5213*0Sstevel@tonic-gate } 5214*0Sstevel@tonic-gate 5215*0Sstevel@tonic-gate /* 5216*0Sstevel@tonic-gate * 'Request Device ID using nibble mode' negotiation 5217*0Sstevel@tonic-gate */ 5218*0Sstevel@tonic-gate static int 5219*0Sstevel@tonic-gate devidnib_negotiation(struct ecppunit *pp) 5220*0Sstevel@tonic-gate { 5221*0Sstevel@tonic-gate uint8_t dsr; 5222*0Sstevel@tonic-gate 5223*0Sstevel@tonic-gate if (ecpp_1284_negotiation(pp, 5224*0Sstevel@tonic-gate ECPP_XREQ_NIBBLE | ECPP_XREQ_ID, &dsr) == FAILURE) { 5225*0Sstevel@tonic-gate return (FAILURE); 5226*0Sstevel@tonic-gate } 5227*0Sstevel@tonic-gate 5228*0Sstevel@tonic-gate /* 5229*0Sstevel@tonic-gate * If peripheral has data available, PE and nErr will 5230*0Sstevel@tonic-gate * be set low at Event 5 & 6. 5231*0Sstevel@tonic-gate */ 5232*0Sstevel@tonic-gate if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) { 5233*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_AVAIL; 5234*0Sstevel@tonic-gate } else { 5235*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_NIBT_NAVAIL; 5236*0Sstevel@tonic-gate } 5237*0Sstevel@tonic-gate 5238*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_devidnib_nego: current_phase=%x\n", 5239*0Sstevel@tonic-gate pp->current_phase); 5240*0Sstevel@tonic-gate 5241*0Sstevel@tonic-gate /* successful negotiation into Nibble mode */ 5242*0Sstevel@tonic-gate pp->current_mode = ECPP_NIBBLE_MODE; 5243*0Sstevel@tonic-gate pp->backchannel = ECPP_NIBBLE_MODE; 5244*0Sstevel@tonic-gate 5245*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_devidnib_nego: ok\n"); 5246*0Sstevel@tonic-gate 5247*0Sstevel@tonic-gate return (SUCCESS); 5248*0Sstevel@tonic-gate } 5249*0Sstevel@tonic-gate 5250*0Sstevel@tonic-gate /* 5251*0Sstevel@tonic-gate * Read 1284 device ID sequence 5252*0Sstevel@tonic-gate * 5253*0Sstevel@tonic-gate * This function should be called two times: 5254*0Sstevel@tonic-gate * 1) ecpp_getdevid(pp, NULL, &len) - to retrieve ID length; 5255*0Sstevel@tonic-gate * 2) ecpp_getdevid(pp, buffer, &len) - to read len bytes into buffer 5256*0Sstevel@tonic-gate * 5257*0Sstevel@tonic-gate * After 2) port is in Compatible mode 5258*0Sstevel@tonic-gate * If the caller fails to make second call, it must reset port to Centronics 5259*0Sstevel@tonic-gate * 5260*0Sstevel@tonic-gate */ 5261*0Sstevel@tonic-gate static int 5262*0Sstevel@tonic-gate ecpp_getdevid(struct ecppunit *pp, uint8_t *id, int *lenp, int mode) 5263*0Sstevel@tonic-gate { 5264*0Sstevel@tonic-gate uint8_t lenhi, lenlo; 5265*0Sstevel@tonic-gate uint8_t dsr; 5266*0Sstevel@tonic-gate int i; 5267*0Sstevel@tonic-gate 5268*0Sstevel@tonic-gate switch (mode) { 5269*0Sstevel@tonic-gate case ECPP_NIBBLE_MODE: 5270*0Sstevel@tonic-gate /* negotiate only if neccessary */ 5271*0Sstevel@tonic-gate if ((pp->current_mode != mode) || (id == NULL)) { 5272*0Sstevel@tonic-gate if (devidnib_negotiation(pp) == FAILURE) { 5273*0Sstevel@tonic-gate return (EIO); 5274*0Sstevel@tonic-gate } 5275*0Sstevel@tonic-gate } 5276*0Sstevel@tonic-gate 5277*0Sstevel@tonic-gate if (pp->current_phase != ECPP_PHASE_NIBT_AVAIL) { 5278*0Sstevel@tonic-gate return (EIO); 5279*0Sstevel@tonic-gate } 5280*0Sstevel@tonic-gate 5281*0Sstevel@tonic-gate /* 5282*0Sstevel@tonic-gate * Event 14: Host tristates data bus, peripheral 5283*0Sstevel@tonic-gate * asserts nERR if data available, usually the 5284*0Sstevel@tonic-gate * status bits (7-0) and requires two reads since 5285*0Sstevel@tonic-gate * only nibbles are transfered. 5286*0Sstevel@tonic-gate */ 5287*0Sstevel@tonic-gate dsr = DSR_READ(pp); 5288*0Sstevel@tonic-gate 5289*0Sstevel@tonic-gate if (id == NULL) { 5290*0Sstevel@tonic-gate /* 5291*0Sstevel@tonic-gate * first two bytes are the length of the sequence 5292*0Sstevel@tonic-gate * (incl. these bytes) 5293*0Sstevel@tonic-gate * first byte is MSB 5294*0Sstevel@tonic-gate */ 5295*0Sstevel@tonic-gate if ((dsr & ECPP_nERR) || 5296*0Sstevel@tonic-gate (nibble_peripheral2host(pp, &lenhi) == FAILURE) || 5297*0Sstevel@tonic-gate (dsr & ECPP_nERR) || 5298*0Sstevel@tonic-gate (nibble_peripheral2host(pp, &lenlo) == FAILURE)) { 5299*0Sstevel@tonic-gate ecpp_error(pp->dip, 5300*0Sstevel@tonic-gate "ecpp_getdevid: id length read error\n"); 5301*0Sstevel@tonic-gate return (EIO); 5302*0Sstevel@tonic-gate } 5303*0Sstevel@tonic-gate 5304*0Sstevel@tonic-gate *lenp = (lenhi << 8) | (lenlo); 5305*0Sstevel@tonic-gate 5306*0Sstevel@tonic-gate ecpp_error(pp->dip, 5307*0Sstevel@tonic-gate "ecpp_getdevid: id length = %d\n", *lenp); 5308*0Sstevel@tonic-gate 5309*0Sstevel@tonic-gate if (*lenp < 2) { 5310*0Sstevel@tonic-gate return (EIO); 5311*0Sstevel@tonic-gate } 5312*0Sstevel@tonic-gate } else { 5313*0Sstevel@tonic-gate /* 5314*0Sstevel@tonic-gate * read the rest of the data 5315*0Sstevel@tonic-gate */ 5316*0Sstevel@tonic-gate i = *lenp; 5317*0Sstevel@tonic-gate while (i && ((dsr & ECPP_nERR) == 0)) { 5318*0Sstevel@tonic-gate if (nibble_peripheral2host(pp, id++) == FAILURE) 5319*0Sstevel@tonic-gate break; 5320*0Sstevel@tonic-gate 5321*0Sstevel@tonic-gate i--; 5322*0Sstevel@tonic-gate dsr = DSR_READ(pp); 5323*0Sstevel@tonic-gate } 5324*0Sstevel@tonic-gate ecpp_error(pp->dip, 5325*0Sstevel@tonic-gate "ecpp_getdevid: read %d bytes\n", *lenp - i); 5326*0Sstevel@tonic-gate 5327*0Sstevel@tonic-gate /* 5328*0Sstevel@tonic-gate * 1284: After receiving the sequence, the host is 5329*0Sstevel@tonic-gate * required to return the link to the Compatibility mode 5330*0Sstevel@tonic-gate */ 5331*0Sstevel@tonic-gate (void) ecpp_1284_termination(pp); 5332*0Sstevel@tonic-gate } 5333*0Sstevel@tonic-gate 5334*0Sstevel@tonic-gate break; 5335*0Sstevel@tonic-gate 5336*0Sstevel@tonic-gate /* Other modes are not yet supported */ 5337*0Sstevel@tonic-gate default: 5338*0Sstevel@tonic-gate return (EINVAL); 5339*0Sstevel@tonic-gate } 5340*0Sstevel@tonic-gate 5341*0Sstevel@tonic-gate return (0); 5342*0Sstevel@tonic-gate } 5343*0Sstevel@tonic-gate 5344*0Sstevel@tonic-gate /* 5345*0Sstevel@tonic-gate * Various hardware support 5346*0Sstevel@tonic-gate * 5347*0Sstevel@tonic-gate * First define some stubs for functions that do nothing 5348*0Sstevel@tonic-gate */ 5349*0Sstevel@tonic-gate 5350*0Sstevel@tonic-gate /*ARGSUSED*/ 5351*0Sstevel@tonic-gate static void 5352*0Sstevel@tonic-gate empty_config_mode(struct ecppunit *pp) 5353*0Sstevel@tonic-gate { 5354*0Sstevel@tonic-gate } 5355*0Sstevel@tonic-gate 5356*0Sstevel@tonic-gate /*ARGSUSED*/ 5357*0Sstevel@tonic-gate static void 5358*0Sstevel@tonic-gate empty_mask_intr(struct ecppunit *pp) 5359*0Sstevel@tonic-gate { 5360*0Sstevel@tonic-gate } 5361*0Sstevel@tonic-gate 5362*0Sstevel@tonic-gate #if defined(__x86) 5363*0Sstevel@tonic-gate static size_t 5364*0Sstevel@tonic-gate x86_getcnt(struct ecppunit *pp) 5365*0Sstevel@tonic-gate { 5366*0Sstevel@tonic-gate int count; 5367*0Sstevel@tonic-gate 5368*0Sstevel@tonic-gate (void) ddi_dmae_getcnt(pp->dip, pp->uh.x86.chn, &count); 5369*0Sstevel@tonic-gate return (count); 5370*0Sstevel@tonic-gate } 5371*0Sstevel@tonic-gate #endif 5372*0Sstevel@tonic-gate 5373*0Sstevel@tonic-gate /* 5374*0Sstevel@tonic-gate * 5375*0Sstevel@tonic-gate * National PC87332 and PC97317 SuperIOs support routines 5376*0Sstevel@tonic-gate * These chips are used in PCI-based Darwin, Quark, Quasar, Excalibur 5377*0Sstevel@tonic-gate * and use EBus DMA facilities (Cheerio or RIO) 5378*0Sstevel@tonic-gate * 5379*0Sstevel@tonic-gate */ 5380*0Sstevel@tonic-gate 5381*0Sstevel@tonic-gate static int 5382*0Sstevel@tonic-gate pc87332_map_regs(struct ecppunit *pp) 5383*0Sstevel@tonic-gate { 5384*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.ebus.c_reg, 0, 5385*0Sstevel@tonic-gate sizeof (struct config_reg), &acc_attr, 5386*0Sstevel@tonic-gate &pp->uh.ebus.c_handle) != DDI_SUCCESS) { 5387*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc87332_map_regs: failed c_reg\n"); 5388*0Sstevel@tonic-gate goto fail; 5389*0Sstevel@tonic-gate } 5390*0Sstevel@tonic-gate 5391*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0, 5392*0Sstevel@tonic-gate sizeof (struct info_reg), &acc_attr, &pp->i_handle) 5393*0Sstevel@tonic-gate != DDI_SUCCESS) { 5394*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc87332_map_regs: failed i_reg\n"); 5395*0Sstevel@tonic-gate goto fail; 5396*0Sstevel@tonic-gate } 5397*0Sstevel@tonic-gate 5398*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400, 5399*0Sstevel@tonic-gate sizeof (struct fifo_reg), &acc_attr, &pp->f_handle) 5400*0Sstevel@tonic-gate != DDI_SUCCESS) { 5401*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc87332_map_regs: failed f_reg\n"); 5402*0Sstevel@tonic-gate goto fail; 5403*0Sstevel@tonic-gate } 5404*0Sstevel@tonic-gate 5405*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 2, (caddr_t *)&pp->uh.ebus.dmac, 0, 5406*0Sstevel@tonic-gate sizeof (struct cheerio_dma_reg), &acc_attr, 5407*0Sstevel@tonic-gate &pp->uh.ebus.d_handle) != DDI_SUCCESS) { 5408*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc87332_map_regs: failed dmac\n"); 5409*0Sstevel@tonic-gate goto fail; 5410*0Sstevel@tonic-gate } 5411*0Sstevel@tonic-gate 5412*0Sstevel@tonic-gate return (SUCCESS); 5413*0Sstevel@tonic-gate 5414*0Sstevel@tonic-gate fail: 5415*0Sstevel@tonic-gate pc87332_unmap_regs(pp); 5416*0Sstevel@tonic-gate return (FAILURE); 5417*0Sstevel@tonic-gate } 5418*0Sstevel@tonic-gate 5419*0Sstevel@tonic-gate static void 5420*0Sstevel@tonic-gate pc87332_unmap_regs(struct ecppunit *pp) 5421*0Sstevel@tonic-gate { 5422*0Sstevel@tonic-gate if (pp->uh.ebus.c_handle) { 5423*0Sstevel@tonic-gate ddi_regs_map_free(&pp->uh.ebus.c_handle); 5424*0Sstevel@tonic-gate } 5425*0Sstevel@tonic-gate if (pp->uh.ebus.d_handle) { 5426*0Sstevel@tonic-gate ddi_regs_map_free(&pp->uh.ebus.d_handle); 5427*0Sstevel@tonic-gate } 5428*0Sstevel@tonic-gate if (pp->i_handle) { 5429*0Sstevel@tonic-gate ddi_regs_map_free(&pp->i_handle); 5430*0Sstevel@tonic-gate } 5431*0Sstevel@tonic-gate if (pp->f_handle) { 5432*0Sstevel@tonic-gate ddi_regs_map_free(&pp->f_handle); 5433*0Sstevel@tonic-gate } 5434*0Sstevel@tonic-gate } 5435*0Sstevel@tonic-gate 5436*0Sstevel@tonic-gate static uint8_t 5437*0Sstevel@tonic-gate pc87332_read_config_reg(struct ecppunit *pp, uint8_t reg_num) 5438*0Sstevel@tonic-gate { 5439*0Sstevel@tonic-gate uint8_t retval; 5440*0Sstevel@tonic-gate 5441*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num); 5442*0Sstevel@tonic-gate retval = PP_GETB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data); 5443*0Sstevel@tonic-gate 5444*0Sstevel@tonic-gate return (retval); 5445*0Sstevel@tonic-gate } 5446*0Sstevel@tonic-gate 5447*0Sstevel@tonic-gate static void 5448*0Sstevel@tonic-gate pc87332_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val) 5449*0Sstevel@tonic-gate { 5450*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num); 5451*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val); 5452*0Sstevel@tonic-gate 5453*0Sstevel@tonic-gate /* 5454*0Sstevel@tonic-gate * second write to this register is needed. the register behaves as 5455*0Sstevel@tonic-gate * a fifo. the first value written goes to the data register. the 5456*0Sstevel@tonic-gate * second write pushes the initial value to the register indexed. 5457*0Sstevel@tonic-gate */ 5458*0Sstevel@tonic-gate 5459*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val); 5460*0Sstevel@tonic-gate } 5461*0Sstevel@tonic-gate 5462*0Sstevel@tonic-gate static int 5463*0Sstevel@tonic-gate pc87332_config_chip(struct ecppunit *pp) 5464*0Sstevel@tonic-gate { 5465*0Sstevel@tonic-gate uint8_t pmc, fcr; 5466*0Sstevel@tonic-gate 5467*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_INIT; 5468*0Sstevel@tonic-gate 5469*0Sstevel@tonic-gate /* ECP DMA configuration bit (PMC4) must be set */ 5470*0Sstevel@tonic-gate pmc = pc87332_read_config_reg(pp, PMC); 5471*0Sstevel@tonic-gate if (!(pmc & PC87332_PMC_ECP_DMA_CONFIG)) { 5472*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PMC, 5473*0Sstevel@tonic-gate pmc | PC87332_PMC_ECP_DMA_CONFIG); 5474*0Sstevel@tonic-gate } 5475*0Sstevel@tonic-gate 5476*0Sstevel@tonic-gate /* 5477*0Sstevel@tonic-gate * The Parallel Port Multiplexor pins must be driven. 5478*0Sstevel@tonic-gate * Check to see if FCR3 is zero, if not clear FCR3. 5479*0Sstevel@tonic-gate */ 5480*0Sstevel@tonic-gate fcr = pc87332_read_config_reg(pp, FCR); 5481*0Sstevel@tonic-gate if (fcr & PC87332_FCR_PPM_FLOAT_CTL) { 5482*0Sstevel@tonic-gate pc87332_write_config_reg(pp, FCR, 5483*0Sstevel@tonic-gate fcr & ~PC87332_FCR_PPM_FLOAT_CTL); 5484*0Sstevel@tonic-gate } 5485*0Sstevel@tonic-gate 5486*0Sstevel@tonic-gate /* 5487*0Sstevel@tonic-gate * clear bits 3-0 in CTR (aka DCR) prior to enabling ECP mode 5488*0Sstevel@tonic-gate * CTR5 can not be cleared in SPP mode, CTR5 will return 1. 5489*0Sstevel@tonic-gate * "FAILURE" in this case is ok. Better to use dcr_write() 5490*0Sstevel@tonic-gate * to ensure reliable writing to DCR. 5491*0Sstevel@tonic-gate */ 5492*0Sstevel@tonic-gate if (dcr_write(pp, ECPP_DCR_SET | ECPP_nINIT) == FAILURE) { 5493*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_config_87332: DCR config\n"); 5494*0Sstevel@tonic-gate } 5495*0Sstevel@tonic-gate 5496*0Sstevel@tonic-gate /* enable ECP mode, level intr (note that DCR bits 3-0 == 0x0) */ 5497*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PCR, 5498*0Sstevel@tonic-gate PC87332_PCR_INTR_LEVL | PC87332_PCR_ECP_EN); 5499*0Sstevel@tonic-gate 5500*0Sstevel@tonic-gate /* put SuperIO in initial state */ 5501*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_001 | 5502*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) { 5503*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_config_87332: ECR\n"); 5504*0Sstevel@tonic-gate } 5505*0Sstevel@tonic-gate 5506*0Sstevel@tonic-gate if (dcr_write(pp, ECPP_DCR_SET | ECPP_SLCTIN | ECPP_nINIT) == FAILURE) { 5507*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_config_87332: w/DCR failed2.\n"); 5508*0Sstevel@tonic-gate return (FAILURE); 5509*0Sstevel@tonic-gate 5510*0Sstevel@tonic-gate } 5511*0Sstevel@tonic-gate /* we are in centronic mode */ 5512*0Sstevel@tonic-gate pp->current_mode = ECPP_CENTRONICS; 5513*0Sstevel@tonic-gate 5514*0Sstevel@tonic-gate /* in compatible mode with no data transfer in progress */ 5515*0Sstevel@tonic-gate pp->current_phase = ECPP_PHASE_C_IDLE; 5516*0Sstevel@tonic-gate 5517*0Sstevel@tonic-gate return (SUCCESS); 5518*0Sstevel@tonic-gate } 5519*0Sstevel@tonic-gate 5520*0Sstevel@tonic-gate /* 5521*0Sstevel@tonic-gate * A new mode was set, do some mode specific reconfiguration 5522*0Sstevel@tonic-gate * in this case - set interrupt characteristic 5523*0Sstevel@tonic-gate */ 5524*0Sstevel@tonic-gate static void 5525*0Sstevel@tonic-gate pc87332_config_mode(struct ecppunit *pp) 5526*0Sstevel@tonic-gate { 5527*0Sstevel@tonic-gate if (COMPAT_PIO(pp)) { 5528*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PCR, 0x04); 5529*0Sstevel@tonic-gate } else { 5530*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PCR, 0x14); 5531*0Sstevel@tonic-gate } 5532*0Sstevel@tonic-gate } 5533*0Sstevel@tonic-gate 5534*0Sstevel@tonic-gate static int 5535*0Sstevel@tonic-gate pc97317_map_regs(struct ecppunit *pp) 5536*0Sstevel@tonic-gate { 5537*0Sstevel@tonic-gate if (pc87332_map_regs(pp) != SUCCESS) { 5538*0Sstevel@tonic-gate return (FAILURE); 5539*0Sstevel@tonic-gate } 5540*0Sstevel@tonic-gate 5541*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->uh.ebus.c2_reg, 5542*0Sstevel@tonic-gate 0x403, sizeof (struct config2_reg), &acc_attr, 5543*0Sstevel@tonic-gate &pp->uh.ebus.c2_handle) != DDI_SUCCESS) { 5544*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc97317_map_regs: failed c2_reg\n"); 5545*0Sstevel@tonic-gate pc87332_unmap_regs(pp); 5546*0Sstevel@tonic-gate return (FAILURE); 5547*0Sstevel@tonic-gate } else { 5548*0Sstevel@tonic-gate return (SUCCESS); 5549*0Sstevel@tonic-gate } 5550*0Sstevel@tonic-gate } 5551*0Sstevel@tonic-gate 5552*0Sstevel@tonic-gate static void 5553*0Sstevel@tonic-gate pc97317_unmap_regs(struct ecppunit *pp) 5554*0Sstevel@tonic-gate { 5555*0Sstevel@tonic-gate if (pp->uh.ebus.c2_handle) { 5556*0Sstevel@tonic-gate ddi_regs_map_free(&pp->uh.ebus.c2_handle); 5557*0Sstevel@tonic-gate } 5558*0Sstevel@tonic-gate 5559*0Sstevel@tonic-gate pc87332_unmap_regs(pp); 5560*0Sstevel@tonic-gate } 5561*0Sstevel@tonic-gate 5562*0Sstevel@tonic-gate /* 5563*0Sstevel@tonic-gate * OBP should configure the PC97317 such that it does not need further 5564*0Sstevel@tonic-gate * configuration. Upon sustaining, it may be necessary to examine 5565*0Sstevel@tonic-gate * or change the configuration registers. This routine is left in 5566*0Sstevel@tonic-gate * the file for that purpose. 5567*0Sstevel@tonic-gate */ 5568*0Sstevel@tonic-gate static int 5569*0Sstevel@tonic-gate pc97317_config_chip(struct ecppunit *pp) 5570*0Sstevel@tonic-gate { 5571*0Sstevel@tonic-gate uint8_t conreg; 5572*0Sstevel@tonic-gate 5573*0Sstevel@tonic-gate /* set the logical device name */ 5574*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4); 5575*0Sstevel@tonic-gate 5576*0Sstevel@tonic-gate /* SPP Compatibility */ 5577*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c2_handle, 5578*0Sstevel@tonic-gate &pp->uh.ebus.c2_reg->eir, PC97317_CONFIG2_CONTROL2); 5579*0Sstevel@tonic-gate PP_PUTB(pp->uh.ebus.c2_handle, &pp->uh.ebus.c2_reg->edr, 0x80); 5580*0Sstevel@tonic-gate 5581*0Sstevel@tonic-gate /* low interrupt polarity */ 5582*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00); 5583*0Sstevel@tonic-gate 5584*0Sstevel@tonic-gate /* ECP mode */ 5585*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_PP_CONFIG, 0xf2); 5586*0Sstevel@tonic-gate 5587*0Sstevel@tonic-gate if (dcr_write(pp, ECPP_SLCTIN | ECPP_nINIT) == FAILURE) { 5588*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc97317_config_chip: failed w/DCR\n"); 5589*0Sstevel@tonic-gate } 5590*0Sstevel@tonic-gate 5591*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_001 | 5592*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) { 5593*0Sstevel@tonic-gate ecpp_error(pp->dip, "pc97317_config_chip: failed w/ECR\n"); 5594*0Sstevel@tonic-gate } 5595*0Sstevel@tonic-gate 5596*0Sstevel@tonic-gate #ifdef DEBUG 5597*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DEV_NO); 5598*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg7(logical dev)=%x\n", conreg); 5599*0Sstevel@tonic-gate 5600*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_MSB); 5601*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg60(addrHi)=%x\n", conreg); 5602*0Sstevel@tonic-gate 5603*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_LSB); 5604*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg61(addrLo)=%x\n", conreg); 5605*0Sstevel@tonic-gate 5606*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_SEL); 5607*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg70(IRQL)=%x\n", conreg); 5608*0Sstevel@tonic-gate 5609*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_TYPE); 5610*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg71(intr type)=%x\n", conreg); 5611*0Sstevel@tonic-gate 5612*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_ACTIVATE); 5613*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg30(Active)=%x\n", conreg); 5614*0Sstevel@tonic-gate 5615*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_IO_RANGE); 5616*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg31(IO Range Check)=%x\n", conreg); 5617*0Sstevel@tonic-gate 5618*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA0_CHAN); 5619*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg74(DMA0 Chan)=%x\n", conreg); 5620*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA1_CHAN); 5621*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conreg75(DMA1 Chan)=%x\n", conreg); 5622*0Sstevel@tonic-gate 5623*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG); 5624*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg); 5625*0Sstevel@tonic-gate 5626*0Sstevel@tonic-gate conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG); 5627*0Sstevel@tonic-gate ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg); 5628*0Sstevel@tonic-gate #endif /* DEBUG */ 5629*0Sstevel@tonic-gate 5630*0Sstevel@tonic-gate return (SUCCESS); 5631*0Sstevel@tonic-gate } 5632*0Sstevel@tonic-gate 5633*0Sstevel@tonic-gate /* 5634*0Sstevel@tonic-gate * A new mode was set, do some mode specific reconfiguration 5635*0Sstevel@tonic-gate * in this case - set interrupt polarity 5636*0Sstevel@tonic-gate */ 5637*0Sstevel@tonic-gate static void 5638*0Sstevel@tonic-gate pc97317_config_mode(struct ecppunit *pp) 5639*0Sstevel@tonic-gate { 5640*0Sstevel@tonic-gate /* set the logical device name */ 5641*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4); 5642*0Sstevel@tonic-gate 5643*0Sstevel@tonic-gate if (COMPAT_PIO(pp) || pp->current_mode == ECPP_NIBBLE_MODE) { 5644*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x02); 5645*0Sstevel@tonic-gate } else { 5646*0Sstevel@tonic-gate pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00); 5647*0Sstevel@tonic-gate } 5648*0Sstevel@tonic-gate } 5649*0Sstevel@tonic-gate 5650*0Sstevel@tonic-gate static void 5651*0Sstevel@tonic-gate cheerio_mask_intr(struct ecppunit *pp) 5652*0Sstevel@tonic-gate { 5653*0Sstevel@tonic-gate /* mask Cheerio interrupts */ 5654*0Sstevel@tonic-gate AND_SET_LONG_R(pp->uh.ebus.d_handle, 5655*0Sstevel@tonic-gate &pp->uh.ebus.dmac->csr, ~DCSR_INT_EN); 5656*0Sstevel@tonic-gate } 5657*0Sstevel@tonic-gate 5658*0Sstevel@tonic-gate static void 5659*0Sstevel@tonic-gate cheerio_unmask_intr(struct ecppunit *pp) 5660*0Sstevel@tonic-gate { 5661*0Sstevel@tonic-gate /* unmask Cheerio interrupts */ 5662*0Sstevel@tonic-gate OR_SET_LONG_R(pp->uh.ebus.d_handle, 5663*0Sstevel@tonic-gate &pp->uh.ebus.dmac->csr, DCSR_INT_EN | DCSR_TCI_DIS); 5664*0Sstevel@tonic-gate } 5665*0Sstevel@tonic-gate 5666*0Sstevel@tonic-gate static int 5667*0Sstevel@tonic-gate cheerio_dma_start(struct ecppunit *pp) 5668*0Sstevel@tonic-gate { 5669*0Sstevel@tonic-gate cheerio_reset_dcsr(pp); 5670*0Sstevel@tonic-gate SET_DMAC_BCR(pp, pp->dma_cookie.dmac_size); 5671*0Sstevel@tonic-gate SET_DMAC_ACR(pp, pp->dma_cookie.dmac_address); 5672*0Sstevel@tonic-gate 5673*0Sstevel@tonic-gate if (pp->dma_dir == DDI_DMA_READ) { 5674*0Sstevel@tonic-gate SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA | 5675*0Sstevel@tonic-gate DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0 | DCSR_WRITE); 5676*0Sstevel@tonic-gate } else { 5677*0Sstevel@tonic-gate SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA | 5678*0Sstevel@tonic-gate DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0); 5679*0Sstevel@tonic-gate } 5680*0Sstevel@tonic-gate 5681*0Sstevel@tonic-gate return (SUCCESS); 5682*0Sstevel@tonic-gate } 5683*0Sstevel@tonic-gate 5684*0Sstevel@tonic-gate /* 5685*0Sstevel@tonic-gate * Note: BCR is reset to 0, so counter should always be read before dma_stop 5686*0Sstevel@tonic-gate */ 5687*0Sstevel@tonic-gate static int 5688*0Sstevel@tonic-gate cheerio_dma_stop(struct ecppunit *pp, size_t *countp) 5689*0Sstevel@tonic-gate { 5690*0Sstevel@tonic-gate uint8_t ecr; 5691*0Sstevel@tonic-gate 5692*0Sstevel@tonic-gate /* disable DMA and byte counter */ 5693*0Sstevel@tonic-gate AND_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr, 5694*0Sstevel@tonic-gate ~(DCSR_EN_DMA | DCSR_EN_CNT| DCSR_INT_EN)); 5695*0Sstevel@tonic-gate 5696*0Sstevel@tonic-gate /* ACK and disable the TC interrupt */ 5697*0Sstevel@tonic-gate OR_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr, 5698*0Sstevel@tonic-gate DCSR_TC | DCSR_TCI_DIS); 5699*0Sstevel@tonic-gate 5700*0Sstevel@tonic-gate /* read DMA count if requested */ 5701*0Sstevel@tonic-gate if (countp) { 5702*0Sstevel@tonic-gate *countp = cheerio_getcnt(pp); 5703*0Sstevel@tonic-gate } 5704*0Sstevel@tonic-gate 5705*0Sstevel@tonic-gate cheerio_reset_dcsr(pp); 5706*0Sstevel@tonic-gate SET_DMAC_BCR(pp, 0); 5707*0Sstevel@tonic-gate 5708*0Sstevel@tonic-gate /* turn off SuperIO's DMA */ 5709*0Sstevel@tonic-gate ecr = ECR_READ(pp); 5710*0Sstevel@tonic-gate if (ecr_write(pp, ecr & ~ECPP_DMA_ENABLE) == FAILURE) { 5711*0Sstevel@tonic-gate return (FAILURE); 5712*0Sstevel@tonic-gate } 5713*0Sstevel@tonic-gate 5714*0Sstevel@tonic-gate /* Disable SuperIO interrupts and DMA */ 5715*0Sstevel@tonic-gate ecr = ECR_READ(pp); 5716*0Sstevel@tonic-gate 5717*0Sstevel@tonic-gate return (ecr_write(pp, ecr | ECPP_INTR_SRV)); 5718*0Sstevel@tonic-gate } 5719*0Sstevel@tonic-gate 5720*0Sstevel@tonic-gate static size_t 5721*0Sstevel@tonic-gate cheerio_getcnt(struct ecppunit *pp) 5722*0Sstevel@tonic-gate { 5723*0Sstevel@tonic-gate return (GET_DMAC_BCR(pp)); 5724*0Sstevel@tonic-gate } 5725*0Sstevel@tonic-gate 5726*0Sstevel@tonic-gate /* 5727*0Sstevel@tonic-gate * Reset the DCSR by first setting the RESET bit to 1. Poll the 5728*0Sstevel@tonic-gate * DCSR_CYC_PEND bit to make sure there are no more pending DMA cycles. 5729*0Sstevel@tonic-gate * If there are no more pending cycles, clear the RESET bit. 5730*0Sstevel@tonic-gate */ 5731*0Sstevel@tonic-gate static void 5732*0Sstevel@tonic-gate cheerio_reset_dcsr(struct ecppunit *pp) 5733*0Sstevel@tonic-gate { 5734*0Sstevel@tonic-gate int timeout = DMAC_RESET_TIMEOUT; 5735*0Sstevel@tonic-gate 5736*0Sstevel@tonic-gate SET_DMAC_CSR(pp, DCSR_RESET); 5737*0Sstevel@tonic-gate 5738*0Sstevel@tonic-gate while (GET_DMAC_CSR(pp) & DCSR_CYC_PEND) { 5739*0Sstevel@tonic-gate if (timeout == 0) { 5740*0Sstevel@tonic-gate ecpp_error(pp->dip, "cheerio_reset_dcsr: timeout\n"); 5741*0Sstevel@tonic-gate break; 5742*0Sstevel@tonic-gate } else { 5743*0Sstevel@tonic-gate drv_usecwait(1); 5744*0Sstevel@tonic-gate timeout--; 5745*0Sstevel@tonic-gate } 5746*0Sstevel@tonic-gate } 5747*0Sstevel@tonic-gate 5748*0Sstevel@tonic-gate SET_DMAC_CSR(pp, 0); 5749*0Sstevel@tonic-gate } 5750*0Sstevel@tonic-gate 5751*0Sstevel@tonic-gate /* 5752*0Sstevel@tonic-gate * 5753*0Sstevel@tonic-gate * Grover Southbridge (M1553) support routines 5754*0Sstevel@tonic-gate * Southbridge contains an Intel 8237 DMAC onboard which is used 5755*0Sstevel@tonic-gate * to transport data to/from PCI space to superio parallel port 5756*0Sstevel@tonic-gate * 5757*0Sstevel@tonic-gate */ 5758*0Sstevel@tonic-gate 5759*0Sstevel@tonic-gate 5760*0Sstevel@tonic-gate static int 5761*0Sstevel@tonic-gate m1553_map_regs(struct ecppunit *pp) 5762*0Sstevel@tonic-gate { 5763*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.m1553.isa_space, 5764*0Sstevel@tonic-gate 0, sizeof (struct isaspace), &acc_attr, 5765*0Sstevel@tonic-gate &pp->uh.m1553.d_handle) != DDI_SUCCESS) { 5766*0Sstevel@tonic-gate ecpp_error(pp->dip, "m1553_map_regs: failed isa space\n"); 5767*0Sstevel@tonic-gate goto fail; 5768*0Sstevel@tonic-gate } 5769*0Sstevel@tonic-gate 5770*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0, 5771*0Sstevel@tonic-gate sizeof (struct info_reg), &acc_attr, &pp->i_handle) 5772*0Sstevel@tonic-gate != DDI_SUCCESS) { 5773*0Sstevel@tonic-gate ecpp_error(pp->dip, "m1553_map_regs: failed i_reg\n"); 5774*0Sstevel@tonic-gate goto fail; 5775*0Sstevel@tonic-gate } 5776*0Sstevel@tonic-gate 5777*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400, 5778*0Sstevel@tonic-gate sizeof (struct fifo_reg), &acc_attr, &pp->f_handle) 5779*0Sstevel@tonic-gate != DDI_SUCCESS) { 5780*0Sstevel@tonic-gate ecpp_error(pp->dip, "m1553_map_regs: failed f_reg\n"); 5781*0Sstevel@tonic-gate goto fail; 5782*0Sstevel@tonic-gate } 5783*0Sstevel@tonic-gate 5784*0Sstevel@tonic-gate return (SUCCESS); 5785*0Sstevel@tonic-gate 5786*0Sstevel@tonic-gate fail: 5787*0Sstevel@tonic-gate m1553_unmap_regs(pp); 5788*0Sstevel@tonic-gate return (FAILURE); 5789*0Sstevel@tonic-gate } 5790*0Sstevel@tonic-gate 5791*0Sstevel@tonic-gate static void 5792*0Sstevel@tonic-gate m1553_unmap_regs(struct ecppunit *pp) 5793*0Sstevel@tonic-gate { 5794*0Sstevel@tonic-gate if (pp->uh.m1553.d_handle) { 5795*0Sstevel@tonic-gate ddi_regs_map_free(&pp->uh.m1553.d_handle); 5796*0Sstevel@tonic-gate } 5797*0Sstevel@tonic-gate if (pp->i_handle) { 5798*0Sstevel@tonic-gate ddi_regs_map_free(&pp->i_handle); 5799*0Sstevel@tonic-gate } 5800*0Sstevel@tonic-gate if (pp->f_handle) { 5801*0Sstevel@tonic-gate ddi_regs_map_free(&pp->f_handle); 5802*0Sstevel@tonic-gate } 5803*0Sstevel@tonic-gate } 5804*0Sstevel@tonic-gate 5805*0Sstevel@tonic-gate #if defined(__x86) 5806*0Sstevel@tonic-gate static int 5807*0Sstevel@tonic-gate x86_map_regs(struct ecppunit *pp) 5808*0Sstevel@tonic-gate { 5809*0Sstevel@tonic-gate int nregs = 0; 5810*0Sstevel@tonic-gate 5811*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0, 5812*0Sstevel@tonic-gate sizeof (struct info_reg), &acc_attr, &pp->i_handle) 5813*0Sstevel@tonic-gate != DDI_SUCCESS) { 5814*0Sstevel@tonic-gate ecpp_error(pp->dip, "x86_map_regs: failed i_reg\n"); 5815*0Sstevel@tonic-gate goto fail; 5816*0Sstevel@tonic-gate } 5817*0Sstevel@tonic-gate if (ddi_dev_nregs(pp->dip, &nregs) == DDI_SUCCESS && nregs == 2) { 5818*0Sstevel@tonic-gate if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->f_reg, 0, 5819*0Sstevel@tonic-gate sizeof (struct fifo_reg), &acc_attr, &pp->f_handle) 5820*0Sstevel@tonic-gate != DDI_SUCCESS) { 5821*0Sstevel@tonic-gate ecpp_error(pp->dip, "x86_map_regs: failed f_reg\n"); 5822*0Sstevel@tonic-gate goto fail; 5823*0Sstevel@tonic-gate } else 5824*0Sstevel@tonic-gate pp->noecpregs = FALSE; 5825*0Sstevel@tonic-gate } else { 5826*0Sstevel@tonic-gate pp->noecpregs = TRUE; 5827*0Sstevel@tonic-gate } 5828*0Sstevel@tonic-gate return (SUCCESS); 5829*0Sstevel@tonic-gate fail: 5830*0Sstevel@tonic-gate x86_unmap_regs(pp); 5831*0Sstevel@tonic-gate return (FAILURE); 5832*0Sstevel@tonic-gate } 5833*0Sstevel@tonic-gate 5834*0Sstevel@tonic-gate static void 5835*0Sstevel@tonic-gate x86_unmap_regs(struct ecppunit *pp) 5836*0Sstevel@tonic-gate { 5837*0Sstevel@tonic-gate if (pp->i_handle) { 5838*0Sstevel@tonic-gate ddi_regs_map_free(&pp->i_handle); 5839*0Sstevel@tonic-gate } 5840*0Sstevel@tonic-gate if (pp->f_handle) { 5841*0Sstevel@tonic-gate ddi_regs_map_free(&pp->f_handle); 5842*0Sstevel@tonic-gate } 5843*0Sstevel@tonic-gate } 5844*0Sstevel@tonic-gate #endif 5845*0Sstevel@tonic-gate 5846*0Sstevel@tonic-gate static uint8_t 5847*0Sstevel@tonic-gate m1553_read_config_reg(struct ecppunit *pp, uint8_t reg_num) 5848*0Sstevel@tonic-gate { 5849*0Sstevel@tonic-gate uint8_t retval; 5850*0Sstevel@tonic-gate 5851*0Sstevel@tonic-gate dma8237_write(pp, 0x3F0, reg_num); 5852*0Sstevel@tonic-gate retval = dma8237_read(pp, 0x3F1); 5853*0Sstevel@tonic-gate 5854*0Sstevel@tonic-gate return (retval); 5855*0Sstevel@tonic-gate } 5856*0Sstevel@tonic-gate 5857*0Sstevel@tonic-gate static void 5858*0Sstevel@tonic-gate m1553_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val) 5859*0Sstevel@tonic-gate { 5860*0Sstevel@tonic-gate dma8237_write(pp, 0x3F0, reg_num); 5861*0Sstevel@tonic-gate dma8237_write(pp, 0x3F1, val); 5862*0Sstevel@tonic-gate } 5863*0Sstevel@tonic-gate 5864*0Sstevel@tonic-gate static int 5865*0Sstevel@tonic-gate m1553_config_chip(struct ecppunit *pp) 5866*0Sstevel@tonic-gate { 5867*0Sstevel@tonic-gate uint8_t conreg; 5868*0Sstevel@tonic-gate 5869*0Sstevel@tonic-gate /* Unlock configuration regs with "key sequence" */ 5870*0Sstevel@tonic-gate dma8237_write(pp, 0x3F0, 0x51); 5871*0Sstevel@tonic-gate dma8237_write(pp, 0x3F0, 0x23); 5872*0Sstevel@tonic-gate 5873*0Sstevel@tonic-gate m1553_write_config_reg(pp, PnP_CONFIG_DEV_NO, 0x3); 5874*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_DEV_NO); 5875*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg7(logical dev)=%x\n", conreg); 5876*0Sstevel@tonic-gate 5877*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_ACTIVATE); 5878*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg30(Active)=%x\n", conreg); 5879*0Sstevel@tonic-gate 5880*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_MSB); 5881*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg60(addrHi)=%x\n", conreg); 5882*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_LSB); 5883*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg61(addrLo)=%x\n", conreg); 5884*0Sstevel@tonic-gate 5885*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_INTR_SEL); 5886*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg70(IRQL)=%x\n", conreg); 5887*0Sstevel@tonic-gate 5888*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_DMA0_CHAN); 5889*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conreg74(DMA0 Chan)=%x\n", conreg); 5890*0Sstevel@tonic-gate 5891*0Sstevel@tonic-gate /* set FIFO threshold 1 and ECP mode, preserve bit 7 (IRQ polarity) */ 5892*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0); 5893*0Sstevel@tonic-gate conreg = (conreg & ~0x7F) | 0x0A; 5894*0Sstevel@tonic-gate m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG0, conreg); 5895*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0); 5896*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conregFO(pport conf)=%x\n", conreg); 5897*0Sstevel@tonic-gate 5898*0Sstevel@tonic-gate m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG1, 0x04); 5899*0Sstevel@tonic-gate conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG1); 5900*0Sstevel@tonic-gate ecpp_error(pp->dip, "M1553:conregF1(outconf)=%x\n", conreg); 5901*0Sstevel@tonic-gate 5902*0Sstevel@tonic-gate /* lock configuration regs with key */ 5903*0Sstevel@tonic-gate dma8237_write(pp, 0x3F0, 0xBB); 5904*0Sstevel@tonic-gate 5905*0Sstevel@tonic-gate /* Set ECR, DCR in known state */ 5906*0Sstevel@tonic-gate ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV); 5907*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT); 5908*0Sstevel@tonic-gate 5909*0Sstevel@tonic-gate ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n", 5910*0Sstevel@tonic-gate ECR_READ(pp), DSR_READ(pp), DCR_READ(pp)); 5911*0Sstevel@tonic-gate 5912*0Sstevel@tonic-gate return (SUCCESS); 5913*0Sstevel@tonic-gate } 5914*0Sstevel@tonic-gate 5915*0Sstevel@tonic-gate #if defined(__x86) 5916*0Sstevel@tonic-gate static int 5917*0Sstevel@tonic-gate x86_config_chip(struct ecppunit *pp) 5918*0Sstevel@tonic-gate { 5919*0Sstevel@tonic-gate if (ecr_write(pp, ECR_mode_001 | 5920*0Sstevel@tonic-gate ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) { 5921*0Sstevel@tonic-gate ecpp_error(pp->dip, "config chip: failed w/ecr\n"); 5922*0Sstevel@tonic-gate pp->noecpregs = TRUE; 5923*0Sstevel@tonic-gate } 5924*0Sstevel@tonic-gate if (pp->noecpregs) 5925*0Sstevel@tonic-gate pp->fast_compat = FALSE; 5926*0Sstevel@tonic-gate DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT); 5927*0Sstevel@tonic-gate ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n", 5928*0Sstevel@tonic-gate ECR_READ(pp), DSR_READ(pp), DCR_READ(pp)); 5929*0Sstevel@tonic-gate return (SUCCESS); 5930*0Sstevel@tonic-gate } 5931*0Sstevel@tonic-gate #endif 5932*0Sstevel@tonic-gate 5933*0Sstevel@tonic-gate /* 5934*0Sstevel@tonic-gate * dma8237_dma_start() programs the selected 8 bit channel 5935*0Sstevel@tonic-gate * of DMAC1 with the dma cookie. pp->dma_cookie must 5936*0Sstevel@tonic-gate * be set before this routine is called. 5937*0Sstevel@tonic-gate */ 5938*0Sstevel@tonic-gate static int 5939*0Sstevel@tonic-gate dma8237_dma_start(struct ecppunit *pp) 5940*0Sstevel@tonic-gate { 5941*0Sstevel@tonic-gate uint8_t chn; 5942*0Sstevel@tonic-gate 5943*0Sstevel@tonic-gate chn = pp->uh.m1553.chn; 5944*0Sstevel@tonic-gate 5945*0Sstevel@tonic-gate ASSERT(chn <= DMAE_CH3 && 5946*0Sstevel@tonic-gate pp->dma_cookie.dmac_size != 0 && 5947*0Sstevel@tonic-gate pp->dma_cookie.dmac_address != NULL); 5948*0Sstevel@tonic-gate 5949*0Sstevel@tonic-gate /* At this point Southbridge has not yet asserted DREQ */ 5950*0Sstevel@tonic-gate 5951*0Sstevel@tonic-gate /* set mode to read-from-memory. */ 5952*0Sstevel@tonic-gate dma8237_write(pp, DMAC2_MODE, DMAMODE_CASC); 5953*0Sstevel@tonic-gate if (pp->dma_dir == DDI_DMA_READ) { 5954*0Sstevel@tonic-gate dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE | 5955*0Sstevel@tonic-gate DMAMODE_READ | chn); 5956*0Sstevel@tonic-gate } else { 5957*0Sstevel@tonic-gate dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE | 5958*0Sstevel@tonic-gate DMAMODE_WRITE | chn); 5959*0Sstevel@tonic-gate } 5960*0Sstevel@tonic-gate 5961*0Sstevel@tonic-gate dma8237_write_addr(pp, pp->dma_cookie.dmac_address); 5962*0Sstevel@tonic-gate dma8237_write_count(pp, pp->dma_cookie.dmac_size - 1); 5963*0Sstevel@tonic-gate 5964*0Sstevel@tonic-gate /* 5965*0Sstevel@tonic-gate * M1553 chip does not permit to access DMA register banks 5966*0Sstevel@tonic-gate * while DMA is in flight. As a result, ecpp and floppy drivers 5967*0Sstevel@tonic-gate * can potentially corrupt each other's DMA. The interlocking mechanism 5968*0Sstevel@tonic-gate * is provided by a parent nexus driver (isadma), which is enabled 5969*0Sstevel@tonic-gate * indirectly through a DMAC1_ALLMASK register access: 5970*0Sstevel@tonic-gate * 5971*0Sstevel@tonic-gate * writing a non-zero value to this register enters a lock, 5972*0Sstevel@tonic-gate * writing zero releases the lock. 5973*0Sstevel@tonic-gate * 5974*0Sstevel@tonic-gate * DMA transfer must only occur after entering a lock. 5975*0Sstevel@tonic-gate * If the lock is already owned by other driver, we will block. 5976*0Sstevel@tonic-gate * 5977*0Sstevel@tonic-gate * The following operation unmasks our channel and masks all others 5978*0Sstevel@tonic-gate */ 5979*0Sstevel@tonic-gate dma8237_write(pp, DMAC1_ALLMASK, ~(1 << chn)); 5980*0Sstevel@tonic-gate pp->uh.m1553.isadma_entered = 1; 5981*0Sstevel@tonic-gate 5982*0Sstevel@tonic-gate return (SUCCESS); 5983*0Sstevel@tonic-gate } 5984*0Sstevel@tonic-gate 5985*0Sstevel@tonic-gate static int 5986*0Sstevel@tonic-gate dma8237_dma_stop(struct ecppunit *pp, size_t *countp) 5987*0Sstevel@tonic-gate { 5988*0Sstevel@tonic-gate uint8_t ecr; 5989*0Sstevel@tonic-gate 5990*0Sstevel@tonic-gate /* stop DMA */ 5991*0Sstevel@tonic-gate ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV; 5992*0Sstevel@tonic-gate (void) ecr_write(pp, ecr); 5993*0Sstevel@tonic-gate 5994*0Sstevel@tonic-gate if (pp->uh.m1553.isadma_entered) { 5995*0Sstevel@tonic-gate /* reset the channel mask so we can issue PIO's to our device */ 5996*0Sstevel@tonic-gate dma8237_write(pp, DMAC1_ALLMASK, 0); 5997*0Sstevel@tonic-gate pp->uh.m1553.isadma_entered = 0; 5998*0Sstevel@tonic-gate 5999*0Sstevel@tonic-gate } 6000*0Sstevel@tonic-gate 6001*0Sstevel@tonic-gate /* read DMA count if requested */ 6002*0Sstevel@tonic-gate if (countp) { 6003*0Sstevel@tonic-gate *countp = dma8237_getcnt(pp); 6004*0Sstevel@tonic-gate if (pp->dma_dir == DDI_DMA_READ && *countp > 0) { 6005*0Sstevel@tonic-gate (*countp)++; /* need correction for reverse xfers */ 6006*0Sstevel@tonic-gate } 6007*0Sstevel@tonic-gate } 6008*0Sstevel@tonic-gate return (SUCCESS); 6009*0Sstevel@tonic-gate } 6010*0Sstevel@tonic-gate #if defined(__x86) 6011*0Sstevel@tonic-gate static int 6012*0Sstevel@tonic-gate x86_dma_start(struct ecppunit *pp) 6013*0Sstevel@tonic-gate { 6014*0Sstevel@tonic-gate uint8_t chn; 6015*0Sstevel@tonic-gate struct ddi_dmae_req dmaereq; 6016*0Sstevel@tonic-gate 6017*0Sstevel@tonic-gate chn = pp->uh.x86.chn; 6018*0Sstevel@tonic-gate ASSERT(chn <= DMAE_CH3 && 6019*0Sstevel@tonic-gate pp->dma_cookie.dmac_size != 0 && 6020*0Sstevel@tonic-gate pp->dma_cookie.dmac_address != NULL); 6021*0Sstevel@tonic-gate bzero(&dmaereq, sizeof (struct ddi_dmae_req)); 6022*0Sstevel@tonic-gate dmaereq.der_command = 6023*0Sstevel@tonic-gate (pp->dma_dir & DDI_DMA_READ) ? DMAE_CMD_READ : DMAE_CMD_WRITE; 6024*0Sstevel@tonic-gate if (ddi_dmae_prog(pp->dip, &dmaereq, &pp->dma_cookie, chn) 6025*0Sstevel@tonic-gate != DDI_SUCCESS) 6026*0Sstevel@tonic-gate ecpp_error(pp->dip, "prog failed !!!\n"); 6027*0Sstevel@tonic-gate ecpp_error(pp->dip, "dma_started..\n"); 6028*0Sstevel@tonic-gate return (SUCCESS); 6029*0Sstevel@tonic-gate } 6030*0Sstevel@tonic-gate 6031*0Sstevel@tonic-gate static int 6032*0Sstevel@tonic-gate x86_dma_stop(struct ecppunit *pp, size_t *countp) 6033*0Sstevel@tonic-gate { 6034*0Sstevel@tonic-gate uint8_t ecr; 6035*0Sstevel@tonic-gate 6036*0Sstevel@tonic-gate /* stop DMA */ 6037*0Sstevel@tonic-gate if (pp->uh.x86.chn == 0xff) 6038*0Sstevel@tonic-gate return (FAILURE); 6039*0Sstevel@tonic-gate ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV; 6040*0Sstevel@tonic-gate (void) ecr_write(pp, ecr); 6041*0Sstevel@tonic-gate ecpp_error(pp->dip, "dma_stop\n"); 6042*0Sstevel@tonic-gate 6043*0Sstevel@tonic-gate /* read DMA count if requested */ 6044*0Sstevel@tonic-gate if (countp) { 6045*0Sstevel@tonic-gate *countp = x86_getcnt(pp); 6046*0Sstevel@tonic-gate } 6047*0Sstevel@tonic-gate ecpp_error(pp->dip, "dma_stoped..\n"); 6048*0Sstevel@tonic-gate return (SUCCESS); 6049*0Sstevel@tonic-gate } 6050*0Sstevel@tonic-gate #endif 6051*0Sstevel@tonic-gate 6052*0Sstevel@tonic-gate /* channel must be masked */ 6053*0Sstevel@tonic-gate static void 6054*0Sstevel@tonic-gate dma8237_write_addr(struct ecppunit *pp, uint32_t addr) 6055*0Sstevel@tonic-gate { 6056*0Sstevel@tonic-gate uint8_t c_addr, c_lpage; 6057*0Sstevel@tonic-gate uint16_t c_hpage, *p; 6058*0Sstevel@tonic-gate 6059*0Sstevel@tonic-gate switch (pp->uh.m1553.chn) { 6060*0Sstevel@tonic-gate case DMAE_CH0: 6061*0Sstevel@tonic-gate c_addr = DMA_0ADR; 6062*0Sstevel@tonic-gate c_lpage = DMA_0PAGE; 6063*0Sstevel@tonic-gate c_hpage = DMA_0HPG; 6064*0Sstevel@tonic-gate break; 6065*0Sstevel@tonic-gate 6066*0Sstevel@tonic-gate case DMAE_CH1: 6067*0Sstevel@tonic-gate c_addr = DMA_1ADR; 6068*0Sstevel@tonic-gate c_lpage = DMA_1PAGE; 6069*0Sstevel@tonic-gate c_hpage = DMA_1HPG; 6070*0Sstevel@tonic-gate break; 6071*0Sstevel@tonic-gate 6072*0Sstevel@tonic-gate case DMAE_CH2: 6073*0Sstevel@tonic-gate c_addr = DMA_2ADR; 6074*0Sstevel@tonic-gate c_lpage = DMA_2PAGE; 6075*0Sstevel@tonic-gate c_hpage = DMA_2HPG; 6076*0Sstevel@tonic-gate break; 6077*0Sstevel@tonic-gate 6078*0Sstevel@tonic-gate case DMAE_CH3: 6079*0Sstevel@tonic-gate c_addr = DMA_3ADR; 6080*0Sstevel@tonic-gate c_lpage = DMA_3PAGE; 6081*0Sstevel@tonic-gate c_hpage = DMA_3HPG; 6082*0Sstevel@tonic-gate break; 6083*0Sstevel@tonic-gate 6084*0Sstevel@tonic-gate default: 6085*0Sstevel@tonic-gate return; 6086*0Sstevel@tonic-gate } 6087*0Sstevel@tonic-gate 6088*0Sstevel@tonic-gate p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr]; 6089*0Sstevel@tonic-gate ddi_put16(pp->uh.m1553.d_handle, p, addr & 0xFFFF); 6090*0Sstevel@tonic-gate 6091*0Sstevel@tonic-gate dma8237_write(pp, c_lpage, (addr & 0xFF0000) >> 16); 6092*0Sstevel@tonic-gate dma8237_write(pp, c_hpage, (addr & 0xFF000000) >> 24); 6093*0Sstevel@tonic-gate 6094*0Sstevel@tonic-gate } 6095*0Sstevel@tonic-gate 6096*0Sstevel@tonic-gate /* 6097*0Sstevel@tonic-gate * This function may be useful during debugging, 6098*0Sstevel@tonic-gate * so we leave it in, but do not include in the binary 6099*0Sstevel@tonic-gate */ 6100*0Sstevel@tonic-gate #ifdef INCLUDE_DMA8237_READ_ADDR 6101*0Sstevel@tonic-gate static uint32_t 6102*0Sstevel@tonic-gate dma8237_read_addr(struct ecppunit *pp) 6103*0Sstevel@tonic-gate { 6104*0Sstevel@tonic-gate uint8_t rval3, rval4; 6105*0Sstevel@tonic-gate uint16_t rval16; 6106*0Sstevel@tonic-gate uint32_t rval; 6107*0Sstevel@tonic-gate uint8_t c_addr, c_lpage; 6108*0Sstevel@tonic-gate uint16_t c_hpage, *p; 6109*0Sstevel@tonic-gate 6110*0Sstevel@tonic-gate switch (pp->uh.m1553.chn) { 6111*0Sstevel@tonic-gate case DMAE_CH0: 6112*0Sstevel@tonic-gate c_addr = DMA_0ADR; 6113*0Sstevel@tonic-gate c_lpage = DMA_0PAGE; 6114*0Sstevel@tonic-gate c_hpage = DMA_0HPG; 6115*0Sstevel@tonic-gate break; 6116*0Sstevel@tonic-gate 6117*0Sstevel@tonic-gate case DMAE_CH1: 6118*0Sstevel@tonic-gate c_addr = DMA_1ADR; 6119*0Sstevel@tonic-gate c_lpage = DMA_1PAGE; 6120*0Sstevel@tonic-gate c_hpage = DMA_1HPG; 6121*0Sstevel@tonic-gate break; 6122*0Sstevel@tonic-gate 6123*0Sstevel@tonic-gate case DMAE_CH2: 6124*0Sstevel@tonic-gate c_addr = DMA_2ADR; 6125*0Sstevel@tonic-gate c_lpage = DMA_2PAGE; 6126*0Sstevel@tonic-gate c_hpage = DMA_2HPG; 6127*0Sstevel@tonic-gate break; 6128*0Sstevel@tonic-gate 6129*0Sstevel@tonic-gate case DMAE_CH3: 6130*0Sstevel@tonic-gate c_addr = DMA_3ADR; 6131*0Sstevel@tonic-gate c_lpage = DMA_3PAGE; 6132*0Sstevel@tonic-gate c_hpage = DMA_3HPG; 6133*0Sstevel@tonic-gate break; 6134*0Sstevel@tonic-gate 6135*0Sstevel@tonic-gate default: 6136*0Sstevel@tonic-gate return (NULL); 6137*0Sstevel@tonic-gate } 6138*0Sstevel@tonic-gate 6139*0Sstevel@tonic-gate p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr]; 6140*0Sstevel@tonic-gate rval16 = ddi_get16(pp->uh.m1553.d_handle, p); 6141*0Sstevel@tonic-gate 6142*0Sstevel@tonic-gate rval3 = dma8237_read(pp, c_lpage); 6143*0Sstevel@tonic-gate rval4 = dma8237_read(pp, c_hpage); 6144*0Sstevel@tonic-gate 6145*0Sstevel@tonic-gate rval = rval16 | (rval3 << 16) | (rval4 <<24); 6146*0Sstevel@tonic-gate 6147*0Sstevel@tonic-gate return (rval); 6148*0Sstevel@tonic-gate } 6149*0Sstevel@tonic-gate #endif 6150*0Sstevel@tonic-gate 6151*0Sstevel@tonic-gate static void 6152*0Sstevel@tonic-gate dma8237_write_count(struct ecppunit *pp, uint32_t count) 6153*0Sstevel@tonic-gate { 6154*0Sstevel@tonic-gate uint8_t c_wcnt; 6155*0Sstevel@tonic-gate uint16_t *p; 6156*0Sstevel@tonic-gate 6157*0Sstevel@tonic-gate switch (pp->uh.m1553.chn) { 6158*0Sstevel@tonic-gate case DMAE_CH0: 6159*0Sstevel@tonic-gate c_wcnt = DMA_0WCNT; 6160*0Sstevel@tonic-gate break; 6161*0Sstevel@tonic-gate 6162*0Sstevel@tonic-gate case DMAE_CH1: 6163*0Sstevel@tonic-gate c_wcnt = DMA_1WCNT; 6164*0Sstevel@tonic-gate break; 6165*0Sstevel@tonic-gate 6166*0Sstevel@tonic-gate case DMAE_CH2: 6167*0Sstevel@tonic-gate c_wcnt = DMA_2WCNT; 6168*0Sstevel@tonic-gate break; 6169*0Sstevel@tonic-gate 6170*0Sstevel@tonic-gate case DMAE_CH3: 6171*0Sstevel@tonic-gate c_wcnt = DMA_3WCNT; 6172*0Sstevel@tonic-gate break; 6173*0Sstevel@tonic-gate 6174*0Sstevel@tonic-gate default: 6175*0Sstevel@tonic-gate return; 6176*0Sstevel@tonic-gate } 6177*0Sstevel@tonic-gate 6178*0Sstevel@tonic-gate p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt]; 6179*0Sstevel@tonic-gate ddi_put16(pp->uh.m1553.d_handle, p, count & 0xFFFF); 6180*0Sstevel@tonic-gate 6181*0Sstevel@tonic-gate } 6182*0Sstevel@tonic-gate 6183*0Sstevel@tonic-gate static uint32_t 6184*0Sstevel@tonic-gate dma8237_read_count(struct ecppunit *pp) 6185*0Sstevel@tonic-gate { 6186*0Sstevel@tonic-gate uint8_t c_wcnt; 6187*0Sstevel@tonic-gate uint16_t *p; 6188*0Sstevel@tonic-gate 6189*0Sstevel@tonic-gate switch (pp->uh.m1553.chn) { 6190*0Sstevel@tonic-gate case DMAE_CH0: 6191*0Sstevel@tonic-gate c_wcnt = DMA_0WCNT; 6192*0Sstevel@tonic-gate break; 6193*0Sstevel@tonic-gate 6194*0Sstevel@tonic-gate case DMAE_CH1: 6195*0Sstevel@tonic-gate c_wcnt = DMA_1WCNT; 6196*0Sstevel@tonic-gate break; 6197*0Sstevel@tonic-gate 6198*0Sstevel@tonic-gate case DMAE_CH2: 6199*0Sstevel@tonic-gate c_wcnt = DMA_2WCNT; 6200*0Sstevel@tonic-gate break; 6201*0Sstevel@tonic-gate 6202*0Sstevel@tonic-gate case DMAE_CH3: 6203*0Sstevel@tonic-gate c_wcnt = DMA_3WCNT; 6204*0Sstevel@tonic-gate break; 6205*0Sstevel@tonic-gate 6206*0Sstevel@tonic-gate default: 6207*0Sstevel@tonic-gate return (NULL); 6208*0Sstevel@tonic-gate } 6209*0Sstevel@tonic-gate 6210*0Sstevel@tonic-gate p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt]; 6211*0Sstevel@tonic-gate return (ddi_get16(pp->uh.m1553.d_handle, p)); 6212*0Sstevel@tonic-gate 6213*0Sstevel@tonic-gate } 6214*0Sstevel@tonic-gate 6215*0Sstevel@tonic-gate static void 6216*0Sstevel@tonic-gate dma8237_write(struct ecppunit *pp, int reg_num, uint8_t val) 6217*0Sstevel@tonic-gate { 6218*0Sstevel@tonic-gate ddi_put8(pp->uh.m1553.d_handle, 6219*0Sstevel@tonic-gate &pp->uh.m1553.isa_space->isa_reg[reg_num], val); 6220*0Sstevel@tonic-gate } 6221*0Sstevel@tonic-gate 6222*0Sstevel@tonic-gate static uint8_t 6223*0Sstevel@tonic-gate dma8237_read(struct ecppunit *pp, int reg_num) 6224*0Sstevel@tonic-gate { 6225*0Sstevel@tonic-gate return (ddi_get8(pp->uh.m1553.d_handle, 6226*0Sstevel@tonic-gate &pp->uh.m1553.isa_space->isa_reg[reg_num])); 6227*0Sstevel@tonic-gate } 6228*0Sstevel@tonic-gate 6229*0Sstevel@tonic-gate static size_t 6230*0Sstevel@tonic-gate dma8237_getcnt(struct ecppunit *pp) 6231*0Sstevel@tonic-gate { 6232*0Sstevel@tonic-gate uint32_t cnt; 6233*0Sstevel@tonic-gate 6234*0Sstevel@tonic-gate if ((cnt = dma8237_read_count(pp)) == 0xffff) 6235*0Sstevel@tonic-gate cnt = 0; 6236*0Sstevel@tonic-gate else 6237*0Sstevel@tonic-gate cnt++; 6238*0Sstevel@tonic-gate return (cnt); 6239*0Sstevel@tonic-gate } 6240*0Sstevel@tonic-gate 6241*0Sstevel@tonic-gate 6242*0Sstevel@tonic-gate /* 6243*0Sstevel@tonic-gate * 6244*0Sstevel@tonic-gate * Kstat support routines 6245*0Sstevel@tonic-gate * 6246*0Sstevel@tonic-gate */ 6247*0Sstevel@tonic-gate static void 6248*0Sstevel@tonic-gate ecpp_kstat_init(struct ecppunit *pp) 6249*0Sstevel@tonic-gate { 6250*0Sstevel@tonic-gate struct ecppkstat *ekp; 6251*0Sstevel@tonic-gate char buf[16]; 6252*0Sstevel@tonic-gate 6253*0Sstevel@tonic-gate /* 6254*0Sstevel@tonic-gate * Allocate, initialize and install interrupt counter kstat 6255*0Sstevel@tonic-gate */ 6256*0Sstevel@tonic-gate (void) sprintf(buf, "ecppc%d", pp->instance); 6257*0Sstevel@tonic-gate pp->intrstats = kstat_create("ecpp", pp->instance, buf, "controller", 6258*0Sstevel@tonic-gate KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT); 6259*0Sstevel@tonic-gate if (pp->intrstats == NULL) { 6260*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_kstat_init:1: kstat_create failed"); 6261*0Sstevel@tonic-gate } else { 6262*0Sstevel@tonic-gate pp->intrstats->ks_update = ecpp_kstatintr_update; 6263*0Sstevel@tonic-gate pp->intrstats->ks_private = (void *) pp; 6264*0Sstevel@tonic-gate kstat_install(pp->intrstats); 6265*0Sstevel@tonic-gate } 6266*0Sstevel@tonic-gate 6267*0Sstevel@tonic-gate /* 6268*0Sstevel@tonic-gate * Allocate, initialize and install misc stats kstat 6269*0Sstevel@tonic-gate */ 6270*0Sstevel@tonic-gate pp->ksp = kstat_create("ecpp", pp->instance, NULL, "misc", 6271*0Sstevel@tonic-gate KSTAT_TYPE_NAMED, 6272*0Sstevel@tonic-gate sizeof (struct ecppkstat) / sizeof (kstat_named_t), 6273*0Sstevel@tonic-gate KSTAT_FLAG_PERSISTENT); 6274*0Sstevel@tonic-gate if (pp->ksp == NULL) { 6275*0Sstevel@tonic-gate ecpp_error(pp->dip, "ecpp_kstat_init:2: kstat_create failed"); 6276*0Sstevel@tonic-gate return; 6277*0Sstevel@tonic-gate } 6278*0Sstevel@tonic-gate 6279*0Sstevel@tonic-gate ekp = (struct ecppkstat *)pp->ksp->ks_data; 6280*0Sstevel@tonic-gate 6281*0Sstevel@tonic-gate #define EK_NAMED_INIT(name) \ 6282*0Sstevel@tonic-gate kstat_named_init(&ekp->ek_##name, #name, KSTAT_DATA_UINT32) 6283*0Sstevel@tonic-gate 6284*0Sstevel@tonic-gate EK_NAMED_INIT(ctx_obytes); 6285*0Sstevel@tonic-gate EK_NAMED_INIT(ctxpio_obytes); 6286*0Sstevel@tonic-gate EK_NAMED_INIT(nib_ibytes); 6287*0Sstevel@tonic-gate EK_NAMED_INIT(ecp_obytes); 6288*0Sstevel@tonic-gate EK_NAMED_INIT(ecp_ibytes); 6289*0Sstevel@tonic-gate EK_NAMED_INIT(epp_obytes); 6290*0Sstevel@tonic-gate EK_NAMED_INIT(epp_ibytes); 6291*0Sstevel@tonic-gate EK_NAMED_INIT(diag_obytes); 6292*0Sstevel@tonic-gate EK_NAMED_INIT(to_ctx); 6293*0Sstevel@tonic-gate EK_NAMED_INIT(to_nib); 6294*0Sstevel@tonic-gate EK_NAMED_INIT(to_ecp); 6295*0Sstevel@tonic-gate EK_NAMED_INIT(to_epp); 6296*0Sstevel@tonic-gate EK_NAMED_INIT(to_diag); 6297*0Sstevel@tonic-gate EK_NAMED_INIT(xfer_tout); 6298*0Sstevel@tonic-gate EK_NAMED_INIT(ctx_cf); 6299*0Sstevel@tonic-gate EK_NAMED_INIT(joblen); 6300*0Sstevel@tonic-gate EK_NAMED_INIT(isr_reattempt_high); 6301*0Sstevel@tonic-gate EK_NAMED_INIT(mode); 6302*0Sstevel@tonic-gate EK_NAMED_INIT(phase); 6303*0Sstevel@tonic-gate EK_NAMED_INIT(backchan); 6304*0Sstevel@tonic-gate EK_NAMED_INIT(iomode); 6305*0Sstevel@tonic-gate EK_NAMED_INIT(state); 6306*0Sstevel@tonic-gate 6307*0Sstevel@tonic-gate pp->ksp->ks_update = ecpp_kstat_update; 6308*0Sstevel@tonic-gate pp->ksp->ks_private = (void *) pp; 6309*0Sstevel@tonic-gate kstat_install(pp->ksp); 6310*0Sstevel@tonic-gate } 6311*0Sstevel@tonic-gate 6312*0Sstevel@tonic-gate static int 6313*0Sstevel@tonic-gate ecpp_kstat_update(kstat_t *ksp, int rw) 6314*0Sstevel@tonic-gate { 6315*0Sstevel@tonic-gate struct ecppunit *pp; 6316*0Sstevel@tonic-gate struct ecppkstat *ekp; 6317*0Sstevel@tonic-gate 6318*0Sstevel@tonic-gate /* 6319*0Sstevel@tonic-gate * For the time being there is no point 6320*0Sstevel@tonic-gate * in supporting writable kstats 6321*0Sstevel@tonic-gate */ 6322*0Sstevel@tonic-gate if (rw == KSTAT_WRITE) { 6323*0Sstevel@tonic-gate return (EACCES); 6324*0Sstevel@tonic-gate } 6325*0Sstevel@tonic-gate 6326*0Sstevel@tonic-gate pp = (struct ecppunit *)ksp->ks_private; 6327*0Sstevel@tonic-gate ekp = (struct ecppkstat *)ksp->ks_data; 6328*0Sstevel@tonic-gate 6329*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 6330*0Sstevel@tonic-gate 6331*0Sstevel@tonic-gate ekp->ek_ctx_obytes.value.ui32 = pp->obytes[ECPP_CENTRONICS] + 6332*0Sstevel@tonic-gate pp->obytes[ECPP_COMPAT_MODE]; 6333*0Sstevel@tonic-gate ekp->ek_ctxpio_obytes.value.ui32 = pp->ctxpio_obytes; 6334*0Sstevel@tonic-gate ekp->ek_nib_ibytes.value.ui32 = pp->ibytes[ECPP_NIBBLE_MODE]; 6335*0Sstevel@tonic-gate ekp->ek_ecp_obytes.value.ui32 = pp->obytes[ECPP_ECP_MODE]; 6336*0Sstevel@tonic-gate ekp->ek_ecp_ibytes.value.ui32 = pp->ibytes[ECPP_ECP_MODE]; 6337*0Sstevel@tonic-gate ekp->ek_epp_obytes.value.ui32 = pp->obytes[ECPP_EPP_MODE]; 6338*0Sstevel@tonic-gate ekp->ek_epp_ibytes.value.ui32 = pp->ibytes[ECPP_EPP_MODE]; 6339*0Sstevel@tonic-gate ekp->ek_diag_obytes.value.ui32 = pp->obytes[ECPP_DIAG_MODE]; 6340*0Sstevel@tonic-gate ekp->ek_to_ctx.value.ui32 = pp->to_mode[ECPP_CENTRONICS] + 6341*0Sstevel@tonic-gate pp->to_mode[ECPP_COMPAT_MODE]; 6342*0Sstevel@tonic-gate ekp->ek_to_nib.value.ui32 = pp->to_mode[ECPP_NIBBLE_MODE]; 6343*0Sstevel@tonic-gate ekp->ek_to_ecp.value.ui32 = pp->to_mode[ECPP_ECP_MODE]; 6344*0Sstevel@tonic-gate ekp->ek_to_epp.value.ui32 = pp->to_mode[ECPP_EPP_MODE]; 6345*0Sstevel@tonic-gate ekp->ek_to_diag.value.ui32 = pp->to_mode[ECPP_DIAG_MODE]; 6346*0Sstevel@tonic-gate ekp->ek_xfer_tout.value.ui32 = pp->xfer_tout; 6347*0Sstevel@tonic-gate ekp->ek_ctx_cf.value.ui32 = pp->ctx_cf; 6348*0Sstevel@tonic-gate ekp->ek_joblen.value.ui32 = pp->joblen; 6349*0Sstevel@tonic-gate ekp->ek_isr_reattempt_high.value.ui32 = pp->isr_reattempt_high; 6350*0Sstevel@tonic-gate ekp->ek_mode.value.ui32 = pp->current_mode; 6351*0Sstevel@tonic-gate ekp->ek_phase.value.ui32 = pp->current_phase; 6352*0Sstevel@tonic-gate ekp->ek_backchan.value.ui32 = pp->backchannel; 6353*0Sstevel@tonic-gate ekp->ek_iomode.value.ui32 = pp->io_mode; 6354*0Sstevel@tonic-gate ekp->ek_state.value.ui32 = pp->e_busy; 6355*0Sstevel@tonic-gate 6356*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 6357*0Sstevel@tonic-gate 6358*0Sstevel@tonic-gate return (0); 6359*0Sstevel@tonic-gate } 6360*0Sstevel@tonic-gate 6361*0Sstevel@tonic-gate static int 6362*0Sstevel@tonic-gate ecpp_kstatintr_update(kstat_t *ksp, int rw) 6363*0Sstevel@tonic-gate { 6364*0Sstevel@tonic-gate struct ecppunit *pp; 6365*0Sstevel@tonic-gate 6366*0Sstevel@tonic-gate /* 6367*0Sstevel@tonic-gate * For the time being there is no point 6368*0Sstevel@tonic-gate * in supporting writable kstats 6369*0Sstevel@tonic-gate */ 6370*0Sstevel@tonic-gate if (rw == KSTAT_WRITE) { 6371*0Sstevel@tonic-gate return (EACCES); 6372*0Sstevel@tonic-gate } 6373*0Sstevel@tonic-gate 6374*0Sstevel@tonic-gate pp = (struct ecppunit *)ksp->ks_private; 6375*0Sstevel@tonic-gate 6376*0Sstevel@tonic-gate mutex_enter(&pp->umutex); 6377*0Sstevel@tonic-gate 6378*0Sstevel@tonic-gate KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_HARD] = pp->intr_hard; 6379*0Sstevel@tonic-gate KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SPURIOUS] = pp->intr_spurious; 6380*0Sstevel@tonic-gate KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SOFT] = pp->intr_soft; 6381*0Sstevel@tonic-gate 6382*0Sstevel@tonic-gate mutex_exit(&pp->umutex); 6383*0Sstevel@tonic-gate 6384*0Sstevel@tonic-gate return (0); 6385*0Sstevel@tonic-gate } 6386