1*3526Sxy150489 /* 2*3526Sxy150489 * This file is provided under a CDDLv1 license. When using or 3*3526Sxy150489 * redistributing this file, you may do so under this license. 4*3526Sxy150489 * In redistributing this file this license must be included 5*3526Sxy150489 * and no other modification of this header file is permitted. 6*3526Sxy150489 * 7*3526Sxy150489 * CDDL LICENSE SUMMARY 8*3526Sxy150489 * 9*3526Sxy150489 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10*3526Sxy150489 * 11*3526Sxy150489 * The contents of this file are subject to the terms of Version 12*3526Sxy150489 * 1.0 of the Common Development and Distribution License (the "License"). 13*3526Sxy150489 * 14*3526Sxy150489 * You should have received a copy of the License with this software. 15*3526Sxy150489 * You can obtain a copy of the License at 16*3526Sxy150489 * http://www.opensolaris.org/os/licensing. 17*3526Sxy150489 * See the License for the specific language governing permissions 18*3526Sxy150489 * and limitations under the License. 19*3526Sxy150489 */ 20*3526Sxy150489 21*3526Sxy150489 /* 22*3526Sxy150489 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23*3526Sxy150489 * Use is subject to license terms of the CDDLv1. 24*3526Sxy150489 */ 25*3526Sxy150489 26*3526Sxy150489 #pragma ident "%Z%%M% %I% %E% SMI" 27*3526Sxy150489 28*3526Sxy150489 /* 29*3526Sxy150489 * ********************************************************************** 30*3526Sxy150489 * * 31*3526Sxy150489 * Module Name: * 32*3526Sxy150489 * e1000g_tx.c * 33*3526Sxy150489 * * 34*3526Sxy150489 * Abstract: * 35*3526Sxy150489 * This file contains some routines that takes care of Transmit * 36*3526Sxy150489 * interrupt and also makes the hardware to send the data pointed * 37*3526Sxy150489 * by the packet out on to the physical medium. * 38*3526Sxy150489 * * 39*3526Sxy150489 * * 40*3526Sxy150489 * Environment: * 41*3526Sxy150489 * Kernel Mode - * 42*3526Sxy150489 * * 43*3526Sxy150489 * Source History: * 44*3526Sxy150489 * The code in this file is based somewhat on the "send" code * 45*3526Sxy150489 * developed for the Intel Pro/100 family(Speedo1 and Speedo3) by * 46*3526Sxy150489 * Steve Lindsay, and partly on some sample DDK code * 47*3526Sxy150489 * of solaris. * 48*3526Sxy150489 * * 49*3526Sxy150489 * March 12, 1997 Steve Lindsay * 50*3526Sxy150489 * 1st created - Ported from E100B send.c file * 51*3526Sxy150489 * * 52*3526Sxy150489 * ********************************************************************** 53*3526Sxy150489 */ 54*3526Sxy150489 55*3526Sxy150489 #include "e1000g_sw.h" 56*3526Sxy150489 #include "e1000g_debug.h" 57*3526Sxy150489 58*3526Sxy150489 static boolean_t e1000g_send(struct e1000g *, mblk_t *); 59*3526Sxy150489 static int e1000g_tx_copy(struct e1000g *, PTX_SW_PACKET, mblk_t *, uint32_t); 60*3526Sxy150489 static int e1000g_tx_bind(struct e1000g *, PTX_SW_PACKET, mblk_t *); 61*3526Sxy150489 static int e1000g_fill_tx_ring(e1000g_tx_ring_t *, LIST_DESCRIBER *, 62*3526Sxy150489 uint_t, boolean_t); 63*3526Sxy150489 static void e1000g_fill_context_descriptor(e1000g_tx_ring_t *, 64*3526Sxy150489 struct e1000_context_desc *); 65*3526Sxy150489 static int e1000g_fill_tx_desc(struct e1000g *, 66*3526Sxy150489 PTX_SW_PACKET, uint64_t, size_t); 67*3526Sxy150489 static uint32_t e1000g_fill_82544_desc(uint64_t Address, size_t Length, 68*3526Sxy150489 PDESC_ARRAY desc_array); 69*3526Sxy150489 static int e1000g_tx_workaround_PCIX_82544(struct e1000g *, 70*3526Sxy150489 PTX_SW_PACKET, uint64_t, size_t); 71*3526Sxy150489 static int e1000g_tx_workaround_jumbo_82544(struct e1000g *, 72*3526Sxy150489 PTX_SW_PACKET, uint64_t, size_t); 73*3526Sxy150489 static uint32_t e1000g_tx_free_desc_num(e1000g_tx_ring_t *); 74*3526Sxy150489 static void e1000g_82547_timeout(void *); 75*3526Sxy150489 static void e1000g_82547_tx_move_tail(e1000g_tx_ring_t *); 76*3526Sxy150489 static void e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *); 77*3526Sxy150489 78*3526Sxy150489 #ifndef e1000g_DEBUG 79*3526Sxy150489 #pragma inline(e1000g_tx_copy) 80*3526Sxy150489 #pragma inline(e1000g_tx_bind) 81*3526Sxy150489 #pragma inline(e1000g_fill_tx_ring) 82*3526Sxy150489 #pragma inline(e1000g_fill_context_descriptor) 83*3526Sxy150489 #pragma inline(e1000g_fill_tx_desc) 84*3526Sxy150489 #pragma inline(e1000g_fill_82544_desc) 85*3526Sxy150489 #pragma inline(e1000g_tx_workaround_PCIX_82544) 86*3526Sxy150489 #pragma inline(e1000g_tx_workaround_jumbo_82544) 87*3526Sxy150489 #pragma inline(FreeTxSwPacket) 88*3526Sxy150489 #pragma inline(e1000g_tx_free_desc_num) 89*3526Sxy150489 #endif 90*3526Sxy150489 91*3526Sxy150489 /* 92*3526Sxy150489 * ********************************************************************** 93*3526Sxy150489 * Name: FreeTxSwPacket * 94*3526Sxy150489 * * 95*3526Sxy150489 * Description: * 96*3526Sxy150489 * Frees up the previusly allocated Dma handle for given * 97*3526Sxy150489 * transmit sw packet. * 98*3526Sxy150489 * * 99*3526Sxy150489 * Parameter Passed: * 100*3526Sxy150489 * * 101*3526Sxy150489 * Return Value: * 102*3526Sxy150489 * * 103*3526Sxy150489 * Functions called: * 104*3526Sxy150489 * * 105*3526Sxy150489 * ********************************************************************** 106*3526Sxy150489 */ 107*3526Sxy150489 void 108*3526Sxy150489 FreeTxSwPacket(register PTX_SW_PACKET packet) 109*3526Sxy150489 { 110*3526Sxy150489 switch (packet->data_transfer_type) { 111*3526Sxy150489 case USE_BCOPY: 112*3526Sxy150489 packet->tx_buf->len = 0; 113*3526Sxy150489 break; 114*3526Sxy150489 #ifdef __sparc 115*3526Sxy150489 case USE_DVMA: 116*3526Sxy150489 dvma_unload(packet->tx_dma_handle, 0, -1); 117*3526Sxy150489 break; 118*3526Sxy150489 #endif 119*3526Sxy150489 case USE_DMA: 120*3526Sxy150489 ddi_dma_unbind_handle(packet->tx_dma_handle); 121*3526Sxy150489 break; 122*3526Sxy150489 default: 123*3526Sxy150489 break; 124*3526Sxy150489 } 125*3526Sxy150489 126*3526Sxy150489 /* 127*3526Sxy150489 * The mblk has been stripped off the sw packet 128*3526Sxy150489 * and will be freed in a triggered soft intr. 129*3526Sxy150489 */ 130*3526Sxy150489 ASSERT(packet->mp == NULL); 131*3526Sxy150489 132*3526Sxy150489 packet->data_transfer_type = USE_NONE; 133*3526Sxy150489 packet->num_mblk_frag = 0; 134*3526Sxy150489 packet->num_desc = 0; 135*3526Sxy150489 } 136*3526Sxy150489 137*3526Sxy150489 uint_t 138*3526Sxy150489 e1000g_tx_freemsg(caddr_t arg1, caddr_t arg2) 139*3526Sxy150489 { 140*3526Sxy150489 struct e1000g *Adapter; 141*3526Sxy150489 mblk_t *mp; 142*3526Sxy150489 143*3526Sxy150489 Adapter = (struct e1000g *)arg1; 144*3526Sxy150489 145*3526Sxy150489 if ((Adapter == NULL) || (arg2 != NULL)) 146*3526Sxy150489 return (DDI_INTR_UNCLAIMED); 147*3526Sxy150489 148*3526Sxy150489 if (!mutex_tryenter(&Adapter->tx_msg_chain->lock)) 149*3526Sxy150489 return (DDI_INTR_CLAIMED); 150*3526Sxy150489 151*3526Sxy150489 mp = Adapter->tx_msg_chain->head; 152*3526Sxy150489 Adapter->tx_msg_chain->head = NULL; 153*3526Sxy150489 Adapter->tx_msg_chain->tail = NULL; 154*3526Sxy150489 155*3526Sxy150489 mutex_exit(&Adapter->tx_msg_chain->lock); 156*3526Sxy150489 157*3526Sxy150489 freemsgchain(mp); 158*3526Sxy150489 159*3526Sxy150489 return (DDI_INTR_CLAIMED); 160*3526Sxy150489 } 161*3526Sxy150489 162*3526Sxy150489 static uint32_t 163*3526Sxy150489 e1000g_tx_free_desc_num(e1000g_tx_ring_t *tx_ring) 164*3526Sxy150489 { 165*3526Sxy150489 struct e1000g *Adapter; 166*3526Sxy150489 int num; 167*3526Sxy150489 168*3526Sxy150489 Adapter = tx_ring->adapter; 169*3526Sxy150489 170*3526Sxy150489 num = tx_ring->tbd_oldest - tx_ring->tbd_next; 171*3526Sxy150489 if (num <= 0) 172*3526Sxy150489 num += Adapter->NumTxDescriptors; 173*3526Sxy150489 174*3526Sxy150489 return (num); 175*3526Sxy150489 } 176*3526Sxy150489 177*3526Sxy150489 mblk_t * 178*3526Sxy150489 e1000g_m_tx(void *arg, mblk_t *mp) 179*3526Sxy150489 { 180*3526Sxy150489 struct e1000g *Adapter = (struct e1000g *)arg; 181*3526Sxy150489 mblk_t *next; 182*3526Sxy150489 183*3526Sxy150489 rw_enter(&Adapter->chip_lock, RW_READER); 184*3526Sxy150489 185*3526Sxy150489 if (!Adapter->started) { 186*3526Sxy150489 freemsgchain(mp); 187*3526Sxy150489 mp = NULL; 188*3526Sxy150489 } 189*3526Sxy150489 190*3526Sxy150489 while (mp != NULL) { 191*3526Sxy150489 next = mp->b_next; 192*3526Sxy150489 mp->b_next = NULL; 193*3526Sxy150489 194*3526Sxy150489 if (!e1000g_send(Adapter, mp)) { 195*3526Sxy150489 mp->b_next = next; 196*3526Sxy150489 break; 197*3526Sxy150489 } 198*3526Sxy150489 199*3526Sxy150489 mp = next; 200*3526Sxy150489 } 201*3526Sxy150489 202*3526Sxy150489 rw_exit(&Adapter->chip_lock); 203*3526Sxy150489 return (mp); 204*3526Sxy150489 } 205*3526Sxy150489 206*3526Sxy150489 /* 207*3526Sxy150489 * ********************************************************************** 208*3526Sxy150489 * Name: e1000g_send * 209*3526Sxy150489 * * 210*3526Sxy150489 * Description: * 211*3526Sxy150489 * Called from e1000g_m_tx with an mp ready to send. this * 212*3526Sxy150489 * routine sets up the transmit descriptors and sends to * 213*3526Sxy150489 * the wire. It also pushes the just transmitted packet to * 214*3526Sxy150489 * the used tx sw packet list * 215*3526Sxy150489 * * 216*3526Sxy150489 * Arguments: * 217*3526Sxy150489 * Pointer to the mblk to be sent, pointer to this adapter * 218*3526Sxy150489 * * 219*3526Sxy150489 * Returns: * 220*3526Sxy150489 * B_TRUE, B_FALSE * 221*3526Sxy150489 * * 222*3526Sxy150489 * Modification log: * 223*3526Sxy150489 * Date Who Description * 224*3526Sxy150489 * -------- --- ----------------------------------------------------- * 225*3526Sxy150489 * ********************************************************************** 226*3526Sxy150489 */ 227*3526Sxy150489 static boolean_t 228*3526Sxy150489 e1000g_send(struct e1000g *Adapter, mblk_t *mp) 229*3526Sxy150489 { 230*3526Sxy150489 PTX_SW_PACKET packet; 231*3526Sxy150489 LIST_DESCRIBER pending_list; 232*3526Sxy150489 size_t len; 233*3526Sxy150489 size_t msg_size; 234*3526Sxy150489 uint32_t frag_count; 235*3526Sxy150489 int desc_count; 236*3526Sxy150489 uint32_t desc_total; 237*3526Sxy150489 uint32_t force_bcopy; 238*3526Sxy150489 mblk_t *nmp; 239*3526Sxy150489 mblk_t *tmp; 240*3526Sxy150489 e1000g_tx_ring_t *tx_ring; 241*3526Sxy150489 /* IP Head/TCP/UDP checksum offload */ 242*3526Sxy150489 uint_t cksum_start; 243*3526Sxy150489 uint_t cksum_stuff; 244*3526Sxy150489 uint_t cksum_flags; 245*3526Sxy150489 boolean_t cksum_load; 246*3526Sxy150489 uint8_t ether_header_size; 247*3526Sxy150489 248*3526Sxy150489 /* Get the total size and frags number of the message */ 249*3526Sxy150489 force_bcopy = 0; 250*3526Sxy150489 frag_count = 0; 251*3526Sxy150489 msg_size = 0; 252*3526Sxy150489 for (nmp = mp; nmp; nmp = nmp->b_cont) { 253*3526Sxy150489 frag_count++; 254*3526Sxy150489 msg_size += MBLKL(nmp); 255*3526Sxy150489 } 256*3526Sxy150489 257*3526Sxy150489 /* Empty packet */ 258*3526Sxy150489 if (msg_size == 0) { 259*3526Sxy150489 freemsg(mp); 260*3526Sxy150489 return (B_TRUE); 261*3526Sxy150489 } 262*3526Sxy150489 263*3526Sxy150489 /* Make sure packet is less than the max frame size */ 264*3526Sxy150489 if (msg_size > Adapter->Shared.max_frame_size + VLAN_TAGSZ) { 265*3526Sxy150489 /* 266*3526Sxy150489 * For the over size packet, we'll just drop it. 267*3526Sxy150489 * So we return B_TRUE here. 268*3526Sxy150489 */ 269*3526Sxy150489 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 270*3526Sxy150489 "Tx packet out of bound. length = %d \n", msg_size); 271*3526Sxy150489 freemsg(mp); 272*3526Sxy150489 Adapter->tx_over_size++; 273*3526Sxy150489 return (B_TRUE); 274*3526Sxy150489 } 275*3526Sxy150489 276*3526Sxy150489 tx_ring = Adapter->tx_ring; 277*3526Sxy150489 278*3526Sxy150489 /* 279*3526Sxy150489 * Check and reclaim tx descriptors. 280*3526Sxy150489 * This low water mark check should be done all the time as 281*3526Sxy150489 * Transmit interrupt delay can produce Transmit interrupts little 282*3526Sxy150489 * late and that may cause few problems related to reaping Tx 283*3526Sxy150489 * Descriptors... As you may run short of them before getting any 284*3526Sxy150489 * transmit interrupt... 285*3526Sxy150489 */ 286*3526Sxy150489 if ((Adapter->NumTxDescriptors - e1000g_tx_free_desc_num(tx_ring)) > 287*3526Sxy150489 Adapter->tx_recycle_low_water) { 288*3526Sxy150489 if (Adapter->Shared.mac_type == e1000_82547) { 289*3526Sxy150489 mutex_enter(&tx_ring->tx_lock); 290*3526Sxy150489 e1000g_82547_tx_move_tail(tx_ring); 291*3526Sxy150489 mutex_exit(&tx_ring->tx_lock); 292*3526Sxy150489 } 293*3526Sxy150489 Adapter->tx_recycle++; 294*3526Sxy150489 (void) e1000g_recycle(tx_ring); 295*3526Sxy150489 } 296*3526Sxy150489 297*3526Sxy150489 if (e1000g_tx_free_desc_num(tx_ring) < MAX_TX_DESC_PER_PACKET) { 298*3526Sxy150489 Adapter->tx_lack_desc++; 299*3526Sxy150489 goto tx_no_resource; 300*3526Sxy150489 } 301*3526Sxy150489 302*3526Sxy150489 /* 303*3526Sxy150489 * If there are many frags of the message, then bcopy them 304*3526Sxy150489 * into one tx descriptor buffer will get better performance. 305*3526Sxy150489 */ 306*3526Sxy150489 if (frag_count >= Adapter->tx_frags_limit) { 307*3526Sxy150489 Adapter->tx_exceed_frags++; 308*3526Sxy150489 force_bcopy |= FORCE_BCOPY_EXCEED_FRAGS; 309*3526Sxy150489 } 310*3526Sxy150489 311*3526Sxy150489 /* 312*3526Sxy150489 * If the message size is less than the minimum ethernet packet size, 313*3526Sxy150489 * we'll use bcopy to send it, and padd it to 60 bytes later. 314*3526Sxy150489 */ 315*3526Sxy150489 if (msg_size < MINIMUM_ETHERNET_PACKET_SIZE) { 316*3526Sxy150489 Adapter->tx_under_size++; 317*3526Sxy150489 force_bcopy |= FORCE_BCOPY_UNDER_SIZE; 318*3526Sxy150489 } 319*3526Sxy150489 320*3526Sxy150489 /* Initialize variables */ 321*3526Sxy150489 desc_count = 1; /* The initial value should be greater than 0 */ 322*3526Sxy150489 desc_total = 0; 323*3526Sxy150489 QUEUE_INIT_LIST(&pending_list); 324*3526Sxy150489 325*3526Sxy150489 /* Retrieve checksum info */ 326*3526Sxy150489 hcksum_retrieve(mp, NULL, NULL, &cksum_start, &cksum_stuff, 327*3526Sxy150489 NULL, NULL, &cksum_flags); 328*3526Sxy150489 329*3526Sxy150489 cksum_load = B_FALSE; 330*3526Sxy150489 if (cksum_flags) { 331*3526Sxy150489 if (((struct ether_vlan_header *)mp->b_rptr)->ether_tpid == 332*3526Sxy150489 htons(ETHERTYPE_VLAN)) 333*3526Sxy150489 ether_header_size = sizeof (struct ether_vlan_header); 334*3526Sxy150489 else 335*3526Sxy150489 ether_header_size = sizeof (struct ether_header); 336*3526Sxy150489 337*3526Sxy150489 if ((ether_header_size != tx_ring->ether_header_size) || 338*3526Sxy150489 (cksum_flags != tx_ring->cksum_flags) || 339*3526Sxy150489 (cksum_stuff != tx_ring->cksum_stuff) || 340*3526Sxy150489 (cksum_start != tx_ring->cksum_start)) { 341*3526Sxy150489 342*3526Sxy150489 tx_ring->ether_header_size = ether_header_size; 343*3526Sxy150489 tx_ring->cksum_flags = cksum_flags; 344*3526Sxy150489 tx_ring->cksum_start = cksum_start; 345*3526Sxy150489 tx_ring->cksum_stuff = cksum_stuff; 346*3526Sxy150489 347*3526Sxy150489 cksum_load = B_TRUE; 348*3526Sxy150489 } 349*3526Sxy150489 } 350*3526Sxy150489 351*3526Sxy150489 /* Process each mblk fragment and fill tx descriptors */ 352*3526Sxy150489 packet = NULL; 353*3526Sxy150489 nmp = mp; 354*3526Sxy150489 while (nmp) { 355*3526Sxy150489 tmp = nmp->b_cont; 356*3526Sxy150489 357*3526Sxy150489 len = MBLKL(nmp); 358*3526Sxy150489 /* Check zero length mblks */ 359*3526Sxy150489 if (len == 0) { 360*3526Sxy150489 Adapter->tx_empty_frags++; 361*3526Sxy150489 /* 362*3526Sxy150489 * If there're no packet buffers have been used, 363*3526Sxy150489 * or we just completed processing a buffer, then 364*3526Sxy150489 * skip the empty mblk fragment. 365*3526Sxy150489 * Otherwise, there's still a pending buffer that 366*3526Sxy150489 * needs to be processed (tx_copy). 367*3526Sxy150489 */ 368*3526Sxy150489 if (desc_count > 0) { 369*3526Sxy150489 nmp = tmp; 370*3526Sxy150489 continue; 371*3526Sxy150489 } 372*3526Sxy150489 } 373*3526Sxy150489 374*3526Sxy150489 /* 375*3526Sxy150489 * Get a new TxSwPacket to process mblk buffers. 376*3526Sxy150489 */ 377*3526Sxy150489 if (desc_count > 0) { 378*3526Sxy150489 379*3526Sxy150489 mutex_enter(&tx_ring->freelist_lock); 380*3526Sxy150489 packet = (PTX_SW_PACKET) 381*3526Sxy150489 QUEUE_POP_HEAD(&tx_ring->free_list); 382*3526Sxy150489 mutex_exit(&tx_ring->freelist_lock); 383*3526Sxy150489 384*3526Sxy150489 if (packet == NULL) { 385*3526Sxy150489 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 386*3526Sxy150489 "No Tx SwPacket available\n"); 387*3526Sxy150489 Adapter->tx_no_swpkt++; 388*3526Sxy150489 goto tx_send_failed; 389*3526Sxy150489 } 390*3526Sxy150489 QUEUE_PUSH_TAIL(&pending_list, &packet->Link); 391*3526Sxy150489 } 392*3526Sxy150489 393*3526Sxy150489 ASSERT(packet); 394*3526Sxy150489 /* 395*3526Sxy150489 * If the size of the fragment is less than the tx_bcopy_thresh 396*3526Sxy150489 * we'll use bcopy; Otherwise, we'll use DMA binding. 397*3526Sxy150489 */ 398*3526Sxy150489 if ((len <= Adapter->tx_bcopy_thresh) || force_bcopy) { 399*3526Sxy150489 desc_count = 400*3526Sxy150489 e1000g_tx_copy(Adapter, packet, nmp, force_bcopy); 401*3526Sxy150489 Adapter->tx_copy++; 402*3526Sxy150489 } else { 403*3526Sxy150489 desc_count = 404*3526Sxy150489 e1000g_tx_bind(Adapter, packet, nmp); 405*3526Sxy150489 Adapter->tx_bind++; 406*3526Sxy150489 } 407*3526Sxy150489 408*3526Sxy150489 if (desc_count < 0) 409*3526Sxy150489 goto tx_send_failed; 410*3526Sxy150489 411*3526Sxy150489 if (desc_count > 0) 412*3526Sxy150489 desc_total += desc_count; 413*3526Sxy150489 414*3526Sxy150489 nmp = tmp; 415*3526Sxy150489 } 416*3526Sxy150489 417*3526Sxy150489 /* Assign the message to the last sw packet */ 418*3526Sxy150489 ASSERT(packet); 419*3526Sxy150489 ASSERT(packet->mp == NULL); 420*3526Sxy150489 packet->mp = mp; 421*3526Sxy150489 422*3526Sxy150489 /* Try to recycle the tx descriptors again */ 423*3526Sxy150489 if (e1000g_tx_free_desc_num(tx_ring) < MAX_TX_DESC_PER_PACKET) { 424*3526Sxy150489 Adapter->tx_recycle_retry++; 425*3526Sxy150489 (void) e1000g_recycle(tx_ring); 426*3526Sxy150489 } 427*3526Sxy150489 428*3526Sxy150489 mutex_enter(&tx_ring->tx_lock); 429*3526Sxy150489 430*3526Sxy150489 /* 431*3526Sxy150489 * If the number of available tx descriptors is not enough for transmit 432*3526Sxy150489 * (one redundant descriptor and one hw checksum context descriptor are 433*3526Sxy150489 * included), then return failure. 434*3526Sxy150489 */ 435*3526Sxy150489 if (e1000g_tx_free_desc_num(tx_ring) < (desc_total + 2)) { 436*3526Sxy150489 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 437*3526Sxy150489 "No Enough Tx descriptors\n"); 438*3526Sxy150489 Adapter->tx_no_desc++; 439*3526Sxy150489 mutex_exit(&tx_ring->tx_lock); 440*3526Sxy150489 goto tx_send_failed; 441*3526Sxy150489 } 442*3526Sxy150489 443*3526Sxy150489 desc_count = e1000g_fill_tx_ring(tx_ring, &pending_list, 444*3526Sxy150489 cksum_flags, cksum_load); 445*3526Sxy150489 446*3526Sxy150489 mutex_exit(&tx_ring->tx_lock); 447*3526Sxy150489 448*3526Sxy150489 ASSERT(desc_count > 0); 449*3526Sxy150489 450*3526Sxy150489 /* Update statistic counters */ 451*3526Sxy150489 if (Adapter->ProfileJumboTraffic) { 452*3526Sxy150489 if ((msg_size > ETHERMAX) && 453*3526Sxy150489 (msg_size <= FRAME_SIZE_UPTO_4K)) 454*3526Sxy150489 Adapter->JumboTx_4K++; 455*3526Sxy150489 456*3526Sxy150489 if ((msg_size > FRAME_SIZE_UPTO_4K) && 457*3526Sxy150489 (msg_size <= FRAME_SIZE_UPTO_8K)) 458*3526Sxy150489 Adapter->JumboTx_8K++; 459*3526Sxy150489 460*3526Sxy150489 if ((msg_size > FRAME_SIZE_UPTO_8K) && 461*3526Sxy150489 (msg_size <= FRAME_SIZE_UPTO_16K)) 462*3526Sxy150489 Adapter->JumboTx_16K++; 463*3526Sxy150489 } 464*3526Sxy150489 465*3526Sxy150489 /* Send successful */ 466*3526Sxy150489 return (B_TRUE); 467*3526Sxy150489 468*3526Sxy150489 tx_send_failed: 469*3526Sxy150489 /* Free pending TxSwPackets */ 470*3526Sxy150489 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&pending_list); 471*3526Sxy150489 while (packet) { 472*3526Sxy150489 packet->mp = NULL; 473*3526Sxy150489 FreeTxSwPacket(packet); 474*3526Sxy150489 packet = (PTX_SW_PACKET) 475*3526Sxy150489 QUEUE_GET_NEXT(&pending_list, &packet->Link); 476*3526Sxy150489 } 477*3526Sxy150489 478*3526Sxy150489 /* Return pending TxSwPackets to the "Free" list */ 479*3526Sxy150489 mutex_enter(&tx_ring->freelist_lock); 480*3526Sxy150489 QUEUE_APPEND(&tx_ring->free_list, &pending_list); 481*3526Sxy150489 mutex_exit(&tx_ring->freelist_lock); 482*3526Sxy150489 483*3526Sxy150489 Adapter->tx_send_fail++; 484*3526Sxy150489 485*3526Sxy150489 freemsg(mp); 486*3526Sxy150489 487*3526Sxy150489 /* Send failed, message dropped */ 488*3526Sxy150489 return (B_TRUE); 489*3526Sxy150489 490*3526Sxy150489 tx_no_resource: 491*3526Sxy150489 /* 492*3526Sxy150489 * Enable Transmit interrupts, so that the interrupt routine can 493*3526Sxy150489 * call mac_tx_update() when transmit descriptors become available. 494*3526Sxy150489 */ 495*3526Sxy150489 Adapter->resched_needed = B_TRUE; 496*3526Sxy150489 if (!Adapter->tx_intr_enable) 497*3526Sxy150489 e1000g_EnableTxInterrupt(Adapter); 498*3526Sxy150489 499*3526Sxy150489 /* Message will be scheduled for re-transmit */ 500*3526Sxy150489 return (B_FALSE); 501*3526Sxy150489 } 502*3526Sxy150489 503*3526Sxy150489 static int 504*3526Sxy150489 e1000g_fill_tx_ring(e1000g_tx_ring_t *tx_ring, LIST_DESCRIBER *pending_list, 505*3526Sxy150489 uint_t cksum_flags, boolean_t cksum_load) 506*3526Sxy150489 { 507*3526Sxy150489 struct e1000g *Adapter; 508*3526Sxy150489 PTX_SW_PACKET first_packet; 509*3526Sxy150489 PTX_SW_PACKET packet; 510*3526Sxy150489 struct e1000_context_desc *cksum_desc; 511*3526Sxy150489 struct e1000_tx_desc *first_data_desc; 512*3526Sxy150489 struct e1000_tx_desc *next_desc; 513*3526Sxy150489 struct e1000_tx_desc *descriptor; 514*3526Sxy150489 uint32_t sync_offset; 515*3526Sxy150489 int sync_len; 516*3526Sxy150489 int desc_count; 517*3526Sxy150489 int i; 518*3526Sxy150489 519*3526Sxy150489 Adapter = tx_ring->adapter; 520*3526Sxy150489 521*3526Sxy150489 desc_count = 0; 522*3526Sxy150489 cksum_desc = NULL; 523*3526Sxy150489 first_data_desc = NULL; 524*3526Sxy150489 descriptor = NULL; 525*3526Sxy150489 526*3526Sxy150489 first_packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(pending_list); 527*3526Sxy150489 ASSERT(first_packet); 528*3526Sxy150489 529*3526Sxy150489 next_desc = tx_ring->tbd_next; 530*3526Sxy150489 531*3526Sxy150489 /* IP Head/TCP/UDP checksum offload */ 532*3526Sxy150489 if (cksum_load) { 533*3526Sxy150489 descriptor = next_desc; 534*3526Sxy150489 535*3526Sxy150489 cksum_desc = (struct e1000_context_desc *)descriptor; 536*3526Sxy150489 537*3526Sxy150489 e1000g_fill_context_descriptor(tx_ring, cksum_desc); 538*3526Sxy150489 539*3526Sxy150489 /* Check the wrap-around case */ 540*3526Sxy150489 if (descriptor == tx_ring->tbd_last) 541*3526Sxy150489 next_desc = tx_ring->tbd_first; 542*3526Sxy150489 else 543*3526Sxy150489 next_desc++; 544*3526Sxy150489 545*3526Sxy150489 desc_count++; 546*3526Sxy150489 } 547*3526Sxy150489 548*3526Sxy150489 if (cksum_desc == NULL) 549*3526Sxy150489 first_packet = NULL; 550*3526Sxy150489 551*3526Sxy150489 first_data_desc = next_desc; 552*3526Sxy150489 553*3526Sxy150489 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(pending_list); 554*3526Sxy150489 while (packet) { 555*3526Sxy150489 ASSERT(packet->num_desc); 556*3526Sxy150489 557*3526Sxy150489 for (i = 0; i < packet->num_desc; i++) { 558*3526Sxy150489 ASSERT(e1000g_tx_free_desc_num(tx_ring) > 0); 559*3526Sxy150489 560*3526Sxy150489 descriptor = next_desc; 561*3526Sxy150489 #ifdef __sparc 562*3526Sxy150489 descriptor->buffer_addr = 563*3526Sxy150489 DWORD_SWAP(packet->desc[i].Address); 564*3526Sxy150489 #else 565*3526Sxy150489 descriptor->buffer_addr = 566*3526Sxy150489 packet->desc[i].Address; 567*3526Sxy150489 #endif 568*3526Sxy150489 descriptor->lower.data = 569*3526Sxy150489 packet->desc[i].Length; 570*3526Sxy150489 571*3526Sxy150489 /* Zero out status */ 572*3526Sxy150489 descriptor->upper.data = 0; 573*3526Sxy150489 574*3526Sxy150489 descriptor->lower.data |= 575*3526Sxy150489 E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 576*3526Sxy150489 /* must set RS on every outgoing descriptor */ 577*3526Sxy150489 descriptor->lower.data |= 578*3526Sxy150489 E1000_TXD_CMD_RS; 579*3526Sxy150489 580*3526Sxy150489 /* Check the wrap-around case */ 581*3526Sxy150489 if (descriptor == tx_ring->tbd_last) 582*3526Sxy150489 next_desc = tx_ring->tbd_first; 583*3526Sxy150489 else 584*3526Sxy150489 next_desc++; 585*3526Sxy150489 586*3526Sxy150489 desc_count++; 587*3526Sxy150489 } 588*3526Sxy150489 589*3526Sxy150489 if (first_packet != NULL) { 590*3526Sxy150489 /* 591*3526Sxy150489 * Count the checksum context descriptor for 592*3526Sxy150489 * the first SwPacket. 593*3526Sxy150489 */ 594*3526Sxy150489 first_packet->num_desc++; 595*3526Sxy150489 first_packet = NULL; 596*3526Sxy150489 } 597*3526Sxy150489 598*3526Sxy150489 packet = (PTX_SW_PACKET) 599*3526Sxy150489 QUEUE_GET_NEXT(pending_list, &packet->Link); 600*3526Sxy150489 } 601*3526Sxy150489 602*3526Sxy150489 ASSERT(descriptor); 603*3526Sxy150489 604*3526Sxy150489 if (cksum_flags) { 605*3526Sxy150489 if (cksum_flags & HCK_IPV4_HDRCKSUM) 606*3526Sxy150489 ((struct e1000_data_desc *)first_data_desc)-> 607*3526Sxy150489 upper.fields.popts |= E1000_TXD_POPTS_IXSM; 608*3526Sxy150489 if (cksum_flags & HCK_PARTIALCKSUM) 609*3526Sxy150489 ((struct e1000_data_desc *)first_data_desc)-> 610*3526Sxy150489 upper.fields.popts |= E1000_TXD_POPTS_TXSM; 611*3526Sxy150489 } 612*3526Sxy150489 613*3526Sxy150489 /* 614*3526Sxy150489 * Last Descriptor of Packet needs End Of Packet (EOP), Report 615*3526Sxy150489 * Status (RS) and append Ethernet CRC (IFCS) bits set. 616*3526Sxy150489 */ 617*3526Sxy150489 if (Adapter->TxInterruptDelay) { 618*3526Sxy150489 descriptor->lower.data |= E1000_TXD_CMD_IDE | 619*3526Sxy150489 E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 620*3526Sxy150489 } else { 621*3526Sxy150489 descriptor->lower.data |= 622*3526Sxy150489 E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 623*3526Sxy150489 } 624*3526Sxy150489 625*3526Sxy150489 /* 626*3526Sxy150489 * Sync the Tx descriptors DMA buffer 627*3526Sxy150489 */ 628*3526Sxy150489 sync_offset = tx_ring->tbd_next - tx_ring->tbd_first; 629*3526Sxy150489 sync_len = descriptor - tx_ring->tbd_next + 1; 630*3526Sxy150489 /* Check the wrap-around case */ 631*3526Sxy150489 if (sync_len > 0) { 632*3526Sxy150489 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 633*3526Sxy150489 sync_offset * sizeof (struct e1000_tx_desc), 634*3526Sxy150489 sync_len * sizeof (struct e1000_tx_desc), 635*3526Sxy150489 DDI_DMA_SYNC_FORDEV); 636*3526Sxy150489 } else { 637*3526Sxy150489 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 638*3526Sxy150489 sync_offset * sizeof (struct e1000_tx_desc), 639*3526Sxy150489 0, 640*3526Sxy150489 DDI_DMA_SYNC_FORDEV); 641*3526Sxy150489 sync_len = descriptor - tx_ring->tbd_first + 1; 642*3526Sxy150489 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 643*3526Sxy150489 0, 644*3526Sxy150489 sync_len * sizeof (struct e1000_tx_desc), 645*3526Sxy150489 DDI_DMA_SYNC_FORDEV); 646*3526Sxy150489 } 647*3526Sxy150489 648*3526Sxy150489 tx_ring->tbd_next = next_desc; 649*3526Sxy150489 650*3526Sxy150489 /* 651*3526Sxy150489 * Advance the Transmit Descriptor Tail (Tdt), this tells the 652*3526Sxy150489 * FX1000 that this frame is available to transmit. 653*3526Sxy150489 */ 654*3526Sxy150489 if (Adapter->Shared.mac_type == e1000_82547) 655*3526Sxy150489 e1000g_82547_tx_move_tail(tx_ring); 656*3526Sxy150489 else 657*3526Sxy150489 E1000_WRITE_REG(&Adapter->Shared, TDT, 658*3526Sxy150489 (uint32_t)(next_desc - tx_ring->tbd_first)); 659*3526Sxy150489 660*3526Sxy150489 /* Put the pending SwPackets to the "Used" list */ 661*3526Sxy150489 mutex_enter(&tx_ring->usedlist_lock); 662*3526Sxy150489 QUEUE_APPEND(&tx_ring->used_list, pending_list); 663*3526Sxy150489 mutex_exit(&tx_ring->usedlist_lock); 664*3526Sxy150489 665*3526Sxy150489 return (desc_count); 666*3526Sxy150489 } 667*3526Sxy150489 668*3526Sxy150489 669*3526Sxy150489 /* 670*3526Sxy150489 * ********************************************************************** 671*3526Sxy150489 * Name: SetupTransmitStructures * 672*3526Sxy150489 * * 673*3526Sxy150489 * Description: This routine initializes all of the transmit related * 674*3526Sxy150489 * structures. This includes the Transmit descriptors, the * 675*3526Sxy150489 * coalesce buffers, and the TX_SW_PACKETs structures. * 676*3526Sxy150489 * * 677*3526Sxy150489 * NOTE -- The device must have been reset before this * 678*3526Sxy150489 * routine is called. * 679*3526Sxy150489 * * 680*3526Sxy150489 * Author: Hari Seshadri * 681*3526Sxy150489 * Functions Called : get_32bit_value * 682*3526Sxy150489 * * 683*3526Sxy150489 * * 684*3526Sxy150489 * * 685*3526Sxy150489 * Arguments: * 686*3526Sxy150489 * Adapter - A pointer to our context sensitive "Adapter" * 687*3526Sxy150489 * structure. * 688*3526Sxy150489 * * 689*3526Sxy150489 * Returns: * 690*3526Sxy150489 * (none) * 691*3526Sxy150489 * * 692*3526Sxy150489 * Modification log: * 693*3526Sxy150489 * Date Who Description * 694*3526Sxy150489 * -------- --- ----------------------------------------------------- * 695*3526Sxy150489 * * 696*3526Sxy150489 * ********************************************************************** 697*3526Sxy150489 */ 698*3526Sxy150489 void 699*3526Sxy150489 SetupTransmitStructures(struct e1000g *Adapter) 700*3526Sxy150489 { 701*3526Sxy150489 struct e1000_hw *hw; 702*3526Sxy150489 PTX_SW_PACKET packet; 703*3526Sxy150489 UINT i; 704*3526Sxy150489 uint32_t buf_high; 705*3526Sxy150489 uint32_t buf_low; 706*3526Sxy150489 uint32_t reg_tipg; 707*3526Sxy150489 uint32_t reg_tctl; 708*3526Sxy150489 uint32_t reg_tarc; 709*3526Sxy150489 uint16_t speed, duplex; 710*3526Sxy150489 int size; 711*3526Sxy150489 e1000g_tx_ring_t *tx_ring; 712*3526Sxy150489 713*3526Sxy150489 hw = &Adapter->Shared; 714*3526Sxy150489 tx_ring = Adapter->tx_ring; 715*3526Sxy150489 716*3526Sxy150489 /* init the lists */ 717*3526Sxy150489 /* 718*3526Sxy150489 * Here we don't need to protect the lists using the 719*3526Sxy150489 * tx_usedlist_lock and tx_freelist_lock, for they have 720*3526Sxy150489 * been protected by the chip_lock. 721*3526Sxy150489 */ 722*3526Sxy150489 QUEUE_INIT_LIST(&tx_ring->used_list); 723*3526Sxy150489 QUEUE_INIT_LIST(&tx_ring->free_list); 724*3526Sxy150489 725*3526Sxy150489 /* Go through and set up each SW_Packet */ 726*3526Sxy150489 packet = tx_ring->packet_area; 727*3526Sxy150489 for (i = 0; i < Adapter->NumTxSwPacket; i++, packet++) { 728*3526Sxy150489 /* Initialize this TX_SW_PACKET area */ 729*3526Sxy150489 FreeTxSwPacket(packet); 730*3526Sxy150489 /* Add this TX_SW_PACKET to the free list */ 731*3526Sxy150489 QUEUE_PUSH_TAIL(&tx_ring->free_list, 732*3526Sxy150489 &packet->Link); 733*3526Sxy150489 } 734*3526Sxy150489 735*3526Sxy150489 /* Setup TX descriptor pointers */ 736*3526Sxy150489 tx_ring->tbd_next = tx_ring->tbd_first; 737*3526Sxy150489 tx_ring->tbd_oldest = tx_ring->tbd_first; 738*3526Sxy150489 739*3526Sxy150489 /* 740*3526Sxy150489 * Setup Hardware TX Registers 741*3526Sxy150489 */ 742*3526Sxy150489 /* Setup the Transmit Control Register (TCTL). */ 743*3526Sxy150489 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 744*3526Sxy150489 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 745*3526Sxy150489 (E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT); 746*3526Sxy150489 747*3526Sxy150489 /* Enable the MULR bit */ 748*3526Sxy150489 if (hw->bus_type == e1000_bus_type_pci_express) 749*3526Sxy150489 reg_tctl |= E1000_TCTL_MULR; 750*3526Sxy150489 751*3526Sxy150489 E1000_WRITE_REG(hw, TCTL, reg_tctl); 752*3526Sxy150489 753*3526Sxy150489 if ((hw->mac_type == e1000_82571) || (hw->mac_type == e1000_82572)) { 754*3526Sxy150489 e1000_get_speed_and_duplex(hw, &speed, &duplex); 755*3526Sxy150489 756*3526Sxy150489 reg_tarc = E1000_READ_REG(hw, TARC0); 757*3526Sxy150489 reg_tarc |= (1 << 25); 758*3526Sxy150489 if (speed == SPEED_1000) 759*3526Sxy150489 reg_tarc |= (1 << 21); 760*3526Sxy150489 E1000_WRITE_REG(hw, TARC0, reg_tarc); 761*3526Sxy150489 762*3526Sxy150489 reg_tarc = E1000_READ_REG(hw, TARC1); 763*3526Sxy150489 reg_tarc |= (1 << 25); 764*3526Sxy150489 if (reg_tctl & E1000_TCTL_MULR) 765*3526Sxy150489 reg_tarc &= ~(1 << 28); 766*3526Sxy150489 else 767*3526Sxy150489 reg_tarc |= (1 << 28); 768*3526Sxy150489 E1000_WRITE_REG(hw, TARC1, reg_tarc); 769*3526Sxy150489 770*3526Sxy150489 } else if (hw->mac_type == e1000_80003es2lan) { 771*3526Sxy150489 reg_tarc = E1000_READ_REG(hw, TARC0); 772*3526Sxy150489 reg_tarc |= 1; 773*3526Sxy150489 if (hw->media_type == e1000_media_type_internal_serdes) 774*3526Sxy150489 reg_tarc |= (1 << 20); 775*3526Sxy150489 E1000_WRITE_REG(hw, TARC0, reg_tarc); 776*3526Sxy150489 777*3526Sxy150489 reg_tarc = E1000_READ_REG(hw, TARC1); 778*3526Sxy150489 reg_tarc |= 1; 779*3526Sxy150489 E1000_WRITE_REG(hw, TARC1, reg_tarc); 780*3526Sxy150489 } 781*3526Sxy150489 782*3526Sxy150489 /* Setup HW Base and Length of Tx descriptor area */ 783*3526Sxy150489 size = (Adapter->NumTxDescriptors * sizeof (struct e1000_tx_desc)); 784*3526Sxy150489 E1000_WRITE_REG(hw, TDLEN, size); 785*3526Sxy150489 size = E1000_READ_REG(hw, TDLEN); 786*3526Sxy150489 787*3526Sxy150489 buf_low = (uint32_t)tx_ring->tbd_dma_addr; 788*3526Sxy150489 buf_high = (uint32_t)(tx_ring->tbd_dma_addr >> 32); 789*3526Sxy150489 790*3526Sxy150489 E1000_WRITE_REG(hw, TDBAL, buf_low); 791*3526Sxy150489 E1000_WRITE_REG(hw, TDBAH, buf_high); 792*3526Sxy150489 793*3526Sxy150489 /* Setup our HW Tx Head & Tail descriptor pointers */ 794*3526Sxy150489 E1000_WRITE_REG(hw, TDH, 0); 795*3526Sxy150489 E1000_WRITE_REG(hw, TDT, 0); 796*3526Sxy150489 797*3526Sxy150489 /* Set the default values for the Tx Inter Packet Gap timer */ 798*3526Sxy150489 switch (hw->mac_type) { 799*3526Sxy150489 case e1000_82542_rev2_0: 800*3526Sxy150489 case e1000_82542_rev2_1: 801*3526Sxy150489 reg_tipg = DEFAULT_82542_TIPG_IPGT; 802*3526Sxy150489 reg_tipg |= 803*3526Sxy150489 DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 804*3526Sxy150489 reg_tipg |= 805*3526Sxy150489 DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 806*3526Sxy150489 break; 807*3526Sxy150489 default: 808*3526Sxy150489 if (hw->media_type == e1000_media_type_fiber) 809*3526Sxy150489 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 810*3526Sxy150489 else 811*3526Sxy150489 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 812*3526Sxy150489 reg_tipg |= 813*3526Sxy150489 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 814*3526Sxy150489 reg_tipg |= 815*3526Sxy150489 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 816*3526Sxy150489 break; 817*3526Sxy150489 } 818*3526Sxy150489 E1000_WRITE_REG(hw, TIPG, reg_tipg); 819*3526Sxy150489 820*3526Sxy150489 /* Setup Transmit Interrupt Delay Value */ 821*3526Sxy150489 if (Adapter->TxInterruptDelay) { 822*3526Sxy150489 E1000_WRITE_REG(hw, TIDV, Adapter->TxInterruptDelay); 823*3526Sxy150489 } 824*3526Sxy150489 825*3526Sxy150489 /* For TCP/UDP checksum offload */ 826*3526Sxy150489 tx_ring->cksum_stuff = 0; 827*3526Sxy150489 tx_ring->cksum_start = 0; 828*3526Sxy150489 tx_ring->cksum_flags = 0; 829*3526Sxy150489 830*3526Sxy150489 /* Initialize tx parameters */ 831*3526Sxy150489 Adapter->tx_bcopy_thresh = DEFAULTTXBCOPYTHRESHOLD; 832*3526Sxy150489 Adapter->tx_recycle_low_water = DEFAULTTXRECYCLELOWWATER; 833*3526Sxy150489 Adapter->tx_recycle_num = DEFAULTTXRECYCLENUM; 834*3526Sxy150489 Adapter->tx_intr_enable = B_TRUE; 835*3526Sxy150489 Adapter->tx_frags_limit = 836*3526Sxy150489 (Adapter->Shared.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 837*3526Sxy150489 if (Adapter->tx_frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 838*3526Sxy150489 Adapter->tx_frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 839*3526Sxy150489 } 840*3526Sxy150489 841*3526Sxy150489 /* 842*3526Sxy150489 * ********************************************************************** 843*3526Sxy150489 * Name: e1000g_recycle * 844*3526Sxy150489 * * 845*3526Sxy150489 * Description: This routine cleans transmit packets. * 846*3526Sxy150489 * * 847*3526Sxy150489 * * 848*3526Sxy150489 * * 849*3526Sxy150489 * Arguments: * 850*3526Sxy150489 * Adapter - A pointer to our context sensitive "Adapter" * 851*3526Sxy150489 * structure. * 852*3526Sxy150489 * * 853*3526Sxy150489 * Returns: * 854*3526Sxy150489 * (none) * 855*3526Sxy150489 * Functions Called: * 856*3526Sxy150489 * None * 857*3526Sxy150489 * * 858*3526Sxy150489 * Modification log: * 859*3526Sxy150489 * Date Who Description * 860*3526Sxy150489 * -------- --- ----------------------------------------------------- * 861*3526Sxy150489 * * 862*3526Sxy150489 * ********************************************************************** 863*3526Sxy150489 */ 864*3526Sxy150489 int 865*3526Sxy150489 e1000g_recycle(e1000g_tx_ring_t *tx_ring) 866*3526Sxy150489 { 867*3526Sxy150489 struct e1000g *Adapter; 868*3526Sxy150489 LIST_DESCRIBER pending_list; 869*3526Sxy150489 PTX_SW_PACKET packet; 870*3526Sxy150489 e1000g_msg_chain_t *msg_chain; 871*3526Sxy150489 mblk_t *mp; 872*3526Sxy150489 mblk_t *nmp; 873*3526Sxy150489 struct e1000_tx_desc *descriptor; 874*3526Sxy150489 int desc_count; 875*3526Sxy150489 876*3526Sxy150489 /* 877*3526Sxy150489 * This function will examine each TxSwPacket in the 'used' queue 878*3526Sxy150489 * if the e1000g is done with it then the associated resources (Tx 879*3526Sxy150489 * Descriptors) will be "freed" and the TxSwPacket will be 880*3526Sxy150489 * returned to the 'free' queue. 881*3526Sxy150489 */ 882*3526Sxy150489 Adapter = tx_ring->adapter; 883*3526Sxy150489 884*3526Sxy150489 desc_count = 0; 885*3526Sxy150489 QUEUE_INIT_LIST(&pending_list); 886*3526Sxy150489 887*3526Sxy150489 mutex_enter(&tx_ring->usedlist_lock); 888*3526Sxy150489 889*3526Sxy150489 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 890*3526Sxy150489 if (packet == NULL) { 891*3526Sxy150489 mutex_exit(&tx_ring->usedlist_lock); 892*3526Sxy150489 Adapter->tx_recycle_fail = 0; 893*3526Sxy150489 Adapter->StallWatchdog = 0; 894*3526Sxy150489 return (0); 895*3526Sxy150489 } 896*3526Sxy150489 897*3526Sxy150489 /* 898*3526Sxy150489 * While there are still TxSwPackets in the used queue check them 899*3526Sxy150489 */ 900*3526Sxy150489 while (packet = 901*3526Sxy150489 (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list)) { 902*3526Sxy150489 903*3526Sxy150489 /* 904*3526Sxy150489 * Get hold of the next descriptor that the e1000g will 905*3526Sxy150489 * report status back to (this will be the last descriptor 906*3526Sxy150489 * of a given TxSwPacket). We only want to free the 907*3526Sxy150489 * TxSwPacket (and it resources) if the e1000g is done 908*3526Sxy150489 * with ALL of the descriptors. If the e1000g is done 909*3526Sxy150489 * with the last one then it is done with all of them. 910*3526Sxy150489 */ 911*3526Sxy150489 ASSERT(packet->num_desc); 912*3526Sxy150489 descriptor = tx_ring->tbd_oldest + 913*3526Sxy150489 (packet->num_desc - 1); 914*3526Sxy150489 915*3526Sxy150489 /* Check for wrap case */ 916*3526Sxy150489 if (descriptor > tx_ring->tbd_last) 917*3526Sxy150489 descriptor -= Adapter->NumTxDescriptors; 918*3526Sxy150489 919*3526Sxy150489 /* Sync the Tx descriptor DMA buffer */ 920*3526Sxy150489 (void) ddi_dma_sync(tx_ring->tbd_dma_handle, 921*3526Sxy150489 (descriptor - tx_ring->tbd_first) * 922*3526Sxy150489 sizeof (struct e1000_tx_desc), 923*3526Sxy150489 sizeof (struct e1000_tx_desc), 924*3526Sxy150489 DDI_DMA_SYNC_FORCPU); 925*3526Sxy150489 926*3526Sxy150489 /* 927*3526Sxy150489 * If the descriptor done bit is set free TxSwPacket and 928*3526Sxy150489 * associated resources 929*3526Sxy150489 */ 930*3526Sxy150489 if (descriptor->upper.fields.status & E1000_TXD_STAT_DD) { 931*3526Sxy150489 QUEUE_POP_HEAD(&tx_ring->used_list); 932*3526Sxy150489 QUEUE_PUSH_TAIL(&pending_list, &packet->Link); 933*3526Sxy150489 934*3526Sxy150489 if (descriptor == tx_ring->tbd_last) 935*3526Sxy150489 tx_ring->tbd_oldest = 936*3526Sxy150489 tx_ring->tbd_first; 937*3526Sxy150489 else 938*3526Sxy150489 tx_ring->tbd_oldest = 939*3526Sxy150489 descriptor + 1; 940*3526Sxy150489 941*3526Sxy150489 desc_count += packet->num_desc; 942*3526Sxy150489 943*3526Sxy150489 if (desc_count >= Adapter->tx_recycle_num) 944*3526Sxy150489 break; 945*3526Sxy150489 } else { 946*3526Sxy150489 /* 947*3526Sxy150489 * Found a TxSwPacket that the e1000g is not done 948*3526Sxy150489 * with then there is no reason to check the rest 949*3526Sxy150489 * of the queue. 950*3526Sxy150489 */ 951*3526Sxy150489 break; 952*3526Sxy150489 } 953*3526Sxy150489 } 954*3526Sxy150489 955*3526Sxy150489 mutex_exit(&tx_ring->usedlist_lock); 956*3526Sxy150489 957*3526Sxy150489 if (desc_count == 0) { 958*3526Sxy150489 Adapter->tx_recycle_fail++; 959*3526Sxy150489 Adapter->tx_recycle_none++; 960*3526Sxy150489 return (0); 961*3526Sxy150489 } 962*3526Sxy150489 963*3526Sxy150489 Adapter->tx_recycle_fail = 0; 964*3526Sxy150489 Adapter->StallWatchdog = 0; 965*3526Sxy150489 966*3526Sxy150489 mp = NULL; 967*3526Sxy150489 nmp = NULL; 968*3526Sxy150489 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&pending_list); 969*3526Sxy150489 ASSERT(packet != NULL); 970*3526Sxy150489 while (packet != NULL) { 971*3526Sxy150489 if (packet->mp != NULL) { 972*3526Sxy150489 ASSERT(packet->mp->b_next == NULL); 973*3526Sxy150489 /* Assemble the message chain */ 974*3526Sxy150489 if (mp == NULL) { 975*3526Sxy150489 mp = packet->mp; 976*3526Sxy150489 nmp = packet->mp; 977*3526Sxy150489 } else { 978*3526Sxy150489 nmp->b_next = packet->mp; 979*3526Sxy150489 nmp = packet->mp; 980*3526Sxy150489 } 981*3526Sxy150489 /* Disconnect the message from the sw packet */ 982*3526Sxy150489 packet->mp = NULL; 983*3526Sxy150489 } 984*3526Sxy150489 985*3526Sxy150489 /* Free the TxSwPackets */ 986*3526Sxy150489 FreeTxSwPacket(packet); 987*3526Sxy150489 988*3526Sxy150489 packet = (PTX_SW_PACKET) 989*3526Sxy150489 QUEUE_GET_NEXT(&pending_list, &packet->Link); 990*3526Sxy150489 } 991*3526Sxy150489 992*3526Sxy150489 /* Save the message chain */ 993*3526Sxy150489 if (mp != NULL) { 994*3526Sxy150489 msg_chain = Adapter->tx_msg_chain; 995*3526Sxy150489 mutex_enter(&msg_chain->lock); 996*3526Sxy150489 if (msg_chain->head == NULL) { 997*3526Sxy150489 msg_chain->head = mp; 998*3526Sxy150489 msg_chain->tail = nmp; 999*3526Sxy150489 } else { 1000*3526Sxy150489 msg_chain->tail->b_next = mp; 1001*3526Sxy150489 msg_chain->tail = nmp; 1002*3526Sxy150489 } 1003*3526Sxy150489 mutex_exit(&msg_chain->lock); 1004*3526Sxy150489 1005*3526Sxy150489 /* 1006*3526Sxy150489 * If the tx interrupt is enabled, the messages will be freed 1007*3526Sxy150489 * in the tx interrupt; Otherwise, they are freed here by 1008*3526Sxy150489 * triggering a soft interrupt. 1009*3526Sxy150489 */ 1010*3526Sxy150489 if (!Adapter->tx_intr_enable) 1011*3526Sxy150489 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1012*3526Sxy150489 NULL); 1013*3526Sxy150489 } 1014*3526Sxy150489 1015*3526Sxy150489 /* Return the TxSwPackets back to the FreeList */ 1016*3526Sxy150489 mutex_enter(&tx_ring->freelist_lock); 1017*3526Sxy150489 QUEUE_APPEND(&tx_ring->free_list, &pending_list); 1018*3526Sxy150489 mutex_exit(&tx_ring->freelist_lock); 1019*3526Sxy150489 1020*3526Sxy150489 return (desc_count); 1021*3526Sxy150489 } 1022*3526Sxy150489 1023*3526Sxy150489 /* 1024*3526Sxy150489 * 82544 Coexistence issue workaround: 1025*3526Sxy150489 * There are 2 issues. 1026*3526Sxy150489 * 1. If a 32 bit split completion happens from P64H2 and another 1027*3526Sxy150489 * agent drives a 64 bit request/split completion after ONLY 1028*3526Sxy150489 * 1 idle clock (BRCM/Emulex/Adaptec fiber channel cards) then 1029*3526Sxy150489 * 82544 has a problem where in to clock all the data in, it 1030*3526Sxy150489 * looks at REQ64# signal and since it has changed so fast (i.e. 1 1031*3526Sxy150489 * idle clock turn around), it will fail to clock all the data in. 1032*3526Sxy150489 * Data coming from certain ending addresses has exposure to this issue. 1033*3526Sxy150489 * 1034*3526Sxy150489 * To detect this issue, following equation can be used... 1035*3526Sxy150489 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 1036*3526Sxy150489 * If SUM[3:0] is in between 1 to 4, we will have this issue. 1037*3526Sxy150489 * 1038*3526Sxy150489 * ROOT CAUSE: 1039*3526Sxy150489 * The erratum involves the 82544 PCIX elasticity FIFO implementations as 1040*3526Sxy150489 * 64-bit FIFO's and flushing of the final partial-bytes corresponding 1041*3526Sxy150489 * to the end of a requested read burst. Under a specific burst condition 1042*3526Sxy150489 * of ending-data alignment and 32-byte split-completions, the final 1043*3526Sxy150489 * byte(s) of split-completion data require an extra clock cycle to flush 1044*3526Sxy150489 * into 64-bit FIFO orientation. An incorrect logic dependency on the 1045*3526Sxy150489 * REQ64# signal occurring during during this clock cycle may cause the 1046*3526Sxy150489 * residual byte(s) to be lost, thereby rendering the internal DMA client 1047*3526Sxy150489 * forever awaiting the final byte(s) for an outbound data-fetch. The 1048*3526Sxy150489 * erratum is confirmed to *only* occur if certain subsequent external 1049*3526Sxy150489 * 64-bit PCIX bus transactions occur immediately (minimum possible bus 1050*3526Sxy150489 * turn- around) following the odd-aligned 32-bit split-completion 1051*3526Sxy150489 * containing the final byte(s). Intel has confirmed that this has been 1052*3526Sxy150489 * seen only with chipset/bridges which have the capability to provide 1053*3526Sxy150489 * 32-bit split-completion data, and in the presence of newer PCIX bus 1054*3526Sxy150489 * agents which fully-optimize the inter-transaction turn-around (zero 1055*3526Sxy150489 * additional initiator latency when pre-granted bus ownership). 1056*3526Sxy150489 * 1057*3526Sxy150489 * This issue does not exist in PCI bus mode, when any agent is operating 1058*3526Sxy150489 * in 32 bit only mode or on chipsets that do not do 32 bit split 1059*3526Sxy150489 * completions for 64 bit read requests (Serverworks chipsets). P64H2 does 1060*3526Sxy150489 * 32 bit split completions for any read request that has bit 2 set to 1 1061*3526Sxy150489 * for the requested address and read request size is more than 8 bytes. 1062*3526Sxy150489 * 1063*3526Sxy150489 * 2. Another issue is related to 82544 driving DACs under the similar 1064*3526Sxy150489 * scenario (32 bit split completion followed by 64 bit transaction with 1065*3526Sxy150489 * only 1 cycle turnaround). This issue is still being root caused. We 1066*3526Sxy150489 * think that both of these issues can be avoided if following workaround 1067*3526Sxy150489 * is implemented. It seems DAC issues is related to ending addresses being 1068*3526Sxy150489 * 0x9, 0xA, 0xB, 0xC and hence ending up at odd boundaries in elasticity 1069*3526Sxy150489 * FIFO which does not get flushed due to REQ64# dependency. We will only 1070*3526Sxy150489 * know the full story after it has been simulated successfully by HW team. 1071*3526Sxy150489 * 1072*3526Sxy150489 * WORKAROUND: 1073*3526Sxy150489 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c(DAC) 1074*3526Sxy150489 */ 1075*3526Sxy150489 static uint32_t 1076*3526Sxy150489 e1000g_fill_82544_desc(uint64_t Address, 1077*3526Sxy150489 size_t Length, PDESC_ARRAY desc_array) 1078*3526Sxy150489 { 1079*3526Sxy150489 /* 1080*3526Sxy150489 * Since issue is sensitive to length and address. 1081*3526Sxy150489 * Let us first check the address... 1082*3526Sxy150489 */ 1083*3526Sxy150489 uint32_t safe_terminator; 1084*3526Sxy150489 1085*3526Sxy150489 if (Length <= 4) { 1086*3526Sxy150489 desc_array->Descriptor[0].Address = Address; 1087*3526Sxy150489 desc_array->Descriptor[0].Length = Length; 1088*3526Sxy150489 desc_array->Elements = 1; 1089*3526Sxy150489 return (desc_array->Elements); 1090*3526Sxy150489 } 1091*3526Sxy150489 safe_terminator = 1092*3526Sxy150489 (uint32_t)((((uint32_t)Address & 0x7) + 1093*3526Sxy150489 (Length & 0xF)) & 0xF); 1094*3526Sxy150489 /* 1095*3526Sxy150489 * if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then 1096*3526Sxy150489 * return 1097*3526Sxy150489 */ 1098*3526Sxy150489 if (safe_terminator == 0 || 1099*3526Sxy150489 (safe_terminator > 4 && 1100*3526Sxy150489 safe_terminator < 9) || 1101*3526Sxy150489 (safe_terminator > 0xC && safe_terminator <= 0xF)) { 1102*3526Sxy150489 desc_array->Descriptor[0].Address = Address; 1103*3526Sxy150489 desc_array->Descriptor[0].Length = Length; 1104*3526Sxy150489 desc_array->Elements = 1; 1105*3526Sxy150489 return (desc_array->Elements); 1106*3526Sxy150489 } 1107*3526Sxy150489 1108*3526Sxy150489 desc_array->Descriptor[0].Address = Address; 1109*3526Sxy150489 desc_array->Descriptor[0].Length = Length - 4; 1110*3526Sxy150489 desc_array->Descriptor[1].Address = Address + (Length - 4); 1111*3526Sxy150489 desc_array->Descriptor[1].Length = 4; 1112*3526Sxy150489 desc_array->Elements = 2; 1113*3526Sxy150489 return (desc_array->Elements); 1114*3526Sxy150489 } 1115*3526Sxy150489 1116*3526Sxy150489 static int 1117*3526Sxy150489 e1000g_tx_copy(struct e1000g *Adapter, PTX_SW_PACKET packet, 1118*3526Sxy150489 mblk_t *mp, uint32_t force_bcopy) 1119*3526Sxy150489 { 1120*3526Sxy150489 size_t len; 1121*3526Sxy150489 size_t len1; 1122*3526Sxy150489 dma_buffer_t *tx_buf; 1123*3526Sxy150489 mblk_t *nmp; 1124*3526Sxy150489 boolean_t finished; 1125*3526Sxy150489 int desc_count; 1126*3526Sxy150489 1127*3526Sxy150489 desc_count = 0; 1128*3526Sxy150489 tx_buf = packet->tx_buf; 1129*3526Sxy150489 len = MBLKL(mp); 1130*3526Sxy150489 1131*3526Sxy150489 ASSERT((tx_buf->len + len) <= tx_buf->size); 1132*3526Sxy150489 1133*3526Sxy150489 if (len > 0) { 1134*3526Sxy150489 bcopy(mp->b_rptr, 1135*3526Sxy150489 tx_buf->address + tx_buf->len, 1136*3526Sxy150489 len); 1137*3526Sxy150489 tx_buf->len += len; 1138*3526Sxy150489 1139*3526Sxy150489 packet->num_mblk_frag++; 1140*3526Sxy150489 } 1141*3526Sxy150489 1142*3526Sxy150489 nmp = mp->b_cont; 1143*3526Sxy150489 if (nmp == NULL) { 1144*3526Sxy150489 finished = B_TRUE; 1145*3526Sxy150489 } else { 1146*3526Sxy150489 len1 = MBLKL(nmp); 1147*3526Sxy150489 if ((tx_buf->len + len1) > tx_buf->size) 1148*3526Sxy150489 finished = B_TRUE; 1149*3526Sxy150489 else if (force_bcopy) 1150*3526Sxy150489 finished = B_FALSE; 1151*3526Sxy150489 else if (len1 > Adapter->tx_bcopy_thresh) 1152*3526Sxy150489 finished = B_TRUE; 1153*3526Sxy150489 else 1154*3526Sxy150489 finished = B_FALSE; 1155*3526Sxy150489 } 1156*3526Sxy150489 1157*3526Sxy150489 if (finished) { 1158*3526Sxy150489 if (tx_buf->len > len) 1159*3526Sxy150489 Adapter->tx_multi_copy++; 1160*3526Sxy150489 1161*3526Sxy150489 /* 1162*3526Sxy150489 * If the packet is smaller than 64 bytes, which is the 1163*3526Sxy150489 * minimum ethernet packet size, pad the packet to make 1164*3526Sxy150489 * it at least 60 bytes. The hardware will add 4 bytes 1165*3526Sxy150489 * for CRC. 1166*3526Sxy150489 */ 1167*3526Sxy150489 if (force_bcopy & FORCE_BCOPY_UNDER_SIZE) { 1168*3526Sxy150489 ASSERT(tx_buf->len < MINIMUM_ETHERNET_PACKET_SIZE); 1169*3526Sxy150489 1170*3526Sxy150489 bzero(tx_buf->address + tx_buf->len, 1171*3526Sxy150489 MINIMUM_ETHERNET_PACKET_SIZE - tx_buf->len); 1172*3526Sxy150489 tx_buf->len = MINIMUM_ETHERNET_PACKET_SIZE; 1173*3526Sxy150489 } 1174*3526Sxy150489 1175*3526Sxy150489 switch (packet->dma_type) { 1176*3526Sxy150489 #ifdef __sparc 1177*3526Sxy150489 case USE_DVMA: 1178*3526Sxy150489 dvma_sync(tx_buf->dma_handle, 0, DDI_DMA_SYNC_FORDEV); 1179*3526Sxy150489 break; 1180*3526Sxy150489 #endif 1181*3526Sxy150489 case USE_DMA: 1182*3526Sxy150489 (void) ddi_dma_sync(tx_buf->dma_handle, 0, 1183*3526Sxy150489 tx_buf->len, DDI_DMA_SYNC_FORDEV); 1184*3526Sxy150489 break; 1185*3526Sxy150489 default: 1186*3526Sxy150489 ASSERT(B_FALSE); 1187*3526Sxy150489 break; 1188*3526Sxy150489 } 1189*3526Sxy150489 1190*3526Sxy150489 packet->data_transfer_type = USE_BCOPY; 1191*3526Sxy150489 1192*3526Sxy150489 desc_count = e1000g_fill_tx_desc(Adapter, 1193*3526Sxy150489 packet, 1194*3526Sxy150489 tx_buf->dma_address, 1195*3526Sxy150489 tx_buf->len); 1196*3526Sxy150489 1197*3526Sxy150489 if (desc_count <= 0) 1198*3526Sxy150489 return (-1); 1199*3526Sxy150489 } 1200*3526Sxy150489 1201*3526Sxy150489 return (desc_count); 1202*3526Sxy150489 } 1203*3526Sxy150489 1204*3526Sxy150489 static int 1205*3526Sxy150489 e1000g_tx_bind(struct e1000g *Adapter, PTX_SW_PACKET packet, mblk_t *mp) 1206*3526Sxy150489 { 1207*3526Sxy150489 int j; 1208*3526Sxy150489 int mystat; 1209*3526Sxy150489 size_t len; 1210*3526Sxy150489 ddi_dma_cookie_t dma_cookie; 1211*3526Sxy150489 uint_t ncookies; 1212*3526Sxy150489 int desc_count; 1213*3526Sxy150489 uint32_t desc_total; 1214*3526Sxy150489 1215*3526Sxy150489 desc_total = 0; 1216*3526Sxy150489 len = MBLKL(mp); 1217*3526Sxy150489 1218*3526Sxy150489 /* 1219*3526Sxy150489 * ddi_dma_addr_bind_handle() allocates DMA resources for a 1220*3526Sxy150489 * memory object such that a device can perform DMA to or from 1221*3526Sxy150489 * the object. DMA resources are allocated considering the 1222*3526Sxy150489 * device's DMA attributes as expressed by ddi_dma_attr(9S) 1223*3526Sxy150489 * (see ddi_dma_alloc_handle(9F)). 1224*3526Sxy150489 * 1225*3526Sxy150489 * ddi_dma_addr_bind_handle() fills in the first DMA cookie 1226*3526Sxy150489 * pointed to by cookiep with the appropriate address, length, 1227*3526Sxy150489 * and bus type. *ccountp is set to the number of DMA cookies 1228*3526Sxy150489 * representing this DMA object. Subsequent DMA cookies must be 1229*3526Sxy150489 * retrieved by calling ddi_dma_nextcookie(9F) the number of 1230*3526Sxy150489 * times specified by *countp - 1. 1231*3526Sxy150489 */ 1232*3526Sxy150489 switch (packet->dma_type) { 1233*3526Sxy150489 #ifdef __sparc 1234*3526Sxy150489 case USE_DVMA: 1235*3526Sxy150489 dvma_kaddr_load(packet->tx_dma_handle, 1236*3526Sxy150489 (caddr_t)mp->b_rptr, len, 0, &dma_cookie); 1237*3526Sxy150489 1238*3526Sxy150489 dvma_sync(packet->tx_dma_handle, 0, 1239*3526Sxy150489 DDI_DMA_SYNC_FORDEV); 1240*3526Sxy150489 1241*3526Sxy150489 ncookies = 1; 1242*3526Sxy150489 packet->data_transfer_type = USE_DVMA; 1243*3526Sxy150489 break; 1244*3526Sxy150489 #endif 1245*3526Sxy150489 case USE_DMA: 1246*3526Sxy150489 if ((mystat = ddi_dma_addr_bind_handle( 1247*3526Sxy150489 packet->tx_dma_handle, NULL, 1248*3526Sxy150489 (caddr_t)mp->b_rptr, len, 1249*3526Sxy150489 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1250*3526Sxy150489 DDI_DMA_DONTWAIT, 0, &dma_cookie, 1251*3526Sxy150489 &ncookies)) != DDI_DMA_MAPPED) { 1252*3526Sxy150489 1253*3526Sxy150489 e1000g_log(Adapter, CE_WARN, 1254*3526Sxy150489 "Couldn't bind mblk buffer to Tx DMA handle: " 1255*3526Sxy150489 "return: %X, Pkt: %X\n", 1256*3526Sxy150489 mystat, packet); 1257*3526Sxy150489 return (-1); 1258*3526Sxy150489 } 1259*3526Sxy150489 1260*3526Sxy150489 /* 1261*3526Sxy150489 * An implicit ddi_dma_sync() is done when the 1262*3526Sxy150489 * ddi_dma_addr_bind_handle() is called. So we 1263*3526Sxy150489 * don't need to explicitly call ddi_dma_sync() 1264*3526Sxy150489 * here any more. 1265*3526Sxy150489 */ 1266*3526Sxy150489 ASSERT(ncookies); 1267*3526Sxy150489 if (ncookies > 1) 1268*3526Sxy150489 Adapter->tx_multi_cookie++; 1269*3526Sxy150489 1270*3526Sxy150489 /* 1271*3526Sxy150489 * The data_transfer_type value must be set after the handle 1272*3526Sxy150489 * has been bound, for it will be used in FreeTxSwPacket() 1273*3526Sxy150489 * to decide whether we need to unbind the handle. 1274*3526Sxy150489 */ 1275*3526Sxy150489 packet->data_transfer_type = USE_DMA; 1276*3526Sxy150489 break; 1277*3526Sxy150489 default: 1278*3526Sxy150489 ASSERT(B_FALSE); 1279*3526Sxy150489 break; 1280*3526Sxy150489 } 1281*3526Sxy150489 1282*3526Sxy150489 packet->num_mblk_frag++; 1283*3526Sxy150489 1284*3526Sxy150489 /* 1285*3526Sxy150489 * Each address could span thru multpile cookie.. 1286*3526Sxy150489 * Each cookie will have one descriptor 1287*3526Sxy150489 */ 1288*3526Sxy150489 for (j = ncookies; j != 0; j--) { 1289*3526Sxy150489 1290*3526Sxy150489 desc_count = e1000g_fill_tx_desc(Adapter, 1291*3526Sxy150489 packet, 1292*3526Sxy150489 dma_cookie.dmac_laddress, 1293*3526Sxy150489 dma_cookie.dmac_size); 1294*3526Sxy150489 1295*3526Sxy150489 if (desc_count <= 0) 1296*3526Sxy150489 return (-1); 1297*3526Sxy150489 1298*3526Sxy150489 desc_total += desc_count; 1299*3526Sxy150489 1300*3526Sxy150489 /* 1301*3526Sxy150489 * ddi_dma_nextcookie() retrieves subsequent DMA 1302*3526Sxy150489 * cookies for a DMA object. 1303*3526Sxy150489 * ddi_dma_nextcookie() fills in the 1304*3526Sxy150489 * ddi_dma_cookie(9S) structure pointed to by 1305*3526Sxy150489 * cookiep. The ddi_dma_cookie(9S) structure 1306*3526Sxy150489 * must be allocated prior to calling 1307*3526Sxy150489 * ddi_dma_nextcookie(). The DMA cookie count 1308*3526Sxy150489 * returned by ddi_dma_buf_bind_handle(9F), 1309*3526Sxy150489 * ddi_dma_addr_bind_handle(9F), or 1310*3526Sxy150489 * ddi_dma_getwin(9F) indicates the number of DMA 1311*3526Sxy150489 * cookies a DMA object consists of. If the 1312*3526Sxy150489 * resulting cookie count, N, is larger than 1, 1313*3526Sxy150489 * ddi_dma_nextcookie() must be called N-1 times 1314*3526Sxy150489 * to retrieve all DMA cookies. 1315*3526Sxy150489 */ 1316*3526Sxy150489 if (j > 1) { 1317*3526Sxy150489 ddi_dma_nextcookie(packet->tx_dma_handle, 1318*3526Sxy150489 &dma_cookie); 1319*3526Sxy150489 } 1320*3526Sxy150489 } 1321*3526Sxy150489 1322*3526Sxy150489 return (desc_total); 1323*3526Sxy150489 } 1324*3526Sxy150489 1325*3526Sxy150489 static void 1326*3526Sxy150489 e1000g_fill_context_descriptor(e1000g_tx_ring_t *tx_ring, 1327*3526Sxy150489 struct e1000_context_desc *cksum_desc) 1328*3526Sxy150489 { 1329*3526Sxy150489 if (tx_ring->cksum_flags & HCK_IPV4_HDRCKSUM) { 1330*3526Sxy150489 cksum_desc->lower_setup.ip_fields.ipcss = 1331*3526Sxy150489 tx_ring->ether_header_size; 1332*3526Sxy150489 cksum_desc->lower_setup.ip_fields.ipcso = 1333*3526Sxy150489 tx_ring->ether_header_size + 1334*3526Sxy150489 offsetof(struct ip, ip_sum); 1335*3526Sxy150489 cksum_desc->lower_setup.ip_fields.ipcse = 1336*3526Sxy150489 tx_ring->ether_header_size + 1337*3526Sxy150489 sizeof (struct ip) - 1; 1338*3526Sxy150489 } else 1339*3526Sxy150489 cksum_desc->lower_setup.ip_config = 0; 1340*3526Sxy150489 1341*3526Sxy150489 if (tx_ring->cksum_flags & HCK_PARTIALCKSUM) { 1342*3526Sxy150489 /* 1343*3526Sxy150489 * The packet with same protocol has the following 1344*3526Sxy150489 * stuff and start offset: 1345*3526Sxy150489 * | Protocol | Stuff | Start | Checksum 1346*3526Sxy150489 * | | Offset | Offset | Enable 1347*3526Sxy150489 * | IPv4 + TCP | 0x24 | 0x14 | Yes 1348*3526Sxy150489 * | IPv4 + UDP | 0x1A | 0x14 | Yes 1349*3526Sxy150489 * | IPv6 + TCP | 0x20 | 0x10 | No 1350*3526Sxy150489 * | IPv6 + UDP | 0x14 | 0x10 | No 1351*3526Sxy150489 */ 1352*3526Sxy150489 cksum_desc->upper_setup.tcp_fields.tucss = 1353*3526Sxy150489 tx_ring->cksum_start + tx_ring->ether_header_size; 1354*3526Sxy150489 cksum_desc->upper_setup.tcp_fields.tucso = 1355*3526Sxy150489 tx_ring->cksum_stuff + tx_ring->ether_header_size; 1356*3526Sxy150489 cksum_desc->upper_setup.tcp_fields.tucse = 0; 1357*3526Sxy150489 } else 1358*3526Sxy150489 cksum_desc->upper_setup.tcp_config = 0; 1359*3526Sxy150489 1360*3526Sxy150489 cksum_desc->cmd_and_length = E1000_TXD_CMD_DEXT; 1361*3526Sxy150489 1362*3526Sxy150489 /* 1363*3526Sxy150489 * Zero out the options for TCP Segmentation Offload, 1364*3526Sxy150489 * since we don't support it in this version 1365*3526Sxy150489 */ 1366*3526Sxy150489 cksum_desc->tcp_seg_setup.data = 0; 1367*3526Sxy150489 } 1368*3526Sxy150489 1369*3526Sxy150489 static int 1370*3526Sxy150489 e1000g_fill_tx_desc(struct e1000g *Adapter, 1371*3526Sxy150489 PTX_SW_PACKET packet, uint64_t address, size_t size) 1372*3526Sxy150489 { 1373*3526Sxy150489 PADDRESS_LENGTH_PAIR desc; 1374*3526Sxy150489 int desc_count; 1375*3526Sxy150489 1376*3526Sxy150489 desc_count = 0; 1377*3526Sxy150489 1378*3526Sxy150489 if ((Adapter->Shared.bus_type == e1000_bus_type_pcix) && 1379*3526Sxy150489 (Adapter->Shared.mac_type == e1000_82544)) { 1380*3526Sxy150489 1381*3526Sxy150489 desc_count = e1000g_tx_workaround_PCIX_82544(Adapter, 1382*3526Sxy150489 packet, address, size); 1383*3526Sxy150489 1384*3526Sxy150489 } else if ((Adapter->Shared.mac_type == e1000_82544) && 1385*3526Sxy150489 (size > JUMBO_FRAG_LENGTH)) { 1386*3526Sxy150489 1387*3526Sxy150489 desc_count = e1000g_tx_workaround_jumbo_82544(Adapter, 1388*3526Sxy150489 packet, address, size); 1389*3526Sxy150489 1390*3526Sxy150489 } else { 1391*3526Sxy150489 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1392*3526Sxy150489 1393*3526Sxy150489 desc = &packet->desc[packet->num_desc]; 1394*3526Sxy150489 1395*3526Sxy150489 desc->Address = address; 1396*3526Sxy150489 desc->Length = size; 1397*3526Sxy150489 1398*3526Sxy150489 packet->num_desc++; 1399*3526Sxy150489 desc_count++; 1400*3526Sxy150489 } 1401*3526Sxy150489 1402*3526Sxy150489 return (desc_count); 1403*3526Sxy150489 } 1404*3526Sxy150489 1405*3526Sxy150489 static int 1406*3526Sxy150489 e1000g_tx_workaround_PCIX_82544(struct e1000g *Adapter, 1407*3526Sxy150489 PTX_SW_PACKET packet, uint64_t address, size_t size) 1408*3526Sxy150489 { 1409*3526Sxy150489 PADDRESS_LENGTH_PAIR desc; 1410*3526Sxy150489 int desc_count; 1411*3526Sxy150489 long size_left; 1412*3526Sxy150489 size_t len; 1413*3526Sxy150489 uint32_t counter; 1414*3526Sxy150489 uint32_t array_elements; 1415*3526Sxy150489 DESC_ARRAY desc_array; 1416*3526Sxy150489 1417*3526Sxy150489 /* 1418*3526Sxy150489 * Coexist Workaround for cordova: RP: 07/04/03 1419*3526Sxy150489 * 1420*3526Sxy150489 * RP: ERRATA: Workaround ISSUE: 1421*3526Sxy150489 * 8kb_buffer_Lockup CONTROLLER: Cordova Breakup 1422*3526Sxy150489 * Eachbuffer in to 8kb pieces until the 1423*3526Sxy150489 * remainder is < 8kb 1424*3526Sxy150489 */ 1425*3526Sxy150489 size_left = size; 1426*3526Sxy150489 desc_count = 0; 1427*3526Sxy150489 1428*3526Sxy150489 while (size_left > 0) { 1429*3526Sxy150489 if (size_left > MAX_TX_BUF_SIZE) 1430*3526Sxy150489 len = MAX_TX_BUF_SIZE; 1431*3526Sxy150489 else 1432*3526Sxy150489 len = size_left; 1433*3526Sxy150489 1434*3526Sxy150489 array_elements = e1000g_fill_82544_desc(address, 1435*3526Sxy150489 len, &desc_array); 1436*3526Sxy150489 1437*3526Sxy150489 for (counter = 0; counter < array_elements; counter++) { 1438*3526Sxy150489 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1439*3526Sxy150489 if (packet->num_desc >= MAX_TX_DESC_PER_PACKET) { 1440*3526Sxy150489 e1000g_log(Adapter, CE_WARN, 1441*3526Sxy150489 "No enough preparing tx descriptors"); 1442*3526Sxy150489 return (-1); 1443*3526Sxy150489 } 1444*3526Sxy150489 /* 1445*3526Sxy150489 * Put in the buffer address 1446*3526Sxy150489 */ 1447*3526Sxy150489 desc = &packet->desc[packet->num_desc]; 1448*3526Sxy150489 1449*3526Sxy150489 desc->Address = 1450*3526Sxy150489 desc_array.Descriptor[counter].Address; 1451*3526Sxy150489 desc->Length = 1452*3526Sxy150489 desc_array.Descriptor[counter].Length; 1453*3526Sxy150489 1454*3526Sxy150489 packet->num_desc++; 1455*3526Sxy150489 desc_count++; 1456*3526Sxy150489 } /* for */ 1457*3526Sxy150489 1458*3526Sxy150489 /* 1459*3526Sxy150489 * Update the buffer address and length 1460*3526Sxy150489 */ 1461*3526Sxy150489 address += MAX_TX_BUF_SIZE; 1462*3526Sxy150489 size_left -= MAX_TX_BUF_SIZE; 1463*3526Sxy150489 } /* while */ 1464*3526Sxy150489 1465*3526Sxy150489 return (desc_count); 1466*3526Sxy150489 } 1467*3526Sxy150489 1468*3526Sxy150489 static int 1469*3526Sxy150489 e1000g_tx_workaround_jumbo_82544(struct e1000g *Adapter, 1470*3526Sxy150489 PTX_SW_PACKET packet, uint64_t address, size_t size) 1471*3526Sxy150489 { 1472*3526Sxy150489 PADDRESS_LENGTH_PAIR desc; 1473*3526Sxy150489 int desc_count; 1474*3526Sxy150489 long size_left; 1475*3526Sxy150489 uint32_t offset; 1476*3526Sxy150489 1477*3526Sxy150489 /* 1478*3526Sxy150489 * Workaround for Jumbo Frames on Cordova 1479*3526Sxy150489 * PSD 06/01/2001 1480*3526Sxy150489 */ 1481*3526Sxy150489 size_left = size; 1482*3526Sxy150489 desc_count = 0; 1483*3526Sxy150489 offset = 0; 1484*3526Sxy150489 while (size_left > 0) { 1485*3526Sxy150489 ASSERT(packet->num_desc < MAX_TX_DESC_PER_PACKET); 1486*3526Sxy150489 if (packet->num_desc >= MAX_TX_DESC_PER_PACKET) { 1487*3526Sxy150489 e1000g_log(Adapter, CE_WARN, 1488*3526Sxy150489 "No enough preparing tx descriptors"); 1489*3526Sxy150489 return (-1); 1490*3526Sxy150489 } 1491*3526Sxy150489 1492*3526Sxy150489 desc = &packet->desc[packet->num_desc]; 1493*3526Sxy150489 1494*3526Sxy150489 desc->Address = address + offset; 1495*3526Sxy150489 1496*3526Sxy150489 if (size_left > JUMBO_FRAG_LENGTH) 1497*3526Sxy150489 desc->Length = JUMBO_FRAG_LENGTH; 1498*3526Sxy150489 else 1499*3526Sxy150489 desc->Length = size_left; 1500*3526Sxy150489 1501*3526Sxy150489 packet->num_desc++; 1502*3526Sxy150489 desc_count++; 1503*3526Sxy150489 1504*3526Sxy150489 offset += desc->Length; 1505*3526Sxy150489 size_left -= JUMBO_FRAG_LENGTH; 1506*3526Sxy150489 } 1507*3526Sxy150489 1508*3526Sxy150489 return (desc_count); 1509*3526Sxy150489 } 1510*3526Sxy150489 1511*3526Sxy150489 static void 1512*3526Sxy150489 e1000g_82547_tx_move_tail_work(e1000g_tx_ring_t *tx_ring) 1513*3526Sxy150489 { 1514*3526Sxy150489 uint16_t hw_tdt; 1515*3526Sxy150489 uint16_t sw_tdt; 1516*3526Sxy150489 struct e1000_tx_desc *tx_desc; 1517*3526Sxy150489 uint16_t length = 0; 1518*3526Sxy150489 boolean_t eop = B_FALSE; 1519*3526Sxy150489 struct e1000g *Adapter; 1520*3526Sxy150489 1521*3526Sxy150489 Adapter = tx_ring->adapter; 1522*3526Sxy150489 1523*3526Sxy150489 hw_tdt = E1000_READ_REG(&Adapter->Shared, TDT); 1524*3526Sxy150489 sw_tdt = tx_ring->tbd_next - tx_ring->tbd_first; 1525*3526Sxy150489 1526*3526Sxy150489 while (hw_tdt != sw_tdt) { 1527*3526Sxy150489 tx_desc = &(tx_ring->tbd_first[hw_tdt]); 1528*3526Sxy150489 length += tx_desc->lower.flags.length; 1529*3526Sxy150489 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1530*3526Sxy150489 if (++hw_tdt == Adapter->NumTxDescriptors) 1531*3526Sxy150489 hw_tdt = 0; 1532*3526Sxy150489 1533*3526Sxy150489 if (eop) { 1534*3526Sxy150489 if ((Adapter->link_duplex == HALF_DUPLEX) && 1535*3526Sxy150489 e1000_82547_fifo_workaround(&Adapter->Shared, 1536*3526Sxy150489 length) != E1000_SUCCESS) { 1537*3526Sxy150489 if (tx_ring->timer_enable_82547) { 1538*3526Sxy150489 ASSERT(tx_ring->timer_id_82547 == 0); 1539*3526Sxy150489 tx_ring->timer_id_82547 = 1540*3526Sxy150489 timeout(e1000g_82547_timeout, 1541*3526Sxy150489 (void *)Adapter, 1542*3526Sxy150489 drv_usectohz(10000)); 1543*3526Sxy150489 } 1544*3526Sxy150489 return; 1545*3526Sxy150489 1546*3526Sxy150489 } else { 1547*3526Sxy150489 E1000_WRITE_REG(&Adapter->Shared, TDT, 1548*3526Sxy150489 hw_tdt); 1549*3526Sxy150489 e1000_update_tx_fifo_head(&Adapter->Shared, 1550*3526Sxy150489 length); 1551*3526Sxy150489 length = 0; 1552*3526Sxy150489 } 1553*3526Sxy150489 } 1554*3526Sxy150489 } 1555*3526Sxy150489 } 1556*3526Sxy150489 1557*3526Sxy150489 static void 1558*3526Sxy150489 e1000g_82547_timeout(void *arg) 1559*3526Sxy150489 { 1560*3526Sxy150489 e1000g_tx_ring_t *tx_ring; 1561*3526Sxy150489 1562*3526Sxy150489 tx_ring = (e1000g_tx_ring_t *)arg; 1563*3526Sxy150489 1564*3526Sxy150489 mutex_enter(&tx_ring->tx_lock); 1565*3526Sxy150489 1566*3526Sxy150489 tx_ring->timer_id_82547 = 0; 1567*3526Sxy150489 e1000g_82547_tx_move_tail_work(tx_ring); 1568*3526Sxy150489 1569*3526Sxy150489 mutex_exit(&tx_ring->tx_lock); 1570*3526Sxy150489 } 1571*3526Sxy150489 1572*3526Sxy150489 static void 1573*3526Sxy150489 e1000g_82547_tx_move_tail(e1000g_tx_ring_t *tx_ring) 1574*3526Sxy150489 { 1575*3526Sxy150489 timeout_id_t tid; 1576*3526Sxy150489 1577*3526Sxy150489 ASSERT(MUTEX_HELD(&tx_ring->tx_lock)); 1578*3526Sxy150489 1579*3526Sxy150489 tid = tx_ring->timer_id_82547; 1580*3526Sxy150489 tx_ring->timer_id_82547 = 0; 1581*3526Sxy150489 if (tid != 0) { 1582*3526Sxy150489 tx_ring->timer_enable_82547 = B_FALSE; 1583*3526Sxy150489 mutex_exit(&tx_ring->tx_lock); 1584*3526Sxy150489 1585*3526Sxy150489 (void) untimeout(tid); 1586*3526Sxy150489 1587*3526Sxy150489 mutex_enter(&tx_ring->tx_lock); 1588*3526Sxy150489 } 1589*3526Sxy150489 tx_ring->timer_enable_82547 = B_TRUE; 1590*3526Sxy150489 e1000g_82547_tx_move_tail_work(tx_ring); 1591*3526Sxy150489 } 1592