1*9865SSaurabh.Mishra@Sun.COM /* 2*9865SSaurabh.Mishra@Sun.COM * CDDL HEADER START 3*9865SSaurabh.Mishra@Sun.COM * 4*9865SSaurabh.Mishra@Sun.COM * The contents of this file are subject to the terms of the 5*9865SSaurabh.Mishra@Sun.COM * Common Development and Distribution License (the "License"). 6*9865SSaurabh.Mishra@Sun.COM * You may not use this file except in compliance with the License. 7*9865SSaurabh.Mishra@Sun.COM * 8*9865SSaurabh.Mishra@Sun.COM * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*9865SSaurabh.Mishra@Sun.COM * or http://www.opensolaris.org/os/licensing. 10*9865SSaurabh.Mishra@Sun.COM * See the License for the specific language governing permissions 11*9865SSaurabh.Mishra@Sun.COM * and limitations under the License. 12*9865SSaurabh.Mishra@Sun.COM * 13*9865SSaurabh.Mishra@Sun.COM * When distributing Covered Code, include this CDDL HEADER in each 14*9865SSaurabh.Mishra@Sun.COM * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*9865SSaurabh.Mishra@Sun.COM * If applicable, add the following below this CDDL HEADER, with the 16*9865SSaurabh.Mishra@Sun.COM * fields enclosed by brackets "[]" replaced with your own identifying 17*9865SSaurabh.Mishra@Sun.COM * information: Portions Copyright [yyyy] [name of copyright owner] 18*9865SSaurabh.Mishra@Sun.COM * 19*9865SSaurabh.Mishra@Sun.COM * CDDL HEADER END 20*9865SSaurabh.Mishra@Sun.COM */ 21*9865SSaurabh.Mishra@Sun.COM 22*9865SSaurabh.Mishra@Sun.COM /* 23*9865SSaurabh.Mishra@Sun.COM * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24*9865SSaurabh.Mishra@Sun.COM * Use is subject to license terms. 25*9865SSaurabh.Mishra@Sun.COM */ 26*9865SSaurabh.Mishra@Sun.COM 27*9865SSaurabh.Mishra@Sun.COM #ifndef _BFE_H 28*9865SSaurabh.Mishra@Sun.COM #define _BFE_H 29*9865SSaurabh.Mishra@Sun.COM 30*9865SSaurabh.Mishra@Sun.COM #include "bfe_hw.h" 31*9865SSaurabh.Mishra@Sun.COM 32*9865SSaurabh.Mishra@Sun.COM #ifdef __cplusplus 33*9865SSaurabh.Mishra@Sun.COM extern "C" { 34*9865SSaurabh.Mishra@Sun.COM #endif 35*9865SSaurabh.Mishra@Sun.COM 36*9865SSaurabh.Mishra@Sun.COM #define BFE_SUCCESS DDI_SUCCESS 37*9865SSaurabh.Mishra@Sun.COM #define BFE_FAILURE DDI_FAILURE 38*9865SSaurabh.Mishra@Sun.COM 39*9865SSaurabh.Mishra@Sun.COM #define BFE_MAX_MULTICAST_TABLE 64 40*9865SSaurabh.Mishra@Sun.COM 41*9865SSaurabh.Mishra@Sun.COM #define BFE_LINK_SPEED_10MBS 1 42*9865SSaurabh.Mishra@Sun.COM #define BFE_LINK_SPEED_100MBS 2 43*9865SSaurabh.Mishra@Sun.COM 44*9865SSaurabh.Mishra@Sun.COM #define VTAG_SIZE 4 45*9865SSaurabh.Mishra@Sun.COM 46*9865SSaurabh.Mishra@Sun.COM #define BFE_MTU ETHERMTU 47*9865SSaurabh.Mishra@Sun.COM 48*9865SSaurabh.Mishra@Sun.COM /* 49*9865SSaurabh.Mishra@Sun.COM * Use to increment descriptor slot number. 50*9865SSaurabh.Mishra@Sun.COM */ 51*9865SSaurabh.Mishra@Sun.COM #define BFE_INC_SLOT(i, p2) \ 52*9865SSaurabh.Mishra@Sun.COM (i = ((i + 1) & (p2 - 1))) 53*9865SSaurabh.Mishra@Sun.COM 54*9865SSaurabh.Mishra@Sun.COM #define BFE_DEC_SLOT(i, p2) \ 55*9865SSaurabh.Mishra@Sun.COM (i = ((i + p2 - 1) % p2)) 56*9865SSaurabh.Mishra@Sun.COM 57*9865SSaurabh.Mishra@Sun.COM /* 58*9865SSaurabh.Mishra@Sun.COM * I/O instructions 59*9865SSaurabh.Mishra@Sun.COM */ 60*9865SSaurabh.Mishra@Sun.COM #define OUTB(bfe, p, v) \ 61*9865SSaurabh.Mishra@Sun.COM ddi_put8((bfe)->bfe_mem_regset.hdl, \ 62*9865SSaurabh.Mishra@Sun.COM (void *)((caddr_t)((bfe)->bfe_mem_regset.addr) + (p)), v) 63*9865SSaurabh.Mishra@Sun.COM 64*9865SSaurabh.Mishra@Sun.COM #define OUTW(bfe, p, v) \ 65*9865SSaurabh.Mishra@Sun.COM ddi_put16((bfe)->bfe_mem_regset.hdl, \ 66*9865SSaurabh.Mishra@Sun.COM (void *)((caddr_t)((bfe)->bfe_mem_regset.addr) + (p)), v) 67*9865SSaurabh.Mishra@Sun.COM 68*9865SSaurabh.Mishra@Sun.COM #define OUTL(bfe, p, v) \ 69*9865SSaurabh.Mishra@Sun.COM ddi_put32((bfe)->bfe_mem_regset.hdl, \ 70*9865SSaurabh.Mishra@Sun.COM (void *)((caddr_t)((bfe)->bfe_mem_regset.addr) + (p)), v) 71*9865SSaurabh.Mishra@Sun.COM 72*9865SSaurabh.Mishra@Sun.COM #define INB(bfe, p) \ 73*9865SSaurabh.Mishra@Sun.COM ddi_get8((bfe)->bfe_mem_regset.hdl, \ 74*9865SSaurabh.Mishra@Sun.COM (void *)(((caddr_t)(bfe)->bfe_mem_regset.addr) + (p))) 75*9865SSaurabh.Mishra@Sun.COM #define INW(bfe, p) \ 76*9865SSaurabh.Mishra@Sun.COM ddi_get16((bfe)->bfe_mem_regset.hdl, \ 77*9865SSaurabh.Mishra@Sun.COM (void *)(((caddr_t)(bfe)->bfe_mem_regset.addr) + (p))) 78*9865SSaurabh.Mishra@Sun.COM 79*9865SSaurabh.Mishra@Sun.COM #define INL(bfe, p) \ 80*9865SSaurabh.Mishra@Sun.COM ddi_get32((bfe)->bfe_mem_regset.hdl, \ 81*9865SSaurabh.Mishra@Sun.COM (void *)(((caddr_t)(bfe)->bfe_mem_regset.addr) + (p))) 82*9865SSaurabh.Mishra@Sun.COM 83*9865SSaurabh.Mishra@Sun.COM #define FLUSH(bfe, reg) \ 84*9865SSaurabh.Mishra@Sun.COM (void) INL(bfe, reg) 85*9865SSaurabh.Mishra@Sun.COM 86*9865SSaurabh.Mishra@Sun.COM #define OUTL_OR(bfe, reg, v) \ 87*9865SSaurabh.Mishra@Sun.COM OUTL(bfe, reg, (INL(bfe, reg) | v)) 88*9865SSaurabh.Mishra@Sun.COM 89*9865SSaurabh.Mishra@Sun.COM #define OUTL_AND(bfe, reg, v) \ 90*9865SSaurabh.Mishra@Sun.COM OUTL(bfe, reg, (INL(bfe, reg) & v)) 91*9865SSaurabh.Mishra@Sun.COM 92*9865SSaurabh.Mishra@Sun.COM /* 93*9865SSaurabh.Mishra@Sun.COM * These macros allows use to write to descriptor memory. 94*9865SSaurabh.Mishra@Sun.COM */ 95*9865SSaurabh.Mishra@Sun.COM #define PUT_DESC(r, member, val) \ 96*9865SSaurabh.Mishra@Sun.COM ddi_put32(r->r_desc_acc_handle, (member), (val)) 97*9865SSaurabh.Mishra@Sun.COM 98*9865SSaurabh.Mishra@Sun.COM #define GET_DESC(r, member) \ 99*9865SSaurabh.Mishra@Sun.COM ddi_get32(r->r_desc_acc_handle, (member)) 100*9865SSaurabh.Mishra@Sun.COM 101*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_cards { 102*9865SSaurabh.Mishra@Sun.COM uint16_t vendor_id; 103*9865SSaurabh.Mishra@Sun.COM uint16_t device_id; 104*9865SSaurabh.Mishra@Sun.COM char *cardname; 105*9865SSaurabh.Mishra@Sun.COM } bfe_cards_t; 106*9865SSaurabh.Mishra@Sun.COM 107*9865SSaurabh.Mishra@Sun.COM 108*9865SSaurabh.Mishra@Sun.COM /* 109*9865SSaurabh.Mishra@Sun.COM * Chip's state. 110*9865SSaurabh.Mishra@Sun.COM */ 111*9865SSaurabh.Mishra@Sun.COM typedef enum { 112*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_UNINITIALIZED = 0, 113*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_INITIALIZED, 114*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_ACTIVE, 115*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_STOPPED, 116*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_HALT, 117*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_RESUME, 118*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_SUSPENDED, 119*9865SSaurabh.Mishra@Sun.COM BFE_CHIP_QUIESCED 120*9865SSaurabh.Mishra@Sun.COM } bfe_chip_state_t; 121*9865SSaurabh.Mishra@Sun.COM 122*9865SSaurabh.Mishra@Sun.COM /* 123*9865SSaurabh.Mishra@Sun.COM * PHY state. 124*9865SSaurabh.Mishra@Sun.COM */ 125*9865SSaurabh.Mishra@Sun.COM typedef enum { 126*9865SSaurabh.Mishra@Sun.COM BFE_PHY_STARTED = 1, 127*9865SSaurabh.Mishra@Sun.COM BFE_PHY_STOPPED, 128*9865SSaurabh.Mishra@Sun.COM BFE_PHY_RESET_DONE, 129*9865SSaurabh.Mishra@Sun.COM BFE_PHY_RESET_TIMEOUT, 130*9865SSaurabh.Mishra@Sun.COM BFE_PHY_NOTFOUND 131*9865SSaurabh.Mishra@Sun.COM } bfe_phy_state_t; 132*9865SSaurabh.Mishra@Sun.COM 133*9865SSaurabh.Mishra@Sun.COM /* 134*9865SSaurabh.Mishra@Sun.COM * Chip's mode 135*9865SSaurabh.Mishra@Sun.COM */ 136*9865SSaurabh.Mishra@Sun.COM #define BFE_RX_MODE_ENABLE 0x1 137*9865SSaurabh.Mishra@Sun.COM #define BFE_RX_MODE_PROMISC 0x2 138*9865SSaurabh.Mishra@Sun.COM #define BFE_RX_MODE_BROADCAST 0x4 139*9865SSaurabh.Mishra@Sun.COM #define BFE_RX_MODE_ALLMULTI 0x8 140*9865SSaurabh.Mishra@Sun.COM 141*9865SSaurabh.Mishra@Sun.COM /* 142*9865SSaurabh.Mishra@Sun.COM * Every packet has this header which is put by the card. 143*9865SSaurabh.Mishra@Sun.COM */ 144*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_rx_header { 145*9865SSaurabh.Mishra@Sun.COM uint16_t len; 146*9865SSaurabh.Mishra@Sun.COM uint16_t flags; 147*9865SSaurabh.Mishra@Sun.COM uint16_t pad[12]; 148*9865SSaurabh.Mishra@Sun.COM } bfe_rx_header_t; 149*9865SSaurabh.Mishra@Sun.COM 150*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_stats { 151*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_align_errors; 152*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_carrier_errors; 153*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_ex_collisions; 154*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_fcs_errors; 155*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_first_collisions; 156*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_macrcv_errors; 157*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_macxmt_errors; 158*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_multi_collisions; 159*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_toolong_errors; 160*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_tooshort_errors; 161*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_tx_late_collisions; 162*9865SSaurabh.Mishra@Sun.COM uint64_t ether_stat_defer_xmts; 163*9865SSaurabh.Mishra@Sun.COM uint64_t brdcstrcv; 164*9865SSaurabh.Mishra@Sun.COM uint64_t brdcstxmt; 165*9865SSaurabh.Mishra@Sun.COM uint64_t multixmt; 166*9865SSaurabh.Mishra@Sun.COM uint64_t collisions; 167*9865SSaurabh.Mishra@Sun.COM uint64_t ierrors; 168*9865SSaurabh.Mishra@Sun.COM uint64_t ipackets; 169*9865SSaurabh.Mishra@Sun.COM uint64_t multircv; 170*9865SSaurabh.Mishra@Sun.COM uint64_t norcvbuf; 171*9865SSaurabh.Mishra@Sun.COM uint64_t noxmtbuf; 172*9865SSaurabh.Mishra@Sun.COM uint64_t obytes; 173*9865SSaurabh.Mishra@Sun.COM uint64_t opackets; 174*9865SSaurabh.Mishra@Sun.COM uint64_t rbytes; 175*9865SSaurabh.Mishra@Sun.COM uint64_t underflows; 176*9865SSaurabh.Mishra@Sun.COM uint64_t overflows; 177*9865SSaurabh.Mishra@Sun.COM uint64_t txchecks; 178*9865SSaurabh.Mishra@Sun.COM uint64_t intr_claimed; 179*9865SSaurabh.Mishra@Sun.COM uint64_t intr_unclaimed; 180*9865SSaurabh.Mishra@Sun.COM uint64_t linkchanges; 181*9865SSaurabh.Mishra@Sun.COM uint64_t txcpybytes; 182*9865SSaurabh.Mishra@Sun.COM uint64_t txmapbytes; 183*9865SSaurabh.Mishra@Sun.COM uint64_t rxcpybytes; 184*9865SSaurabh.Mishra@Sun.COM uint64_t rxmapbytes; 185*9865SSaurabh.Mishra@Sun.COM uint64_t txreclaim0; 186*9865SSaurabh.Mishra@Sun.COM uint64_t txreclaims; 187*9865SSaurabh.Mishra@Sun.COM uint32_t txstalls; 188*9865SSaurabh.Mishra@Sun.COM uint32_t resets; 189*9865SSaurabh.Mishra@Sun.COM } bfe_stats_t; 190*9865SSaurabh.Mishra@Sun.COM 191*9865SSaurabh.Mishra@Sun.COM typedef struct { 192*9865SSaurabh.Mishra@Sun.COM int state; 193*9865SSaurabh.Mishra@Sun.COM int speed; 194*9865SSaurabh.Mishra@Sun.COM int duplex; 195*9865SSaurabh.Mishra@Sun.COM int flowctrl; 196*9865SSaurabh.Mishra@Sun.COM int mau; 197*9865SSaurabh.Mishra@Sun.COM } bfe_link_t; 198*9865SSaurabh.Mishra@Sun.COM 199*9865SSaurabh.Mishra@Sun.COM /* 200*9865SSaurabh.Mishra@Sun.COM * Device registers handle 201*9865SSaurabh.Mishra@Sun.COM */ 202*9865SSaurabh.Mishra@Sun.COM typedef struct { 203*9865SSaurabh.Mishra@Sun.COM ddi_acc_handle_t hdl; 204*9865SSaurabh.Mishra@Sun.COM caddr_t addr; 205*9865SSaurabh.Mishra@Sun.COM } bfe_acc_t; 206*9865SSaurabh.Mishra@Sun.COM 207*9865SSaurabh.Mishra@Sun.COM /* 208*9865SSaurabh.Mishra@Sun.COM * BCM4401 Chip state 209*9865SSaurabh.Mishra@Sun.COM */ 210*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_chip { 211*9865SSaurabh.Mishra@Sun.COM int link; 212*9865SSaurabh.Mishra@Sun.COM int state; 213*9865SSaurabh.Mishra@Sun.COM int speed; 214*9865SSaurabh.Mishra@Sun.COM int duplex; 215*9865SSaurabh.Mishra@Sun.COM uint32_t bmsr; 216*9865SSaurabh.Mishra@Sun.COM uint32_t phyaddr; 217*9865SSaurabh.Mishra@Sun.COM } bfe_chip_t; 218*9865SSaurabh.Mishra@Sun.COM 219*9865SSaurabh.Mishra@Sun.COM 220*9865SSaurabh.Mishra@Sun.COM /* 221*9865SSaurabh.Mishra@Sun.COM * Ring Management framework. 222*9865SSaurabh.Mishra@Sun.COM */ 223*9865SSaurabh.Mishra@Sun.COM 224*9865SSaurabh.Mishra@Sun.COM /* 225*9865SSaurabh.Mishra@Sun.COM * TX and RX descriptor format in the hardware. 226*9865SSaurabh.Mishra@Sun.COM */ 227*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_desc { 228*9865SSaurabh.Mishra@Sun.COM volatile uint32_t desc_ctl; 229*9865SSaurabh.Mishra@Sun.COM volatile uint32_t desc_addr; 230*9865SSaurabh.Mishra@Sun.COM } bfe_desc_t; 231*9865SSaurabh.Mishra@Sun.COM 232*9865SSaurabh.Mishra@Sun.COM /* 233*9865SSaurabh.Mishra@Sun.COM * DMA handle for each descriptor 234*9865SSaurabh.Mishra@Sun.COM */ 235*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_dma { 236*9865SSaurabh.Mishra@Sun.COM ddi_dma_handle_t handle; 237*9865SSaurabh.Mishra@Sun.COM ddi_acc_handle_t acchdl; 238*9865SSaurabh.Mishra@Sun.COM ddi_dma_cookie_t cookie; 239*9865SSaurabh.Mishra@Sun.COM caddr_t addr; 240*9865SSaurabh.Mishra@Sun.COM size_t len; 241*9865SSaurabh.Mishra@Sun.COM } bfe_dma_t; 242*9865SSaurabh.Mishra@Sun.COM 243*9865SSaurabh.Mishra@Sun.COM /* Keep it power of 2 */ 244*9865SSaurabh.Mishra@Sun.COM #define TX_NUM_DESC 128 245*9865SSaurabh.Mishra@Sun.COM #define RX_NUM_DESC 128 246*9865SSaurabh.Mishra@Sun.COM 247*9865SSaurabh.Mishra@Sun.COM 248*9865SSaurabh.Mishra@Sun.COM #define BFE_RING_UNALLOCATED 0 249*9865SSaurabh.Mishra@Sun.COM #define BFE_RING_ALLOCATED 1 250*9865SSaurabh.Mishra@Sun.COM 251*9865SSaurabh.Mishra@Sun.COM struct bfe; 252*9865SSaurabh.Mishra@Sun.COM 253*9865SSaurabh.Mishra@Sun.COM typedef struct bfe_ring { 254*9865SSaurabh.Mishra@Sun.COM /* Lock for the ring */ 255*9865SSaurabh.Mishra@Sun.COM kmutex_t r_lock; 256*9865SSaurabh.Mishra@Sun.COM 257*9865SSaurabh.Mishra@Sun.COM /* Actual lock pointer. It may point to global lock */ 258*9865SSaurabh.Mishra@Sun.COM kmutex_t *r_lockp; 259*9865SSaurabh.Mishra@Sun.COM 260*9865SSaurabh.Mishra@Sun.COM /* DMA handle for all buffers in descriptor table */ 261*9865SSaurabh.Mishra@Sun.COM bfe_dma_t *r_buf_dma; 262*9865SSaurabh.Mishra@Sun.COM 263*9865SSaurabh.Mishra@Sun.COM /* DMA buffer holding descriptor table */ 264*9865SSaurabh.Mishra@Sun.COM bfe_desc_t *r_desc; 265*9865SSaurabh.Mishra@Sun.COM 266*9865SSaurabh.Mishra@Sun.COM /* DMA handle for the descriptor table */ 267*9865SSaurabh.Mishra@Sun.COM ddi_dma_handle_t r_desc_dma_handle; 268*9865SSaurabh.Mishra@Sun.COM ddi_acc_handle_t r_desc_acc_handle; 269*9865SSaurabh.Mishra@Sun.COM ddi_dma_cookie_t r_desc_cookie; 270*9865SSaurabh.Mishra@Sun.COM uint32_t r_ndesc; /* number of descriptors for the ring */ 271*9865SSaurabh.Mishra@Sun.COM size_t r_desc_len; /* Actual descriptor size */ 272*9865SSaurabh.Mishra@Sun.COM 273*9865SSaurabh.Mishra@Sun.COM /* DMA buffer length */ 274*9865SSaurabh.Mishra@Sun.COM size_t r_buf_len; 275*9865SSaurabh.Mishra@Sun.COM 276*9865SSaurabh.Mishra@Sun.COM /* Flags associated to the ring */ 277*9865SSaurabh.Mishra@Sun.COM int r_flags; 278*9865SSaurabh.Mishra@Sun.COM 279*9865SSaurabh.Mishra@Sun.COM /* Pointer back to bfe instance */ 280*9865SSaurabh.Mishra@Sun.COM struct bfe *r_bfe; 281*9865SSaurabh.Mishra@Sun.COM 282*9865SSaurabh.Mishra@Sun.COM /* Current slot number (or descriptor number) in the ring */ 283*9865SSaurabh.Mishra@Sun.COM uint_t r_curr_desc; 284*9865SSaurabh.Mishra@Sun.COM /* Consumed descriptor if got the interrupt (only used for TX) */ 285*9865SSaurabh.Mishra@Sun.COM uint_t r_cons_desc; 286*9865SSaurabh.Mishra@Sun.COM 287*9865SSaurabh.Mishra@Sun.COM uint_t r_avail_desc; 288*9865SSaurabh.Mishra@Sun.COM } bfe_ring_t; 289*9865SSaurabh.Mishra@Sun.COM 290*9865SSaurabh.Mishra@Sun.COM /* 291*9865SSaurabh.Mishra@Sun.COM * Device driver's private data per instance. 292*9865SSaurabh.Mishra@Sun.COM */ 293*9865SSaurabh.Mishra@Sun.COM typedef struct bfe { 294*9865SSaurabh.Mishra@Sun.COM /* devinfo stuff */ 295*9865SSaurabh.Mishra@Sun.COM dev_info_t *bfe_dip; 296*9865SSaurabh.Mishra@Sun.COM int bfe_unit; 297*9865SSaurabh.Mishra@Sun.COM 298*9865SSaurabh.Mishra@Sun.COM /* PCI Configuration handle */ 299*9865SSaurabh.Mishra@Sun.COM ddi_acc_handle_t bfe_conf_handle; 300*9865SSaurabh.Mishra@Sun.COM 301*9865SSaurabh.Mishra@Sun.COM /* Device registers handle and regset */ 302*9865SSaurabh.Mishra@Sun.COM bfe_acc_t bfe_mem_regset; 303*9865SSaurabh.Mishra@Sun.COM 304*9865SSaurabh.Mishra@Sun.COM /* Ethernet addr */ 305*9865SSaurabh.Mishra@Sun.COM ether_addr_t bfe_ether_addr; 306*9865SSaurabh.Mishra@Sun.COM ether_addr_t bfe_dev_addr; 307*9865SSaurabh.Mishra@Sun.COM 308*9865SSaurabh.Mishra@Sun.COM /* MAC layer handle */ 309*9865SSaurabh.Mishra@Sun.COM mac_handle_t bfe_machdl; 310*9865SSaurabh.Mishra@Sun.COM 311*9865SSaurabh.Mishra@Sun.COM /* Interrupt management */ 312*9865SSaurabh.Mishra@Sun.COM ddi_intr_handle_t bfe_intrhdl; 313*9865SSaurabh.Mishra@Sun.COM uint_t bfe_intrpri; 314*9865SSaurabh.Mishra@Sun.COM 315*9865SSaurabh.Mishra@Sun.COM /* Ring Management */ 316*9865SSaurabh.Mishra@Sun.COM bfe_ring_t bfe_tx_ring; 317*9865SSaurabh.Mishra@Sun.COM bfe_ring_t bfe_rx_ring; 318*9865SSaurabh.Mishra@Sun.COM int bfe_tx_resched; 319*9865SSaurabh.Mishra@Sun.COM 320*9865SSaurabh.Mishra@Sun.COM /* Chip details */ 321*9865SSaurabh.Mishra@Sun.COM bfe_chip_t bfe_chip; 322*9865SSaurabh.Mishra@Sun.COM bfe_stats_t bfe_stats; 323*9865SSaurabh.Mishra@Sun.COM bfe_chip_state_t bfe_chip_state; 324*9865SSaurabh.Mishra@Sun.COM uint_t bfe_chip_mode; 325*9865SSaurabh.Mishra@Sun.COM int32_t bfe_phy_addr; 326*9865SSaurabh.Mishra@Sun.COM uchar_t bfe_chip_action; 327*9865SSaurabh.Mishra@Sun.COM bfe_hw_stats_t bfe_hw_stats; 328*9865SSaurabh.Mishra@Sun.COM 329*9865SSaurabh.Mishra@Sun.COM /* rw lock for chip */ 330*9865SSaurabh.Mishra@Sun.COM krwlock_t bfe_rwlock; 331*9865SSaurabh.Mishra@Sun.COM 332*9865SSaurabh.Mishra@Sun.COM /* Multicast table */ 333*9865SSaurabh.Mishra@Sun.COM uint32_t bfe_mcast_cnt; 334*9865SSaurabh.Mishra@Sun.COM 335*9865SSaurabh.Mishra@Sun.COM /* Timeout and PHY state */ 336*9865SSaurabh.Mishra@Sun.COM ddi_periodic_t bfe_periodic_id; 337*9865SSaurabh.Mishra@Sun.COM hrtime_t bfe_tx_stall_time; 338*9865SSaurabh.Mishra@Sun.COM bfe_phy_state_t bfe_phy_state; 339*9865SSaurabh.Mishra@Sun.COM int bfe_phy_id; 340*9865SSaurabh.Mishra@Sun.COM 341*9865SSaurabh.Mishra@Sun.COM /* MII register set */ 342*9865SSaurabh.Mishra@Sun.COM uint16_t bfe_mii_exp; 343*9865SSaurabh.Mishra@Sun.COM uint16_t bfe_mii_bmsr; 344*9865SSaurabh.Mishra@Sun.COM uint16_t bfe_mii_anar; 345*9865SSaurabh.Mishra@Sun.COM uint16_t bfe_mii_anlpar; 346*9865SSaurabh.Mishra@Sun.COM uint16_t bfe_mii_bmcr; 347*9865SSaurabh.Mishra@Sun.COM 348*9865SSaurabh.Mishra@Sun.COM /* Transceiver fields */ 349*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_aneg; 350*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_100T4; 351*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_100fdx; 352*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_100hdx; 353*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_10fdx; 354*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_adv_10hdx; 355*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_aneg; 356*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_100T4; 357*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_100fdx; 358*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_100hdx; 359*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_10fdx; 360*9865SSaurabh.Mishra@Sun.COM uint8_t bfe_cap_10hdx; 361*9865SSaurabh.Mishra@Sun.COM } bfe_t; 362*9865SSaurabh.Mishra@Sun.COM 363*9865SSaurabh.Mishra@Sun.COM static int bfe_identify_hardware(bfe_t *); 364*9865SSaurabh.Mishra@Sun.COM 365*9865SSaurabh.Mishra@Sun.COM #ifdef __cplusplus 366*9865SSaurabh.Mishra@Sun.COM } 367*9865SSaurabh.Mishra@Sun.COM #endif 368*9865SSaurabh.Mishra@Sun.COM #endif /* _BFE_H */ 369