1*9999SWang.Lin@Sun.COM /* 2*9999SWang.Lin@Sun.COM * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3*9999SWang.Lin@Sun.COM * Use is subject to license terms. 4*9999SWang.Lin@Sun.COM */ 5*9999SWang.Lin@Sun.COM 6*9999SWang.Lin@Sun.COM /* 7*9999SWang.Lin@Sun.COM * Copyright (c) 2008 Atheros Communications Inc. 8*9999SWang.Lin@Sun.COM * 9*9999SWang.Lin@Sun.COM * Permission to use, copy, modify, and/or distribute this software for any 10*9999SWang.Lin@Sun.COM * purpose with or without fee is hereby granted, provided that the above 11*9999SWang.Lin@Sun.COM * copyright notice and this permission notice appear in all copies. 12*9999SWang.Lin@Sun.COM * 13*9999SWang.Lin@Sun.COM * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14*9999SWang.Lin@Sun.COM * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15*9999SWang.Lin@Sun.COM * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16*9999SWang.Lin@Sun.COM * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17*9999SWang.Lin@Sun.COM * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18*9999SWang.Lin@Sun.COM * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19*9999SWang.Lin@Sun.COM * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20*9999SWang.Lin@Sun.COM */ 21*9999SWang.Lin@Sun.COM 22*9999SWang.Lin@Sun.COM #ifndef _ARN_PHY_H 23*9999SWang.Lin@Sun.COM #define _ARN_PHY_H 24*9999SWang.Lin@Sun.COM 25*9999SWang.Lin@Sun.COM #ifdef __cplusplus 26*9999SWang.Lin@Sun.COM extern "C" { 27*9999SWang.Lin@Sun.COM #endif 28*9999SWang.Lin@Sun.COM 29*9999SWang.Lin@Sun.COM boolean_t ath9k_hw_ar9280_set_channel(struct ath_hal *ah, 30*9999SWang.Lin@Sun.COM struct ath9k_channel *chan); 31*9999SWang.Lin@Sun.COM boolean_t ath9k_hw_set_channel(struct ath_hal *ah, 32*9999SWang.Lin@Sun.COM struct ath9k_channel *chan); 33*9999SWang.Lin@Sun.COM void ath9k_hw_write_regs(struct ath_hal *ah, uint32_t modesIndex, 34*9999SWang.Lin@Sun.COM uint32_t freqIndex, int regWrites); 35*9999SWang.Lin@Sun.COM boolean_t ath9k_hw_set_rf_regs(struct ath_hal *ah, 36*9999SWang.Lin@Sun.COM struct ath9k_channel *chan, uint16_t modesIndex); 37*9999SWang.Lin@Sun.COM void ath9k_hw_decrease_chain_power(struct ath_hal *ah, 38*9999SWang.Lin@Sun.COM struct ath9k_channel *chan); 39*9999SWang.Lin@Sun.COM boolean_t ath9k_hw_init_rf(struct ath_hal *ah, int *status); 40*9999SWang.Lin@Sun.COM 41*9999SWang.Lin@Sun.COM #define AR_PHY_BASE 0x9800 42*9999SWang.Lin@Sun.COM #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 43*9999SWang.Lin@Sun.COM 44*9999SWang.Lin@Sun.COM #define AR_PHY_TEST 0x9800 45*9999SWang.Lin@Sun.COM #define PHY_AGC_CLR 0x10000000 46*9999SWang.Lin@Sun.COM #define RFSILENT_BB 0x00002000 47*9999SWang.Lin@Sun.COM 48*9999SWang.Lin@Sun.COM #define AR_PHY_TURBO 0x9804 49*9999SWang.Lin@Sun.COM #define AR_PHY_FC_TURBO_MODE 0x00000001 50*9999SWang.Lin@Sun.COM #define AR_PHY_FC_TURBO_SHORT 0x00000002 51*9999SWang.Lin@Sun.COM #define AR_PHY_FC_DYN2040_EN 0x00000004 52*9999SWang.Lin@Sun.COM #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 53*9999SWang.Lin@Sun.COM #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 54*9999SWang.Lin@Sun.COM #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 55*9999SWang.Lin@Sun.COM #define AR_PHY_FC_HT_EN 0x00000040 56*9999SWang.Lin@Sun.COM #define AR_PHY_FC_SHORT_GI_40 0x00000080 57*9999SWang.Lin@Sun.COM #define AR_PHY_FC_WALSH 0x00000100 58*9999SWang.Lin@Sun.COM #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 59*9999SWang.Lin@Sun.COM #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 60*9999SWang.Lin@Sun.COM #define AR_PHY_TEST2 0x9808 61*9999SWang.Lin@Sun.COM 62*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING2 0x9810 63*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING3 0x9814 64*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 65*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING3_DSC_MAN_S 17 66*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 67*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING3_DSC_EXP_S 13 68*9999SWang.Lin@Sun.COM 69*9999SWang.Lin@Sun.COM #define AR_PHY_CHIP_ID 0x9818 70*9999SWang.Lin@Sun.COM #define AR_PHY_CHIP_ID_REV_0 0x80 71*9999SWang.Lin@Sun.COM #define AR_PHY_CHIP_ID_REV_1 0x81 72*9999SWang.Lin@Sun.COM #define AR_PHY_CHIP_ID_9160_REV_0 0xb0 73*9999SWang.Lin@Sun.COM 74*9999SWang.Lin@Sun.COM #define AR_PHY_ACTIVE 0x981C 75*9999SWang.Lin@Sun.COM #define AR_PHY_ACTIVE_EN 0x00000001 76*9999SWang.Lin@Sun.COM #define AR_PHY_ACTIVE_DIS 0x00000000 77*9999SWang.Lin@Sun.COM 78*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL2 0x9824 79*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_DATA_START 0x000000FF 80*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_DATA_START_S 0 81*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_PA_ON 0x0000FF00 82*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_PA_ON_S 8 83*9999SWang.Lin@Sun.COM 84*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL3 0x9828 85*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 86*9999SWang.Lin@Sun.COM #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 87*9999SWang.Lin@Sun.COM 88*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL 0x982C 89*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 90*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 91*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 92*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 93*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 94*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 95*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 96*9999SWang.Lin@Sun.COM 97*9999SWang.Lin@Sun.COM #define AR_PHY_ADC_SERIAL_CTL 0x9830 98*9999SWang.Lin@Sun.COM #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 99*9999SWang.Lin@Sun.COM #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 100*9999SWang.Lin@Sun.COM 101*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4 0x9834 102*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 103*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 104*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 105*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 106*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 107*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 108*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 109*9999SWang.Lin@Sun.COM #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 110*9999SWang.Lin@Sun.COM #define AR_PHY_TSTDAC_CONST 0x983c 111*9999SWang.Lin@Sun.COM 112*9999SWang.Lin@Sun.COM #define AR_PHY_SETTLING 0x9844 113*9999SWang.Lin@Sun.COM #define AR_PHY_SETTLING_SWITCH 0x00003F80 114*9999SWang.Lin@Sun.COM #define AR_PHY_SETTLING_SWITCH_S 7 115*9999SWang.Lin@Sun.COM 116*9999SWang.Lin@Sun.COM #define AR_PHY_RXGAIN 0x9848 117*9999SWang.Lin@Sun.COM #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 118*9999SWang.Lin@Sun.COM #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 119*9999SWang.Lin@Sun.COM #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 120*9999SWang.Lin@Sun.COM #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 121*9999SWang.Lin@Sun.COM #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 122*9999SWang.Lin@Sun.COM #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 123*9999SWang.Lin@Sun.COM #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 124*9999SWang.Lin@Sun.COM #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 125*9999SWang.Lin@Sun.COM 126*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ 0x9850 127*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 128*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_ADC_S 0 129*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 130*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_PGA_S 8 131*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 132*9999SWang.Lin@Sun.COM #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 133*9999SWang.Lin@Sun.COM 134*9999SWang.Lin@Sun.COM #define AR_PHY_FIND_SIG 0x9858 135*9999SWang.Lin@Sun.COM #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 136*9999SWang.Lin@Sun.COM #define AR_PHY_FIND_SIG_FIRSTEP_S 12 137*9999SWang.Lin@Sun.COM #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 138*9999SWang.Lin@Sun.COM #define AR_PHY_FIND_SIG_FIRPWR_S 18 139*9999SWang.Lin@Sun.COM 140*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CTL1 0x985C 141*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 142*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 143*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 144*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 145*9999SWang.Lin@Sun.COM 146*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL 0x9860 147*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL_CAL 0x00000001 148*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL_NF 0x00000002 149*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 150*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 151*9999SWang.Lin@Sun.COM #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 152*9999SWang.Lin@Sun.COM 153*9999SWang.Lin@Sun.COM #define AR_PHY_CCA 0x9864 154*9999SWang.Lin@Sun.COM #define AR_PHY_MINCCA_PWR 0x0FF80000 155*9999SWang.Lin@Sun.COM #define AR_PHY_MINCCA_PWR_S 19 156*9999SWang.Lin@Sun.COM #define AR_PHY_CCA_THRESH62 0x0007F000 157*9999SWang.Lin@Sun.COM #define AR_PHY_CCA_THRESH62_S 12 158*9999SWang.Lin@Sun.COM #define AR9280_PHY_MINCCA_PWR 0x1FF00000 159*9999SWang.Lin@Sun.COM #define AR9280_PHY_MINCCA_PWR_S 20 160*9999SWang.Lin@Sun.COM #define AR9280_PHY_CCA_THRESH62 0x000FF000 161*9999SWang.Lin@Sun.COM #define AR9280_PHY_CCA_THRESH62_S 12 162*9999SWang.Lin@Sun.COM 163*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW 0x986C 164*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 165*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 166*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 167*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 168*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 169*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 170*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 171*9999SWang.Lin@Sun.COM 172*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR 0x9868 173*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 174*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M2COUNT_THR_S 0 175*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 176*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M1_THRESH_S 17 177*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 178*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_M2_THRESH_S 24 179*9999SWang.Lin@Sun.COM 180*9999SWang.Lin@Sun.COM #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 181*9999SWang.Lin@Sun.COM #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 182*9999SWang.Lin@Sun.COM #define AR_PHY_SYNTH_CONTROL 0x9874 183*9999SWang.Lin@Sun.COM #define AR_PHY_SLEEP_SCAL 0x9878 184*9999SWang.Lin@Sun.COM 185*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL 0x987c 186*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL_40 0xaa 187*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL_40_5413 0x04 188*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL_44 0xab 189*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL_44_2133 0xeb 190*9999SWang.Lin@Sun.COM #define AR_PHY_PLL_CTL_40_2133 0xea 191*9999SWang.Lin@Sun.COM 192*9999SWang.Lin@Sun.COM #define AR_PHY_RX_DELAY 0x9914 193*9999SWang.Lin@Sun.COM #define AR_PHY_SEARCH_START_DELAY 0x9918 194*9999SWang.Lin@Sun.COM #define AR_PHY_RX_DELAY_DELAY 0x00003FFF 195*9999SWang.Lin@Sun.COM 196*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) 197*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F 198*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 199*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 200*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 201*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 202*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 203*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 204*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 205*9999SWang.Lin@Sun.COM 206*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 207*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 208*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 209*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 210*9999SWang.Lin@Sun.COM 211*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING5 0x9924 212*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 213*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 214*9999SWang.Lin@Sun.COM 215*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE1 0x9934 216*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE2 0x9938 217*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE_MAX 0x993c 218*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 219*9999SWang.Lin@Sun.COM 220*9999SWang.Lin@Sun.COM #define AR_PHY_FRAME_CTL 0x9944 221*9999SWang.Lin@Sun.COM #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 222*9999SWang.Lin@Sun.COM #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 223*9999SWang.Lin@Sun.COM 224*9999SWang.Lin@Sun.COM #define AR_PHY_TXPWRADJ 0x994C 225*9999SWang.Lin@Sun.COM #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 226*9999SWang.Lin@Sun.COM #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 227*9999SWang.Lin@Sun.COM #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 228*9999SWang.Lin@Sun.COM #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 229*9999SWang.Lin@Sun.COM 230*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_EXT 0x9940 231*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_EXT_ENA 0x00004000 232*9999SWang.Lin@Sun.COM 233*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0 0x9954 234*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_ENA 0x00000001 235*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 236*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_INBAND 0x0000003e 237*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_INBAND_S 1 238*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 239*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_PRSSI_S 6 240*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 241*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_HEIGHT_S 12 242*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 243*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_RRSSI_S 18 244*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 245*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_0_FIRPWR_S 24 246*9999SWang.Lin@Sun.COM 247*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1 0x9958 248*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 249*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 250*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 251*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 252*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 253*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 254*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 255*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 256*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 257*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_MAXLEN 0x000000FF 258*9999SWang.Lin@Sun.COM #define AR_PHY_RADAR_1_MAXLEN_S 0 259*9999SWang.Lin@Sun.COM 260*9999SWang.Lin@Sun.COM #define AR_PHY_SWITCH_CHAIN_0 0x9960 261*9999SWang.Lin@Sun.COM #define AR_PHY_SWITCH_COM 0x9964 262*9999SWang.Lin@Sun.COM 263*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA 0x996C 264*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 265*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 266*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 267*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_FILT2_S 3 268*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 269*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_FILT1_S 8 270*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 271*9999SWang.Lin@Sun.COM #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 272*9999SWang.Lin@Sun.COM 273*9999SWang.Lin@Sun.COM #define AR_PHY_RESTART 0x9970 274*9999SWang.Lin@Sun.COM #define AR_PHY_RESTART_DIV_GC 0x001C0000 275*9999SWang.Lin@Sun.COM #define AR_PHY_RESTART_DIV_GC_S 18 276*9999SWang.Lin@Sun.COM 277*9999SWang.Lin@Sun.COM #define AR_PHY_RFBUS_REQ 0x997C 278*9999SWang.Lin@Sun.COM #define AR_PHY_RFBUS_REQ_EN 0x00000001 279*9999SWang.Lin@Sun.COM 280*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING7 0x9980 281*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING8 0x9984 282*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 283*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 284*9999SWang.Lin@Sun.COM 285*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_1 0x9988 286*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_2 0x998c 287*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_3 0x9990 288*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_4 0x9994 289*9999SWang.Lin@Sun.COM 290*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK_1 0x9900 291*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK_2 0x9904 292*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK_3 0x9908 293*9999SWang.Lin@Sun.COM 294*9999SWang.Lin@Sun.COM #define AR_PHY_MASK_CTL 0x990c 295*9999SWang.Lin@Sun.COM 296*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 297*9999SWang.Lin@Sun.COM #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 298*9999SWang.Lin@Sun.COM 299*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING9 0x9998 300*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING10 0x999c 301*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 302*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 303*9999SWang.Lin@Sun.COM 304*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11 0x99a0 305*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 306*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 307*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 308*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 309*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 310*9999SWang.Lin@Sun.COM #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 311*9999SWang.Lin@Sun.COM 312*9999SWang.Lin@Sun.COM #define AR_PHY_RX_CHAINMASK 0x99a4 313*9999SWang.Lin@Sun.COM #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 314*9999SWang.Lin@Sun.COM #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 315*9999SWang.Lin@Sun.COM #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 316*9999SWang.Lin@Sun.COM #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 317*9999SWang.Lin@Sun.COM 318*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA0 0x99b8 319*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 320*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA0_THRESH62_S 0 321*9999SWang.Lin@Sun.COM 322*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA 0x99bc 323*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 324*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 325*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 326*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_CCA_THRESH62_S 16 327*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_MINCCA_PWR 0xFF800000 328*9999SWang.Lin@Sun.COM #define AR_PHY_EXT_MINCCA_PWR_S 23 329*9999SWang.Lin@Sun.COM #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 330*9999SWang.Lin@Sun.COM #define AR9280_PHY_EXT_MINCCA_PWR_S 16 331*9999SWang.Lin@Sun.COM 332*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT 0x99c0 333*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 334*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 335*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 336*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 337*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 338*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 339*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 340*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 341*9999SWang.Lin@Sun.COM #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 342*9999SWang.Lin@Sun.COM 343*9999SWang.Lin@Sun.COM #define AR_PHY_HALFGI 0x99D0 344*9999SWang.Lin@Sun.COM #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 345*9999SWang.Lin@Sun.COM #define AR_PHY_HALFGI_DSC_MAN_S 4 346*9999SWang.Lin@Sun.COM #define AR_PHY_HALFGI_DSC_EXP 0x0000000F 347*9999SWang.Lin@Sun.COM #define AR_PHY_HALFGI_DSC_EXP_S 0 348*9999SWang.Lin@Sun.COM 349*9999SWang.Lin@Sun.COM #define AR_PHY_CHAN_INFO_MEMORY 0x99DC 350*9999SWang.Lin@Sun.COM #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 351*9999SWang.Lin@Sun.COM 352*9999SWang.Lin@Sun.COM #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 353*9999SWang.Lin@Sun.COM 354*9999SWang.Lin@Sun.COM #define AR_PHY_M_SLEEP 0x99f0 355*9999SWang.Lin@Sun.COM #define AR_PHY_REFCLKDLY 0x99f4 356*9999SWang.Lin@Sun.COM #define AR_PHY_REFCLKPD 0x99f8 357*9999SWang.Lin@Sun.COM 358*9999SWang.Lin@Sun.COM #define AR_PHY_CALMODE 0x99f0 359*9999SWang.Lin@Sun.COM 360*9999SWang.Lin@Sun.COM #define AR_PHY_CALMODE_IQ 0x00000000 361*9999SWang.Lin@Sun.COM #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 362*9999SWang.Lin@Sun.COM #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 363*9999SWang.Lin@Sun.COM #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 364*9999SWang.Lin@Sun.COM 365*9999SWang.Lin@Sun.COM #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 366*9999SWang.Lin@Sun.COM #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 367*9999SWang.Lin@Sun.COM #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 368*9999SWang.Lin@Sun.COM #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 369*9999SWang.Lin@Sun.COM 370*9999SWang.Lin@Sun.COM #define AR_PHY_CURRENT_RSSI 0x9c1c 371*9999SWang.Lin@Sun.COM #define AR9280_PHY_CURRENT_RSSI 0x9c3c 372*9999SWang.Lin@Sun.COM 373*9999SWang.Lin@Sun.COM #define AR_PHY_RFBUS_GRANT 0x9C20 374*9999SWang.Lin@Sun.COM #define AR_PHY_RFBUS_GRANT_EN 0x00000001 375*9999SWang.Lin@Sun.COM 376*9999SWang.Lin@Sun.COM #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 377*9999SWang.Lin@Sun.COM #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 378*9999SWang.Lin@Sun.COM 379*9999SWang.Lin@Sun.COM #define AR_PHY_CHAN_INFO_GAIN 0x9CFC 380*9999SWang.Lin@Sun.COM 381*9999SWang.Lin@Sun.COM #define AR_PHY_MODE 0xA200 382*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_AR2133 0x08 383*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_AR5111 0x00 384*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_AR5112 0x08 385*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_DYNAMIC 0x04 386*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_RF2GHZ 0x02 387*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_RF5GHZ 0x00 388*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_CCK 0x01 389*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_OFDM 0x00 390*9999SWang.Lin@Sun.COM #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 391*9999SWang.Lin@Sun.COM 392*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_TX_CTRL 0xA204 393*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 394*9999SWang.Lin@Sun.COM 395*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT 0xA208 396*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 397*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 398*9999SWang.Lin@Sun.COM /* [12:6] settling time for antenna switch */ 399*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 400*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 401*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 402*9999SWang.Lin@Sun.COM 403*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ 0xA20C 404*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 405*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 406*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 407*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 408*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 409*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 410*9999SWang.Lin@Sun.COM 411*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 412*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 413*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 414*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 415*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 416*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 417*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 418*9999SWang.Lin@Sun.COM #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 419*9999SWang.Lin@Sun.COM 420*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_RXCTRL4 0xA21C 421*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 422*9999SWang.Lin@Sun.COM #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 423*9999SWang.Lin@Sun.COM 424*9999SWang.Lin@Sun.COM #define AR_PHY_DAG_CTRLCCK 0xA228 425*9999SWang.Lin@Sun.COM #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 426*9999SWang.Lin@Sun.COM #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 427*9999SWang.Lin@Sun.COM #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 428*9999SWang.Lin@Sun.COM 429*9999SWang.Lin@Sun.COM #define AR_PHY_FORCE_CLKEN_CCK 0xA22C 430*9999SWang.Lin@Sun.COM #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 431*9999SWang.Lin@Sun.COM 432*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE3 0xA234 433*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE4 0xA238 434*9999SWang.Lin@Sun.COM 435*9999SWang.Lin@Sun.COM #define AR_PHY_SCRM_SEQ_XR 0xA23C 436*9999SWang.Lin@Sun.COM #define AR_PHY_HEADER_DETECT_XR 0xA240 437*9999SWang.Lin@Sun.COM #define AR_PHY_CHIRP_DETECTED_XR 0xA244 438*9999SWang.Lin@Sun.COM #define AR_PHY_BLUETOOTH 0xA254 439*9999SWang.Lin@Sun.COM 440*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1 0xA258 441*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 442*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 443*9999SWang.Lin@Sun.COM 444*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 445*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 446*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 447*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 448*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 449*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 450*9999SWang.Lin@Sun.COM 451*9999SWang.Lin@Sun.COM #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 452*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_M_31_45 0xa3a4 453*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_M_16_30 0xa3a8 454*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_M_00_15 0xa3ac 455*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_P_15_01 0xa3b8 456*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_P_30_16 0xa3bc 457*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_P_45_31 0xa3c0 458*9999SWang.Lin@Sun.COM #define AR_PHY_MASK2_P_61_45 0xa3c4 459*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG 0x994c 460*9999SWang.Lin@Sun.COM 461*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 462*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 463*9999SWang.Lin@Sun.COM 464*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 465*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) 466*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 467*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 468*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 469*9999SWang.Lin@Sun.COM #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 470*9999SWang.Lin@Sun.COM 471*9999SWang.Lin@Sun.COM #define AR_PHY_PILOT_MASK_01_30 0xa3b0 472*9999SWang.Lin@Sun.COM #define AR_PHY_PILOT_MASK_31_60 0xa3b4 473*9999SWang.Lin@Sun.COM 474*9999SWang.Lin@Sun.COM #define AR_PHY_CHANNEL_MASK_01_30 0x99d4 475*9999SWang.Lin@Sun.COM #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 476*9999SWang.Lin@Sun.COM 477*9999SWang.Lin@Sun.COM #define AR_PHY_ANALOG_SWAP 0xa268 478*9999SWang.Lin@Sun.COM #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 479*9999SWang.Lin@Sun.COM 480*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5 0xA26C 481*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 482*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 483*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 484*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 485*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 486*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 487*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 488*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 489*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 490*9999SWang.Lin@Sun.COM #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 491*9999SWang.Lin@Sun.COM 492*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE5 0xA38C 493*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE6 0xA390 494*9999SWang.Lin@Sun.COM 495*9999SWang.Lin@Sun.COM #define AR_PHY_CAL_CHAINMASK 0xA39C 496*9999SWang.Lin@Sun.COM 497*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_SUB 0xA3C8 498*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE7 0xA3CC 499*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE8 0xA3D0 500*9999SWang.Lin@Sun.COM #define AR_PHY_POWER_TX_RATE9 0xA3D4 501*9999SWang.Lin@Sun.COM 502*9999SWang.Lin@Sun.COM #define AR_PHY_XPA_CFG 0xA3D8 503*9999SWang.Lin@Sun.COM #define AR_PHY_FORCE_XPA_CFG 0x000000001 504*9999SWang.Lin@Sun.COM #define AR_PHY_FORCE_XPA_CFG_S 0 505*9999SWang.Lin@Sun.COM 506*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_CCA 0xa864 507*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 508*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_MINCCA_PWR_S 19 509*9999SWang.Lin@Sun.COM #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 510*9999SWang.Lin@Sun.COM #define AR9280_PHY_CH1_MINCCA_PWR_S 20 511*9999SWang.Lin@Sun.COM 512*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_CCA 0xb864 513*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 514*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_MINCCA_PWR_S 19 515*9999SWang.Lin@Sun.COM 516*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_EXT_CCA 0xa9bc 517*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 518*9999SWang.Lin@Sun.COM #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 519*9999SWang.Lin@Sun.COM #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 520*9999SWang.Lin@Sun.COM #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 521*9999SWang.Lin@Sun.COM 522*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_EXT_CCA 0xb9bc 523*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 524*9999SWang.Lin@Sun.COM #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 525*9999SWang.Lin@Sun.COM 526*9999SWang.Lin@Sun.COM #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ 527*9999SWang.Lin@Sun.COM int r; \ 528*9999SWang.Lin@Sun.COM for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 529*9999SWang.Lin@Sun.COM REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ 530*9999SWang.Lin@Sun.COM } \ 531*9999SWang.Lin@Sun.COM _NOTE(CONSTCOND) \ 532*9999SWang.Lin@Sun.COM } while (0) 533*9999SWang.Lin@Sun.COM 534*9999SWang.Lin@Sun.COM #define ATH9K_KEY_XOR 0xaau 535*9999SWang.Lin@Sun.COM 536*9999SWang.Lin@Sun.COM #define ATH9K_IS_MIC_ENABLED(ah) \ 537*9999SWang.Lin@Sun.COM (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) 538*9999SWang.Lin@Sun.COM 539*9999SWang.Lin@Sun.COM #define ANTSWAP_AB 0x0001 540*9999SWang.Lin@Sun.COM #define REDUCE_CHAIN_0 0x00000050 541*9999SWang.Lin@Sun.COM #define REDUCE_CHAIN_1 0x00000051 542*9999SWang.Lin@Sun.COM 543*9999SWang.Lin@Sun.COM #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ 544*9999SWang.Lin@Sun.COM int i; \ 545*9999SWang.Lin@Sun.COM for (i = 0; i < (_iniarray)->ia_rows; i++) \ 546*9999SWang.Lin@Sun.COM (_bank)[i] = INI_RA((_iniarray), i, _col); \ 547*9999SWang.Lin@Sun.COM _NOTE(CONSTCOND) \ 548*9999SWang.Lin@Sun.COM } while (0) 549*9999SWang.Lin@Sun.COM 550*9999SWang.Lin@Sun.COM #ifdef __cplusplus 551*9999SWang.Lin@Sun.COM } 552*9999SWang.Lin@Sun.COM #endif 553*9999SWang.Lin@Sun.COM 554*9999SWang.Lin@Sun.COM 555*9999SWang.Lin@Sun.COM #endif /* _ARN_PHY_H */ 556