xref: /onnv-gate/usr/src/uts/common/io/aggr/aggr_dev.c (revision 1537:5af1ac4922f2)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*1537Snd99603  * Common Development and Distribution License (the "License").
6*1537Snd99603  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
22*1537Snd99603  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
270Sstevel@tonic-gate 
280Sstevel@tonic-gate /*
290Sstevel@tonic-gate  * IEEE 802.3ad Link Aggregation.
300Sstevel@tonic-gate  */
310Sstevel@tonic-gate 
320Sstevel@tonic-gate #include <sys/types.h>
330Sstevel@tonic-gate #include <sys/sysmacros.h>
340Sstevel@tonic-gate #include <sys/conf.h>
350Sstevel@tonic-gate #include <sys/cmn_err.h>
360Sstevel@tonic-gate #include <sys/list.h>
370Sstevel@tonic-gate #include <sys/ksynch.h>
380Sstevel@tonic-gate #include <sys/kmem.h>
390Sstevel@tonic-gate #include <sys/stream.h>
40269Sericheng #include <sys/strsun.h>
410Sstevel@tonic-gate #include <sys/modctl.h>
420Sstevel@tonic-gate #include <sys/ddi.h>
430Sstevel@tonic-gate #include <sys/sunddi.h>
440Sstevel@tonic-gate #include <sys/atomic.h>
450Sstevel@tonic-gate #include <sys/stat.h>
460Sstevel@tonic-gate 
47269Sericheng #include <sys/dld_impl.h>
480Sstevel@tonic-gate #include <sys/aggr.h>
490Sstevel@tonic-gate #include <sys/aggr_impl.h>
50269Sericheng #include <inet/common.h>
510Sstevel@tonic-gate 
520Sstevel@tonic-gate /* module description */
530Sstevel@tonic-gate #define	AGGR_LINKINFO	"Link Aggregation MAC"
54269Sericheng #define	AGGR_DRIVER_NAME	"aggr"
550Sstevel@tonic-gate 
560Sstevel@tonic-gate /* device info ptr, only one for instance 0 */
570Sstevel@tonic-gate dev_info_t *aggr_dip;
580Sstevel@tonic-gate 
590Sstevel@tonic-gate static void aggr_dev_init(void);
600Sstevel@tonic-gate static int aggr_dev_fini(void);
610Sstevel@tonic-gate static int aggr_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
620Sstevel@tonic-gate static int aggr_attach(dev_info_t *, ddi_attach_cmd_t);
630Sstevel@tonic-gate static int aggr_detach(dev_info_t *, ddi_detach_cmd_t);
64269Sericheng static int aggr_open(queue_t *, dev_t *, int, int, cred_t *);
65269Sericheng static int aggr_close(queue_t *);
66269Sericheng static void aggr_wput(queue_t *, mblk_t *);
670Sstevel@tonic-gate 
68269Sericheng /*
69269Sericheng  * mi_hiwat is set to 1 because of the flow control mechanism implemented
70269Sericheng  * in dld. refer to the comments in dld_str.c for details.
71269Sericheng  */
72269Sericheng static struct module_info aggr_module_info = {
73269Sericheng 	0,
74269Sericheng 	AGGR_DRIVER_NAME,
75269Sericheng 	0,
76269Sericheng 	INFPSZ,
77269Sericheng 	1,
78269Sericheng 	0
79269Sericheng };
80269Sericheng 
81269Sericheng static struct qinit aggr_r_qinit = {	/* read queues */
82269Sericheng 	NULL,
83269Sericheng 	NULL,
84269Sericheng 	aggr_open,
85269Sericheng 	aggr_close,
86269Sericheng 	NULL,
87269Sericheng 	&aggr_module_info
880Sstevel@tonic-gate };
890Sstevel@tonic-gate 
90269Sericheng static struct qinit aggr_w_qinit = {	/* write queues */
91269Sericheng 	(pfi_t)dld_wput,
92269Sericheng 	(pfi_t)dld_wsrv,
93269Sericheng 	NULL,
94269Sericheng 	NULL,
95269Sericheng 	NULL,
96269Sericheng 	&aggr_module_info
97269Sericheng };
98269Sericheng 
99269Sericheng /*
100269Sericheng  * Entry points for aggr control node
101269Sericheng  */
102269Sericheng static struct qinit aggr_w_ctl_qinit = {
103269Sericheng 	(pfi_t)aggr_wput,
104269Sericheng 	NULL,
105269Sericheng 	NULL,
106269Sericheng 	NULL,
107269Sericheng 	NULL,
108269Sericheng 	&aggr_module_info
1090Sstevel@tonic-gate };
1100Sstevel@tonic-gate 
111269Sericheng static struct streamtab aggr_streamtab = {
112269Sericheng 	&aggr_r_qinit,
113269Sericheng 	&aggr_w_qinit
1140Sstevel@tonic-gate };
1150Sstevel@tonic-gate 
116269Sericheng DDI_DEFINE_STREAM_OPS(aggr_dev_ops, nulldev, nulldev, aggr_attach, aggr_detach,
117269Sericheng     nodev, aggr_getinfo, D_MP, &aggr_streamtab);
118269Sericheng 
119269Sericheng static struct modldrv aggr_modldrv = {
120269Sericheng 	&mod_driverops,		/* Type of module.  This one is a driver */
121269Sericheng 	AGGR_LINKINFO,		/* short description */
122269Sericheng 	&aggr_dev_ops		/* driver specific ops */
123269Sericheng };
124269Sericheng 
125269Sericheng static struct modlinkage modlinkage = {
1260Sstevel@tonic-gate 	MODREV_1,
127269Sericheng 	&aggr_modldrv,
1280Sstevel@tonic-gate 	NULL
1290Sstevel@tonic-gate };
1300Sstevel@tonic-gate 
131269Sericheng 
1320Sstevel@tonic-gate int
1330Sstevel@tonic-gate _init(void)
1340Sstevel@tonic-gate {
1350Sstevel@tonic-gate 	int err;
1360Sstevel@tonic-gate 
1370Sstevel@tonic-gate 	aggr_dev_init();
1380Sstevel@tonic-gate 
1390Sstevel@tonic-gate 	if ((err = mod_install(&modlinkage)) != 0) {
1400Sstevel@tonic-gate 		(void) aggr_dev_fini();
1410Sstevel@tonic-gate 		return (err);
1420Sstevel@tonic-gate 	}
1430Sstevel@tonic-gate 
1440Sstevel@tonic-gate 	aggr_dip = NULL;
1450Sstevel@tonic-gate 	return (0);
1460Sstevel@tonic-gate }
1470Sstevel@tonic-gate 
1480Sstevel@tonic-gate int
1490Sstevel@tonic-gate _fini(void)
1500Sstevel@tonic-gate {
1510Sstevel@tonic-gate 	int err;
1520Sstevel@tonic-gate 
1530Sstevel@tonic-gate 	if ((err = aggr_dev_fini()) != 0)
1540Sstevel@tonic-gate 		return (err);
1550Sstevel@tonic-gate 
1560Sstevel@tonic-gate 	if ((err = mod_remove(&modlinkage)) != 0) {
1570Sstevel@tonic-gate 		aggr_dev_init();
1580Sstevel@tonic-gate 		return (err);
1590Sstevel@tonic-gate 	}
1600Sstevel@tonic-gate 
1610Sstevel@tonic-gate 	return (0);
1620Sstevel@tonic-gate }
1630Sstevel@tonic-gate 
1640Sstevel@tonic-gate int
1650Sstevel@tonic-gate _info(struct modinfo *modinfop)
1660Sstevel@tonic-gate {
1670Sstevel@tonic-gate 	return (mod_info(&modlinkage, modinfop));
1680Sstevel@tonic-gate }
1690Sstevel@tonic-gate 
170269Sericheng static int
171269Sericheng aggr_open(queue_t *q, dev_t *devp, int flag, int sflag, cred_t *credp)
172269Sericheng {
173269Sericheng 	if (q->q_ptr != NULL)
174269Sericheng 		return (EBUSY);
175269Sericheng 
176269Sericheng 	if (getminor(*devp) == AGGR_MINOR_CTL) {
177269Sericheng 		dld_str_t	*dsp;
178269Sericheng 
179269Sericheng 		dsp = dld_str_create(q, DLD_CONTROL, getmajor(*devp),
180269Sericheng 		    DL_STYLE1);
181269Sericheng 		if (dsp == NULL)
182269Sericheng 			return (ENOSR);
183269Sericheng 
184269Sericheng 		/*
185269Sericheng 		 * The aggr control node uses its own set of entry points.
186269Sericheng 		 */
187269Sericheng 		WR(q)->q_qinfo = &aggr_w_ctl_qinit;
188269Sericheng 		*devp = makedevice(getmajor(*devp), dsp->ds_minor);
189269Sericheng 		qprocson(q);
190269Sericheng 		return (0);
191269Sericheng 	}
192269Sericheng 	return (dld_open(q, devp, flag, sflag, credp));
193269Sericheng }
194269Sericheng 
195269Sericheng static int
196269Sericheng aggr_close(queue_t *q)
197269Sericheng {
198269Sericheng 	dld_str_t	*dsp = q->q_ptr;
199269Sericheng 
200269Sericheng 	if (dsp->ds_type == DLD_CONTROL) {
201269Sericheng 		qprocsoff(q);
202269Sericheng 		dld_str_destroy(dsp);
203269Sericheng 		return (0);
204269Sericheng 	}
205269Sericheng 	return (dld_close(q));
206269Sericheng }
207269Sericheng 
208269Sericheng static void
209269Sericheng aggr_wput(queue_t *q, mblk_t *mp)
210269Sericheng {
211269Sericheng 	if (DB_TYPE(mp) == M_IOCTL)
212269Sericheng 		aggr_ioctl(q, mp);
213269Sericheng 	else
214269Sericheng 		freemsg(mp);
215269Sericheng }
216269Sericheng 
2170Sstevel@tonic-gate static void
2180Sstevel@tonic-gate aggr_dev_init(void)
2190Sstevel@tonic-gate {
2200Sstevel@tonic-gate 	aggr_port_init();
2210Sstevel@tonic-gate 	aggr_grp_init();
222*1537Snd99603 	aggr_lacp_init();
2230Sstevel@tonic-gate }
2240Sstevel@tonic-gate 
2250Sstevel@tonic-gate static int
2260Sstevel@tonic-gate aggr_dev_fini(void)
2270Sstevel@tonic-gate {
2280Sstevel@tonic-gate 	int err;
2290Sstevel@tonic-gate 
2300Sstevel@tonic-gate 	if ((err = aggr_grp_fini()) != 0)
2310Sstevel@tonic-gate 		return (err);
2320Sstevel@tonic-gate 	if ((err = aggr_port_fini()) != 0) {
2330Sstevel@tonic-gate 		/*
2340Sstevel@tonic-gate 		 * re-initialize the groups to keep a consistent
2350Sstevel@tonic-gate 		 * state.
2360Sstevel@tonic-gate 		 */
2370Sstevel@tonic-gate 		aggr_grp_init();
2380Sstevel@tonic-gate 	}
239*1537Snd99603 	aggr_lacp_fini();
2400Sstevel@tonic-gate 
2410Sstevel@tonic-gate 	return (err);
2420Sstevel@tonic-gate }
2430Sstevel@tonic-gate 
2440Sstevel@tonic-gate /*ARGSUSED*/
2450Sstevel@tonic-gate static int
2460Sstevel@tonic-gate aggr_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
2470Sstevel@tonic-gate     void **result)
2480Sstevel@tonic-gate {
2490Sstevel@tonic-gate 	switch (infocmd) {
2500Sstevel@tonic-gate 	case DDI_INFO_DEVT2DEVINFO:
2510Sstevel@tonic-gate 		*result = aggr_dip;
2520Sstevel@tonic-gate 		return (DDI_SUCCESS);
2530Sstevel@tonic-gate 	case DDI_INFO_DEVT2INSTANCE:
2540Sstevel@tonic-gate 		*result = NULL;
2550Sstevel@tonic-gate 		return (DDI_SUCCESS);
2560Sstevel@tonic-gate 	}
2570Sstevel@tonic-gate 	return (DDI_FAILURE);
2580Sstevel@tonic-gate }
2590Sstevel@tonic-gate 
2600Sstevel@tonic-gate static int
2610Sstevel@tonic-gate aggr_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2620Sstevel@tonic-gate {
2630Sstevel@tonic-gate 	switch (cmd) {
2640Sstevel@tonic-gate 	case DDI_ATTACH:
2650Sstevel@tonic-gate 		if (ddi_get_instance(dip) != 0) {
2660Sstevel@tonic-gate 			/* we only allow instance 0 to attach */
2670Sstevel@tonic-gate 			return (DDI_FAILURE);
2680Sstevel@tonic-gate 		}
2690Sstevel@tonic-gate 
2700Sstevel@tonic-gate 		/* create minor node for control interface */
2710Sstevel@tonic-gate 		if (ddi_create_minor_node(dip, AGGR_DEVNAME_CTL, S_IFCHR,
2720Sstevel@tonic-gate 		    AGGR_MINOR_CTL, DDI_PSEUDO, 0) != DDI_SUCCESS) {
2730Sstevel@tonic-gate 			return (DDI_FAILURE);
2740Sstevel@tonic-gate 		}
2750Sstevel@tonic-gate 
2760Sstevel@tonic-gate 		aggr_dip = dip;
2770Sstevel@tonic-gate 		return (DDI_SUCCESS);
2780Sstevel@tonic-gate 
2790Sstevel@tonic-gate 	case DDI_RESUME:
2800Sstevel@tonic-gate 		return (DDI_SUCCESS);
2810Sstevel@tonic-gate 
2820Sstevel@tonic-gate 	default:
2830Sstevel@tonic-gate 		return (DDI_FAILURE);
2840Sstevel@tonic-gate 	}
2850Sstevel@tonic-gate }
2860Sstevel@tonic-gate 
2870Sstevel@tonic-gate /*ARGSUSED*/
2880Sstevel@tonic-gate static int
2890Sstevel@tonic-gate aggr_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2900Sstevel@tonic-gate {
2910Sstevel@tonic-gate 	switch (cmd) {
2920Sstevel@tonic-gate 	case DDI_DETACH:
293269Sericheng 		if (aggr_grp_count() > 0)
294269Sericheng 			return (DDI_FAILURE);
295269Sericheng 
2960Sstevel@tonic-gate 		aggr_dip = NULL;
297269Sericheng 		ddi_remove_minor_node(dip, AGGR_DEVNAME_CTL);
2980Sstevel@tonic-gate 
2990Sstevel@tonic-gate 		return (DDI_SUCCESS);
3000Sstevel@tonic-gate 
3010Sstevel@tonic-gate 	case DDI_SUSPEND:
3020Sstevel@tonic-gate 		return (DDI_SUCCESS);
3030Sstevel@tonic-gate 
3040Sstevel@tonic-gate 	default:
3050Sstevel@tonic-gate 		return (DDI_FAILURE);
3060Sstevel@tonic-gate 	}
3070Sstevel@tonic-gate }
308