1*21Sap25164 /*
2*21Sap25164 * CDDL HEADER START
3*21Sap25164 *
4*21Sap25164 * The contents of this file are subject to the terms of the
5*21Sap25164 * Common Development and Distribution License, Version 1.0 only
6*21Sap25164 * (the "License"). You may not use this file except in compliance
7*21Sap25164 * with the License.
8*21Sap25164 *
9*21Sap25164 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*21Sap25164 * or http://www.opensolaris.org/os/licensing.
11*21Sap25164 * See the License for the specific language governing permissions
12*21Sap25164 * and limitations under the License.
13*21Sap25164 *
14*21Sap25164 * When distributing Covered Code, include this CDDL HEADER in each
15*21Sap25164 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*21Sap25164 * If applicable, add the following below this CDDL HEADER, with the
17*21Sap25164 * fields enclosed by brackets "[]" replaced with your own identifying
18*21Sap25164 * information: Portions Copyright [yyyy] [name of copyright owner]
19*21Sap25164 *
20*21Sap25164 * CDDL HEADER END
21*21Sap25164 */
22*21Sap25164 /*
23*21Sap25164 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24*21Sap25164 * Use is subject to license terms.
25*21Sap25164 */
26*21Sap25164
27*21Sap25164 #pragma ident "%Z%%M% %I% %E% SMI"
28*21Sap25164
29*21Sap25164 /*
30*21Sap25164 * dcam_reg.c
31*21Sap25164 *
32*21Sap25164 * dcam1394 driver. Control register access support.
33*21Sap25164 */
34*21Sap25164
35*21Sap25164 #include <sys/tnf_probe.h>
36*21Sap25164 #include <sys/1394/targets/dcam1394/dcam_reg.h>
37*21Sap25164
38*21Sap25164
39*21Sap25164 /*
40*21Sap25164 * dcam_reg_read
41*21Sap25164 */
42*21Sap25164 int
dcam_reg_read(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)43*21Sap25164 dcam_reg_read(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
44*21Sap25164 {
45*21Sap25164 cmd1394_cmd_t *cmdp;
46*21Sap25164
47*21Sap25164 if (t1394_alloc_cmd(soft_state->sl_handle, 1, &cmdp) != DDI_SUCCESS) {
48*21Sap25164 return (-1);
49*21Sap25164 }
50*21Sap25164
51*21Sap25164 cmdp->cmd_type = CMD1394_ASYNCH_RD_QUAD;
52*21Sap25164 cmdp->cmd_addr = 0x0000FFFFF0F00000 |
53*21Sap25164 (uint64_t)(arg->offs & 0x00000FFC);
54*21Sap25164 cmdp->cmd_options = CMD1394_BLOCKING;
55*21Sap25164
56*21Sap25164 #ifdef GRAPHICS_DELAY
57*21Sap25164 /*
58*21Sap25164 * This delay should not be necessary, but was added for some
59*21Sap25164 * unknown reason. Should it ever be determined that it
60*21Sap25164 * is necessary, this delay should be reenabled.
61*21Sap25164 */
62*21Sap25164 delay(drv_usectohz(500));
63*21Sap25164 #endif
64*21Sap25164
65*21Sap25164 if (t1394_read(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
66*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
67*21Sap25164 return (-1);
68*21Sap25164 }
69*21Sap25164
70*21Sap25164 if (cmdp->cmd_result != DDI_SUCCESS) {
71*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
72*21Sap25164 return (-1);
73*21Sap25164 }
74*21Sap25164
75*21Sap25164 /* perform endian adjustment */
76*21Sap25164 cmdp->cmd_u.q.quadlet_data = T1394_DATA32(cmdp->cmd_u.q.quadlet_data);
77*21Sap25164 arg->val = cmdp->cmd_u.q.quadlet_data;
78*21Sap25164
79*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
80*21Sap25164
81*21Sap25164 return (0);
82*21Sap25164 }
83*21Sap25164
84*21Sap25164
85*21Sap25164 /*
86*21Sap25164 * dcam_reg_write
87*21Sap25164 */
88*21Sap25164 int
dcam_reg_write(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)89*21Sap25164 dcam_reg_write(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
90*21Sap25164 {
91*21Sap25164 cmd1394_cmd_t *cmdp;
92*21Sap25164
93*21Sap25164 if (t1394_alloc_cmd(soft_state->sl_handle, 0, &cmdp) != DDI_SUCCESS) {
94*21Sap25164 return (-1);
95*21Sap25164 }
96*21Sap25164
97*21Sap25164 cmdp->cmd_type = CMD1394_ASYNCH_WR_QUAD;
98*21Sap25164 cmdp->cmd_addr = 0x0000FFFFF0F00000 |
99*21Sap25164 (uint64_t)(arg->offs & 0x00000FFC);
100*21Sap25164 cmdp->cmd_options = CMD1394_BLOCKING;
101*21Sap25164
102*21Sap25164 /* perform endian adjustment */
103*21Sap25164 cmdp->cmd_u.q.quadlet_data = T1394_DATA32(arg->val);
104*21Sap25164
105*21Sap25164 #ifdef GRAPHICS_DELAY
106*21Sap25164 /*
107*21Sap25164 * See the description in dcam_reg_read() above.
108*21Sap25164 */
109*21Sap25164 delay(drv_usectohz(500));
110*21Sap25164 #endif
111*21Sap25164
112*21Sap25164 if (t1394_write(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
113*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
114*21Sap25164 return (-1);
115*21Sap25164 }
116*21Sap25164
117*21Sap25164 if (cmdp->cmd_result != DDI_SUCCESS) {
118*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
119*21Sap25164 return (-1);
120*21Sap25164 }
121*21Sap25164
122*21Sap25164 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
123*21Sap25164
124*21Sap25164 return (0);
125*21Sap25164 }
126