1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
24*0Sstevel@tonic-gate * All rights reserved.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate /*
30*0Sstevel@tonic-gate * s1394_csr.c
31*0Sstevel@tonic-gate * 1394 Services Layer CSR and Config ROM Routines
32*0Sstevel@tonic-gate * Contains all of the CSR callback routines for various required
33*0Sstevel@tonic-gate * CSR registers. Also contains routines for their initialization
34*0Sstevel@tonic-gate * and destruction, as well as routines to handle the processing
35*0Sstevel@tonic-gate * of Config ROM update requests.
36*0Sstevel@tonic-gate */
37*0Sstevel@tonic-gate
38*0Sstevel@tonic-gate #include <sys/conf.h>
39*0Sstevel@tonic-gate #include <sys/ddi.h>
40*0Sstevel@tonic-gate #include <sys/sunddi.h>
41*0Sstevel@tonic-gate #include <sys/types.h>
42*0Sstevel@tonic-gate #include <sys/kmem.h>
43*0Sstevel@tonic-gate #include <sys/tnf_probe.h>
44*0Sstevel@tonic-gate
45*0Sstevel@tonic-gate #include <sys/1394/t1394.h>
46*0Sstevel@tonic-gate #include <sys/1394/s1394.h>
47*0Sstevel@tonic-gate #include <sys/1394/h1394.h>
48*0Sstevel@tonic-gate #include <sys/1394/ieee1394.h>
49*0Sstevel@tonic-gate #include <sys/1394/ieee1212.h>
50*0Sstevel@tonic-gate
51*0Sstevel@tonic-gate static void s1394_CSR_state_clear(cmd1394_cmd_t *req);
52*0Sstevel@tonic-gate
53*0Sstevel@tonic-gate static void s1394_CSR_state_set(cmd1394_cmd_t *req);
54*0Sstevel@tonic-gate
55*0Sstevel@tonic-gate static void s1394_CSR_node_ids(cmd1394_cmd_t *req);
56*0Sstevel@tonic-gate
57*0Sstevel@tonic-gate static void s1394_CSR_reset_start(cmd1394_cmd_t *req);
58*0Sstevel@tonic-gate
59*0Sstevel@tonic-gate static void s1394_CSR_split_timeout(cmd1394_cmd_t *req);
60*0Sstevel@tonic-gate
61*0Sstevel@tonic-gate static void s1394_CSR_argument_regs(cmd1394_cmd_t *req);
62*0Sstevel@tonic-gate
63*0Sstevel@tonic-gate static void s1394_CSR_test_regs(cmd1394_cmd_t *req);
64*0Sstevel@tonic-gate
65*0Sstevel@tonic-gate static void s1394_CSR_interrupt_regs(cmd1394_cmd_t *req);
66*0Sstevel@tonic-gate
67*0Sstevel@tonic-gate static void s1394_CSR_clock_regs(cmd1394_cmd_t *req);
68*0Sstevel@tonic-gate
69*0Sstevel@tonic-gate static void s1394_CSR_message_regs(cmd1394_cmd_t *req);
70*0Sstevel@tonic-gate
71*0Sstevel@tonic-gate static void s1394_CSR_cycle_time(cmd1394_cmd_t *req);
72*0Sstevel@tonic-gate
73*0Sstevel@tonic-gate static void s1394_CSR_bus_time(cmd1394_cmd_t *req);
74*0Sstevel@tonic-gate
75*0Sstevel@tonic-gate static void s1394_CSR_busy_timeout(cmd1394_cmd_t *req);
76*0Sstevel@tonic-gate
77*0Sstevel@tonic-gate static void s1394_CSR_IRM_regs(cmd1394_cmd_t *req);
78*0Sstevel@tonic-gate
79*0Sstevel@tonic-gate static void s1394_CSR_topology_map(cmd1394_cmd_t *req);
80*0Sstevel@tonic-gate
81*0Sstevel@tonic-gate static void s1394_common_CSR_routine(s1394_hal_t *hal, cmd1394_cmd_t *req);
82*0Sstevel@tonic-gate
83*0Sstevel@tonic-gate static int s1394_init_config_rom_structures(s1394_hal_t *hal);
84*0Sstevel@tonic-gate
85*0Sstevel@tonic-gate static int s1394_destroy_config_rom_structures(s1394_hal_t *hal);
86*0Sstevel@tonic-gate
87*0Sstevel@tonic-gate /*
88*0Sstevel@tonic-gate * s1394_setup_CSR_space()
89*0Sstevel@tonic-gate * setups up the local host's CSR registers and callback routines.
90*0Sstevel@tonic-gate */
91*0Sstevel@tonic-gate int
s1394_setup_CSR_space(s1394_hal_t * hal)92*0Sstevel@tonic-gate s1394_setup_CSR_space(s1394_hal_t *hal)
93*0Sstevel@tonic-gate {
94*0Sstevel@tonic-gate s1394_addr_space_blk_t *curr_blk;
95*0Sstevel@tonic-gate t1394_alloc_addr_t addr;
96*0Sstevel@tonic-gate t1394_addr_enable_t rw_flags;
97*0Sstevel@tonic-gate int result;
98*0Sstevel@tonic-gate
99*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_enter, S1394_TNF_SL_CSR_STACK,
100*0Sstevel@tonic-gate "");
101*0Sstevel@tonic-gate
102*0Sstevel@tonic-gate /*
103*0Sstevel@tonic-gate * Although they are not freed up in this routine, if
104*0Sstevel@tonic-gate * one of the s1394_claim_addr_blk() routines fails,
105*0Sstevel@tonic-gate * all of the previously successful claims will be
106*0Sstevel@tonic-gate * freed up in s1394_destroy_addr_space() upon returning
107*0Sstevel@tonic-gate * DDI_FAILURE from this routine.
108*0Sstevel@tonic-gate */
109*0Sstevel@tonic-gate
110*0Sstevel@tonic-gate rw_flags = T1394_ADDR_RDENBL | T1394_ADDR_WRENBL;
111*0Sstevel@tonic-gate
112*0Sstevel@tonic-gate /*
113*0Sstevel@tonic-gate * STATE_CLEAR
114*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.1 or
115*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.1
116*0Sstevel@tonic-gate */
117*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_STATE_CLEAR;
118*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
119*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
120*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
121*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_state_clear;
122*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_state_clear;
123*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
124*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
125*0Sstevel@tonic-gate addr.aa_arg = hal;
126*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
127*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
128*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
129*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
130*0Sstevel@tonic-gate "STATE_CLEAR: CSR setup failed");
131*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
132*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
133*0Sstevel@tonic-gate return (DDI_FAILURE);
134*0Sstevel@tonic-gate }
135*0Sstevel@tonic-gate
136*0Sstevel@tonic-gate /*
137*0Sstevel@tonic-gate * STATE_SET
138*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.2 or
139*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.2
140*0Sstevel@tonic-gate */
141*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_STATE_SET;
142*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
143*0Sstevel@tonic-gate addr.aa_enable = T1394_ADDR_WRENBL;
144*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
145*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = NULL;
146*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_state_set;
147*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
148*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
149*0Sstevel@tonic-gate addr.aa_arg = hal;
150*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
151*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
152*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
153*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
154*0Sstevel@tonic-gate "STATE_SET: CSR setup failed");
155*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
156*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
157*0Sstevel@tonic-gate return (DDI_FAILURE);
158*0Sstevel@tonic-gate }
159*0Sstevel@tonic-gate
160*0Sstevel@tonic-gate /*
161*0Sstevel@tonic-gate * NODE_IDS
162*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.3 or
163*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.3
164*0Sstevel@tonic-gate */
165*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_NODE_IDS;
166*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
167*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
168*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
169*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_node_ids;
170*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_node_ids;
171*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
172*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
173*0Sstevel@tonic-gate addr.aa_arg = hal;
174*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
175*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
176*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
177*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
178*0Sstevel@tonic-gate "NODE_IDS: CSR setup failed");
179*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
180*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
181*0Sstevel@tonic-gate return (DDI_FAILURE);
182*0Sstevel@tonic-gate }
183*0Sstevel@tonic-gate
184*0Sstevel@tonic-gate /*
185*0Sstevel@tonic-gate * RESET_START
186*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.4 or
187*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.4
188*0Sstevel@tonic-gate */
189*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_RESET_START;
190*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
191*0Sstevel@tonic-gate addr.aa_enable = T1394_ADDR_WRENBL;
192*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
193*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = NULL;
194*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_reset_start;
195*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
196*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
197*0Sstevel@tonic-gate addr.aa_arg = hal;
198*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
199*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
200*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
201*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
202*0Sstevel@tonic-gate "RESET_START: CSR setup failed");
203*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
204*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
205*0Sstevel@tonic-gate return (DDI_FAILURE);
206*0Sstevel@tonic-gate }
207*0Sstevel@tonic-gate
208*0Sstevel@tonic-gate /*
209*0Sstevel@tonic-gate * SPLIT_TIMEOUT
210*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.6 or
211*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.7
212*0Sstevel@tonic-gate */
213*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_SPLIT_TIMEOUT_HI;
214*0Sstevel@tonic-gate addr.aa_length = IEEE1394_OCTLET;
215*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
216*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
217*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_split_timeout;
218*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_split_timeout;
219*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
220*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
221*0Sstevel@tonic-gate addr.aa_arg = hal;
222*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
223*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
224*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
225*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
226*0Sstevel@tonic-gate "SPLIT_TIMEOUT: CSR setup failed");
227*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
228*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
229*0Sstevel@tonic-gate return (DDI_FAILURE);
230*0Sstevel@tonic-gate }
231*0Sstevel@tonic-gate
232*0Sstevel@tonic-gate /*
233*0Sstevel@tonic-gate * ARGUMENT_HI and ARGUMENT_LO
234*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.7 or
235*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.8
236*0Sstevel@tonic-gate */
237*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_ARG_HI;
238*0Sstevel@tonic-gate addr.aa_length = 2 * (IEEE1394_QUADLET);
239*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
240*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
241*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_argument_regs;
242*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_argument_regs;
243*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
244*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
245*0Sstevel@tonic-gate addr.aa_arg = hal;
246*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
247*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
248*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
249*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
250*0Sstevel@tonic-gate "ARGUMENT registers: CSR setup failed");
251*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
252*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
253*0Sstevel@tonic-gate return (DDI_FAILURE);
254*0Sstevel@tonic-gate }
255*0Sstevel@tonic-gate
256*0Sstevel@tonic-gate /*
257*0Sstevel@tonic-gate * TEST_START and TEST_STATUS
258*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.7 or
259*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.9 - 7.4.10
260*0Sstevel@tonic-gate */
261*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_TEST_START;
262*0Sstevel@tonic-gate addr.aa_length = 2 * (IEEE1394_QUADLET);
263*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
264*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
265*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_test_regs;
266*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_test_regs;
267*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
268*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
269*0Sstevel@tonic-gate addr.aa_arg = hal;
270*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
271*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
272*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
273*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
274*0Sstevel@tonic-gate "TEST registers: CSR setup failed");
275*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
276*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
277*0Sstevel@tonic-gate return (DDI_FAILURE);
278*0Sstevel@tonic-gate }
279*0Sstevel@tonic-gate
280*0Sstevel@tonic-gate /*
281*0Sstevel@tonic-gate * INTERRUPT_TARGET and INTERRUPT_MASK
282*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.9 or
283*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.15 - 7.4.16
284*0Sstevel@tonic-gate */
285*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_INTERRUPT_TARGET;
286*0Sstevel@tonic-gate addr.aa_length = 2 * (IEEE1394_QUADLET);
287*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
288*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
289*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_interrupt_regs;
290*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_interrupt_regs;
291*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
292*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
293*0Sstevel@tonic-gate addr.aa_arg = hal;
294*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
295*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
296*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
297*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
298*0Sstevel@tonic-gate "INTERRUPT registers: CSR setup failed");
299*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
300*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
301*0Sstevel@tonic-gate return (DDI_FAILURE);
302*0Sstevel@tonic-gate }
303*0Sstevel@tonic-gate
304*0Sstevel@tonic-gate /*
305*0Sstevel@tonic-gate * CLOCK_VALUE, CLOCK_TICK_PERIOD, CLOCK_INFO, etc.
306*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.10 or
307*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.17 - 7.4.20
308*0Sstevel@tonic-gate */
309*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_CLOCK_VALUE;
310*0Sstevel@tonic-gate addr.aa_length = IEEE1394_CSR_CLOCK_VALUE_SZ;
311*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
312*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
313*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_clock_regs;
314*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_clock_regs;
315*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
316*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
317*0Sstevel@tonic-gate addr.aa_arg = hal;
318*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
319*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
320*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
321*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
322*0Sstevel@tonic-gate "CLOCK registers: CSR setup failed");
323*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
324*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
325*0Sstevel@tonic-gate return (DDI_FAILURE);
326*0Sstevel@tonic-gate }
327*0Sstevel@tonic-gate
328*0Sstevel@tonic-gate /*
329*0Sstevel@tonic-gate * MESSAGE_REQUEST and MESSAGE_RESPONSE
330*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.2.11 or
331*0Sstevel@tonic-gate * IEEE 1212-1994, Section 7.4.21
332*0Sstevel@tonic-gate */
333*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CSR_MESSAGE_REQUEST;
334*0Sstevel@tonic-gate addr.aa_length = IEEE1394_CSR_MESSAGE_REQUEST_SZ;
335*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
336*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
337*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_message_regs;
338*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_message_regs;
339*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
340*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
341*0Sstevel@tonic-gate addr.aa_arg = hal;
342*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
343*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
344*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
345*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
346*0Sstevel@tonic-gate "MESSAGE registers: CSR setup failed");
347*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
348*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
349*0Sstevel@tonic-gate return (DDI_FAILURE);
350*0Sstevel@tonic-gate }
351*0Sstevel@tonic-gate
352*0Sstevel@tonic-gate /*
353*0Sstevel@tonic-gate * CYCLE_TIME
354*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.3.1
355*0Sstevel@tonic-gate */
356*0Sstevel@tonic-gate addr.aa_address = IEEE1394_SCSR_CYCLE_TIME;
357*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
358*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
359*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
360*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_cycle_time;
361*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_cycle_time;
362*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
363*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
364*0Sstevel@tonic-gate addr.aa_arg = hal;
365*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
366*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
367*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
368*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
369*0Sstevel@tonic-gate "CYCLE_TIME: CSR setup failed");
370*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
371*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
372*0Sstevel@tonic-gate return (DDI_FAILURE);
373*0Sstevel@tonic-gate }
374*0Sstevel@tonic-gate
375*0Sstevel@tonic-gate /*
376*0Sstevel@tonic-gate * BUS_TIME
377*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.3.2
378*0Sstevel@tonic-gate */
379*0Sstevel@tonic-gate addr.aa_address = IEEE1394_SCSR_BUS_TIME;
380*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
381*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
382*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
383*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_bus_time;
384*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_bus_time;
385*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
386*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
387*0Sstevel@tonic-gate addr.aa_arg = hal;
388*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
389*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
390*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
391*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
392*0Sstevel@tonic-gate "BUS_TIME: CSR setup failed");
393*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
394*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
395*0Sstevel@tonic-gate return (DDI_FAILURE);
396*0Sstevel@tonic-gate }
397*0Sstevel@tonic-gate
398*0Sstevel@tonic-gate /*
399*0Sstevel@tonic-gate * BUSY_TIMEOUT
400*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.3.5
401*0Sstevel@tonic-gate */
402*0Sstevel@tonic-gate addr.aa_address = IEEE1394_SCSR_BUSY_TIMEOUT;
403*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
404*0Sstevel@tonic-gate addr.aa_enable = rw_flags;
405*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
406*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_busy_timeout;
407*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = s1394_CSR_busy_timeout;
408*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
409*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
410*0Sstevel@tonic-gate addr.aa_arg = hal;
411*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
412*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
413*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
414*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
415*0Sstevel@tonic-gate "BUSY_TIMEOUT: CSR setup failed");
416*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
417*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
418*0Sstevel@tonic-gate return (DDI_FAILURE);
419*0Sstevel@tonic-gate }
420*0Sstevel@tonic-gate
421*0Sstevel@tonic-gate /*
422*0Sstevel@tonic-gate * BUS_MANAGER_ID
423*0Sstevel@tonic-gate * BANDWIDTH_AVAILABLE
424*0Sstevel@tonic-gate * CHANNELS_AVAILABLE
425*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.3.6 - 8.3.2.3.8
426*0Sstevel@tonic-gate */
427*0Sstevel@tonic-gate addr.aa_address = IEEE1394_SCSR_BUSMGR_ID;
428*0Sstevel@tonic-gate addr.aa_length = 3 * (IEEE1394_QUADLET);
429*0Sstevel@tonic-gate addr.aa_enable = T1394_ADDR_RDENBL | T1394_ADDR_LKENBL;
430*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
431*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_IRM_regs;
432*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = NULL;
433*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = s1394_CSR_IRM_regs;
434*0Sstevel@tonic-gate addr.aa_kmem_bufp = NULL;
435*0Sstevel@tonic-gate addr.aa_arg = hal;
436*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
437*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
438*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
439*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
440*0Sstevel@tonic-gate "IRM registers: CSR setup failed");
441*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
442*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
443*0Sstevel@tonic-gate return (DDI_FAILURE);
444*0Sstevel@tonic-gate }
445*0Sstevel@tonic-gate
446*0Sstevel@tonic-gate /*
447*0Sstevel@tonic-gate * Reserved for Configuration ROM
448*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.5.3
449*0Sstevel@tonic-gate */
450*0Sstevel@tonic-gate addr.aa_address = IEEE1394_CONFIG_ROM_ADDR;
451*0Sstevel@tonic-gate addr.aa_length = IEEE1394_CONFIG_ROM_SZ;
452*0Sstevel@tonic-gate result = s1394_reserve_addr_blk(hal, &addr);
453*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
454*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
455*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
456*0Sstevel@tonic-gate "Unable to reserve Config ROM");
457*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
458*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
459*0Sstevel@tonic-gate return (DDI_FAILURE);
460*0Sstevel@tonic-gate }
461*0Sstevel@tonic-gate
462*0Sstevel@tonic-gate /*
463*0Sstevel@tonic-gate * TOPOLOGY_MAP
464*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.4.1
465*0Sstevel@tonic-gate */
466*0Sstevel@tonic-gate hal->CSR_topology_map = kmem_zalloc(IEEE1394_UCSR_TOPOLOGY_MAP_SZ,
467*0Sstevel@tonic-gate KM_SLEEP);
468*0Sstevel@tonic-gate addr.aa_address = IEEE1394_UCSR_TOPOLOGY_MAP;
469*0Sstevel@tonic-gate addr.aa_length = IEEE1394_UCSR_TOPOLOGY_MAP_SZ;
470*0Sstevel@tonic-gate addr.aa_enable = T1394_ADDR_RDENBL;
471*0Sstevel@tonic-gate addr.aa_type = T1394_ADDR_FIXED;
472*0Sstevel@tonic-gate addr.aa_evts.recv_read_request = s1394_CSR_topology_map;
473*0Sstevel@tonic-gate addr.aa_evts.recv_write_request = NULL;
474*0Sstevel@tonic-gate addr.aa_evts.recv_lock_request = NULL;
475*0Sstevel@tonic-gate addr.aa_kmem_bufp = (caddr_t)hal->CSR_topology_map;
476*0Sstevel@tonic-gate addr.aa_arg = hal;
477*0Sstevel@tonic-gate result = s1394_claim_addr_blk(hal, &addr);
478*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
479*0Sstevel@tonic-gate kmem_free((void *)hal->CSR_topology_map,
480*0Sstevel@tonic-gate IEEE1394_UCSR_TOPOLOGY_MAP_SZ);
481*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
482*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
483*0Sstevel@tonic-gate "TOPOLOGY_MAP: CSR setup failed");
484*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
485*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
486*0Sstevel@tonic-gate return (DDI_FAILURE);
487*0Sstevel@tonic-gate }
488*0Sstevel@tonic-gate curr_blk = (s1394_addr_space_blk_t *)(addr.aa_hdl);
489*0Sstevel@tonic-gate /* Set up the block so that we free kmem_bufp at detach */
490*0Sstevel@tonic-gate curr_blk->free_kmem_bufp = B_TRUE;
491*0Sstevel@tonic-gate
492*0Sstevel@tonic-gate /*
493*0Sstevel@tonic-gate * Reserve the SPEED_MAP
494*0Sstevel@tonic-gate * see IEEE 1394-1995, Section 8.3.2.4.1
495*0Sstevel@tonic-gate * (obsoleted in P1394A)
496*0Sstevel@tonic-gate */
497*0Sstevel@tonic-gate addr.aa_address = IEEE1394_UCSR_SPEED_MAP;
498*0Sstevel@tonic-gate addr.aa_length = IEEE1394_UCSR_SPEED_MAP_SZ;
499*0Sstevel@tonic-gate result = s1394_reserve_addr_blk(hal, &addr);
500*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
501*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
502*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
503*0Sstevel@tonic-gate "SPEED_MAP: CSR setup failed");
504*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
505*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
506*0Sstevel@tonic-gate return (DDI_FAILURE);
507*0Sstevel@tonic-gate }
508*0Sstevel@tonic-gate
509*0Sstevel@tonic-gate /*
510*0Sstevel@tonic-gate * Reserved - Boundary between reserved Serial Bus
511*0Sstevel@tonic-gate * dependent registers and other CSR register space.
512*0Sstevel@tonic-gate * See IEEE 1394-1995, Table 8-4 for this address.
513*0Sstevel@tonic-gate *
514*0Sstevel@tonic-gate * This quadlet is reserved as a way of preventing
515*0Sstevel@tonic-gate * the inadvertant allocation of a part of CSR space
516*0Sstevel@tonic-gate * that will likely be used by future specifications
517*0Sstevel@tonic-gate */
518*0Sstevel@tonic-gate addr.aa_address = IEEE1394_UCSR_RESERVED_BOUNDARY;
519*0Sstevel@tonic-gate addr.aa_length = IEEE1394_QUADLET;
520*0Sstevel@tonic-gate result = s1394_reserve_addr_blk(hal, &addr);
521*0Sstevel@tonic-gate if (result != DDI_SUCCESS) {
522*0Sstevel@tonic-gate TNF_PROBE_1(s1394_setup_CSR_space_error,
523*0Sstevel@tonic-gate S1394_TNF_SL_CSR_ERROR, "", tnf_string, msg,
524*0Sstevel@tonic-gate "Unable to reserve boundary quadlet");
525*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit,
526*0Sstevel@tonic-gate "stacktrace 1394 s1394", "");
527*0Sstevel@tonic-gate return (DDI_FAILURE);
528*0Sstevel@tonic-gate }
529*0Sstevel@tonic-gate
530*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_setup_CSR_space_exit, S1394_TNF_SL_CSR_STACK,
531*0Sstevel@tonic-gate "");
532*0Sstevel@tonic-gate return (DDI_SUCCESS);
533*0Sstevel@tonic-gate }
534*0Sstevel@tonic-gate
535*0Sstevel@tonic-gate /*
536*0Sstevel@tonic-gate * s1394_CSR_state_clear()
537*0Sstevel@tonic-gate * handles all requests to the STATE_CLEAR CSR register. It enforces
538*0Sstevel@tonic-gate * that certain bits that can be twiddled only by a given node (IRM or
539*0Sstevel@tonic-gate * Bus Manager).
540*0Sstevel@tonic-gate */
541*0Sstevel@tonic-gate static void
s1394_CSR_state_clear(cmd1394_cmd_t * req)542*0Sstevel@tonic-gate s1394_CSR_state_clear(cmd1394_cmd_t *req)
543*0Sstevel@tonic-gate {
544*0Sstevel@tonic-gate s1394_hal_t *hal;
545*0Sstevel@tonic-gate uint32_t data;
546*0Sstevel@tonic-gate uint_t offset;
547*0Sstevel@tonic-gate uint_t is_from;
548*0Sstevel@tonic-gate uint_t should_be_from;
549*0Sstevel@tonic-gate int result;
550*0Sstevel@tonic-gate
551*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_clear_enter, S1394_TNF_SL_CSR_STACK,
552*0Sstevel@tonic-gate "");
553*0Sstevel@tonic-gate
554*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
555*0Sstevel@tonic-gate
556*0Sstevel@tonic-gate /* Register offset */
557*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
558*0Sstevel@tonic-gate
559*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
560*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
561*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
562*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
563*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_clear_exit,
564*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
565*0Sstevel@tonic-gate return;
566*0Sstevel@tonic-gate }
567*0Sstevel@tonic-gate
568*0Sstevel@tonic-gate /* Only writes from IRM or Bus Mgr allowed (in some cases) */
569*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
570*0Sstevel@tonic-gate is_from = IEEE1394_NODE_NUM(req->nodeID);
571*0Sstevel@tonic-gate if (hal->bus_mgr_node != -1)
572*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->bus_mgr_node);
573*0Sstevel@tonic-gate else if (hal->IRM_node != -1)
574*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->IRM_node);
575*0Sstevel@tonic-gate else
576*0Sstevel@tonic-gate should_be_from = S1394_INVALID_NODE_NUM;
577*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
578*0Sstevel@tonic-gate
579*0Sstevel@tonic-gate switch (req->cmd_type) {
580*0Sstevel@tonic-gate case CMD1394_ASYNCH_RD_QUAD:
581*0Sstevel@tonic-gate /*
582*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
583*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
584*0Sstevel@tonic-gate * unimplemented. But although the STATE_CLEAR register
585*0Sstevel@tonic-gate * is required to be implemented and readable, we will
586*0Sstevel@tonic-gate * return IEEE1394_RESP_ADDRESS_ERROR in the response if
587*0Sstevel@tonic-gate * we ever see this error.
588*0Sstevel@tonic-gate */
589*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_read(hal->halinfo.hal_private,
590*0Sstevel@tonic-gate offset, &data);
591*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
592*0Sstevel@tonic-gate req->cmd_u.q.quadlet_data = data;
593*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
594*0Sstevel@tonic-gate } else {
595*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
596*0Sstevel@tonic-gate }
597*0Sstevel@tonic-gate break;
598*0Sstevel@tonic-gate
599*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
600*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
601*0Sstevel@tonic-gate
602*0Sstevel@tonic-gate /* CMSTR bit - request must be from bus_mgr/IRM */
603*0Sstevel@tonic-gate if (is_from != should_be_from) {
604*0Sstevel@tonic-gate data = data & ~IEEE1394_CSR_STATE_CMSTR;
605*0Sstevel@tonic-gate }
606*0Sstevel@tonic-gate
607*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
608*0Sstevel@tonic-gate /* DREQ bit - disabling DREQ can come from anyone */
609*0Sstevel@tonic-gate if (data & IEEE1394_CSR_STATE_DREQ) {
610*0Sstevel@tonic-gate hal->disable_requests_bit = 0;
611*0Sstevel@tonic-gate if (hal->hal_state == S1394_HAL_DREQ)
612*0Sstevel@tonic-gate hal->hal_state = S1394_HAL_NORMAL;
613*0Sstevel@tonic-gate }
614*0Sstevel@tonic-gate
615*0Sstevel@tonic-gate /* ABDICATE bit */
616*0Sstevel@tonic-gate if (data & IEEE1394_CSR_STATE_ABDICATE) {
617*0Sstevel@tonic-gate hal->abdicate_bus_mgr_bit = 0;
618*0Sstevel@tonic-gate }
619*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
620*0Sstevel@tonic-gate /*
621*0Sstevel@tonic-gate * The csr_write() call can return DDI_FAILURE if the HAL
622*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
623*0Sstevel@tonic-gate * unimplemented. But although the STATE_CLEAR register
624*0Sstevel@tonic-gate * is required to be implemented and writeable, we will
625*0Sstevel@tonic-gate * return IEEE1394_RESP_ADDRESS_ERROR in the response if
626*0Sstevel@tonic-gate * we ever see this error.
627*0Sstevel@tonic-gate */
628*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
629*0Sstevel@tonic-gate offset, data);
630*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
631*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
632*0Sstevel@tonic-gate } else {
633*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
634*0Sstevel@tonic-gate }
635*0Sstevel@tonic-gate break;
636*0Sstevel@tonic-gate
637*0Sstevel@tonic-gate default:
638*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
639*0Sstevel@tonic-gate }
640*0Sstevel@tonic-gate
641*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
642*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_clear_exit, S1394_TNF_SL_CSR_STACK,
643*0Sstevel@tonic-gate "");
644*0Sstevel@tonic-gate }
645*0Sstevel@tonic-gate
646*0Sstevel@tonic-gate /*
647*0Sstevel@tonic-gate * s1394_CSR_state_set()
648*0Sstevel@tonic-gate * handles all requests to the STATE_SET CSR register. It enforces that
649*0Sstevel@tonic-gate * certain bits that can be twiddled only by a given node (IRM or Bus
650*0Sstevel@tonic-gate * Manager).
651*0Sstevel@tonic-gate */
652*0Sstevel@tonic-gate static void
s1394_CSR_state_set(cmd1394_cmd_t * req)653*0Sstevel@tonic-gate s1394_CSR_state_set(cmd1394_cmd_t *req)
654*0Sstevel@tonic-gate {
655*0Sstevel@tonic-gate s1394_hal_t *hal;
656*0Sstevel@tonic-gate uint32_t data;
657*0Sstevel@tonic-gate uint_t offset;
658*0Sstevel@tonic-gate uint_t is_from;
659*0Sstevel@tonic-gate uint_t should_be_from;
660*0Sstevel@tonic-gate uint_t hal_node_num;
661*0Sstevel@tonic-gate uint_t hal_number_of_nodes;
662*0Sstevel@tonic-gate int result;
663*0Sstevel@tonic-gate
664*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_set_enter, S1394_TNF_SL_CSR_STACK,
665*0Sstevel@tonic-gate "");
666*0Sstevel@tonic-gate
667*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
668*0Sstevel@tonic-gate
669*0Sstevel@tonic-gate /* Register offset */
670*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
671*0Sstevel@tonic-gate
672*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
673*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
674*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
675*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
676*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_set_exit,
677*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
678*0Sstevel@tonic-gate return;
679*0Sstevel@tonic-gate }
680*0Sstevel@tonic-gate
681*0Sstevel@tonic-gate /* Only writes from IRM or Bus Mgr allowed (in some cases) */
682*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
683*0Sstevel@tonic-gate is_from = IEEE1394_NODE_NUM(req->nodeID);
684*0Sstevel@tonic-gate if (hal->bus_mgr_node != -1)
685*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->bus_mgr_node);
686*0Sstevel@tonic-gate else if (hal->IRM_node != -1)
687*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->IRM_node);
688*0Sstevel@tonic-gate else
689*0Sstevel@tonic-gate should_be_from = S1394_INVALID_NODE_NUM;
690*0Sstevel@tonic-gate hal_node_num = IEEE1394_NODE_NUM(hal->node_id);
691*0Sstevel@tonic-gate hal_number_of_nodes = hal->number_of_nodes;
692*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
693*0Sstevel@tonic-gate
694*0Sstevel@tonic-gate switch (req->cmd_type) {
695*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
696*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
697*0Sstevel@tonic-gate
698*0Sstevel@tonic-gate /* CMSTR bit - request must be from bus_mgr/IRM */
699*0Sstevel@tonic-gate /* & must be root to have bit set */
700*0Sstevel@tonic-gate if ((is_from != should_be_from) ||
701*0Sstevel@tonic-gate (hal_node_num != (hal_number_of_nodes - 1))) {
702*0Sstevel@tonic-gate data = data & ~IEEE1394_CSR_STATE_CMSTR;
703*0Sstevel@tonic-gate }
704*0Sstevel@tonic-gate
705*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
706*0Sstevel@tonic-gate /* DREQ bit - only bus_mgr/IRM can set this bit */
707*0Sstevel@tonic-gate if (is_from != should_be_from) {
708*0Sstevel@tonic-gate data = data & ~IEEE1394_CSR_STATE_DREQ;
709*0Sstevel@tonic-gate
710*0Sstevel@tonic-gate } else if (data & IEEE1394_CSR_STATE_DREQ) {
711*0Sstevel@tonic-gate hal->disable_requests_bit = 1;
712*0Sstevel@tonic-gate if (hal->hal_state == S1394_HAL_NORMAL)
713*0Sstevel@tonic-gate hal->hal_state = S1394_HAL_DREQ;
714*0Sstevel@tonic-gate }
715*0Sstevel@tonic-gate /* ABDICATE bit */
716*0Sstevel@tonic-gate if (data & IEEE1394_CSR_STATE_ABDICATE) {
717*0Sstevel@tonic-gate hal->abdicate_bus_mgr_bit = 1;
718*0Sstevel@tonic-gate }
719*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
720*0Sstevel@tonic-gate /*
721*0Sstevel@tonic-gate * The csr_write() call can return DDI_FAILURE if the HAL
722*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
723*0Sstevel@tonic-gate * unimplemented. But although the STATE_SET register
724*0Sstevel@tonic-gate * is required to be implemented and writeable, we will
725*0Sstevel@tonic-gate * return IEEE1394_RESP_ADDRESS_ERROR in the response if
726*0Sstevel@tonic-gate * we ever see this error.
727*0Sstevel@tonic-gate */
728*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
729*0Sstevel@tonic-gate offset, data);
730*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
731*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
732*0Sstevel@tonic-gate } else {
733*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
734*0Sstevel@tonic-gate }
735*0Sstevel@tonic-gate break;
736*0Sstevel@tonic-gate
737*0Sstevel@tonic-gate default:
738*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
739*0Sstevel@tonic-gate }
740*0Sstevel@tonic-gate
741*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
742*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_state_set_exit, S1394_TNF_SL_CSR_STACK,
743*0Sstevel@tonic-gate "");
744*0Sstevel@tonic-gate }
745*0Sstevel@tonic-gate
746*0Sstevel@tonic-gate /*
747*0Sstevel@tonic-gate * s1394_CSR_node_ids()
748*0Sstevel@tonic-gate * handles all requests to the NODE_IDS CSR register. It passes all
749*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
750*0Sstevel@tonic-gate */
751*0Sstevel@tonic-gate static void
s1394_CSR_node_ids(cmd1394_cmd_t * req)752*0Sstevel@tonic-gate s1394_CSR_node_ids(cmd1394_cmd_t *req)
753*0Sstevel@tonic-gate {
754*0Sstevel@tonic-gate s1394_hal_t *hal;
755*0Sstevel@tonic-gate
756*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_node_ids_enter, S1394_TNF_SL_CSR_STACK, "");
757*0Sstevel@tonic-gate
758*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
759*0Sstevel@tonic-gate
760*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
761*0Sstevel@tonic-gate
762*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_node_ids_exit, S1394_TNF_SL_CSR_STACK, "");
763*0Sstevel@tonic-gate }
764*0Sstevel@tonic-gate
765*0Sstevel@tonic-gate /*
766*0Sstevel@tonic-gate * s1394_CSR_reset_start()
767*0Sstevel@tonic-gate * handles all requests to the RESET_START CSR register. Only write
768*0Sstevel@tonic-gate * requests are legal, everything else gets a type_error response.
769*0Sstevel@tonic-gate */
770*0Sstevel@tonic-gate static void
s1394_CSR_reset_start(cmd1394_cmd_t * req)771*0Sstevel@tonic-gate s1394_CSR_reset_start(cmd1394_cmd_t *req)
772*0Sstevel@tonic-gate {
773*0Sstevel@tonic-gate s1394_hal_t *hal;
774*0Sstevel@tonic-gate uint32_t data;
775*0Sstevel@tonic-gate uint_t offset;
776*0Sstevel@tonic-gate
777*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_reset_start_enter, S1394_TNF_SL_CSR_STACK,
778*0Sstevel@tonic-gate "");
779*0Sstevel@tonic-gate
780*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
781*0Sstevel@tonic-gate
782*0Sstevel@tonic-gate /* RESET_START register offset */
783*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
784*0Sstevel@tonic-gate
785*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
786*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
787*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
788*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
789*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_reset_start_exit,
790*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
791*0Sstevel@tonic-gate return;
792*0Sstevel@tonic-gate }
793*0Sstevel@tonic-gate
794*0Sstevel@tonic-gate switch (req->cmd_type) {
795*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
796*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
797*0Sstevel@tonic-gate /*
798*0Sstevel@tonic-gate * The csr_write() call can return DDI_FAILURE if the HAL
799*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
800*0Sstevel@tonic-gate * unimplemented. Because we don't do any thing with
801*0Sstevel@tonic-gate * the RESET_START register we will ignore failures and
802*0Sstevel@tonic-gate * return IEEE1394_RESP_COMPLETE regardless.
803*0Sstevel@tonic-gate */
804*0Sstevel@tonic-gate (void) HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
805*0Sstevel@tonic-gate offset, data);
806*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
807*0Sstevel@tonic-gate break;
808*0Sstevel@tonic-gate
809*0Sstevel@tonic-gate default:
810*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
811*0Sstevel@tonic-gate }
812*0Sstevel@tonic-gate
813*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
814*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_reset_start_exit, S1394_TNF_SL_CSR_STACK,
815*0Sstevel@tonic-gate "");
816*0Sstevel@tonic-gate }
817*0Sstevel@tonic-gate
818*0Sstevel@tonic-gate /*
819*0Sstevel@tonic-gate * s1394_CSR_split_timeout()
820*0Sstevel@tonic-gate * handles all requests to the SPLIT_TIMEOUT CSR register. It passes all
821*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
822*0Sstevel@tonic-gate */
823*0Sstevel@tonic-gate static void
s1394_CSR_split_timeout(cmd1394_cmd_t * req)824*0Sstevel@tonic-gate s1394_CSR_split_timeout(cmd1394_cmd_t *req)
825*0Sstevel@tonic-gate {
826*0Sstevel@tonic-gate s1394_hal_t *hal;
827*0Sstevel@tonic-gate
828*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_split_timeout_enter,
829*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
830*0Sstevel@tonic-gate
831*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
832*0Sstevel@tonic-gate
833*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
834*0Sstevel@tonic-gate
835*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_split_timeout_exit,
836*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
837*0Sstevel@tonic-gate }
838*0Sstevel@tonic-gate
839*0Sstevel@tonic-gate /*
840*0Sstevel@tonic-gate * s1394_CSR_argument_regs()
841*0Sstevel@tonic-gate * handles all requests to the ARGUMENT CSR registers. It passes all
842*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
843*0Sstevel@tonic-gate */
844*0Sstevel@tonic-gate static void
s1394_CSR_argument_regs(cmd1394_cmd_t * req)845*0Sstevel@tonic-gate s1394_CSR_argument_regs(cmd1394_cmd_t *req)
846*0Sstevel@tonic-gate {
847*0Sstevel@tonic-gate s1394_hal_t *hal;
848*0Sstevel@tonic-gate
849*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_argument_regs_enter,
850*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
851*0Sstevel@tonic-gate
852*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
853*0Sstevel@tonic-gate
854*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
855*0Sstevel@tonic-gate
856*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_argument_regs_exit,
857*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
858*0Sstevel@tonic-gate }
859*0Sstevel@tonic-gate
860*0Sstevel@tonic-gate /*
861*0Sstevel@tonic-gate * s1394_CSR_test_regs()
862*0Sstevel@tonic-gate * handles all requests to the TEST CSR registers. It passes all requests
863*0Sstevel@tonic-gate * to the common routine - s1394_common_CSR_routine().
864*0Sstevel@tonic-gate */
865*0Sstevel@tonic-gate static void
s1394_CSR_test_regs(cmd1394_cmd_t * req)866*0Sstevel@tonic-gate s1394_CSR_test_regs(cmd1394_cmd_t *req)
867*0Sstevel@tonic-gate {
868*0Sstevel@tonic-gate s1394_hal_t *hal;
869*0Sstevel@tonic-gate uint_t offset;
870*0Sstevel@tonic-gate
871*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_test_regs_enter,
872*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
873*0Sstevel@tonic-gate
874*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
875*0Sstevel@tonic-gate
876*0Sstevel@tonic-gate /* TEST register offset */
877*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
878*0Sstevel@tonic-gate
879*0Sstevel@tonic-gate /* TEST_STATUS is Read-Only */
880*0Sstevel@tonic-gate if ((offset == (IEEE1394_CSR_TEST_STATUS & IEEE1394_CSR_OFFSET_MASK)) &&
881*0Sstevel@tonic-gate (req->cmd_type == CMD1394_ASYNCH_WR_QUAD)) {
882*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
883*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
884*0Sstevel@tonic-gate } else {
885*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
886*0Sstevel@tonic-gate }
887*0Sstevel@tonic-gate
888*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_test_regs_exit,
889*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
890*0Sstevel@tonic-gate }
891*0Sstevel@tonic-gate
892*0Sstevel@tonic-gate /*
893*0Sstevel@tonic-gate * s1394_CSR_interrupt_regs()
894*0Sstevel@tonic-gate * handles all requests to the INTERRUPT CSR registers. It passes all
895*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
896*0Sstevel@tonic-gate */
897*0Sstevel@tonic-gate static void
s1394_CSR_interrupt_regs(cmd1394_cmd_t * req)898*0Sstevel@tonic-gate s1394_CSR_interrupt_regs(cmd1394_cmd_t *req)
899*0Sstevel@tonic-gate {
900*0Sstevel@tonic-gate s1394_hal_t *hal;
901*0Sstevel@tonic-gate
902*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_interrupt_regs_enter,
903*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
904*0Sstevel@tonic-gate
905*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
906*0Sstevel@tonic-gate
907*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
908*0Sstevel@tonic-gate
909*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_interrupt_regs_exit,
910*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
911*0Sstevel@tonic-gate }
912*0Sstevel@tonic-gate
913*0Sstevel@tonic-gate /*
914*0Sstevel@tonic-gate * s1394_CSR_clock_regs()
915*0Sstevel@tonic-gate * handles all requests to the CLOCK CSR registers. It passes all
916*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
917*0Sstevel@tonic-gate */
918*0Sstevel@tonic-gate static void
s1394_CSR_clock_regs(cmd1394_cmd_t * req)919*0Sstevel@tonic-gate s1394_CSR_clock_regs(cmd1394_cmd_t *req)
920*0Sstevel@tonic-gate {
921*0Sstevel@tonic-gate s1394_hal_t *hal;
922*0Sstevel@tonic-gate
923*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_clock_regs_enter,
924*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
925*0Sstevel@tonic-gate
926*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
927*0Sstevel@tonic-gate
928*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
929*0Sstevel@tonic-gate
930*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_clock_regs_exit,
931*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
932*0Sstevel@tonic-gate }
933*0Sstevel@tonic-gate
934*0Sstevel@tonic-gate /*
935*0Sstevel@tonic-gate * s1394_CSR_message_regs()
936*0Sstevel@tonic-gate * handles all requests to the MESSAGE CSR registers. It passes all
937*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
938*0Sstevel@tonic-gate */
939*0Sstevel@tonic-gate static void
s1394_CSR_message_regs(cmd1394_cmd_t * req)940*0Sstevel@tonic-gate s1394_CSR_message_regs(cmd1394_cmd_t *req)
941*0Sstevel@tonic-gate {
942*0Sstevel@tonic-gate s1394_hal_t *hal;
943*0Sstevel@tonic-gate
944*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_message_regs_enter,
945*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
946*0Sstevel@tonic-gate
947*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
948*0Sstevel@tonic-gate
949*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
950*0Sstevel@tonic-gate
951*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_message_regs_exit,
952*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
953*0Sstevel@tonic-gate }
954*0Sstevel@tonic-gate
955*0Sstevel@tonic-gate /*
956*0Sstevel@tonic-gate * s1394_CSR_cycle_time()
957*0Sstevel@tonic-gate * handles all requests to the CYCLE_TIME CSR register.
958*0Sstevel@tonic-gate */
959*0Sstevel@tonic-gate static void
s1394_CSR_cycle_time(cmd1394_cmd_t * req)960*0Sstevel@tonic-gate s1394_CSR_cycle_time(cmd1394_cmd_t *req)
961*0Sstevel@tonic-gate {
962*0Sstevel@tonic-gate s1394_hal_t *hal;
963*0Sstevel@tonic-gate uint32_t data;
964*0Sstevel@tonic-gate uint_t offset;
965*0Sstevel@tonic-gate int result;
966*0Sstevel@tonic-gate
967*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_cycle_time_enter,
968*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
969*0Sstevel@tonic-gate
970*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
971*0Sstevel@tonic-gate
972*0Sstevel@tonic-gate /* CYCLE_TIME register offset */
973*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
974*0Sstevel@tonic-gate
975*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
976*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
977*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
978*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
979*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_cycle_time_exit,
980*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
981*0Sstevel@tonic-gate return;
982*0Sstevel@tonic-gate }
983*0Sstevel@tonic-gate
984*0Sstevel@tonic-gate switch (req->cmd_type) {
985*0Sstevel@tonic-gate case CMD1394_ASYNCH_RD_QUAD:
986*0Sstevel@tonic-gate /*
987*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
988*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
989*0Sstevel@tonic-gate * unimplemented. But although the CYCLE_TIME register
990*0Sstevel@tonic-gate * is required to be implemented on devices capable of
991*0Sstevel@tonic-gate * providing isochronous services (like us), we will
992*0Sstevel@tonic-gate * return IEEE1394_RESP_ADDRESS_ERROR in the response
993*0Sstevel@tonic-gate * if we ever see this error.
994*0Sstevel@tonic-gate */
995*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_read(hal->halinfo.hal_private,
996*0Sstevel@tonic-gate offset, &data);
997*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
998*0Sstevel@tonic-gate req->cmd_u.q.quadlet_data = data;
999*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1000*0Sstevel@tonic-gate } else {
1001*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1002*0Sstevel@tonic-gate }
1003*0Sstevel@tonic-gate break;
1004*0Sstevel@tonic-gate
1005*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
1006*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
1007*0Sstevel@tonic-gate /*
1008*0Sstevel@tonic-gate * The csr_write() call can return DDI_FAILURE if the HAL
1009*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1010*0Sstevel@tonic-gate * unimplemented. But although the CYCLE_TIME register
1011*0Sstevel@tonic-gate * is required to be implemented on devices capable of
1012*0Sstevel@tonic-gate * providing isochronous services (like us), the effects
1013*0Sstevel@tonic-gate * of a write are "node-dependent" so we will return
1014*0Sstevel@tonic-gate * IEEE1394_RESP_ADDRESS_ERROR in the response if we
1015*0Sstevel@tonic-gate * ever see this error.
1016*0Sstevel@tonic-gate */
1017*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
1018*0Sstevel@tonic-gate offset, data);
1019*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1020*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1021*0Sstevel@tonic-gate } else {
1022*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1023*0Sstevel@tonic-gate }
1024*0Sstevel@tonic-gate break;
1025*0Sstevel@tonic-gate
1026*0Sstevel@tonic-gate default:
1027*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1028*0Sstevel@tonic-gate }
1029*0Sstevel@tonic-gate
1030*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1031*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_cycle_time_exit,
1032*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1033*0Sstevel@tonic-gate }
1034*0Sstevel@tonic-gate
1035*0Sstevel@tonic-gate /*
1036*0Sstevel@tonic-gate * s1394_CSR_bus_time()
1037*0Sstevel@tonic-gate * handles all requests to the BUS_TIME CSR register. It enforces that
1038*0Sstevel@tonic-gate * only a broadcast write request from the IRM or Bus Manager can change
1039*0Sstevel@tonic-gate * its value.
1040*0Sstevel@tonic-gate */
1041*0Sstevel@tonic-gate static void
s1394_CSR_bus_time(cmd1394_cmd_t * req)1042*0Sstevel@tonic-gate s1394_CSR_bus_time(cmd1394_cmd_t *req)
1043*0Sstevel@tonic-gate {
1044*0Sstevel@tonic-gate s1394_hal_t *hal;
1045*0Sstevel@tonic-gate uint32_t data;
1046*0Sstevel@tonic-gate uint_t offset;
1047*0Sstevel@tonic-gate uint_t is_from;
1048*0Sstevel@tonic-gate uint_t should_be_from;
1049*0Sstevel@tonic-gate int result;
1050*0Sstevel@tonic-gate
1051*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_bus_time_enter, S1394_TNF_SL_CSR_STACK, "");
1052*0Sstevel@tonic-gate
1053*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
1054*0Sstevel@tonic-gate
1055*0Sstevel@tonic-gate /* BUS_TIME register offset */
1056*0Sstevel@tonic-gate offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
1057*0Sstevel@tonic-gate
1058*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
1059*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
1060*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1061*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1062*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_bus_time_exit,
1063*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1064*0Sstevel@tonic-gate return;
1065*0Sstevel@tonic-gate }
1066*0Sstevel@tonic-gate
1067*0Sstevel@tonic-gate switch (req->cmd_type) {
1068*0Sstevel@tonic-gate case CMD1394_ASYNCH_RD_QUAD:
1069*0Sstevel@tonic-gate /*
1070*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
1071*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1072*0Sstevel@tonic-gate * unimplemented. But although the BUS_TIME register
1073*0Sstevel@tonic-gate * is required to be implemented by devices capable of
1074*0Sstevel@tonic-gate * being cycle master (like us), we will return
1075*0Sstevel@tonic-gate * IEEE1394_RESP_ADDRESS_ERROR in the response if we
1076*0Sstevel@tonic-gate * ever see this error.
1077*0Sstevel@tonic-gate */
1078*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_read(hal->halinfo.hal_private,
1079*0Sstevel@tonic-gate offset, &data);
1080*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1081*0Sstevel@tonic-gate req->cmd_u.q.quadlet_data = data;
1082*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1083*0Sstevel@tonic-gate } else {
1084*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1085*0Sstevel@tonic-gate }
1086*0Sstevel@tonic-gate break;
1087*0Sstevel@tonic-gate
1088*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
1089*0Sstevel@tonic-gate /* Only broadcast writes from IRM or Bus Mgr allowed */
1090*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
1091*0Sstevel@tonic-gate is_from = IEEE1394_NODE_NUM(req->nodeID);
1092*0Sstevel@tonic-gate if (hal->bus_mgr_node != -1)
1093*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->bus_mgr_node);
1094*0Sstevel@tonic-gate else if (hal->IRM_node != -1)
1095*0Sstevel@tonic-gate should_be_from = IEEE1394_NODE_NUM(hal->IRM_node);
1096*0Sstevel@tonic-gate else
1097*0Sstevel@tonic-gate should_be_from = S1394_INVALID_NODE_NUM;
1098*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
1099*0Sstevel@tonic-gate
1100*0Sstevel@tonic-gate if ((req->broadcast != 1) || (is_from != should_be_from)) {
1101*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1102*0Sstevel@tonic-gate break;
1103*0Sstevel@tonic-gate }
1104*0Sstevel@tonic-gate
1105*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
1106*0Sstevel@tonic-gate /*
1107*0Sstevel@tonic-gate * The csr_write() call can return DDI_FAILURE if the HAL
1108*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1109*0Sstevel@tonic-gate * unimplemented. But although the BUS_TIME register
1110*0Sstevel@tonic-gate * is required to be implemented on devices capable of
1111*0Sstevel@tonic-gate * being cycle master (like us), we will return
1112*0Sstevel@tonic-gate * IEEE1394_RESP_ADDRESS_ERROR in the response if we
1113*0Sstevel@tonic-gate * ever see this error.
1114*0Sstevel@tonic-gate */
1115*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
1116*0Sstevel@tonic-gate offset, data);
1117*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1118*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1119*0Sstevel@tonic-gate } else {
1120*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1121*0Sstevel@tonic-gate }
1122*0Sstevel@tonic-gate break;
1123*0Sstevel@tonic-gate
1124*0Sstevel@tonic-gate default:
1125*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1126*0Sstevel@tonic-gate }
1127*0Sstevel@tonic-gate
1128*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1129*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_bus_time_exit, S1394_TNF_SL_CSR_STACK, "");
1130*0Sstevel@tonic-gate }
1131*0Sstevel@tonic-gate
1132*0Sstevel@tonic-gate /*
1133*0Sstevel@tonic-gate * s1394_CSR_busy_timeout()
1134*0Sstevel@tonic-gate * handles all requests to the BUSY_TIMEOUT CSR register. It passes all
1135*0Sstevel@tonic-gate * requests to the common routine - s1394_common_CSR_routine().
1136*0Sstevel@tonic-gate */
1137*0Sstevel@tonic-gate static void
s1394_CSR_busy_timeout(cmd1394_cmd_t * req)1138*0Sstevel@tonic-gate s1394_CSR_busy_timeout(cmd1394_cmd_t *req)
1139*0Sstevel@tonic-gate {
1140*0Sstevel@tonic-gate s1394_hal_t *hal;
1141*0Sstevel@tonic-gate
1142*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_busy_timeout_enter,
1143*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1144*0Sstevel@tonic-gate
1145*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
1146*0Sstevel@tonic-gate
1147*0Sstevel@tonic-gate s1394_common_CSR_routine(hal, req);
1148*0Sstevel@tonic-gate
1149*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_busy_timeout_exit,
1150*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1151*0Sstevel@tonic-gate }
1152*0Sstevel@tonic-gate
1153*0Sstevel@tonic-gate /*
1154*0Sstevel@tonic-gate * s1394_CSR_IRM_regs()
1155*0Sstevel@tonic-gate * handles all requests to the IRM registers, including BANDWIDTH_AVAILABLE,
1156*0Sstevel@tonic-gate * CHANNELS_AVAILABLE, and the BUS_MANAGER_ID. Only quadlet read and lock
1157*0Sstevel@tonic-gate * requests are allowed.
1158*0Sstevel@tonic-gate */
1159*0Sstevel@tonic-gate static void
s1394_CSR_IRM_regs(cmd1394_cmd_t * req)1160*0Sstevel@tonic-gate s1394_CSR_IRM_regs(cmd1394_cmd_t *req)
1161*0Sstevel@tonic-gate {
1162*0Sstevel@tonic-gate s1394_hal_t *hal;
1163*0Sstevel@tonic-gate uint32_t generation;
1164*0Sstevel@tonic-gate uint32_t data;
1165*0Sstevel@tonic-gate uint32_t compare;
1166*0Sstevel@tonic-gate uint32_t swap;
1167*0Sstevel@tonic-gate uint32_t old;
1168*0Sstevel@tonic-gate uint_t offset;
1169*0Sstevel@tonic-gate int result;
1170*0Sstevel@tonic-gate
1171*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_IRM_regs_enter, S1394_TNF_SL_CSR_STACK, "");
1172*0Sstevel@tonic-gate
1173*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
1174*0Sstevel@tonic-gate
1175*0Sstevel@tonic-gate /* IRM register offset */
1176*0Sstevel@tonic-gate offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK);
1177*0Sstevel@tonic-gate
1178*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
1179*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
1180*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1181*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1182*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_IRM_regs_exit,
1183*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1184*0Sstevel@tonic-gate return;
1185*0Sstevel@tonic-gate }
1186*0Sstevel@tonic-gate
1187*0Sstevel@tonic-gate switch (req->cmd_type) {
1188*0Sstevel@tonic-gate case CMD1394_ASYNCH_RD_QUAD:
1189*0Sstevel@tonic-gate /*
1190*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
1191*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1192*0Sstevel@tonic-gate * unimplemented. In many cases these registers will
1193*0Sstevel@tonic-gate * have been implemented in HW. We are not likely to ever
1194*0Sstevel@tonic-gate * receive this callback. If we do, though, we will
1195*0Sstevel@tonic-gate * return IEEE1394_RESP_ADDRESS_ERROR when we get an error
1196*0Sstevel@tonic-gate * and IEEE1394_RESP_COMPLETE for success.
1197*0Sstevel@tonic-gate */
1198*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_read(hal->halinfo.hal_private,
1199*0Sstevel@tonic-gate offset, &data);
1200*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1201*0Sstevel@tonic-gate req->cmd_u.q.quadlet_data = data;
1202*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1203*0Sstevel@tonic-gate } else {
1204*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1205*0Sstevel@tonic-gate }
1206*0Sstevel@tonic-gate break;
1207*0Sstevel@tonic-gate
1208*0Sstevel@tonic-gate case CMD1394_ASYNCH_LOCK_32:
1209*0Sstevel@tonic-gate mutex_enter(&hal->topology_tree_mutex);
1210*0Sstevel@tonic-gate generation = hal->generation_count;
1211*0Sstevel@tonic-gate mutex_exit(&hal->topology_tree_mutex);
1212*0Sstevel@tonic-gate if (req->cmd_u.l32.lock_type == CMD1394_LOCK_COMPARE_SWAP) {
1213*0Sstevel@tonic-gate compare = req->cmd_u.l32.arg_value;
1214*0Sstevel@tonic-gate swap = req->cmd_u.l32.data_value;
1215*0Sstevel@tonic-gate /*
1216*0Sstevel@tonic-gate * The csr_cswap32() call can return DDI_FAILURE if
1217*0Sstevel@tonic-gate * the HAL is shutdown, if the register at "offset"
1218*0Sstevel@tonic-gate * is unimplemented, or if the generation has changed.
1219*0Sstevel@tonic-gate * In the last case, it shouldn't matter because the
1220*0Sstevel@tonic-gate * call to s1394_send_response will fail on a bad
1221*0Sstevel@tonic-gate * generation and the command will be freed.
1222*0Sstevel@tonic-gate */
1223*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_cswap32(
1224*0Sstevel@tonic-gate hal->halinfo.hal_private, generation,
1225*0Sstevel@tonic-gate offset, compare, swap, &old);
1226*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1227*0Sstevel@tonic-gate req->cmd_u.l32.old_value = old;
1228*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1229*0Sstevel@tonic-gate } else {
1230*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1231*0Sstevel@tonic-gate }
1232*0Sstevel@tonic-gate break;
1233*0Sstevel@tonic-gate } else {
1234*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1235*0Sstevel@tonic-gate }
1236*0Sstevel@tonic-gate
1237*0Sstevel@tonic-gate break;
1238*0Sstevel@tonic-gate
1239*0Sstevel@tonic-gate default:
1240*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1241*0Sstevel@tonic-gate }
1242*0Sstevel@tonic-gate
1243*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1244*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_IRM_regs_exit, S1394_TNF_SL_CSR_STACK, "");
1245*0Sstevel@tonic-gate }
1246*0Sstevel@tonic-gate
1247*0Sstevel@tonic-gate /*
1248*0Sstevel@tonic-gate * s1394_CSR_topology_map()
1249*0Sstevel@tonic-gate * handles all request for the TOPOLOGY_MAP[]. Since it is implemented
1250*0Sstevel@tonic-gate * with backing store, there isn't much to do besides return success or
1251*0Sstevel@tonic-gate * failure.
1252*0Sstevel@tonic-gate */
1253*0Sstevel@tonic-gate static void
s1394_CSR_topology_map(cmd1394_cmd_t * req)1254*0Sstevel@tonic-gate s1394_CSR_topology_map(cmd1394_cmd_t *req)
1255*0Sstevel@tonic-gate {
1256*0Sstevel@tonic-gate s1394_hal_t *hal;
1257*0Sstevel@tonic-gate
1258*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_enter,
1259*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1260*0Sstevel@tonic-gate
1261*0Sstevel@tonic-gate hal = (s1394_hal_t *)req->cmd_callback_arg;
1262*0Sstevel@tonic-gate
1263*0Sstevel@tonic-gate /* Make sure it's a quadlet read request */
1264*0Sstevel@tonic-gate if (req->cmd_type == CMD1394_ASYNCH_RD_QUAD)
1265*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1266*0Sstevel@tonic-gate else
1267*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1268*0Sstevel@tonic-gate
1269*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1270*0Sstevel@tonic-gate
1271*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_exit,
1272*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1273*0Sstevel@tonic-gate }
1274*0Sstevel@tonic-gate
1275*0Sstevel@tonic-gate /*
1276*0Sstevel@tonic-gate * s1394_CSR_topology_map_update()
1277*0Sstevel@tonic-gate * is used to update the local host's TOPOLOGY_MAP[] buffer. It copies in
1278*0Sstevel@tonic-gate * the SelfID packets, updates the generation and other fields, and
1279*0Sstevel@tonic-gate * computes the necessary CRC values before returning.
1280*0Sstevel@tonic-gate * Callers must be holding the topology_tree_mutex.
1281*0Sstevel@tonic-gate */
1282*0Sstevel@tonic-gate void
s1394_CSR_topology_map_update(s1394_hal_t * hal)1283*0Sstevel@tonic-gate s1394_CSR_topology_map_update(s1394_hal_t *hal)
1284*0Sstevel@tonic-gate {
1285*0Sstevel@tonic-gate s1394_selfid_pkt_t *selfid_packet;
1286*0Sstevel@tonic-gate uint32_t *tm_ptr;
1287*0Sstevel@tonic-gate uint32_t *data_ptr;
1288*0Sstevel@tonic-gate uint32_t node_count;
1289*0Sstevel@tonic-gate uint32_t self_id_count;
1290*0Sstevel@tonic-gate uint_t CRC;
1291*0Sstevel@tonic-gate uint32_t length;
1292*0Sstevel@tonic-gate int i, j, c;
1293*0Sstevel@tonic-gate
1294*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_update_enter,
1295*0Sstevel@tonic-gate S1394_TNF_SL_BR_CSR_STACK, "");
1296*0Sstevel@tonic-gate
1297*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->topology_tree_mutex));
1298*0Sstevel@tonic-gate
1299*0Sstevel@tonic-gate tm_ptr = (uint32_t *)hal->CSR_topology_map;
1300*0Sstevel@tonic-gate data_ptr = (uint32_t *)&(tm_ptr[3]);
1301*0Sstevel@tonic-gate
1302*0Sstevel@tonic-gate c = 0;
1303*0Sstevel@tonic-gate for (i = 0; i < hal->number_of_nodes; i++) {
1304*0Sstevel@tonic-gate j = -1;
1305*0Sstevel@tonic-gate selfid_packet = hal->selfid_ptrs[i];
1306*0Sstevel@tonic-gate
1307*0Sstevel@tonic-gate do {
1308*0Sstevel@tonic-gate j++;
1309*0Sstevel@tonic-gate data_ptr[c++] = selfid_packet[j].spkt_data;
1310*0Sstevel@tonic-gate }
1311*0Sstevel@tonic-gate while (IEEE1394_SELFID_ISMORE(&selfid_packet[j]));
1312*0Sstevel@tonic-gate }
1313*0Sstevel@tonic-gate
1314*0Sstevel@tonic-gate /* Update Topology Map Generation */
1315*0Sstevel@tonic-gate tm_ptr[1] = tm_ptr[1] + 1;
1316*0Sstevel@tonic-gate
1317*0Sstevel@tonic-gate /* Update Node_Count and Self_Id_Count */
1318*0Sstevel@tonic-gate node_count = (i & IEEE1394_TOP_MAP_LEN_MASK);
1319*0Sstevel@tonic-gate self_id_count = (c & IEEE1394_TOP_MAP_LEN_MASK);
1320*0Sstevel@tonic-gate tm_ptr[2] = (node_count << IEEE1394_TOP_MAP_LEN_SHIFT) |
1321*0Sstevel@tonic-gate (self_id_count);
1322*0Sstevel@tonic-gate
1323*0Sstevel@tonic-gate /* Calculate CRC-16 */
1324*0Sstevel@tonic-gate length = self_id_count + 2;
1325*0Sstevel@tonic-gate CRC = s1394_CRC16(&(tm_ptr[1]), length);
1326*0Sstevel@tonic-gate tm_ptr[0] = (length << IEEE1394_TOP_MAP_LEN_SHIFT) | CRC;
1327*0Sstevel@tonic-gate
1328*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_update_exit,
1329*0Sstevel@tonic-gate S1394_TNF_SL_BR_CSR_STACK, "");
1330*0Sstevel@tonic-gate }
1331*0Sstevel@tonic-gate
1332*0Sstevel@tonic-gate /*
1333*0Sstevel@tonic-gate * s1394_CSR_topology_map_disable()
1334*0Sstevel@tonic-gate * is used to disable the local host's TOPOLOGY_MAP[] buffer (during bus
1335*0Sstevel@tonic-gate * reset processing). It sets the topology map's length to zero to
1336*0Sstevel@tonic-gate * indicate that it is invalid.
1337*0Sstevel@tonic-gate */
1338*0Sstevel@tonic-gate void
s1394_CSR_topology_map_disable(s1394_hal_t * hal)1339*0Sstevel@tonic-gate s1394_CSR_topology_map_disable(s1394_hal_t *hal)
1340*0Sstevel@tonic-gate {
1341*0Sstevel@tonic-gate uint32_t *tm_ptr;
1342*0Sstevel@tonic-gate
1343*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_disable_enter,
1344*0Sstevel@tonic-gate S1394_TNF_SL_BR_CSR_STACK, "");
1345*0Sstevel@tonic-gate
1346*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->topology_tree_mutex));
1347*0Sstevel@tonic-gate
1348*0Sstevel@tonic-gate tm_ptr = (uint32_t *)hal->CSR_topology_map;
1349*0Sstevel@tonic-gate
1350*0Sstevel@tonic-gate /* Set length = 0 */
1351*0Sstevel@tonic-gate tm_ptr[0] = tm_ptr[0] & IEEE1394_TOP_MAP_LEN_MASK;
1352*0Sstevel@tonic-gate
1353*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_CSR_topology_map_disable_exit,
1354*0Sstevel@tonic-gate S1394_TNF_SL_BR_CSR_STACK, "");
1355*0Sstevel@tonic-gate }
1356*0Sstevel@tonic-gate
1357*0Sstevel@tonic-gate /*
1358*0Sstevel@tonic-gate * s1394_common_CSR_routine()
1359*0Sstevel@tonic-gate * is used to handle most of the CSR register requests. They are passed
1360*0Sstevel@tonic-gate * to the appropriate HAL entry point for further processing. Then they
1361*0Sstevel@tonic-gate * are filled in with an appropriate response code, and the response is sent.
1362*0Sstevel@tonic-gate */
1363*0Sstevel@tonic-gate static void
s1394_common_CSR_routine(s1394_hal_t * hal,cmd1394_cmd_t * req)1364*0Sstevel@tonic-gate s1394_common_CSR_routine(s1394_hal_t *hal, cmd1394_cmd_t *req)
1365*0Sstevel@tonic-gate {
1366*0Sstevel@tonic-gate uint32_t data;
1367*0Sstevel@tonic-gate uint_t offset;
1368*0Sstevel@tonic-gate int result;
1369*0Sstevel@tonic-gate
1370*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_common_CSR_routine_enter,
1371*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1372*0Sstevel@tonic-gate
1373*0Sstevel@tonic-gate /* Register offset */
1374*0Sstevel@tonic-gate offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK);
1375*0Sstevel@tonic-gate
1376*0Sstevel@tonic-gate /* Verify that request is quadlet aligned */
1377*0Sstevel@tonic-gate if ((offset & 0x3) != 0) {
1378*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1379*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1380*0Sstevel@tonic-gate }
1381*0Sstevel@tonic-gate
1382*0Sstevel@tonic-gate switch (req->cmd_type) {
1383*0Sstevel@tonic-gate case CMD1394_ASYNCH_RD_QUAD:
1384*0Sstevel@tonic-gate /*
1385*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
1386*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1387*0Sstevel@tonic-gate * unimplemented. We will return IEEE1394_RESP_ADDRESS_ERROR
1388*0Sstevel@tonic-gate * in the response if we see this error.
1389*0Sstevel@tonic-gate */
1390*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_read(hal->halinfo.hal_private,
1391*0Sstevel@tonic-gate offset, &data);
1392*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1393*0Sstevel@tonic-gate req->cmd_u.q.quadlet_data = data;
1394*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1395*0Sstevel@tonic-gate } else {
1396*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1397*0Sstevel@tonic-gate }
1398*0Sstevel@tonic-gate break;
1399*0Sstevel@tonic-gate
1400*0Sstevel@tonic-gate case CMD1394_ASYNCH_WR_QUAD:
1401*0Sstevel@tonic-gate data = req->cmd_u.q.quadlet_data;
1402*0Sstevel@tonic-gate /*
1403*0Sstevel@tonic-gate * The csr_read() call can return DDI_FAILURE if the HAL
1404*0Sstevel@tonic-gate * is shutdown or if the register at "offset" is
1405*0Sstevel@tonic-gate * unimplemented. We will return IEEE1394_RESP_ADDRESS_ERROR
1406*0Sstevel@tonic-gate * in the response if we see this error.
1407*0Sstevel@tonic-gate */
1408*0Sstevel@tonic-gate result = HAL_CALL(hal).csr_write(hal->halinfo.hal_private,
1409*0Sstevel@tonic-gate offset, data);
1410*0Sstevel@tonic-gate if (result == DDI_SUCCESS) {
1411*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_COMPLETE;
1412*0Sstevel@tonic-gate } else {
1413*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_ADDRESS_ERROR;
1414*0Sstevel@tonic-gate }
1415*0Sstevel@tonic-gate break;
1416*0Sstevel@tonic-gate
1417*0Sstevel@tonic-gate default:
1418*0Sstevel@tonic-gate req->cmd_result = IEEE1394_RESP_TYPE_ERROR;
1419*0Sstevel@tonic-gate }
1420*0Sstevel@tonic-gate
1421*0Sstevel@tonic-gate (void) s1394_send_response(hal, req);
1422*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_common_CSR_routine_exit,
1423*0Sstevel@tonic-gate S1394_TNF_SL_CSR_STACK, "");
1424*0Sstevel@tonic-gate }
1425*0Sstevel@tonic-gate
1426*0Sstevel@tonic-gate /*
1427*0Sstevel@tonic-gate * s1394_init_local_config_rom()
1428*0Sstevel@tonic-gate * is called in the HAL attach routine - h1394_attach() - to setup the
1429*0Sstevel@tonic-gate * initial Config ROM entries on the local host, including the
1430*0Sstevel@tonic-gate * bus_info_block and the root and unit directories.
1431*0Sstevel@tonic-gate */
1432*0Sstevel@tonic-gate int
s1394_init_local_config_rom(s1394_hal_t * hal)1433*0Sstevel@tonic-gate s1394_init_local_config_rom(s1394_hal_t *hal)
1434*0Sstevel@tonic-gate {
1435*0Sstevel@tonic-gate uint32_t *config_rom;
1436*0Sstevel@tonic-gate uint32_t *node_unique_id_leaf;
1437*0Sstevel@tonic-gate uint32_t *unit_dir;
1438*0Sstevel@tonic-gate uint32_t *text_leaf;
1439*0Sstevel@tonic-gate void *n_handle;
1440*0Sstevel@tonic-gate uint64_t guid;
1441*0Sstevel@tonic-gate uint32_t guid_hi, guid_lo;
1442*0Sstevel@tonic-gate uint32_t bus_capabilities;
1443*0Sstevel@tonic-gate uint32_t irmc, g;
1444*0Sstevel@tonic-gate uint32_t module_vendor_id;
1445*0Sstevel@tonic-gate uint32_t node_capabilities;
1446*0Sstevel@tonic-gate uint32_t root_dir_len;
1447*0Sstevel@tonic-gate uint32_t CRC;
1448*0Sstevel@tonic-gate int status, i, ret;
1449*0Sstevel@tonic-gate
1450*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_enter,
1451*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1452*0Sstevel@tonic-gate
1453*0Sstevel@tonic-gate /* Setup Config ROM mutex */
1454*0Sstevel@tonic-gate mutex_init(&hal->local_config_rom_mutex,
1455*0Sstevel@tonic-gate NULL, MUTEX_DRIVER, hal->halinfo.hw_interrupt);
1456*0Sstevel@tonic-gate
1457*0Sstevel@tonic-gate /* Allocate 1K for the Config ROM buffer */
1458*0Sstevel@tonic-gate hal->local_config_rom = (uint32_t *)kmem_zalloc(IEEE1394_CONFIG_ROM_SZ,
1459*0Sstevel@tonic-gate KM_SLEEP);
1460*0Sstevel@tonic-gate
1461*0Sstevel@tonic-gate /* Allocate 1K for the temporary buffer */
1462*0Sstevel@tonic-gate hal->temp_config_rom_buf = (uint32_t *)kmem_zalloc(
1463*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ, KM_SLEEP);
1464*0Sstevel@tonic-gate
1465*0Sstevel@tonic-gate config_rom = hal->local_config_rom;
1466*0Sstevel@tonic-gate
1467*0Sstevel@tonic-gate /* Lock the Config ROM buffer */
1468*0Sstevel@tonic-gate mutex_enter(&hal->local_config_rom_mutex);
1469*0Sstevel@tonic-gate
1470*0Sstevel@tonic-gate /* Build the config ROM structures */
1471*0Sstevel@tonic-gate ret = s1394_init_config_rom_structures(hal);
1472*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) {
1473*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1474*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1475*0Sstevel@tonic-gate kmem_free((void *)hal->temp_config_rom_buf,
1476*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1477*0Sstevel@tonic-gate kmem_free((void *)hal->local_config_rom,
1478*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1479*0Sstevel@tonic-gate mutex_destroy(&hal->local_config_rom_mutex);
1480*0Sstevel@tonic-gate TNF_PROBE_1(s1394_init_local_config_rom_error,
1481*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_ERROR, "", tnf_string, msg,
1482*0Sstevel@tonic-gate "Failed in s1394_init_config_rom_structures()");
1483*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_exit,
1484*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1485*0Sstevel@tonic-gate return (DDI_FAILURE);
1486*0Sstevel@tonic-gate }
1487*0Sstevel@tonic-gate /* Build the Bus_Info_Block - see IEEE 1394-1995, Section 8.3.2.5.4 */
1488*0Sstevel@tonic-gate bus_capabilities = hal->halinfo.bus_capabilities;
1489*0Sstevel@tonic-gate
1490*0Sstevel@tonic-gate /*
1491*0Sstevel@tonic-gate * If we are Isoch Resource Manager capable then we are
1492*0Sstevel@tonic-gate * Bus Manager capable too.
1493*0Sstevel@tonic-gate */
1494*0Sstevel@tonic-gate irmc = (bus_capabilities & IEEE1394_BIB_IRMC_MASK) >>
1495*0Sstevel@tonic-gate IEEE1394_BIB_IRMC_SHIFT;
1496*0Sstevel@tonic-gate if (irmc)
1497*0Sstevel@tonic-gate bus_capabilities = bus_capabilities | IEEE1394_BIB_BMC_MASK;
1498*0Sstevel@tonic-gate
1499*0Sstevel@tonic-gate /*
1500*0Sstevel@tonic-gate * Set generation to P1394a valid (but changeable)
1501*0Sstevel@tonic-gate * Even if we have a 1995 PHY, we will still provide
1502*0Sstevel@tonic-gate * certain P1394A functionality (especially with respect
1503*0Sstevel@tonic-gate * to Config ROM updates). So we must publish this
1504*0Sstevel@tonic-gate * information.
1505*0Sstevel@tonic-gate */
1506*0Sstevel@tonic-gate g = 2 << IEEE1394_BIB_GEN_SHIFT;
1507*0Sstevel@tonic-gate bus_capabilities = bus_capabilities | g;
1508*0Sstevel@tonic-gate
1509*0Sstevel@tonic-gate /* Get the GUID */
1510*0Sstevel@tonic-gate guid = hal->halinfo.guid;
1511*0Sstevel@tonic-gate guid_hi = (uint32_t)(guid >> 32);
1512*0Sstevel@tonic-gate guid_lo = (uint32_t)(guid & 0x00000000FFFFFFFF);
1513*0Sstevel@tonic-gate
1514*0Sstevel@tonic-gate config_rom[1] = 0x31333934; /* "1394" */
1515*0Sstevel@tonic-gate config_rom[2] = bus_capabilities;
1516*0Sstevel@tonic-gate config_rom[3] = guid_hi;
1517*0Sstevel@tonic-gate config_rom[4] = guid_lo;
1518*0Sstevel@tonic-gate
1519*0Sstevel@tonic-gate /* The CRC covers only our Bus_Info_Block */
1520*0Sstevel@tonic-gate CRC = s1394_CRC16(&config_rom[1], 4);
1521*0Sstevel@tonic-gate config_rom[0] = (0x04040000) | CRC;
1522*0Sstevel@tonic-gate
1523*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1524*0Sstevel@tonic-gate for (i = 0; i < IEEE1394_BIB_QUAD_SZ; i++)
1525*0Sstevel@tonic-gate config_rom[i] = T1394_DATA32(config_rom[i]);
1526*0Sstevel@tonic-gate
1527*0Sstevel@tonic-gate /* Build the Root_Directory - see IEEE 1394-1995, Section 8.3.2.5.5 */
1528*0Sstevel@tonic-gate
1529*0Sstevel@tonic-gate /* MODULE_VENDOR_ID - see IEEE 1394-1995, Section 8.3.2.5.5.1 */
1530*0Sstevel@tonic-gate module_vendor_id = S1394_SUNW_OUI;
1531*0Sstevel@tonic-gate
1532*0Sstevel@tonic-gate /* NODE_CAPABILITIES - see IEEE 1394-1995, Section 8.3.2.5.5.2 */
1533*0Sstevel@tonic-gate node_capabilities = hal->halinfo.node_capabilities &
1534*0Sstevel@tonic-gate IEEE1212_NODE_CAPABILITIES_MASK;
1535*0Sstevel@tonic-gate root_dir_len = 2;
1536*0Sstevel@tonic-gate
1537*0Sstevel@tonic-gate config_rom[6] = (IEEE1212_MODULE_VENDOR_ID <<
1538*0Sstevel@tonic-gate IEEE1212_KEY_VALUE_SHIFT) | module_vendor_id;
1539*0Sstevel@tonic-gate config_rom[7] = (IEEE1212_NODE_CAPABILITIES <<
1540*0Sstevel@tonic-gate IEEE1212_KEY_VALUE_SHIFT) | node_capabilities;
1541*0Sstevel@tonic-gate
1542*0Sstevel@tonic-gate CRC = s1394_CRC16(&config_rom[6], root_dir_len);
1543*0Sstevel@tonic-gate config_rom[IEEE1394_BIB_QUAD_SZ] =
1544*0Sstevel@tonic-gate (root_dir_len << IEEE1394_CFG_ROM_LEN_SHIFT) | CRC;
1545*0Sstevel@tonic-gate
1546*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1547*0Sstevel@tonic-gate for (i = IEEE1394_BIB_QUAD_SZ; i < 8; i++)
1548*0Sstevel@tonic-gate config_rom[i] = T1394_DATA32(config_rom[i]);
1549*0Sstevel@tonic-gate
1550*0Sstevel@tonic-gate /* Build the Root Text leaf - see IEEE 1394-1995, Section 8.3.2.5.7 */
1551*0Sstevel@tonic-gate text_leaf = (uint32_t *)kmem_zalloc(S1394_ROOT_TEXT_LEAF_SZ, KM_SLEEP);
1552*0Sstevel@tonic-gate text_leaf[1] = 0x00000000;
1553*0Sstevel@tonic-gate text_leaf[2] = 0x00000000;
1554*0Sstevel@tonic-gate text_leaf[3] = 0x53756e20; /* "Sun " */
1555*0Sstevel@tonic-gate text_leaf[4] = 0x4d696372; /* "Micr" */
1556*0Sstevel@tonic-gate text_leaf[5] = 0x6f737973; /* "osys" */
1557*0Sstevel@tonic-gate text_leaf[6] = 0x74656d73; /* "tems" */
1558*0Sstevel@tonic-gate text_leaf[7] = 0x2c20496e; /* ", In" */
1559*0Sstevel@tonic-gate text_leaf[8] = 0x632e0000; /* "c." */
1560*0Sstevel@tonic-gate CRC = s1394_CRC16(&text_leaf[1], S1394_ROOT_TEXT_LEAF_QUAD_SZ - 1);
1561*0Sstevel@tonic-gate text_leaf[0] = (0x00080000) | CRC;
1562*0Sstevel@tonic-gate
1563*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1564*0Sstevel@tonic-gate for (i = 0; i < 9; i++)
1565*0Sstevel@tonic-gate text_leaf[i] = T1394_DATA32(text_leaf[i]);
1566*0Sstevel@tonic-gate
1567*0Sstevel@tonic-gate ret = s1394_add_config_rom_entry(hal, S1394_ROOT_TEXT_KEY, text_leaf,
1568*0Sstevel@tonic-gate S1394_ROOT_TEXT_LEAF_QUAD_SZ, &n_handle, &status);
1569*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) {
1570*0Sstevel@tonic-gate kmem_free((void *)text_leaf, S1394_ROOT_TEXT_LEAF_SZ);
1571*0Sstevel@tonic-gate /* Destroy the config_rom structures */
1572*0Sstevel@tonic-gate (void) s1394_destroy_config_rom_structures(hal);
1573*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1574*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1575*0Sstevel@tonic-gate kmem_free((void *)hal->temp_config_rom_buf,
1576*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1577*0Sstevel@tonic-gate kmem_free((void *)hal->local_config_rom,
1578*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1579*0Sstevel@tonic-gate mutex_destroy(&hal->local_config_rom_mutex);
1580*0Sstevel@tonic-gate TNF_PROBE_1(s1394_init_local_config_rom_error,
1581*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_ERROR, "", tnf_string, msg,
1582*0Sstevel@tonic-gate "Failure in kmem_zalloc");
1583*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_exit,
1584*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1585*0Sstevel@tonic-gate return (DDI_FAILURE);
1586*0Sstevel@tonic-gate }
1587*0Sstevel@tonic-gate kmem_free((void *)text_leaf, S1394_ROOT_TEXT_LEAF_SZ);
1588*0Sstevel@tonic-gate
1589*0Sstevel@tonic-gate /* Build the Node_Unique_Id leaf - IEEE 1394-1995, Sect. 8.3.2.5.7.1 */
1590*0Sstevel@tonic-gate node_unique_id_leaf = (uint32_t *)kmem_zalloc(S1394_NODE_UNIQUE_ID_SZ,
1591*0Sstevel@tonic-gate KM_SLEEP);
1592*0Sstevel@tonic-gate node_unique_id_leaf[1] = guid_hi;
1593*0Sstevel@tonic-gate node_unique_id_leaf[2] = guid_lo;
1594*0Sstevel@tonic-gate CRC = s1394_CRC16(&node_unique_id_leaf[1],
1595*0Sstevel@tonic-gate S1394_NODE_UNIQUE_ID_QUAD_SZ - 1);
1596*0Sstevel@tonic-gate node_unique_id_leaf[0] = (0x00020000) | CRC;
1597*0Sstevel@tonic-gate
1598*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1599*0Sstevel@tonic-gate for (i = 0; i < S1394_NODE_UNIQUE_ID_QUAD_SZ; i++)
1600*0Sstevel@tonic-gate node_unique_id_leaf[i] = T1394_DATA32(node_unique_id_leaf[i]);
1601*0Sstevel@tonic-gate
1602*0Sstevel@tonic-gate ret = s1394_add_config_rom_entry(hal, S1394_NODE_UNIQUE_ID_KEY,
1603*0Sstevel@tonic-gate node_unique_id_leaf, S1394_NODE_UNIQUE_ID_QUAD_SZ, &n_handle,
1604*0Sstevel@tonic-gate &status);
1605*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) {
1606*0Sstevel@tonic-gate kmem_free((void *)node_unique_id_leaf,
1607*0Sstevel@tonic-gate S1394_NODE_UNIQUE_ID_SZ);
1608*0Sstevel@tonic-gate /* Destroy the config_rom structures */
1609*0Sstevel@tonic-gate (void) s1394_destroy_config_rom_structures(hal);
1610*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1611*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1612*0Sstevel@tonic-gate kmem_free((void *)hal->temp_config_rom_buf,
1613*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1614*0Sstevel@tonic-gate kmem_free((void *)hal->local_config_rom,
1615*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1616*0Sstevel@tonic-gate mutex_destroy(&hal->local_config_rom_mutex);
1617*0Sstevel@tonic-gate TNF_PROBE_1(s1394_init_local_config_rom_error,
1618*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_ERROR, "", tnf_string, msg,
1619*0Sstevel@tonic-gate "Failure in kmem_zalloc");
1620*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_exit,
1621*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1622*0Sstevel@tonic-gate return (DDI_FAILURE);
1623*0Sstevel@tonic-gate }
1624*0Sstevel@tonic-gate kmem_free((void *)node_unique_id_leaf, S1394_NODE_UNIQUE_ID_SZ);
1625*0Sstevel@tonic-gate
1626*0Sstevel@tonic-gate /* Build the Unit_Directory for 1394 Framework */
1627*0Sstevel@tonic-gate unit_dir = (uint32_t *)kmem_zalloc(S1394_UNIT_DIR_SZ, KM_SLEEP);
1628*0Sstevel@tonic-gate unit_dir[1] = 0x12080020; /* Sun Microsystems */
1629*0Sstevel@tonic-gate unit_dir[2] = 0x13000001; /* Version 1 */
1630*0Sstevel@tonic-gate unit_dir[3] = 0x81000001; /* offset to the text leaf */
1631*0Sstevel@tonic-gate CRC = s1394_CRC16(&unit_dir[1], 3);
1632*0Sstevel@tonic-gate unit_dir[0] = (0x00030000) | CRC;
1633*0Sstevel@tonic-gate
1634*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1635*0Sstevel@tonic-gate for (i = 0; i < 4; i++)
1636*0Sstevel@tonic-gate unit_dir[i] = T1394_DATA32(unit_dir[i]);
1637*0Sstevel@tonic-gate
1638*0Sstevel@tonic-gate /* Build the Unit Directory text leaf */
1639*0Sstevel@tonic-gate unit_dir[5] = 0x00000000;
1640*0Sstevel@tonic-gate unit_dir[6] = 0x00000000;
1641*0Sstevel@tonic-gate unit_dir[7] = 0x536f6c61; /* "Sola" */
1642*0Sstevel@tonic-gate unit_dir[8] = 0x72697320; /* "ris " */
1643*0Sstevel@tonic-gate unit_dir[9] = 0x31333934; /* "1394" */
1644*0Sstevel@tonic-gate unit_dir[10] = 0x20535720; /* " SW " */
1645*0Sstevel@tonic-gate unit_dir[11] = 0x4672616d; /* "Fram" */
1646*0Sstevel@tonic-gate unit_dir[12] = 0x65576f72; /* "ewor" */
1647*0Sstevel@tonic-gate unit_dir[13] = 0x6b000000; /* "k" */
1648*0Sstevel@tonic-gate CRC = s1394_CRC16(&unit_dir[5], 9);
1649*0Sstevel@tonic-gate unit_dir[4] = (0x00090000) | CRC;
1650*0Sstevel@tonic-gate
1651*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1652*0Sstevel@tonic-gate for (i = 4; i < S1394_UNIT_DIR_QUAD_SZ; i++)
1653*0Sstevel@tonic-gate unit_dir[i] = T1394_DATA32(unit_dir[i]);
1654*0Sstevel@tonic-gate
1655*0Sstevel@tonic-gate ret = s1394_add_config_rom_entry(hal, S1394_UNIT_DIR_KEY, unit_dir,
1656*0Sstevel@tonic-gate S1394_UNIT_DIR_QUAD_SZ, &n_handle, &status);
1657*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) {
1658*0Sstevel@tonic-gate kmem_free((void *)unit_dir, S1394_UNIT_DIR_SZ);
1659*0Sstevel@tonic-gate /* Destroy the config_rom structures */
1660*0Sstevel@tonic-gate (void) s1394_destroy_config_rom_structures(hal);
1661*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1662*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1663*0Sstevel@tonic-gate kmem_free((void *)hal->temp_config_rom_buf,
1664*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1665*0Sstevel@tonic-gate /* Free the 1K for the Config ROM buffer */
1666*0Sstevel@tonic-gate kmem_free((void *)hal->local_config_rom,
1667*0Sstevel@tonic-gate IEEE1394_CONFIG_ROM_SZ);
1668*0Sstevel@tonic-gate mutex_destroy(&hal->local_config_rom_mutex);
1669*0Sstevel@tonic-gate TNF_PROBE_1(s1394_init_local_config_rom_error,
1670*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_ERROR, "", tnf_string, msg,
1671*0Sstevel@tonic-gate "Failure in kmem_zalloc");
1672*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_exit,
1673*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1674*0Sstevel@tonic-gate return (DDI_FAILURE);
1675*0Sstevel@tonic-gate }
1676*0Sstevel@tonic-gate kmem_free((void *)unit_dir, S1394_UNIT_DIR_SZ);
1677*0Sstevel@tonic-gate
1678*0Sstevel@tonic-gate hal->config_rom_update_amount = (IEEE1394_CONFIG_ROM_QUAD_SZ -
1679*0Sstevel@tonic-gate hal->free_space);
1680*0Sstevel@tonic-gate
1681*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1682*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1683*0Sstevel@tonic-gate
1684*0Sstevel@tonic-gate /*
1685*0Sstevel@tonic-gate * The update_config_rom() call can return DDI_FAILURE if the
1686*0Sstevel@tonic-gate * HAL is shutdown.
1687*0Sstevel@tonic-gate */
1688*0Sstevel@tonic-gate (void) HAL_CALL(hal).update_config_rom(hal->halinfo.hal_private,
1689*0Sstevel@tonic-gate config_rom, IEEE1394_CONFIG_ROM_QUAD_SZ);
1690*0Sstevel@tonic-gate
1691*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_local_config_rom_exit,
1692*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1693*0Sstevel@tonic-gate return (DDI_SUCCESS);
1694*0Sstevel@tonic-gate }
1695*0Sstevel@tonic-gate
1696*0Sstevel@tonic-gate /*
1697*0Sstevel@tonic-gate * s1394_destroy_local_config_rom()
1698*0Sstevel@tonic-gate * is necessary for h1394_detach(). It undoes all the work that
1699*0Sstevel@tonic-gate * s1394_init_local_config_rom() had setup and more. By pulling
1700*0Sstevel@tonic-gate * everything out of the conig rom structures and freeing them and their
1701*0Sstevel@tonic-gate * associated mutexes, the Config ROM is completely cleaned up.
1702*0Sstevel@tonic-gate */
1703*0Sstevel@tonic-gate void
s1394_destroy_local_config_rom(s1394_hal_t * hal)1704*0Sstevel@tonic-gate s1394_destroy_local_config_rom(s1394_hal_t *hal)
1705*0Sstevel@tonic-gate {
1706*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_destroy_local_config_rom_enter,
1707*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1708*0Sstevel@tonic-gate
1709*0Sstevel@tonic-gate /* Lock the Config ROM buffer */
1710*0Sstevel@tonic-gate mutex_enter(&hal->local_config_rom_mutex);
1711*0Sstevel@tonic-gate
1712*0Sstevel@tonic-gate /* Destroy the config_rom structures */
1713*0Sstevel@tonic-gate (void) s1394_destroy_config_rom_structures(hal);
1714*0Sstevel@tonic-gate
1715*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
1716*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
1717*0Sstevel@tonic-gate
1718*0Sstevel@tonic-gate /* Free the 1K for the temporary buffer */
1719*0Sstevel@tonic-gate kmem_free((void *)hal->temp_config_rom_buf, IEEE1394_CONFIG_ROM_SZ);
1720*0Sstevel@tonic-gate /* Free the 1K for the Config ROM buffer */
1721*0Sstevel@tonic-gate kmem_free((void *)hal->local_config_rom, IEEE1394_CONFIG_ROM_SZ);
1722*0Sstevel@tonic-gate
1723*0Sstevel@tonic-gate /* Setup Config ROM mutex */
1724*0Sstevel@tonic-gate mutex_destroy(&hal->local_config_rom_mutex);
1725*0Sstevel@tonic-gate
1726*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_destroy_local_config_rom_exit,
1727*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1728*0Sstevel@tonic-gate }
1729*0Sstevel@tonic-gate
1730*0Sstevel@tonic-gate /*
1731*0Sstevel@tonic-gate * s1394_init_config_rom_structures()
1732*0Sstevel@tonic-gate * initializes the structures that are used to maintain the local Config ROM.
1733*0Sstevel@tonic-gate * Callers must be holding the local_config_rom_mutex.
1734*0Sstevel@tonic-gate */
1735*0Sstevel@tonic-gate static int
s1394_init_config_rom_structures(s1394_hal_t * hal)1736*0Sstevel@tonic-gate s1394_init_config_rom_structures(s1394_hal_t *hal)
1737*0Sstevel@tonic-gate {
1738*0Sstevel@tonic-gate s1394_config_rom_t *root_directory;
1739*0Sstevel@tonic-gate s1394_config_rom_t *rest_of_config_rom;
1740*0Sstevel@tonic-gate
1741*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_config_rom_structures_enter,
1742*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1743*0Sstevel@tonic-gate
1744*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->local_config_rom_mutex));
1745*0Sstevel@tonic-gate
1746*0Sstevel@tonic-gate root_directory = (s1394_config_rom_t *)kmem_zalloc(
1747*0Sstevel@tonic-gate sizeof (s1394_config_rom_t), KM_SLEEP);
1748*0Sstevel@tonic-gate
1749*0Sstevel@tonic-gate root_directory->cfgrom_used = B_TRUE;
1750*0Sstevel@tonic-gate root_directory->cfgrom_addr_lo = IEEE1394_BIB_QUAD_SZ;
1751*0Sstevel@tonic-gate root_directory->cfgrom_addr_hi = IEEE1394_BIB_QUAD_SZ + 2;
1752*0Sstevel@tonic-gate
1753*0Sstevel@tonic-gate rest_of_config_rom = (s1394_config_rom_t *)kmem_zalloc(
1754*0Sstevel@tonic-gate sizeof (s1394_config_rom_t), KM_SLEEP);
1755*0Sstevel@tonic-gate
1756*0Sstevel@tonic-gate rest_of_config_rom->cfgrom_used = B_FALSE;
1757*0Sstevel@tonic-gate rest_of_config_rom->cfgrom_addr_lo = root_directory->cfgrom_addr_hi + 1;
1758*0Sstevel@tonic-gate rest_of_config_rom->cfgrom_addr_hi = IEEE1394_CONFIG_ROM_QUAD_SZ - 1;
1759*0Sstevel@tonic-gate
1760*0Sstevel@tonic-gate root_directory->cfgrom_next = rest_of_config_rom;
1761*0Sstevel@tonic-gate root_directory->cfgrom_prev = NULL;
1762*0Sstevel@tonic-gate rest_of_config_rom->cfgrom_next = NULL;
1763*0Sstevel@tonic-gate rest_of_config_rom->cfgrom_prev = root_directory;
1764*0Sstevel@tonic-gate
1765*0Sstevel@tonic-gate hal->root_directory = root_directory;
1766*0Sstevel@tonic-gate hal->free_space = IEEE1394_CONFIG_ROM_QUAD_SZ -
1767*0Sstevel@tonic-gate (rest_of_config_rom->cfgrom_addr_lo);
1768*0Sstevel@tonic-gate
1769*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_init_config_rom_structures_exit,
1770*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1771*0Sstevel@tonic-gate return (DDI_SUCCESS);
1772*0Sstevel@tonic-gate }
1773*0Sstevel@tonic-gate
1774*0Sstevel@tonic-gate /*
1775*0Sstevel@tonic-gate * s1394_destroy_config_rom_structures()
1776*0Sstevel@tonic-gate * is used to destroy the structures that maintain the local Config ROM.
1777*0Sstevel@tonic-gate * Callers must be holding the local_config_rom_mutex.
1778*0Sstevel@tonic-gate */
1779*0Sstevel@tonic-gate static int
s1394_destroy_config_rom_structures(s1394_hal_t * hal)1780*0Sstevel@tonic-gate s1394_destroy_config_rom_structures(s1394_hal_t *hal)
1781*0Sstevel@tonic-gate {
1782*0Sstevel@tonic-gate s1394_config_rom_t *curr_blk;
1783*0Sstevel@tonic-gate s1394_config_rom_t *next_blk;
1784*0Sstevel@tonic-gate
1785*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_destroy_config_rom_structures_enter,
1786*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1787*0Sstevel@tonic-gate
1788*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->local_config_rom_mutex));
1789*0Sstevel@tonic-gate
1790*0Sstevel@tonic-gate curr_blk = hal->root_directory;
1791*0Sstevel@tonic-gate
1792*0Sstevel@tonic-gate while (curr_blk != NULL) {
1793*0Sstevel@tonic-gate next_blk = curr_blk->cfgrom_next;
1794*0Sstevel@tonic-gate kmem_free(curr_blk, sizeof (s1394_config_rom_t));
1795*0Sstevel@tonic-gate curr_blk = next_blk;
1796*0Sstevel@tonic-gate }
1797*0Sstevel@tonic-gate
1798*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_destroy_config_rom_structures_exit,
1799*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1800*0Sstevel@tonic-gate return (DDI_SUCCESS);
1801*0Sstevel@tonic-gate }
1802*0Sstevel@tonic-gate
1803*0Sstevel@tonic-gate /*
1804*0Sstevel@tonic-gate * s1394_add_config_rom_entry()
1805*0Sstevel@tonic-gate * is used to add a new entry to the local host's config ROM. By
1806*0Sstevel@tonic-gate * specifying a key and a buffer, it is possible to update the Root
1807*0Sstevel@tonic-gate * Directory to point to the new entry (in buffer). Additionally, all
1808*0Sstevel@tonic-gate * of the relevant CRCs, lengths, and generations are updated as well.
1809*0Sstevel@tonic-gate * By returning a Config ROM "handle", we can allow targets to remove
1810*0Sstevel@tonic-gate * the corresponding entry.
1811*0Sstevel@tonic-gate * Callers must be holding the local_config_rom_mutex.
1812*0Sstevel@tonic-gate */
1813*0Sstevel@tonic-gate int
s1394_add_config_rom_entry(s1394_hal_t * hal,uint8_t key,uint32_t * buffer,uint_t size,void ** handle,int * status)1814*0Sstevel@tonic-gate s1394_add_config_rom_entry(s1394_hal_t *hal, uint8_t key, uint32_t *buffer,
1815*0Sstevel@tonic-gate uint_t size, void **handle, int *status)
1816*0Sstevel@tonic-gate {
1817*0Sstevel@tonic-gate s1394_config_rom_t *curr_blk;
1818*0Sstevel@tonic-gate s1394_config_rom_t *new_blk;
1819*0Sstevel@tonic-gate uint32_t *config_rom;
1820*0Sstevel@tonic-gate uint32_t *temp_buf;
1821*0Sstevel@tonic-gate uint32_t CRC;
1822*0Sstevel@tonic-gate uint_t tmp_offset;
1823*0Sstevel@tonic-gate uint_t tmp_size, temp;
1824*0Sstevel@tonic-gate uint_t last_entry_offset;
1825*0Sstevel@tonic-gate int i;
1826*0Sstevel@tonic-gate
1827*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_add_config_rom_entry_enter,
1828*0Sstevel@tonic-gate "stacktrace 1394 s1394", "");
1829*0Sstevel@tonic-gate
1830*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->local_config_rom_mutex));
1831*0Sstevel@tonic-gate
1832*0Sstevel@tonic-gate if (size > hal->free_space) {
1833*0Sstevel@tonic-gate /* Out of space */
1834*0Sstevel@tonic-gate *status = CMD1394_ERSRC_CONFLICT;
1835*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_add_config_rom_entry_exit,
1836*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1837*0Sstevel@tonic-gate return (DDI_FAILURE);
1838*0Sstevel@tonic-gate }
1839*0Sstevel@tonic-gate
1840*0Sstevel@tonic-gate config_rom = hal->local_config_rom;
1841*0Sstevel@tonic-gate temp_buf = hal->temp_config_rom_buf;
1842*0Sstevel@tonic-gate
1843*0Sstevel@tonic-gate /* Copy the Bus_Info_Block */
1844*0Sstevel@tonic-gate bcopy(&config_rom[0], &temp_buf[0], IEEE1394_BIB_SZ);
1845*0Sstevel@tonic-gate
1846*0Sstevel@tonic-gate /* Copy and add to the Root_Directory */
1847*0Sstevel@tonic-gate tmp_offset = hal->root_directory->cfgrom_addr_lo;
1848*0Sstevel@tonic-gate tmp_size = (hal->root_directory->cfgrom_addr_hi - tmp_offset) + 1;
1849*0Sstevel@tonic-gate tmp_size = tmp_size + 1; /* For the new entry */
1850*0Sstevel@tonic-gate bcopy(&config_rom[tmp_offset], &temp_buf[tmp_offset], tmp_size << 2);
1851*0Sstevel@tonic-gate last_entry_offset = hal->root_directory->cfgrom_addr_hi + 1;
1852*0Sstevel@tonic-gate
1853*0Sstevel@tonic-gate curr_blk = hal->root_directory;
1854*0Sstevel@tonic-gate curr_blk->cfgrom_addr_hi = curr_blk->cfgrom_addr_hi + 1;
1855*0Sstevel@tonic-gate while (curr_blk->cfgrom_next != NULL) {
1856*0Sstevel@tonic-gate if (curr_blk->cfgrom_next->cfgrom_used == B_TRUE) {
1857*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_next->cfgrom_addr_lo;
1858*0Sstevel@tonic-gate tmp_size = (curr_blk->cfgrom_next->cfgrom_addr_hi -
1859*0Sstevel@tonic-gate tmp_offset) + 1;
1860*0Sstevel@tonic-gate
1861*0Sstevel@tonic-gate bcopy(&config_rom[tmp_offset],
1862*0Sstevel@tonic-gate &temp_buf[tmp_offset + 1], tmp_size << 2);
1863*0Sstevel@tonic-gate curr_blk->cfgrom_next->cfgrom_addr_lo++;
1864*0Sstevel@tonic-gate curr_blk->cfgrom_next->cfgrom_addr_hi++;
1865*0Sstevel@tonic-gate last_entry_offset =
1866*0Sstevel@tonic-gate curr_blk->cfgrom_next->cfgrom_addr_hi;
1867*0Sstevel@tonic-gate
1868*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_next->root_dir_offset;
1869*0Sstevel@tonic-gate
1870*0Sstevel@tonic-gate /* Swap... add one... then unswap */
1871*0Sstevel@tonic-gate temp = T1394_DATA32(temp_buf[tmp_offset]);
1872*0Sstevel@tonic-gate temp++;
1873*0Sstevel@tonic-gate temp_buf[tmp_offset] = T1394_DATA32(temp);
1874*0Sstevel@tonic-gate } else {
1875*0Sstevel@tonic-gate curr_blk->cfgrom_next->cfgrom_addr_lo++;
1876*0Sstevel@tonic-gate hal->free_space--;
1877*0Sstevel@tonic-gate break;
1878*0Sstevel@tonic-gate }
1879*0Sstevel@tonic-gate
1880*0Sstevel@tonic-gate curr_blk = curr_blk->cfgrom_next;
1881*0Sstevel@tonic-gate }
1882*0Sstevel@tonic-gate
1883*0Sstevel@tonic-gate /* Get the pointer to the "free" space */
1884*0Sstevel@tonic-gate curr_blk = curr_blk->cfgrom_next;
1885*0Sstevel@tonic-gate
1886*0Sstevel@tonic-gate /* Is it an exact fit? */
1887*0Sstevel@tonic-gate if (hal->free_space == size) {
1888*0Sstevel@tonic-gate curr_blk->cfgrom_used = B_TRUE;
1889*0Sstevel@tonic-gate
1890*0Sstevel@tonic-gate } else { /* Must break this piece */
1891*0Sstevel@tonic-gate new_blk = (s1394_config_rom_t *)kmem_zalloc(
1892*0Sstevel@tonic-gate sizeof (s1394_config_rom_t), KM_SLEEP);
1893*0Sstevel@tonic-gate if (new_blk == NULL) {
1894*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_add_config_rom_entry_exit,
1895*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1896*0Sstevel@tonic-gate return (DDI_FAILURE);
1897*0Sstevel@tonic-gate }
1898*0Sstevel@tonic-gate
1899*0Sstevel@tonic-gate new_blk->cfgrom_addr_hi = curr_blk->cfgrom_addr_hi;
1900*0Sstevel@tonic-gate new_blk->cfgrom_addr_lo = curr_blk->cfgrom_addr_lo + size;
1901*0Sstevel@tonic-gate curr_blk->cfgrom_addr_hi = new_blk->cfgrom_addr_lo - 1;
1902*0Sstevel@tonic-gate new_blk->cfgrom_next = curr_blk->cfgrom_next;
1903*0Sstevel@tonic-gate curr_blk->cfgrom_next = new_blk;
1904*0Sstevel@tonic-gate new_blk->cfgrom_prev = curr_blk;
1905*0Sstevel@tonic-gate curr_blk->cfgrom_used = B_TRUE;
1906*0Sstevel@tonic-gate last_entry_offset = curr_blk->cfgrom_addr_hi;
1907*0Sstevel@tonic-gate }
1908*0Sstevel@tonic-gate hal->free_space = hal->free_space - size;
1909*0Sstevel@tonic-gate
1910*0Sstevel@tonic-gate /* Copy in the new entry */
1911*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_addr_lo;
1912*0Sstevel@tonic-gate bcopy(buffer, &temp_buf[tmp_offset], size << 2);
1913*0Sstevel@tonic-gate
1914*0Sstevel@tonic-gate /* Update root directory */
1915*0Sstevel@tonic-gate tmp_offset = hal->root_directory->cfgrom_addr_hi;
1916*0Sstevel@tonic-gate tmp_size = tmp_offset - hal->root_directory->cfgrom_addr_lo;
1917*0Sstevel@tonic-gate curr_blk->root_dir_offset = tmp_offset;
1918*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_addr_lo - tmp_offset;
1919*0Sstevel@tonic-gate
1920*0Sstevel@tonic-gate temp_buf[hal->root_directory->cfgrom_addr_hi] =
1921*0Sstevel@tonic-gate T1394_DATA32((((uint32_t)key) << IEEE1212_KEY_VALUE_SHIFT) |
1922*0Sstevel@tonic-gate tmp_offset);
1923*0Sstevel@tonic-gate tmp_offset = hal->root_directory->cfgrom_addr_lo;
1924*0Sstevel@tonic-gate
1925*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
1926*0Sstevel@tonic-gate for (i = (tmp_offset + 1); i <= hal->root_directory->cfgrom_addr_hi;
1927*0Sstevel@tonic-gate i++)
1928*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(temp_buf[i]);
1929*0Sstevel@tonic-gate
1930*0Sstevel@tonic-gate CRC = s1394_CRC16(&temp_buf[tmp_offset + 1], tmp_size);
1931*0Sstevel@tonic-gate temp_buf[tmp_offset] = (tmp_size << IEEE1394_CFG_ROM_LEN_SHIFT) | CRC;
1932*0Sstevel@tonic-gate
1933*0Sstevel@tonic-gate /* Redo byte-swapping if necessary (x86) */
1934*0Sstevel@tonic-gate for (i = tmp_offset; i <= hal->root_directory->cfgrom_addr_hi; i++)
1935*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(temp_buf[i]);
1936*0Sstevel@tonic-gate
1937*0Sstevel@tonic-gate /* Copy it back to config_rom buffer */
1938*0Sstevel@tonic-gate last_entry_offset++;
1939*0Sstevel@tonic-gate bcopy(&temp_buf[0], &config_rom[0], last_entry_offset << 2);
1940*0Sstevel@tonic-gate
1941*0Sstevel@tonic-gate /* Return a handle to this block */
1942*0Sstevel@tonic-gate *handle = curr_blk;
1943*0Sstevel@tonic-gate
1944*0Sstevel@tonic-gate *status = T1394_NOERROR;
1945*0Sstevel@tonic-gate
1946*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_add_config_rom_entry_exit,
1947*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1948*0Sstevel@tonic-gate return (DDI_SUCCESS);
1949*0Sstevel@tonic-gate }
1950*0Sstevel@tonic-gate
1951*0Sstevel@tonic-gate /*
1952*0Sstevel@tonic-gate * s1394_remove_config_rom_entry()
1953*0Sstevel@tonic-gate * is used to remove an entry from the local host's config ROM. By
1954*0Sstevel@tonic-gate * specifying the Config ROM "handle" that was given in the allocation,
1955*0Sstevel@tonic-gate * it is possible to remove the entry. Subsequently, the Config ROM is
1956*0Sstevel@tonic-gate * updated again.
1957*0Sstevel@tonic-gate * Callers must be holding the local_config_rom_mutex.
1958*0Sstevel@tonic-gate */
1959*0Sstevel@tonic-gate int
s1394_remove_config_rom_entry(s1394_hal_t * hal,void ** handle,int * status)1960*0Sstevel@tonic-gate s1394_remove_config_rom_entry(s1394_hal_t *hal, void **handle, int *status)
1961*0Sstevel@tonic-gate {
1962*0Sstevel@tonic-gate s1394_config_rom_t *del_blk;
1963*0Sstevel@tonic-gate s1394_config_rom_t *curr_blk;
1964*0Sstevel@tonic-gate s1394_config_rom_t *last_blk;
1965*0Sstevel@tonic-gate s1394_config_rom_t *free_blk;
1966*0Sstevel@tonic-gate uint32_t *config_rom;
1967*0Sstevel@tonic-gate uint32_t *temp_buf;
1968*0Sstevel@tonic-gate uint32_t entry;
1969*0Sstevel@tonic-gate uint_t CRC;
1970*0Sstevel@tonic-gate uint_t root_offset;
1971*0Sstevel@tonic-gate uint_t del_offset;
1972*0Sstevel@tonic-gate uint_t tmp_offset;
1973*0Sstevel@tonic-gate uint_t tmp_size;
1974*0Sstevel@tonic-gate int i;
1975*0Sstevel@tonic-gate
1976*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_remove_config_rom_entry_enter,
1977*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
1978*0Sstevel@tonic-gate
1979*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&hal->local_config_rom_mutex));
1980*0Sstevel@tonic-gate
1981*0Sstevel@tonic-gate del_blk = (s1394_config_rom_t *)(*handle);
1982*0Sstevel@tonic-gate
1983*0Sstevel@tonic-gate config_rom = hal->local_config_rom;
1984*0Sstevel@tonic-gate temp_buf = hal->temp_config_rom_buf;
1985*0Sstevel@tonic-gate
1986*0Sstevel@tonic-gate /* Copy the Bus_Info_Block */
1987*0Sstevel@tonic-gate bcopy(&config_rom[0], &temp_buf[0], IEEE1394_BIB_SZ);
1988*0Sstevel@tonic-gate
1989*0Sstevel@tonic-gate root_offset = hal->root_directory->cfgrom_addr_lo;
1990*0Sstevel@tonic-gate del_offset = del_blk->root_dir_offset;
1991*0Sstevel@tonic-gate
1992*0Sstevel@tonic-gate /* Update Root_Directory entries before the deleted one */
1993*0Sstevel@tonic-gate for (i = root_offset; i < del_offset; i++) {
1994*0Sstevel@tonic-gate entry = T1394_DATA32(config_rom[i]);
1995*0Sstevel@tonic-gate
1996*0Sstevel@tonic-gate /* If entry is an offset address - update it */
1997*0Sstevel@tonic-gate if (entry & 0x80000000)
1998*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(entry - 1);
1999*0Sstevel@tonic-gate else
2000*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(entry);
2001*0Sstevel@tonic-gate }
2002*0Sstevel@tonic-gate
2003*0Sstevel@tonic-gate /* Move all Unit_Directories prior to the deleted one */
2004*0Sstevel@tonic-gate curr_blk = hal->root_directory->cfgrom_next;
2005*0Sstevel@tonic-gate
2006*0Sstevel@tonic-gate while (curr_blk != del_blk) {
2007*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_addr_lo;
2008*0Sstevel@tonic-gate tmp_size = (curr_blk->cfgrom_addr_hi - tmp_offset) + 1;
2009*0Sstevel@tonic-gate
2010*0Sstevel@tonic-gate bcopy(&config_rom[tmp_offset], &temp_buf[tmp_offset - 1],
2011*0Sstevel@tonic-gate tmp_size << 2);
2012*0Sstevel@tonic-gate curr_blk->cfgrom_addr_lo--;
2013*0Sstevel@tonic-gate curr_blk->cfgrom_addr_hi--;
2014*0Sstevel@tonic-gate curr_blk = curr_blk->cfgrom_next;
2015*0Sstevel@tonic-gate }
2016*0Sstevel@tonic-gate
2017*0Sstevel@tonic-gate /* Move all Unit_Directories after the deleted one */
2018*0Sstevel@tonic-gate curr_blk = del_blk->cfgrom_next;
2019*0Sstevel@tonic-gate last_blk = del_blk->cfgrom_prev;
2020*0Sstevel@tonic-gate
2021*0Sstevel@tonic-gate del_offset = (del_blk->cfgrom_addr_hi - del_blk->cfgrom_addr_lo) + 1;
2022*0Sstevel@tonic-gate
2023*0Sstevel@tonic-gate while ((curr_blk != NULL) && (curr_blk->cfgrom_used == B_TRUE)) {
2024*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_addr_lo;
2025*0Sstevel@tonic-gate tmp_size = (curr_blk->cfgrom_addr_hi - tmp_offset) + 1;
2026*0Sstevel@tonic-gate
2027*0Sstevel@tonic-gate bcopy(&config_rom[tmp_offset],
2028*0Sstevel@tonic-gate &temp_buf[tmp_offset - (del_offset + 1)], tmp_size << 2);
2029*0Sstevel@tonic-gate
2030*0Sstevel@tonic-gate root_offset = curr_blk->root_dir_offset;
2031*0Sstevel@tonic-gate temp_buf[root_offset - 1] =
2032*0Sstevel@tonic-gate config_rom[root_offset] - del_offset;
2033*0Sstevel@tonic-gate curr_blk->root_dir_offset--;
2034*0Sstevel@tonic-gate curr_blk->cfgrom_addr_lo = curr_blk->cfgrom_addr_lo -
2035*0Sstevel@tonic-gate (del_offset + 1);
2036*0Sstevel@tonic-gate curr_blk->cfgrom_addr_hi = curr_blk->cfgrom_addr_hi -
2037*0Sstevel@tonic-gate (del_offset + 1);
2038*0Sstevel@tonic-gate
2039*0Sstevel@tonic-gate last_blk = curr_blk;
2040*0Sstevel@tonic-gate curr_blk = curr_blk->cfgrom_next;
2041*0Sstevel@tonic-gate }
2042*0Sstevel@tonic-gate
2043*0Sstevel@tonic-gate /* Remove del_blk from the list */
2044*0Sstevel@tonic-gate if (del_blk->cfgrom_prev != NULL)
2045*0Sstevel@tonic-gate del_blk->cfgrom_prev->cfgrom_next = del_blk->cfgrom_next;
2046*0Sstevel@tonic-gate
2047*0Sstevel@tonic-gate if (del_blk->cfgrom_next != NULL)
2048*0Sstevel@tonic-gate del_blk->cfgrom_next->cfgrom_prev = del_blk->cfgrom_prev;
2049*0Sstevel@tonic-gate
2050*0Sstevel@tonic-gate del_blk->cfgrom_prev = NULL;
2051*0Sstevel@tonic-gate del_blk->cfgrom_next = NULL;
2052*0Sstevel@tonic-gate kmem_free((void *)del_blk, sizeof (s1394_config_rom_t));
2053*0Sstevel@tonic-gate
2054*0Sstevel@tonic-gate /* Update and zero out the "free" block */
2055*0Sstevel@tonic-gate if (curr_blk != NULL) {
2056*0Sstevel@tonic-gate curr_blk->cfgrom_addr_lo = curr_blk->cfgrom_addr_lo -
2057*0Sstevel@tonic-gate (del_offset + 1);
2058*0Sstevel@tonic-gate
2059*0Sstevel@tonic-gate } else {
2060*0Sstevel@tonic-gate free_blk = (s1394_config_rom_t *)kmem_zalloc(
2061*0Sstevel@tonic-gate sizeof (s1394_config_rom_t), KM_SLEEP);
2062*0Sstevel@tonic-gate if (free_blk == NULL) {
2063*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_remove_config_rom_entry_exit,
2064*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
2065*0Sstevel@tonic-gate return (DDI_FAILURE);
2066*0Sstevel@tonic-gate }
2067*0Sstevel@tonic-gate
2068*0Sstevel@tonic-gate free_blk->cfgrom_used = B_FALSE;
2069*0Sstevel@tonic-gate free_blk->cfgrom_addr_lo = (IEEE1394_CONFIG_ROM_QUAD_SZ - 1) -
2070*0Sstevel@tonic-gate (del_offset + 1);
2071*0Sstevel@tonic-gate free_blk->cfgrom_addr_hi = (IEEE1394_CONFIG_ROM_QUAD_SZ - 1);
2072*0Sstevel@tonic-gate
2073*0Sstevel@tonic-gate free_blk->cfgrom_prev = last_blk;
2074*0Sstevel@tonic-gate free_blk->cfgrom_next = NULL;
2075*0Sstevel@tonic-gate curr_blk = free_blk;
2076*0Sstevel@tonic-gate }
2077*0Sstevel@tonic-gate hal->free_space = hal->free_space + (del_offset + 1);
2078*0Sstevel@tonic-gate tmp_offset = curr_blk->cfgrom_addr_lo;
2079*0Sstevel@tonic-gate tmp_size = (curr_blk->cfgrom_addr_hi - tmp_offset) + 1;
2080*0Sstevel@tonic-gate bzero(&temp_buf[tmp_offset], tmp_size << 2);
2081*0Sstevel@tonic-gate
2082*0Sstevel@tonic-gate
2083*0Sstevel@tonic-gate /* Update root directory */
2084*0Sstevel@tonic-gate hal->root_directory->cfgrom_addr_hi--;
2085*0Sstevel@tonic-gate tmp_offset = hal->root_directory->cfgrom_addr_lo;
2086*0Sstevel@tonic-gate tmp_size = hal->root_directory->cfgrom_addr_hi - tmp_offset;
2087*0Sstevel@tonic-gate
2088*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
2089*0Sstevel@tonic-gate for (i = (tmp_offset + 1); i <= hal->root_directory->cfgrom_addr_hi;
2090*0Sstevel@tonic-gate i++)
2091*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(temp_buf[i]);
2092*0Sstevel@tonic-gate
2093*0Sstevel@tonic-gate CRC = s1394_CRC16(&temp_buf[tmp_offset + 1], tmp_size);
2094*0Sstevel@tonic-gate temp_buf[tmp_offset] = (tmp_size << IEEE1394_CFG_ROM_LEN_SHIFT) | CRC;
2095*0Sstevel@tonic-gate
2096*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
2097*0Sstevel@tonic-gate for (i = (tmp_offset + 1); i <= hal->root_directory->cfgrom_addr_hi;
2098*0Sstevel@tonic-gate i++)
2099*0Sstevel@tonic-gate temp_buf[i] = T1394_DATA32(temp_buf[i]);
2100*0Sstevel@tonic-gate
2101*0Sstevel@tonic-gate /* Copy it back to config_rom buffer */
2102*0Sstevel@tonic-gate tmp_size = IEEE1394_CONFIG_ROM_SZ - (hal->free_space << 2);
2103*0Sstevel@tonic-gate bcopy(&temp_buf[0], &config_rom[0], tmp_size);
2104*0Sstevel@tonic-gate
2105*0Sstevel@tonic-gate /* Return a handle to this block */
2106*0Sstevel@tonic-gate *handle = NULL;
2107*0Sstevel@tonic-gate
2108*0Sstevel@tonic-gate *status = T1394_NOERROR;
2109*0Sstevel@tonic-gate
2110*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_remove_config_rom_entry_exit,
2111*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
2112*0Sstevel@tonic-gate return (DDI_SUCCESS);
2113*0Sstevel@tonic-gate }
2114*0Sstevel@tonic-gate
2115*0Sstevel@tonic-gate /*
2116*0Sstevel@tonic-gate * s1394_update_config_rom_callback()
2117*0Sstevel@tonic-gate * is the callback used by t1394_add_cfgrom_entry() and
2118*0Sstevel@tonic-gate * t1394_rem_cfgrom_entry(). After a target updates the Config ROM, a
2119*0Sstevel@tonic-gate * timer is set with this as its callback function. This is to reduce
2120*0Sstevel@tonic-gate * the number of bus resets that would be necessary if many targets
2121*0Sstevel@tonic-gate * wished to update the Config ROM simultaneously.
2122*0Sstevel@tonic-gate */
2123*0Sstevel@tonic-gate void
s1394_update_config_rom_callback(void * arg)2124*0Sstevel@tonic-gate s1394_update_config_rom_callback(void *arg)
2125*0Sstevel@tonic-gate {
2126*0Sstevel@tonic-gate s1394_hal_t *hal;
2127*0Sstevel@tonic-gate uint32_t *config_rom;
2128*0Sstevel@tonic-gate uint32_t bus_capabilities;
2129*0Sstevel@tonic-gate uint32_t g;
2130*0Sstevel@tonic-gate uint_t CRC;
2131*0Sstevel@tonic-gate uint_t last_entry_offset;
2132*0Sstevel@tonic-gate int i, ret;
2133*0Sstevel@tonic-gate
2134*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_update_config_rom_callback_enter,
2135*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
2136*0Sstevel@tonic-gate
2137*0Sstevel@tonic-gate hal = (s1394_hal_t *)arg;
2138*0Sstevel@tonic-gate
2139*0Sstevel@tonic-gate /* Lock the Config ROM buffer */
2140*0Sstevel@tonic-gate mutex_enter(&hal->local_config_rom_mutex);
2141*0Sstevel@tonic-gate
2142*0Sstevel@tonic-gate config_rom = hal->local_config_rom;
2143*0Sstevel@tonic-gate
2144*0Sstevel@tonic-gate /* Update Generation and CRC for Bus_Info_Block */
2145*0Sstevel@tonic-gate
2146*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
2147*0Sstevel@tonic-gate for (i = 0; i < IEEE1394_BIB_QUAD_SZ; i++)
2148*0Sstevel@tonic-gate config_rom[i] = T1394_DATA32(config_rom[i]);
2149*0Sstevel@tonic-gate
2150*0Sstevel@tonic-gate bus_capabilities = config_rom[IEEE1212_NODE_CAP_QUAD];
2151*0Sstevel@tonic-gate g = ((bus_capabilities & IEEE1394_BIB_GEN_MASK) >>
2152*0Sstevel@tonic-gate IEEE1394_BIB_GEN_SHIFT) + 1;
2153*0Sstevel@tonic-gate if (g > 15)
2154*0Sstevel@tonic-gate g = 2;
2155*0Sstevel@tonic-gate g = g << IEEE1394_BIB_GEN_SHIFT;
2156*0Sstevel@tonic-gate
2157*0Sstevel@tonic-gate bus_capabilities = (bus_capabilities & (~IEEE1394_BIB_GEN_MASK)) | g;
2158*0Sstevel@tonic-gate config_rom[IEEE1212_NODE_CAP_QUAD] = bus_capabilities;
2159*0Sstevel@tonic-gate
2160*0Sstevel@tonic-gate CRC = s1394_CRC16(&config_rom[1], IEEE1394_BIB_QUAD_SZ - 1);
2161*0Sstevel@tonic-gate config_rom[0] = (0x04040000) | CRC;
2162*0Sstevel@tonic-gate
2163*0Sstevel@tonic-gate /* Do byte-swapping if necessary (x86) */
2164*0Sstevel@tonic-gate for (i = 0; i < IEEE1394_BIB_QUAD_SZ; i++)
2165*0Sstevel@tonic-gate config_rom[i] = T1394_DATA32(config_rom[i]);
2166*0Sstevel@tonic-gate
2167*0Sstevel@tonic-gate /* Make sure we update only what is necessary */
2168*0Sstevel@tonic-gate last_entry_offset = (IEEE1394_CONFIG_ROM_QUAD_SZ - hal->free_space);
2169*0Sstevel@tonic-gate if (last_entry_offset < hal->config_rom_update_amount)
2170*0Sstevel@tonic-gate last_entry_offset = hal->config_rom_update_amount;
2171*0Sstevel@tonic-gate
2172*0Sstevel@tonic-gate hal->config_rom_update_amount = (IEEE1394_CONFIG_ROM_QUAD_SZ -
2173*0Sstevel@tonic-gate hal->free_space);
2174*0Sstevel@tonic-gate
2175*0Sstevel@tonic-gate /* Clear the timer flag */
2176*0Sstevel@tonic-gate hal->config_rom_timer_set = B_FALSE;
2177*0Sstevel@tonic-gate
2178*0Sstevel@tonic-gate /* Unlock the Config ROM buffer */
2179*0Sstevel@tonic-gate mutex_exit(&hal->local_config_rom_mutex);
2180*0Sstevel@tonic-gate
2181*0Sstevel@tonic-gate /*
2182*0Sstevel@tonic-gate * The update_config_rom() call can return DDI_FAILURE if the
2183*0Sstevel@tonic-gate * HAL is shutdown.
2184*0Sstevel@tonic-gate */
2185*0Sstevel@tonic-gate (void) HAL_CALL(hal).update_config_rom(hal->halinfo.hal_private,\
2186*0Sstevel@tonic-gate config_rom, last_entry_offset);
2187*0Sstevel@tonic-gate
2188*0Sstevel@tonic-gate /* Initiate a bus reset */
2189*0Sstevel@tonic-gate ret = HAL_CALL(hal).bus_reset(hal->halinfo.hal_private);
2190*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) {
2191*0Sstevel@tonic-gate TNF_PROBE_1(s1394_update_config_rom_callback_error,
2192*0Sstevel@tonic-gate S1394_TNF_SL_ERROR, "", tnf_string, msg,
2193*0Sstevel@tonic-gate "Error initiating bus reset");
2194*0Sstevel@tonic-gate }
2195*0Sstevel@tonic-gate
2196*0Sstevel@tonic-gate TNF_PROBE_0_DEBUG(s1394_update_config_rom_callback_exit,
2197*0Sstevel@tonic-gate S1394_TNF_SL_CFGROM_STACK, "");
2198*0Sstevel@tonic-gate }
2199