1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * hci1394_extern.c 31*0Sstevel@tonic-gate * Central location for externs. There are two exceptions to this, 32*0Sstevel@tonic-gate * hci1394_statep (located in hci1394.c) and hci1394_evts (located in 33*0Sstevel@tonic-gate * hci1394_s1394if.c). 34*0Sstevel@tonic-gate */ 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #include <sys/conf.h> 37*0Sstevel@tonic-gate #include <sys/ddi.h> 38*0Sstevel@tonic-gate #include <sys/modctl.h> 39*0Sstevel@tonic-gate #include <sys/stat.h> 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate #include <sys/1394/h1394.h> 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate #include <sys/1394/adapters/hci1394.h> 44*0Sstevel@tonic-gate 45*0Sstevel@tonic-gate 46*0Sstevel@tonic-gate 47*0Sstevel@tonic-gate /* 48*0Sstevel@tonic-gate * The 1394 bus ticks are in 125uS increments. split_timeout is represented in 49*0Sstevel@tonic-gate * 1394 bus ticks. 800 bus ticks is 100mS. 50*0Sstevel@tonic-gate */ 51*0Sstevel@tonic-gate uint32_t hci1394_split_timeout = 800; 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate /* 55*0Sstevel@tonic-gate * 1394 address map for OpenHCI adpaters. 56*0Sstevel@tonic-gate * 57*0Sstevel@tonic-gate * This is what is reported to the services layer. The hci1394 driver does not 58*0Sstevel@tonic-gate * modify the HW to reflect this. This should reflect what the OpenHCI 1.0 HW 59*0Sstevel@tonic-gate * is set to. The comments below give the actual address ranges where the 60*0Sstevel@tonic-gate * actual structure has the format of - start address, size, type. 61*0Sstevel@tonic-gate * 62*0Sstevel@tonic-gate * physical => 0x0000000000000000 - 0x00000000FFFFFFFF 63*0Sstevel@tonic-gate * posted write => 0x0000000100000000 - 0x0000FFFEFFFFFFFF 64*0Sstevel@tonic-gate * normal => 0x0000FFFF00000000 - 0x0000FFFFEFFFFFFF 65*0Sstevel@tonic-gate * csr => 0x0000FFFFF0000000 - 0x0000FFFFFFFFFFFF 66*0Sstevel@tonic-gate */ 67*0Sstevel@tonic-gate h1394_addr_map_t hci1394_addr_map[HCI1394_ADDR_MAP_SIZE] = { 68*0Sstevel@tonic-gate {0x0000000000000000, 0x0000000100000000, H1394_ADDR_PHYSICAL}, 69*0Sstevel@tonic-gate {0x0000000100000000, 0x0000FFFE00000000, H1394_ADDR_POSTED_WRITE}, 70*0Sstevel@tonic-gate {0x0000FFFF00000000, 0x00000000F0000000, H1394_ADDR_NORMAL}, 71*0Sstevel@tonic-gate {0x0000FFFFF0000000, 0x0000000010000000, H1394_ADDR_CSR} 72*0Sstevel@tonic-gate }; 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate /* Max number of uS to wait for phy reads & writes to finish */ 76*0Sstevel@tonic-gate uint_t hci1394_phy_delay_uS = 10; 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate /* 79*0Sstevel@tonic-gate * Time to wait for PHY to SCLK to be stable. There does not seem to be standard 80*0Sstevel@tonic-gate * time for how long wait for the PHY to come up. The problem is that the PHY 81*0Sstevel@tonic-gate * provides a clock to the link layer and if that is not stable, we could get a 82*0Sstevel@tonic-gate * PCI timeout error when reading/writing a phy register (and maybe an OpenHCI 83*0Sstevel@tonic-gate * register?) This used to be set to 10mS which works for just about every 84*0Sstevel@tonic-gate * adapter we tested on. We got a new TI adapter which would crash the system 85*0Sstevel@tonic-gate * once in a while if nothing (1394 device) was plugged into the adapter? 86*0Sstevel@tonic-gate * Changing this delay to 50mS made that problem go away. 87*0Sstevel@tonic-gate * 88*0Sstevel@tonic-gate * NOTE: Do not this delay unless you know what your doing!!!! 89*0Sstevel@tonic-gate */ 90*0Sstevel@tonic-gate uint_t hci1394_phy_stabilization_delay_uS = 50000; 91