1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 2008, Intel Corporation 29 * All rights reserved. 30 */ 31 32/* 33 * Portions Copyright 2009 Advanced Micro Devices, Inc. 34 */ 35 36/* 37 * Assembler support routines to getcpuid information used to set 38 * cache size information. Cache information used by memset, strcpy, etc.. 39 */ 40 41 .file "proc64_support.s" 42 43#include <sys/asm_linkage.h> 44#include "proc64_id.h" 45 46 .global .memops_method 47 .global .amd64cache1, .amd64cache1half, .amd64cache2, .amd64cache2half 48 .global .largest_level_cache_size 49 50 51/* 52 * Defaults for Core 2 Duo and AMD's SledgeHammer 53 */ 54 .data 55 .balign 8 56.memops_method: 57 .int NO_SSE 58 59 .balign 8 60.amd64cache1: .quad AMD_DFLT_L1_CACHE_SIZE 61.amd64cache1half: .quad AMD_DFLT_L1_CACHE_SIZE/2 62.amd64cache2: .quad AMD_DFLT_L2_CACHE_SIZE 63.amd64cache2half: .quad AMD_DFLT_L2_CACHE_SIZE/2 64.largest_level_cache_size: 65 .int AMD_DFLT_L2_CACHE_SIZE 66 67/* 68 * Get cpuid data. 69 * (void)__libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index ) 70 */ 71 .text 72 73 ENTRY(__libc_get_cpuid) 74 # rdi = cpuid function, rsi = out_reg addr, rdx = cache index(fn 4) 75 push %rbx 76 mov %edx,%ecx 77 mov %edi,%eax 78 cpuid 79 mov %eax,(%rsi) 80 mov %ebx,0x4(%rsi) 81 mov %ecx,0x8(%rsi) 82 mov %edx,0xc(%rsi) 83 pop %rbx 84 ret 85 SET_SIZE(__libc_get_cpuid) 86 87/* 88 * Set memops SSE level to use. 89 * void __intel_set_memops_method(long sse_level); 90 */ 91 ENTRY(__intel_set_memops_method) 92 mov %edi,.memops_method(%rip) 93 ret 94 SET_SIZE(__intel_set_memops_method) 95 96/* 97 * Set cache info global variables used by various libc primitives. 98 * __set_cache_sizes(long l1_cache_size, long l2_cache_size, 99 * long largest_level_cache); 100 */ 101 ENTRY(__set_cache_sizes) 102 # rdi = l1_cache_size, rsi = l2_cache_size, rdx = largest_level_cache 103 104 mov %rdi,.amd64cache1(%rip) 105 shr $1, %rdi 106 mov %rdi,.amd64cache1half(%rip) 107 108 mov %rsi,.amd64cache2(%rip) 109 shr $1, %rsi 110 mov %rsi,.amd64cache2half(%rip) 111 112 mov %rdx,.largest_level_cache_size(%rip) 113 ret 114 SET_SIZE(__set_cache_sizes) 115