16429Svs195195 /* 26429Svs195195 * CDDL HEADER START 36429Svs195195 * 46429Svs195195 * The contents of this file are subject to the terms of the 56429Svs195195 * Common Development and Distribution License (the "License"). 66429Svs195195 * You may not use this file except in compliance with the License. 76429Svs195195 * 86429Svs195195 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96429Svs195195 * or http://www.opensolaris.org/os/licensing. 106429Svs195195 * See the License for the specific language governing permissions 116429Svs195195 * and limitations under the License. 126429Svs195195 * 136429Svs195195 * When distributing Covered Code, include this CDDL HEADER in each 146429Svs195195 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156429Svs195195 * If applicable, add the following below this CDDL HEADER, with the 166429Svs195195 * fields enclosed by brackets "[]" replaced with your own identifying 176429Svs195195 * information: Portions Copyright [yyyy] [name of copyright owner] 186429Svs195195 * 196429Svs195195 * CDDL HEADER END 206429Svs195195 */ 216429Svs195195 226429Svs195195 /* 23*6491Sia112686 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 246429Svs195195 * Use is subject to license terms. 256429Svs195195 */ 266429Svs195195 276429Svs195195 #ifndef _CHEETAH_SDC_H 286429Svs195195 #define _CHEETAH_SDC_H 296429Svs195195 306429Svs195195 #pragma ident "%Z%%M% %I% %E% SMI" 316429Svs195195 326429Svs195195 /* 336429Svs195195 * TARGET_REG: The register that is being tested 346429Svs195195 * TEMP_REG: The register that is used for the random 356429Svs195195 * instructions. This must be a odd register. 366429Svs195195 * The fault does not occur if even registers 376429Svs195195 * are used. 386429Svs195195 * CHECK_REG1: The register to which the contents of the 396429Svs195195 * TARGET_REG will be moved. 406429Svs195195 * CHECK_REG2: Same as CHECK_REG1. 416429Svs195195 */ 426429Svs195195 436429Svs195195 #ifdef __cplusplus 446429Svs195195 extern "C" { 456429Svs195195 #endif 466429Svs195195 476429Svs195195 /* Global Registers */ 486429Svs195195 496429Svs195195 #ifdef GLOBALS 506429Svs195195 #define TEMP_REG l1 516429Svs195195 #define CHECK_REG1 o0 526429Svs195195 #define CHECK_REG2 o1 536429Svs195195 #endif 546429Svs195195 556429Svs195195 #ifdef G1 566429Svs195195 #define TARGET_REG g1 576429Svs195195 #endif 586429Svs195195 596429Svs195195 #ifdef G2 606429Svs195195 #define TARGET_REG g2 616429Svs195195 .register %g2, #scratch 626429Svs195195 #endif 636429Svs195195 646429Svs195195 #ifdef G3 656429Svs195195 #define TARGET_REG g3 666429Svs195195 .register %g3, #scratch 676429Svs195195 #endif 686429Svs195195 696429Svs195195 #ifdef G4 706429Svs195195 #define TARGET_REG g4 716429Svs195195 #endif 726429Svs195195 736429Svs195195 746429Svs195195 /* Local Registers */ 756429Svs195195 766429Svs195195 #ifdef LOCALS 776429Svs195195 #define TEMP_REG o3 786429Svs195195 #define CHECK_REG1 o0 796429Svs195195 #define CHECK_REG2 o1 806429Svs195195 #endif 816429Svs195195 826429Svs195195 #ifdef L0 836429Svs195195 #define TARGET_REG l0 846429Svs195195 #endif 856429Svs195195 866429Svs195195 #ifdef L1 876429Svs195195 #define TARGET_REG l1 886429Svs195195 #endif 896429Svs195195 906429Svs195195 #ifdef L2 916429Svs195195 #define TARGET_REG l2 926429Svs195195 #endif 936429Svs195195 946429Svs195195 #ifdef L3 956429Svs195195 #define TARGET_REG l3 966429Svs195195 #endif 976429Svs195195 986429Svs195195 #ifdef L4 996429Svs195195 #define TARGET_REG l4 1006429Svs195195 #endif 1016429Svs195195 1026429Svs195195 #ifdef L5 1036429Svs195195 #define TARGET_REG l5 1046429Svs195195 #endif 1056429Svs195195 1066429Svs195195 #ifdef L6 1076429Svs195195 #define TARGET_REG l6 1086429Svs195195 #endif 1096429Svs195195 1106429Svs195195 #ifdef L7 1116429Svs195195 #define TARGET_REG l7 1126429Svs195195 #endif 1136429Svs195195 1146429Svs195195 1156429Svs195195 /* Out Registers */ 1166429Svs195195 1176429Svs195195 #ifdef OUTS 1186429Svs195195 #define TEMP_REG l3 1196429Svs195195 #define CHECK_REG1 l0 1206429Svs195195 #define CHECK_REG2 l1 1216429Svs195195 #endif 1226429Svs195195 1236429Svs195195 #ifdef O0 1246429Svs195195 #define TARGET_REG o0 1256429Svs195195 #endif 1266429Svs195195 1276429Svs195195 #ifdef O1 1286429Svs195195 #define TARGET_REG o1 1296429Svs195195 #endif 1306429Svs195195 1316429Svs195195 #ifdef O2 1326429Svs195195 #define TARGET_REG o2 1336429Svs195195 #endif 1346429Svs195195 1356429Svs195195 #ifdef O3 1366429Svs195195 #define TARGET_REG o3 1376429Svs195195 #endif 1386429Svs195195 1396429Svs195195 #ifdef O4 1406429Svs195195 #define TARGET_REG o4 1416429Svs195195 #endif 1426429Svs195195 1436429Svs195195 #ifdef O5 1446429Svs195195 #define TARGET_REG o5 1456429Svs195195 #endif 1466429Svs195195 1476429Svs195195 /* %o6 not tested as it is the %sp */ 1486429Svs195195 1496429Svs195195 #ifdef O7 1506429Svs195195 #define TARGET_REG o7 1516429Svs195195 #endif 1526429Svs195195 1536429Svs195195 #ifdef __cplusplus 1546429Svs195195 } 1556429Svs195195 #endif 1566429Svs195195 1576429Svs195195 #endif /* _CHEETAH_SDC_H */ 158