1 /* $NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.40 2013/07/16 09:54:30 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 155 */ 156 static const char * const i386_intel_brand[] = { 157 "", /* Unsupported */ 158 "Celeron", /* Intel (R) Celeron (TM) processor */ 159 "Pentium III", /* Intel (R) Pentium (R) III processor */ 160 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "", /* Reserved */ 163 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 164 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 165 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 166 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 167 "Celeron", /* Intel (R) Celeron (TM) processor */ 168 "Xeon", /* Intel (R) Xeon (TM) processor */ 169 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 170 "", /* Reserved */ 171 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 172 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 173 }; 174 175 /* 176 * AMD processors don't have Brand IDs, so we need these names for probe. 177 */ 178 static const char * const amd_brand[] = { 179 "", 180 "Duron", /* AMD Duron(tm) */ 181 "MP", /* AMD Athlon(tm) MP */ 182 "XP", /* AMD Athlon(tm) XP */ 183 "4" /* AMD Athlon(tm) 4 */ 184 }; 185 186 static int cpu_vendor; 187 static char cpu_brand_string[49]; 188 static char amd_brand_name[48]; 189 static int use_pae, largepagesize; 190 191 static void via_cpu_probe(struct cpu_info *); 192 static void amd_family6_probe(struct cpu_info *); 193 static void intel_family_new_probe(struct cpu_info *); 194 static const char *intel_family6_name(struct cpu_info *); 195 static const char *amd_amd64_name(struct cpu_info *); 196 static void amd_family5_setup(struct cpu_info *); 197 static void transmeta_cpu_info(struct cpu_info *); 198 static const char *print_cache_config(struct cpu_info *, int, const char *, 199 const char *); 200 static const char *print_tlb_config(struct cpu_info *, int, const char *, 201 const char *); 202 static void amd_cpu_cacheinfo(struct cpu_info *); 203 static void via_cpu_cacheinfo(struct cpu_info *); 204 static void x86_print_cacheinfo(struct cpu_info *); 205 static const struct x86_cache_info *cache_info_lookup( 206 const struct x86_cache_info *, uint8_t); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 static void amd_family5_setup(struct cpu_info *); 210 static void powernow_probe(struct cpu_info *); 211 212 /* 213 * Note: these are just the ones that may not have a cpuid instruction. 214 * We deal with the rest in a different way. 215 */ 216 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 217 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 218 NULL, NULL, NULL }, /* CPU_386SX */ 219 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 220 NULL, NULL, NULL }, /* CPU_386 */ 221 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 222 NULL, NULL, NULL }, /* CPU_486SX */ 223 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 224 NULL, NULL, NULL }, /* CPU_486 */ 225 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 226 NULL, NULL, NULL }, /* CPU_486DLC */ 227 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 228 NULL, NULL, NULL }, /* CPU_6x86 */ 229 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 230 NULL, NULL, NULL }, /* CPU_NX586 */ 231 }; 232 233 const char *classnames[] = { 234 "386", 235 "486", 236 "586", 237 "686" 238 }; 239 240 const char *modifiers[] = { 241 "", 242 "OverDrive", 243 "Dual", 244 "" 245 }; 246 247 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 248 { 249 "GenuineIntel", 250 CPUVENDOR_INTEL, 251 "Intel", 252 /* Family 4 */ 253 { { 254 CPUCLASS_486, 255 { 256 "486DX", "486DX", "486SX", "486DX2", "486SL", 257 "486SX2", 0, "486DX2 W/B Enhanced", 258 "486DX4", 0, 0, 0, 0, 0, 0, 0, 259 }, 260 "486", /* Default */ 261 NULL, 262 NULL, 263 NULL, 264 }, 265 /* Family 5 */ 266 { 267 CPUCLASS_586, 268 { 269 "Pentium (P5 A-step)", "Pentium (P5)", 270 "Pentium (P54C)", "Pentium (P24T)", 271 "Pentium/MMX", "Pentium", 0, 272 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 273 0, 0, 0, 0, 0, 0, 0, 274 }, 275 "Pentium", /* Default */ 276 NULL, 277 NULL, 278 NULL, 279 }, 280 /* Family 6 */ 281 { 282 CPUCLASS_686, 283 { 284 /* Updated from intel_x86_325486.pdf Aug 2012 */ 285 [0x00] = "Pentium Pro (A-step)", 286 [0x01] = "Pentium Pro", 287 [0x03] = "Pentium II (Klamath)", 288 [0x04] = "Pentium Pro", 289 [0x05] = "Pentium II/Celeron (Deschutes)", 290 [0x06] = "Celeron (Mendocino)", 291 [0x07] = "Pentium III (Katmai)", 292 [0x08] = "Pentium III (Coppermine)", 293 [0x09] = "Pentium M (Banias)", 294 [0x0a] = "Pentium III Xeon (Cascades)", 295 [0x0b] = "Pentium III (Tualatin)", 296 [0x0d] = "Pentium M (Dothan)", 297 [0x0e] = "Pentium Core Duo, Core solo", 298 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 299 "Core 2 Quad 6xxx, " 300 "Core 2 Extreme 6xxx, " 301 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 302 "and Pentium DC", 303 [0x15] = "EP80579 Integrated Processor", 304 [0x16] = "Celeron (45nm)", 305 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 306 "Core 2 Quad 8xxx and 9xxx", 307 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 308 "(Nehalem)", 309 [0x1c] = "Atom Family", 310 [0x1d] = "XeonMP 74xx (Nehalem)", 311 [0x1e] = "Core i7 and i5", 312 [0x1f] = "Core i7 and i5", 313 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 314 [0x26] = "Atom Family", 315 [0x27] = "Atom Family", 316 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 317 "i3 2xxx", 318 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 319 [0x2d] = "Xeon E5 Sandy bridy family", 320 [0x2e] = "Xeon 75xx & 65xx", 321 [0x2f] = "Xeon E7 family", 322 [0x35] = "Atom Family", 323 [0x36] = "Atom S", 324 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 325 "Ivy bridge", 326 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 327 "(Haswell)", 328 [0x3e] = "Next gen Xeon E5/E7, Ivy bridge", 329 [0x3f] = "Future gen Xeon", 330 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 331 "(Haswell)", 332 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 333 "(Haswell)", 334 }, 335 "Pentium Pro, II or III", /* Default */ 336 NULL, 337 intel_family_new_probe, 338 NULL, 339 }, 340 /* Family > 6 */ 341 { 342 CPUCLASS_686, 343 { 344 0, 0, 0, 0, 0, 0, 0, 0, 345 0, 0, 0, 0, 0, 0, 0, 0, 346 }, 347 "Pentium 4", /* Default */ 348 NULL, 349 intel_family_new_probe, 350 NULL, 351 } } 352 }, 353 { 354 "AuthenticAMD", 355 CPUVENDOR_AMD, 356 "AMD", 357 /* Family 4 */ 358 { { 359 CPUCLASS_486, 360 { 361 0, 0, 0, "Am486DX2 W/T", 362 0, 0, 0, "Am486DX2 W/B", 363 "Am486DX4 W/T or Am5x86 W/T 150", 364 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 365 0, 0, "Am5x86 W/T 133/160", 366 "Am5x86 W/B 133/160", 367 }, 368 "Am486 or Am5x86", /* Default */ 369 NULL, 370 NULL, 371 NULL, 372 }, 373 /* Family 5 */ 374 { 375 CPUCLASS_586, 376 { 377 "K5", "K5", "K5", "K5", 0, 0, "K6", 378 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 379 "K6-2+/III+", 0, 0, 380 }, 381 "K5 or K6", /* Default */ 382 amd_family5_setup, 383 NULL, 384 amd_cpu_cacheinfo, 385 }, 386 /* Family 6 */ 387 { 388 CPUCLASS_686, 389 { 390 0, "Athlon Model 1", "Athlon Model 2", 391 "Duron", "Athlon Model 4 (Thunderbird)", 392 0, "Athlon", "Duron", "Athlon", 0, 393 "Athlon", 0, 0, 0, 0, 0, 394 }, 395 "K7 (Athlon)", /* Default */ 396 NULL, 397 amd_family6_probe, 398 amd_cpu_cacheinfo, 399 }, 400 /* Family > 6 */ 401 { 402 CPUCLASS_686, 403 { 404 0, 0, 0, 0, 0, 0, 0, 0, 405 0, 0, 0, 0, 0, 0, 0, 0, 406 }, 407 "Unknown K8 (Athlon)", /* Default */ 408 NULL, 409 amd_family6_probe, 410 amd_cpu_cacheinfo, 411 } } 412 }, 413 { 414 "CyrixInstead", 415 CPUVENDOR_CYRIX, 416 "Cyrix", 417 /* Family 4 */ 418 { { 419 CPUCLASS_486, 420 { 421 0, 0, 0, 422 "MediaGX", 423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 424 }, 425 "486", /* Default */ 426 cyrix6x86_cpu_setup, /* XXX ?? */ 427 NULL, 428 NULL, 429 }, 430 /* Family 5 */ 431 { 432 CPUCLASS_586, 433 { 434 0, 0, "6x86", 0, 435 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 437 }, 438 "6x86", /* Default */ 439 cyrix6x86_cpu_setup, 440 NULL, 441 NULL, 442 }, 443 /* Family 6 */ 444 { 445 CPUCLASS_686, 446 { 447 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 448 0, 0, 0, 0, 0, 0, 0, 0, 449 }, 450 "6x86MX", /* Default */ 451 cyrix6x86_cpu_setup, 452 NULL, 453 NULL, 454 }, 455 /* Family > 6 */ 456 { 457 CPUCLASS_686, 458 { 459 0, 0, 0, 0, 0, 0, 0, 0, 460 0, 0, 0, 0, 0, 0, 0, 0, 461 }, 462 "Unknown 6x86MX", /* Default */ 463 NULL, 464 NULL, 465 NULL, 466 } } 467 }, 468 { /* MediaGX is now owned by National Semiconductor */ 469 "Geode by NSC", 470 CPUVENDOR_CYRIX, /* XXX */ 471 "National Semiconductor", 472 /* Family 4, NSC never had any of these */ 473 { { 474 CPUCLASS_486, 475 { 476 0, 0, 0, 0, 0, 0, 0, 0, 477 0, 0, 0, 0, 0, 0, 0, 0, 478 }, 479 "486 compatible", /* Default */ 480 NULL, 481 NULL, 482 NULL, 483 }, 484 /* Family 5: Geode family, formerly MediaGX */ 485 { 486 CPUCLASS_586, 487 { 488 0, 0, 0, 0, 489 "Geode GX1", 490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 491 }, 492 "Geode", /* Default */ 493 cyrix6x86_cpu_setup, 494 NULL, 495 amd_cpu_cacheinfo, 496 }, 497 /* Family 6, not yet available from NSC */ 498 { 499 CPUCLASS_686, 500 { 501 0, 0, 0, 0, 0, 0, 0, 0, 502 0, 0, 0, 0, 0, 0, 0, 0, 503 }, 504 "Pentium Pro compatible", /* Default */ 505 NULL, 506 NULL, 507 NULL, 508 }, 509 /* Family > 6, not yet available from NSC */ 510 { 511 CPUCLASS_686, 512 { 513 0, 0, 0, 0, 0, 0, 0, 0, 514 0, 0, 0, 0, 0, 0, 0, 0, 515 }, 516 "Pentium Pro compatible", /* Default */ 517 NULL, 518 NULL, 519 NULL, 520 } } 521 }, 522 { 523 "CentaurHauls", 524 CPUVENDOR_IDT, 525 "IDT", 526 /* Family 4, IDT never had any of these */ 527 { { 528 CPUCLASS_486, 529 { 530 0, 0, 0, 0, 0, 0, 0, 0, 531 0, 0, 0, 0, 0, 0, 0, 0, 532 }, 533 "486 compatible", /* Default */ 534 NULL, 535 NULL, 536 NULL, 537 }, 538 /* Family 5 */ 539 { 540 CPUCLASS_586, 541 { 542 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 543 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 544 }, 545 "WinChip", /* Default */ 546 winchip_cpu_setup, 547 NULL, 548 NULL, 549 }, 550 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 551 { 552 CPUCLASS_686, 553 { 554 0, 0, 0, 0, 0, 0, "C3 Samuel", 555 "C3 Samuel 2/Ezra", "C3 Ezra-T", 556 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 557 0, "VIA Nano", 558 }, 559 "Unknown VIA/IDT", /* Default */ 560 NULL, 561 via_cpu_probe, 562 via_cpu_cacheinfo, 563 }, 564 /* Family > 6, not yet available from VIA */ 565 { 566 CPUCLASS_686, 567 { 568 0, 0, 0, 0, 0, 0, 0, 0, 569 0, 0, 0, 0, 0, 0, 0, 0, 570 }, 571 "Pentium Pro compatible", /* Default */ 572 NULL, 573 NULL, 574 NULL, 575 } } 576 }, 577 { 578 "GenuineTMx86", 579 CPUVENDOR_TRANSMETA, 580 "Transmeta", 581 /* Family 4, Transmeta never had any of these */ 582 { { 583 CPUCLASS_486, 584 { 585 0, 0, 0, 0, 0, 0, 0, 0, 586 0, 0, 0, 0, 0, 0, 0, 0, 587 }, 588 "486 compatible", /* Default */ 589 NULL, 590 NULL, 591 NULL, 592 }, 593 /* Family 5 */ 594 { 595 CPUCLASS_586, 596 { 597 0, 0, 0, 0, 0, 0, 0, 0, 598 0, 0, 0, 0, 0, 0, 0, 0, 599 }, 600 "Crusoe", /* Default */ 601 NULL, 602 NULL, 603 transmeta_cpu_info, 604 }, 605 /* Family 6, not yet available from Transmeta */ 606 { 607 CPUCLASS_686, 608 { 609 0, 0, 0, 0, 0, 0, 0, 0, 610 0, 0, 0, 0, 0, 0, 0, 0, 611 }, 612 "Pentium Pro compatible", /* Default */ 613 NULL, 614 NULL, 615 NULL, 616 }, 617 /* Family > 6, not yet available from Transmeta */ 618 { 619 CPUCLASS_686, 620 { 621 0, 0, 0, 0, 0, 0, 0, 0, 622 0, 0, 0, 0, 0, 0, 0, 0, 623 }, 624 "Pentium Pro compatible", /* Default */ 625 NULL, 626 NULL, 627 NULL, 628 } } 629 } 630 }; 631 632 /* 633 * disable the TSC such that we don't use the TSC in microtime(9) 634 * because some CPUs got the implementation wrong. 635 */ 636 static void 637 disable_tsc(struct cpu_info *ci) 638 { 639 if (ci->ci_feat_val[0] & CPUID_TSC) { 640 ci->ci_feat_val[0] &= ~CPUID_TSC; 641 aprint_error("WARNING: broken TSC disabled\n"); 642 } 643 } 644 645 static void 646 cyrix6x86_cpu_setup(struct cpu_info *ci) 647 { 648 649 /* 650 * Do not disable the TSC on the Geode GX, it's reported to 651 * work fine. 652 */ 653 if (ci->ci_signature != 0x552) 654 disable_tsc(ci); 655 } 656 657 void 658 winchip_cpu_setup(struct cpu_info *ci) 659 { 660 switch (ci->ci_model) { 661 case 4: /* WinChip C6 */ 662 disable_tsc(ci); 663 } 664 } 665 666 667 static void 668 identifycpu_cpuids(struct cpu_info *ci) 669 { 670 const char *cpuname = ci->ci_dev; 671 u_int lp_max = 1; /* logical processors per package */ 672 u_int smt_max; /* smt per core */ 673 u_int core_max = 1; /* core per package */ 674 u_int smt_bits, core_bits; 675 uint32_t descs[4]; 676 uint32_t highest_basic_info; 677 678 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 679 ci->ci_packageid = ci->ci_initapicid; 680 ci->ci_coreid = 0; 681 ci->ci_smtid = 0; 682 if (cpu_vendor != CPUVENDOR_INTEL) { 683 return; 684 } 685 686 /* 687 * 253668.pdf 7.10.2 688 */ 689 690 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 691 x86_cpuid(1, descs); 692 lp_max = (descs[1] >> 16) & 0xff; 693 } 694 x86_cpuid(0, descs); 695 highest_basic_info = descs[0]; 696 if (highest_basic_info >= 4) { 697 x86_cpuid2(4, 0, descs); 698 core_max = (descs[0] >> 26) + 1; 699 } 700 assert(lp_max >= core_max); 701 smt_max = lp_max / core_max; 702 smt_bits = ilog2(smt_max - 1) + 1; 703 core_bits = ilog2(core_max - 1) + 1; 704 if (smt_bits + core_bits) { 705 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 706 } 707 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 708 ci->ci_packageid); 709 if (core_bits) { 710 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 711 712 ci->ci_coreid = 713 __SHIFTOUT(ci->ci_initapicid, core_mask); 714 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 715 } 716 if (smt_bits) { 717 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 718 719 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 720 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 721 } 722 } 723 724 static void 725 via_cpu_probe(struct cpu_info *ci) 726 { 727 u_int stepping = CPUID2STEPPING(ci->ci_signature); 728 u_int descs[4]; 729 u_int lfunc; 730 731 /* 732 * Determine the largest extended function value. 733 */ 734 x86_cpuid(0x80000000, descs); 735 lfunc = descs[0]; 736 737 /* 738 * Determine the extended feature flags. 739 */ 740 if (lfunc >= 0x80000001) { 741 x86_cpuid(0x80000001, descs); 742 ci->ci_feat_val[2] |= descs[3]; 743 } 744 745 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 746 return; 747 748 /* Nehemiah or Esther */ 749 x86_cpuid(0xc0000000, descs); 750 lfunc = descs[0]; 751 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 752 return; 753 754 x86_cpuid(0xc0000001, descs); 755 lfunc = descs[3]; 756 ci->ci_feat_val[4] = lfunc; 757 } 758 759 static const char * 760 intel_family6_name(struct cpu_info *ci) 761 { 762 const char *ret = NULL; 763 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 764 765 if (ci->ci_model == 5) { 766 switch (l2cache) { 767 case 0: 768 case 128 * 1024: 769 ret = "Celeron (Covington)"; 770 break; 771 case 256 * 1024: 772 ret = "Mobile Pentium II (Dixon)"; 773 break; 774 case 512 * 1024: 775 ret = "Pentium II"; 776 break; 777 case 1 * 1024 * 1024: 778 case 2 * 1024 * 1024: 779 ret = "Pentium II Xeon"; 780 break; 781 } 782 } else if (ci->ci_model == 6) { 783 switch (l2cache) { 784 case 256 * 1024: 785 case 512 * 1024: 786 ret = "Mobile Pentium II"; 787 break; 788 } 789 } else if (ci->ci_model == 7) { 790 switch (l2cache) { 791 case 512 * 1024: 792 ret = "Pentium III"; 793 break; 794 case 1 * 1024 * 1024: 795 case 2 * 1024 * 1024: 796 ret = "Pentium III Xeon"; 797 break; 798 } 799 } else if (ci->ci_model >= 8) { 800 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 801 switch (ci->ci_brand_id) { 802 case 0x3: 803 if (ci->ci_signature == 0x6B1) 804 ret = "Celeron"; 805 break; 806 case 0x8: 807 if (ci->ci_signature >= 0xF13) 808 ret = "genuine processor"; 809 break; 810 case 0xB: 811 if (ci->ci_signature >= 0xF13) 812 ret = "Xeon MP"; 813 break; 814 case 0xE: 815 if (ci->ci_signature < 0xF13) 816 ret = "Xeon"; 817 break; 818 } 819 if (ret == NULL) 820 ret = i386_intel_brand[ci->ci_brand_id]; 821 } 822 } 823 824 return ret; 825 } 826 827 /* 828 * Identify AMD64 CPU names from cpuid. 829 * 830 * Based on: 831 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 832 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 833 * "Revision Guide for AMD NPT Family 0Fh Processors" 834 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 835 * and other miscellaneous reports. 836 * 837 * This is all rather pointless, these are cross 'brand' since the raw 838 * silicon is shared. 839 */ 840 static const char * 841 amd_amd64_name(struct cpu_info *ci) 842 { 843 static char family_str[32]; 844 845 /* Only called if family >= 15 */ 846 847 switch (ci->ci_family) { 848 case 15: 849 switch (ci->ci_model) { 850 case 0x21: /* rev JH-E1/E6 */ 851 case 0x41: /* rev JH-F2 */ 852 return "Dual-Core Opteron"; 853 case 0x23: /* rev JH-E6 (Toledo) */ 854 return "Dual-Core Opteron or Athlon 64 X2"; 855 case 0x43: /* rev JH-F2 (Windsor) */ 856 return "Athlon 64 FX or Athlon 64 X2"; 857 case 0x24: /* rev SH-E5 (Lancaster?) */ 858 return "Mobile Athlon 64 or Turion 64"; 859 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 860 return "Opteron or Athlon 64 FX"; 861 case 0x15: /* rev SH-D0 */ 862 case 0x25: /* rev SH-E4 */ 863 return "Opteron"; 864 case 0x27: /* rev DH-E4, SH-E4 */ 865 return "Athlon 64 or Athlon 64 FX or Opteron"; 866 case 0x48: /* rev BH-F2 */ 867 return "Turion 64 X2"; 868 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 869 case 0x07: /* rev SH-CG (ClawHammer) */ 870 case 0x0b: /* rev CH-CG */ 871 case 0x14: /* rev SH-D0 */ 872 case 0x17: /* rev SH-D0 */ 873 case 0x1b: /* rev CH-D0 */ 874 return "Athlon 64"; 875 case 0x2b: /* rev BH-E4 (Manchester) */ 876 case 0x4b: /* rev BH-F2 (Windsor) */ 877 return "Athlon 64 X2"; 878 case 0x6b: /* rev BH-G1 (Brisbane) */ 879 return "Athlon X2 or Athlon 64 X2"; 880 case 0x08: /* rev CH-CG */ 881 case 0x0c: /* rev DH-CG (Newcastle) */ 882 case 0x0e: /* rev DH-CG (Newcastle?) */ 883 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 884 case 0x18: /* rev CH-D0 */ 885 case 0x1c: /* rev DH-D0 (Winchester) */ 886 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 887 case 0x2c: /* rev DH-E3/E6 */ 888 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 889 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 890 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 891 case 0x6f: /* rev DH-G1 */ 892 return "Athlon 64 or Sempron"; 893 default: 894 break; 895 } 896 return "Unknown AMD64 CPU"; 897 898 #if 0 899 case 16: 900 return "Family 10h"; 901 case 17: 902 return "Family 11h"; 903 case 18: 904 return "Family 12h"; 905 case 19: 906 return "Family 14h"; 907 case 20: 908 return "Family 15h"; 909 #endif 910 911 default: 912 break; 913 } 914 915 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 916 return family_str; 917 } 918 919 static void 920 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 921 { 922 const struct x86_cache_info *cai; 923 u_int descs[4]; 924 int iterations, i, j; 925 uint8_t desc; 926 uint32_t brand[12]; 927 928 memset(ci, 0, sizeof(*ci)); 929 ci->ci_dev = cpuname; 930 931 ci->ci_cpu_type = x86_identify(); 932 if (ci->ci_cpu_type >= 0) { 933 /* Old pre-cpuid instruction cpu */ 934 ci->ci_cpuid_level = -1; 935 return; 936 } 937 938 x86_cpuid(0, descs); 939 ci->ci_cpuid_level = descs[0]; 940 ci->ci_vendor[0] = descs[1]; 941 ci->ci_vendor[2] = descs[2]; 942 ci->ci_vendor[1] = descs[3]; 943 ci->ci_vendor[3] = 0; 944 945 x86_cpuid(0x80000000, brand); 946 if (brand[0] >= 0x80000004) { 947 x86_cpuid(0x80000002, brand); 948 x86_cpuid(0x80000003, brand + 4); 949 x86_cpuid(0x80000004, brand + 8); 950 for (i = 0; i < 48; i++) 951 if (((char *) brand)[i] != ' ') 952 break; 953 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 954 } 955 956 if (ci->ci_cpuid_level < 1) 957 return; 958 959 x86_cpuid(1, descs); 960 ci->ci_signature = descs[0]; 961 962 /* Extract full family/model values */ 963 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 964 ci->ci_model = CPUID2MODEL(ci->ci_signature); 965 if (ci->ci_family == 15) 966 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 967 if (ci->ci_family == 6 || ci->ci_family == 15) 968 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 969 970 /* Brand is low order 8 bits of ebx */ 971 ci->ci_brand_id = descs[1] & 0xff; 972 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 973 974 ci->ci_feat_val[1] = descs[2]; 975 ci->ci_feat_val[0] = descs[3]; 976 977 if (ci->ci_cpuid_level < 2) 978 return; 979 980 /* 981 * Parse the cache info from `cpuid', if we have it. 982 * XXX This is kinda ugly, but hey, so is the architecture... 983 */ 984 985 x86_cpuid(2, descs); 986 987 iterations = descs[0] & 0xff; 988 while (iterations-- > 0) { 989 for (i = 0; i < 4; i++) { 990 if (descs[i] & 0x80000000) 991 continue; 992 for (j = 0; j < 4; j++) { 993 if (i == 0 && j == 0) 994 continue; 995 desc = (descs[i] >> (j * 8)) & 0xff; 996 if (desc == 0) 997 continue; 998 cai = cache_info_lookup(intel_cpuid_cache_info, 999 desc); 1000 if (cai != NULL) 1001 ci->ci_cinfo[cai->cai_index] = *cai; 1002 } 1003 } 1004 x86_cpuid(2, descs); 1005 } 1006 1007 if (ci->ci_cpuid_level < 3) 1008 return; 1009 1010 /* 1011 * If the processor serial number misfeature is present and supported, 1012 * extract it here. 1013 */ 1014 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1015 ci->ci_cpu_serial[0] = ci->ci_signature; 1016 x86_cpuid(3, descs); 1017 ci->ci_cpu_serial[2] = descs[2]; 1018 ci->ci_cpu_serial[1] = descs[3]; 1019 } 1020 1021 if (ci->ci_cpuid_level < 0xd) 1022 return; 1023 1024 /* Get support XRC0 bits */ 1025 x86_cpuid2(0xd, 0, descs); 1026 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1027 ci->ci_cur_xsave = descs[1]; 1028 ci->ci_max_xsave = descs[2]; 1029 1030 /* Additional flags (eg xsaveopt support) */ 1031 x86_cpuid2(0xd, 1, descs); 1032 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1033 } 1034 1035 static void 1036 cpu_probe_features(struct cpu_info *ci) 1037 { 1038 const struct cpu_cpuid_nameclass *cpup = NULL; 1039 unsigned int i; 1040 1041 if (ci->ci_cpuid_level < 1) 1042 return; 1043 1044 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1045 if (!strncmp((char *)ci->ci_vendor, 1046 i386_cpuid_cpus[i].cpu_id, 12)) { 1047 cpup = &i386_cpuid_cpus[i]; 1048 break; 1049 } 1050 } 1051 1052 if (cpup == NULL) 1053 return; 1054 1055 i = ci->ci_family - CPU_MINFAMILY; 1056 1057 if (i >= __arraycount(cpup->cpu_family)) 1058 i = __arraycount(cpup->cpu_family) - 1; 1059 1060 if (cpup->cpu_family[i].cpu_probe == NULL) 1061 return; 1062 1063 (*cpup->cpu_family[i].cpu_probe)(ci); 1064 } 1065 1066 static void 1067 intel_family_new_probe(struct cpu_info *ci) 1068 { 1069 uint32_t descs[4]; 1070 1071 x86_cpuid(0x80000000, descs); 1072 1073 /* 1074 * Determine extended feature flags. 1075 */ 1076 if (descs[0] >= 0x80000001) { 1077 x86_cpuid(0x80000001, descs); 1078 ci->ci_feat_val[2] |= descs[3]; 1079 ci->ci_feat_val[3] |= descs[2]; 1080 } 1081 } 1082 1083 static void 1084 amd_family6_probe(struct cpu_info *ci) 1085 { 1086 uint32_t descs[4]; 1087 char *p; 1088 size_t i; 1089 1090 x86_cpuid(0x80000000, descs); 1091 1092 /* 1093 * Determine the extended feature flags. 1094 */ 1095 if (descs[0] >= 0x80000001) { 1096 x86_cpuid(0x80000001, descs); 1097 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1098 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1099 } 1100 1101 if (*cpu_brand_string == '\0') 1102 return; 1103 1104 for (i = 1; i < __arraycount(amd_brand); i++) 1105 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1106 ci->ci_brand_id = i; 1107 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1108 break; 1109 } 1110 } 1111 1112 static void 1113 amd_family5_setup(struct cpu_info *ci) 1114 { 1115 1116 switch (ci->ci_model) { 1117 case 0: /* AMD-K5 Model 0 */ 1118 /* 1119 * According to the AMD Processor Recognition App Note, 1120 * the AMD-K5 Model 0 uses the wrong bit to indicate 1121 * support for global PTEs, instead using bit 9 (APIC) 1122 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1123 */ 1124 if (ci->ci_feat_val[0] & CPUID_APIC) 1125 ci->ci_feat_val[0] = 1126 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1127 /* 1128 * XXX But pmap_pg_g is already initialized -- need to kick 1129 * XXX the pmap somehow. How does the MP branch do this? 1130 */ 1131 break; 1132 } 1133 } 1134 1135 static void 1136 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1137 { 1138 u_int descs[4]; 1139 1140 x86_cpuid(0x80860007, descs); 1141 *frequency = descs[0]; 1142 *voltage = descs[1]; 1143 *percentage = descs[2]; 1144 } 1145 1146 static void 1147 transmeta_cpu_info(struct cpu_info *ci) 1148 { 1149 u_int descs[4], nreg; 1150 u_int frequency, voltage, percentage; 1151 1152 x86_cpuid(0x80860000, descs); 1153 nreg = descs[0]; 1154 if (nreg >= 0x80860001) { 1155 x86_cpuid(0x80860001, descs); 1156 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1157 (descs[1] >> 24) & 0xff, 1158 (descs[1] >> 16) & 0xff, 1159 (descs[1] >> 8) & 0xff, 1160 descs[1] & 0xff); 1161 } 1162 if (nreg >= 0x80860002) { 1163 x86_cpuid(0x80860002, descs); 1164 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1165 (descs[1] >> 24) & 0xff, 1166 (descs[1] >> 16) & 0xff, 1167 (descs[1] >> 8) & 0xff, 1168 descs[1] & 0xff, 1169 descs[2]); 1170 } 1171 if (nreg >= 0x80860006) { 1172 union { 1173 char text[65]; 1174 u_int descs[4][4]; 1175 } info; 1176 int i; 1177 1178 for (i=0; i<4; i++) { 1179 x86_cpuid(0x80860003 + i, info.descs[i]); 1180 } 1181 info.text[64] = '\0'; 1182 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1183 } 1184 1185 if (nreg >= 0x80860007) { 1186 tmx86_get_longrun_status(&frequency, 1187 &voltage, &percentage); 1188 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1189 frequency, voltage, percentage); 1190 } 1191 } 1192 1193 static void 1194 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1195 { 1196 char buf[32 * 16]; 1197 char *bp; 1198 1199 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1200 1201 if (val == 0 || fmt == NULL) 1202 return; 1203 1204 snprintb_m(buf, sizeof(buf), fmt, val, 1205 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1206 bp = buf; 1207 while (*bp != '\0') { 1208 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1209 bp += strlen(bp) + 1; 1210 } 1211 } 1212 1213 void 1214 identifycpu(int fd, const char *cpuname) 1215 { 1216 const char *name = "", *modifier, *vendorname, *brand = ""; 1217 int class = CPUCLASS_386; 1218 unsigned int i; 1219 int modif, family; 1220 const struct cpu_cpuid_nameclass *cpup = NULL; 1221 const struct cpu_cpuid_family *cpufam; 1222 struct cpu_info *ci, cistore; 1223 size_t sz; 1224 struct cpu_ucode_version ucode; 1225 union { 1226 struct cpu_ucode_version_amd amd; 1227 struct cpu_ucode_version_intel1 intel1; 1228 } ucvers; 1229 1230 ci = &cistore; 1231 cpu_probe_base_features(ci, cpuname); 1232 cpu_probe_features(ci); 1233 1234 if (ci->ci_cpu_type >= 0) { 1235 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1236 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1237 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1238 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1239 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1240 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1241 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1242 modifier = ""; 1243 } else { 1244 modif = (ci->ci_signature >> 12) & 0x3; 1245 family = ci->ci_family; 1246 if (family < CPU_MINFAMILY) 1247 errx(1, "identifycpu: strange family value"); 1248 if (family > CPU_MAXFAMILY) 1249 family = CPU_MAXFAMILY; 1250 1251 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1252 if (!strncmp((char *)ci->ci_vendor, 1253 i386_cpuid_cpus[i].cpu_id, 12)) { 1254 cpup = &i386_cpuid_cpus[i]; 1255 break; 1256 } 1257 } 1258 1259 if (cpup == NULL) { 1260 cpu_vendor = CPUVENDOR_UNKNOWN; 1261 if (ci->ci_vendor[0] != '\0') 1262 vendorname = (char *)&ci->ci_vendor[0]; 1263 else 1264 vendorname = "Unknown"; 1265 class = family - 3; 1266 modifier = ""; 1267 name = ""; 1268 ci->ci_info = NULL; 1269 } else { 1270 cpu_vendor = cpup->cpu_vendor; 1271 vendorname = cpup->cpu_vendorname; 1272 modifier = modifiers[modif]; 1273 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1274 name = cpufam->cpu_models[ci->ci_model]; 1275 if (name == NULL || *name == '\0') 1276 name = cpufam->cpu_model_default; 1277 class = cpufam->cpu_class; 1278 ci->ci_info = cpufam->cpu_info; 1279 1280 if (cpu_vendor == CPUVENDOR_INTEL) { 1281 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1282 const char *tmp; 1283 tmp = intel_family6_name(ci); 1284 if (tmp != NULL) 1285 name = tmp; 1286 } 1287 if (ci->ci_family == 15 && 1288 ci->ci_brand_id < 1289 __arraycount(i386_intel_brand) && 1290 i386_intel_brand[ci->ci_brand_id]) 1291 name = 1292 i386_intel_brand[ci->ci_brand_id]; 1293 } 1294 1295 if (cpu_vendor == CPUVENDOR_AMD) { 1296 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1297 if (ci->ci_brand_id == 1) 1298 /* 1299 * It's Duron. We override the 1300 * name, since it might have 1301 * been misidentified as Athlon. 1302 */ 1303 name = 1304 amd_brand[ci->ci_brand_id]; 1305 else 1306 brand = amd_brand_name; 1307 } 1308 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1309 /* Identify AMD64 CPU names. */ 1310 const char *tmp; 1311 tmp = amd_amd64_name(ci); 1312 if (tmp != NULL) 1313 name = tmp; 1314 } 1315 } 1316 1317 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1318 vendorname = "VIA"; 1319 } 1320 } 1321 1322 ci->ci_cpu_class = class; 1323 1324 sz = sizeof(ci->ci_tsc_freq); 1325 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1326 sz = sizeof(use_pae); 1327 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1328 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1329 1330 /* 1331 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1332 * we try to determine from the family/model values. 1333 */ 1334 if (*cpu_brand_string != '\0') 1335 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1336 1337 aprint_normal("%s: %s", cpuname, vendorname); 1338 if (*modifier) 1339 aprint_normal(" %s", modifier); 1340 if (*name) 1341 aprint_normal(" %s", name); 1342 if (*brand) 1343 aprint_normal(" %s", brand); 1344 aprint_normal(" (%s-class)", classnames[class]); 1345 1346 if (ci->ci_tsc_freq != 0) 1347 aprint_normal(", %ju.%02ju MHz\n", 1348 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1349 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1350 1351 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1352 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1353 if (ci->ci_signature != 0) 1354 aprint_normal(" (id %#x)", ci->ci_signature); 1355 aprint_normal("\n"); 1356 1357 if (ci->ci_info) 1358 (*ci->ci_info)(ci); 1359 1360 /* 1361 * display CPU feature flags 1362 */ 1363 1364 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1365 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1366 1367 /* These next two are actually common definitions! */ 1368 print_bits(cpuname, "features2", 1369 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1370 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1371 print_bits(cpuname, "features3", 1372 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1373 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1374 1375 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1376 ci->ci_feat_val[4]); 1377 1378 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1379 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1380 ci->ci_feat_val[6]); 1381 1382 if (ci->ci_max_xsave != 0) { 1383 aprint_normal("%s: xsave area size: current %d, maximum %d", 1384 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1385 aprint_normal(", xgetbv %sabled\n", 1386 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1387 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1388 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1389 x86_xgetbv()); 1390 } 1391 1392 x86_print_cacheinfo(ci); 1393 1394 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1395 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1396 cpuname, 1397 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1398 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1399 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1400 } 1401 1402 if (ci->ci_cpu_class == CPUCLASS_386) { 1403 errx(1, "NetBSD requires an 80486 or later processor"); 1404 } 1405 1406 if (ci->ci_cpu_type == CPU_486DLC) { 1407 #ifndef CYRIX_CACHE_WORKS 1408 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1409 #else 1410 #ifndef CYRIX_CACHE_REALLY_WORKS 1411 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1412 #else 1413 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1414 #endif 1415 #endif 1416 } 1417 1418 /* 1419 * Everything past this point requires a Pentium or later. 1420 */ 1421 if (ci->ci_cpuid_level < 0) 1422 return; 1423 1424 identifycpu_cpuids(ci); 1425 1426 #ifdef INTEL_CORETEMP 1427 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1428 coretemp_register(ci); 1429 #endif 1430 1431 if (cpu_vendor == CPUVENDOR_AMD) { 1432 uint32_t data[4]; 1433 1434 x86_cpuid(0x80000000, data); 1435 if (data[0] >= 0x80000007) 1436 powernow_probe(ci); 1437 1438 if ((data[0] >= 0x8000000a) 1439 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1440 x86_cpuid(0x8000000a, data); 1441 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1442 data[0] & 0xf); 1443 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1444 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1445 data[3]); 1446 } 1447 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1448 uint32_t data[4]; 1449 uint32_t highest_basic_info; 1450 uint32_t bi_index; 1451 1452 x86_cpuid(0x00000000, data); 1453 highest_basic_info = data[0]; 1454 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1455 highest_basic_info); 1456 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1457 x86_cpuid(bi_index, data); 1458 switch (bi_index) { 1459 case 6: 1460 print_bits(cpuname, "DSPM-eax", 1461 CPUID_DSPM_FLAGS, data[0]); 1462 print_bits(cpuname, "DSPM-ecx", 1463 CPUID_DSPM_FLAGS1, data[2]); 1464 break; 1465 case 7: 1466 aprint_verbose("%s: SEF highest subleaf %08x\n", 1467 cpuname, data[0]); 1468 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1469 data[1]); 1470 break; 1471 #if 0 1472 default: 1473 aprint_verbose("%s: basic %08x-eax %08x\n", 1474 cpuname, bi_index, data[0]); 1475 aprint_verbose("%s: basic %08x-ebx %08x\n", 1476 cpuname, bi_index, data[1]); 1477 aprint_verbose("%s: basic %08x-ecx %08x\n", 1478 cpuname, bi_index, data[2]); 1479 aprint_verbose("%s: basic %08x-edx %08x\n", 1480 cpuname, bi_index, data[3]); 1481 break; 1482 #endif 1483 } 1484 } 1485 } 1486 1487 #ifdef INTEL_ONDEMAND_CLOCKMOD 1488 clockmod_init(); 1489 #endif 1490 1491 if (cpu_vendor == CPUVENDOR_AMD) 1492 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1493 else if (cpu_vendor == CPUVENDOR_INTEL) 1494 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1495 else 1496 return; 1497 1498 ucode.data = &ucvers; 1499 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1500 #ifdef __i386__ 1501 struct cpu_ucode_version_64 ucode_64; 1502 if (errno != ENOTTY) 1503 return; 1504 /* Try the 64 bit ioctl */ 1505 memset(&ucode_64, 0, sizeof ucode_64); 1506 ucode_64.data = &ucvers; 1507 ucode_64.loader_version = ucode.loader_version; 1508 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1509 return; 1510 #endif 1511 } 1512 1513 if (cpu_vendor == CPUVENDOR_AMD) 1514 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1515 else if (cpu_vendor == CPUVENDOR_INTEL) 1516 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1517 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1518 } 1519 1520 static const char * 1521 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1522 const char *sep) 1523 { 1524 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1525 char human_num[HUMAN_BUFSIZE]; 1526 1527 if (cai->cai_totalsize == 0) 1528 return sep; 1529 1530 if (sep == NULL) 1531 aprint_verbose_dev(ci->ci_dev, ""); 1532 else 1533 aprint_verbose("%s", sep); 1534 if (name != NULL) 1535 aprint_verbose("%s ", name); 1536 1537 if (cai->cai_string != NULL) { 1538 aprint_verbose("%s ", cai->cai_string); 1539 } else { 1540 (void)humanize_number(human_num, sizeof(human_num), 1541 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1542 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1543 } 1544 switch (cai->cai_associativity) { 1545 case 0: 1546 aprint_verbose("disabled"); 1547 break; 1548 case 1: 1549 aprint_verbose("direct-mapped"); 1550 break; 1551 case 0xff: 1552 aprint_verbose("fully associative"); 1553 break; 1554 default: 1555 aprint_verbose("%d-way", cai->cai_associativity); 1556 break; 1557 } 1558 return ", "; 1559 } 1560 1561 static const char * 1562 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1563 const char *sep) 1564 { 1565 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1566 char human_num[HUMAN_BUFSIZE]; 1567 1568 if (cai->cai_totalsize == 0) 1569 return sep; 1570 1571 if (sep == NULL) 1572 aprint_verbose_dev(ci->ci_dev, ""); 1573 else 1574 aprint_verbose("%s", sep); 1575 if (name != NULL) 1576 aprint_verbose("%s ", name); 1577 1578 if (cai->cai_string != NULL) { 1579 aprint_verbose("%s", cai->cai_string); 1580 } else { 1581 (void)humanize_number(human_num, sizeof(human_num), 1582 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1583 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1584 human_num); 1585 switch (cai->cai_associativity) { 1586 case 0: 1587 aprint_verbose("disabled"); 1588 break; 1589 case 1: 1590 aprint_verbose("direct-mapped"); 1591 break; 1592 case 0xff: 1593 aprint_verbose("fully associative"); 1594 break; 1595 default: 1596 aprint_verbose("%d-way", cai->cai_associativity); 1597 break; 1598 } 1599 } 1600 return ", "; 1601 } 1602 1603 static const struct x86_cache_info * 1604 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1605 { 1606 int i; 1607 1608 for (i = 0; cai[i].cai_desc != 0; i++) { 1609 if (cai[i].cai_desc == desc) 1610 return (&cai[i]); 1611 } 1612 1613 return (NULL); 1614 } 1615 1616 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1617 AMD_L2CACHE_INFO; 1618 1619 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1620 AMD_L3CACHE_INFO; 1621 1622 static void 1623 amd_cpu_cacheinfo(struct cpu_info *ci) 1624 { 1625 const struct x86_cache_info *cp; 1626 struct x86_cache_info *cai; 1627 u_int descs[4]; 1628 u_int lfunc; 1629 1630 /* 1631 * K5 model 0 has none of this info. 1632 */ 1633 if (ci->ci_family == 5 && ci->ci_model == 0) 1634 return; 1635 1636 /* 1637 * Determine the largest extended function value. 1638 */ 1639 x86_cpuid(0x80000000, descs); 1640 lfunc = descs[0]; 1641 1642 /* 1643 * Determine L1 cache/TLB info. 1644 */ 1645 if (lfunc < 0x80000005) { 1646 /* No L1 cache info available. */ 1647 return; 1648 } 1649 1650 x86_cpuid(0x80000005, descs); 1651 1652 /* 1653 * K6-III and higher have large page TLBs. 1654 */ 1655 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1656 cai = &ci->ci_cinfo[CAI_ITLB2]; 1657 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1658 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1659 cai->cai_linesize = largepagesize; 1660 1661 cai = &ci->ci_cinfo[CAI_DTLB2]; 1662 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1663 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1664 cai->cai_linesize = largepagesize; 1665 } 1666 1667 cai = &ci->ci_cinfo[CAI_ITLB]; 1668 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1669 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1670 cai->cai_linesize = (4 * 1024); 1671 1672 cai = &ci->ci_cinfo[CAI_DTLB]; 1673 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1674 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1675 cai->cai_linesize = (4 * 1024); 1676 1677 cai = &ci->ci_cinfo[CAI_DCACHE]; 1678 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1679 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1680 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1681 1682 cai = &ci->ci_cinfo[CAI_ICACHE]; 1683 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1684 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1685 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1686 1687 /* 1688 * Determine L2 cache/TLB info. 1689 */ 1690 if (lfunc < 0x80000006) { 1691 /* No L2 cache info available. */ 1692 return; 1693 } 1694 1695 x86_cpuid(0x80000006, descs); 1696 1697 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1698 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1699 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1700 cai->cai_linesize = (4 * 1024); 1701 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1702 cai->cai_associativity); 1703 if (cp != NULL) 1704 cai->cai_associativity = cp->cai_associativity; 1705 else 1706 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1707 1708 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1709 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1710 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1711 cai->cai_linesize = largepagesize; 1712 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1713 cai->cai_associativity); 1714 if (cp != NULL) 1715 cai->cai_associativity = cp->cai_associativity; 1716 else 1717 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1718 1719 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1720 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1721 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1722 cai->cai_linesize = (4 * 1024); 1723 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1724 cai->cai_associativity); 1725 if (cp != NULL) 1726 cai->cai_associativity = cp->cai_associativity; 1727 else 1728 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1729 1730 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1731 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1732 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1733 cai->cai_linesize = largepagesize; 1734 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1735 cai->cai_associativity); 1736 if (cp != NULL) 1737 cai->cai_associativity = cp->cai_associativity; 1738 else 1739 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1740 1741 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1742 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1743 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1744 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1745 1746 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1747 cai->cai_associativity); 1748 if (cp != NULL) 1749 cai->cai_associativity = cp->cai_associativity; 1750 else 1751 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1752 1753 /* 1754 * Determine L3 cache info on AMD Family 10h and newer processors 1755 */ 1756 if (ci->ci_family >= 0x10) { 1757 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1758 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1759 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1760 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1761 1762 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1763 cai->cai_associativity); 1764 if (cp != NULL) 1765 cai->cai_associativity = cp->cai_associativity; 1766 else 1767 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1768 } 1769 1770 /* 1771 * Determine 1GB TLB info. 1772 */ 1773 if (lfunc < 0x80000019) { 1774 /* No 1GB TLB info available. */ 1775 return; 1776 } 1777 1778 x86_cpuid(0x80000019, descs); 1779 1780 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1781 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1782 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1783 cai->cai_linesize = (1024 * 1024 * 1024); 1784 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1785 cai->cai_associativity); 1786 if (cp != NULL) 1787 cai->cai_associativity = cp->cai_associativity; 1788 else 1789 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1790 1791 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1792 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1793 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1794 cai->cai_linesize = (1024 * 1024 * 1024); 1795 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1796 cai->cai_associativity); 1797 if (cp != NULL) 1798 cai->cai_associativity = cp->cai_associativity; 1799 else 1800 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1801 1802 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1803 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1804 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1805 cai->cai_linesize = (1024 * 1024 * 1024); 1806 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1807 cai->cai_associativity); 1808 if (cp != NULL) 1809 cai->cai_associativity = cp->cai_associativity; 1810 else 1811 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1812 1813 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1814 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1815 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1816 cai->cai_linesize = (1024 * 1024 * 1024); 1817 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1818 cai->cai_associativity); 1819 if (cp != NULL) 1820 cai->cai_associativity = cp->cai_associativity; 1821 else 1822 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1823 } 1824 1825 static void 1826 via_cpu_cacheinfo(struct cpu_info *ci) 1827 { 1828 struct x86_cache_info *cai; 1829 int stepping; 1830 u_int descs[4]; 1831 u_int lfunc; 1832 1833 stepping = CPUID2STEPPING(ci->ci_signature); 1834 1835 /* 1836 * Determine the largest extended function value. 1837 */ 1838 x86_cpuid(0x80000000, descs); 1839 lfunc = descs[0]; 1840 1841 /* 1842 * Determine L1 cache/TLB info. 1843 */ 1844 if (lfunc < 0x80000005) { 1845 /* No L1 cache info available. */ 1846 return; 1847 } 1848 1849 x86_cpuid(0x80000005, descs); 1850 1851 cai = &ci->ci_cinfo[CAI_ITLB]; 1852 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1853 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1854 cai->cai_linesize = (4 * 1024); 1855 1856 cai = &ci->ci_cinfo[CAI_DTLB]; 1857 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1858 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1859 cai->cai_linesize = (4 * 1024); 1860 1861 cai = &ci->ci_cinfo[CAI_DCACHE]; 1862 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1863 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1864 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1865 if (ci->ci_model == 9 && stepping == 8) { 1866 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1867 cai->cai_associativity = 2; 1868 } 1869 1870 cai = &ci->ci_cinfo[CAI_ICACHE]; 1871 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1872 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1873 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1874 if (ci->ci_model == 9 && stepping == 8) { 1875 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1876 cai->cai_associativity = 2; 1877 } 1878 1879 /* 1880 * Determine L2 cache/TLB info. 1881 */ 1882 if (lfunc < 0x80000006) { 1883 /* No L2 cache info available. */ 1884 return; 1885 } 1886 1887 x86_cpuid(0x80000006, descs); 1888 1889 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1890 if (ci->ci_model >= 9) { 1891 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1892 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1893 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1894 } else { 1895 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1896 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1897 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1898 } 1899 } 1900 1901 static void 1902 x86_print_cacheinfo(struct cpu_info *ci) 1903 { 1904 const char *sep; 1905 1906 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1907 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1908 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1909 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1910 if (sep != NULL) 1911 aprint_verbose("\n"); 1912 } 1913 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1914 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1915 if (sep != NULL) 1916 aprint_verbose("\n"); 1917 } 1918 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1919 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1920 if (sep != NULL) 1921 aprint_verbose("\n"); 1922 } 1923 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1924 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1925 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1926 if (sep != NULL) 1927 aprint_verbose("\n"); 1928 } 1929 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1930 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1931 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1932 if (sep != NULL) 1933 aprint_verbose("\n"); 1934 } 1935 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1936 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1937 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1938 if (sep != NULL) 1939 aprint_verbose("\n"); 1940 } 1941 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1942 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1943 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1944 if (sep != NULL) 1945 aprint_verbose("\n"); 1946 } 1947 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1948 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 1949 if (sep != NULL) 1950 aprint_verbose("\n"); 1951 } 1952 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1953 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 1954 if (sep != NULL) 1955 aprint_verbose("\n"); 1956 } 1957 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1958 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 1959 if (sep != NULL) 1960 aprint_verbose("\n"); 1961 } 1962 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 1963 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 1964 if (sep != NULL) 1965 aprint_verbose("\n"); 1966 } 1967 } 1968 1969 static void 1970 powernow_probe(struct cpu_info *ci) 1971 { 1972 uint32_t regs[4]; 1973 char buf[256]; 1974 1975 x86_cpuid(0x80000007, regs); 1976 1977 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 1978 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1979 buf); 1980 } 1981 1982 int 1983 ucodeupdate_check(int fd, struct cpu_ucode *uc) 1984 { 1985 struct cpu_info ci; 1986 int loader_version, res; 1987 struct cpu_ucode_version versreq; 1988 1989 cpu_probe_base_features(&ci, "unknown"); 1990 1991 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 1992 loader_version = CPU_UCODE_LOADER_AMD; 1993 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 1994 loader_version = CPU_UCODE_LOADER_INTEL1; 1995 else 1996 return -1; 1997 1998 /* check whether the kernel understands this loader version */ 1999 versreq.loader_version = loader_version; 2000 versreq.data = 0; 2001 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2002 if (res) 2003 return -1; 2004 2005 switch (loader_version) { 2006 case CPU_UCODE_LOADER_AMD: 2007 if (uc->cpu_nr != -1) { 2008 /* printf? */ 2009 return -1; 2010 } 2011 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2012 break; 2013 case CPU_UCODE_LOADER_INTEL1: 2014 if (uc->cpu_nr == -1) 2015 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2016 else 2017 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2018 break; 2019 default: /* can't happen */ 2020 return -1; 2021 } 2022 uc->loader_version = loader_version; 2023 return 0; 2024 } 2025