1/* $NetBSD: i386-asm.S,v 1.3 2013/01/07 23:20:42 dsl Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2000, 2004, 2006, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <machine/asm.h> 30#include <machine/cputypes.h> 31#include <machine/psl.h> 32 33 .text 34 35ENTRY(x86_cpuid2) 36 pushl %ebx 37 pushl %edi 38 movl 12(%esp), %eax 39 movl 16(%esp), %ecx 40 movl 20(%esp), %edi 41 cpuid 42 movl %eax, 0(%edi) 43 movl %ebx, 4(%edi) 44 movl %ecx, 8(%edi) 45 movl %edx, 12(%edi) 46 popl %edi 47 popl %ebx 48 ret 49END(x86_cpuid2) 50 51ENTRY(x86_xgetbv) 52 xgetbv 53 ret 54END(x86_xgetbv) 55 56ENTRY(x86_identify) 57 /* Try to toggle alignment check flag; does not exist on 386. */ 58 pushfl 59 popl %eax 60 movl %eax,%ecx 61 orl $PSL_AC,%eax 62 pushl %eax 63 popfl 64 pushfl 65 popl %eax 66 xorl %ecx,%eax 67 andl $PSL_AC,%eax 68 pushl %ecx 69 popfl 70 testl %eax,%eax 71 jnz try486 72 73 /* 74 * Try the test of a NexGen CPU -- ZF will not change on a DIV 75 * instruction on a NexGen, it will on an i386. Documented in 76 * Nx586 Processor Recognition Application Note, NexGen, Inc. 77 */ 78 movl $0x5555,%eax 79 xorl %edx,%edx 80 movl $2,%ecx 81 divl %ecx 82 jnz is386 83 84isnx586: 85 /* 86 * Don't try cpuid, as Nx586s reportedly don't support the 87 * PSL_ID bit. 88 */ 89 movl $CPU_NX586,%eax 90 ret 91is386: 92 movl $CPU_386,%eax 93 ret 94 95try486: /* Try to toggle identification flag; does not exist on early 486s. */ 96 pushfl 97 popl %eax 98 movl %eax,%ecx 99 xorl $PSL_ID,%eax 100 pushl %eax 101 popfl 102 pushfl 103 popl %eax 104 xorl %ecx,%eax 105 andl $PSL_ID,%eax 106 pushl %ecx 107 popfl 108 109 testl %eax,%eax 110 jz is486 111 112 /* Later cpu, caller will use cpuid instruction */ 113 movl $-1,%eax 114 ret 115 116is486: 117 /* 118 * Check Cyrix CPU 119 * Cyrix CPUs do not change the undefined flags following 120 * execution of the divide instruction which divides 5 by 2. 121 * 122 * Note: CPUID is enabled on M2, so it passes another way. 123 */ 124 pushfl 125 movl $0x5555, %eax 126 xorl %edx, %edx 127 movl $2, %ecx 128 clc 129 divl %ecx 130 jnc trycyrix486 131 popfl 132 movl $CPU_486,%eax 133 ret 134 135trycyrix486: 136 popfl 137 /* 138 * Check for Cyrix 486 CPU by seeing if the flags change during a 139 * divide. This is documented in the Cx486SLC/e SMM Programmer's 140 * Guide. 141 */ 142 xorl %edx,%edx 143 cmpl %edx,%edx # set flags to known state 144 pushl %ebx 145 pushfl 146 popl %ecx # store flags in ecx 147 movl $-1,%eax 148 movl $4,%ebx 149 divl %ebx # do a long division 150 pushfl 151 popl %eax 152 popl %ebx 153 xorl %ecx,%eax # are the flags different? 154 testl $0x8d5,%eax # only check C|PF|AF|Z|N|V 155 je is486dlc # yes => must be Cyrix 6x86 CPU 156 movl $CPU_6x86,%eax 157 ret 158 159is486dlc: 160 movl $CPU_486DLC,%eax 161 ret 162