1/* $NetBSD: sdivsi3.S,v 1.4 2003/08/07 16:32:19 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)udivsi3.s 5.1 (Berkeley) 5/15/90 35 */ 36 37#include <machine/asm.h> 38#if defined(LIBC_SCCS) 39 RCSID("$NetBSD: sdivsi3.S,v 1.4 2003/08/07 16:32:19 agc Exp $") 40#endif 41 42/* r0 <= r4 / r5 */ 43ENTRY(__sdivsi3) 44 mov r4, r0 45 mov r5, r1 46 47 tst r1, r1 48 bt div_by_zero 49 50 mov #0, r2 51 div0s r2, r0 52 subc r3, r3 53 subc r2, r0 54 div0s r1, r3 55#define DIVSTEP rotcl r0; div1 r1, r3 56 /* repeat 32 times */ 57 DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; 58 DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; 59 DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; 60 DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; 61#undef DIVSTEP 62 rotcl r0 63 64 rts 65 addc r2, r0 /* delay slot */ 66 67div_by_zero: 68#if defined(_KERNEL) || defined(_STANDALONE) 69 rts 70 mov #0, r0 /* delay slot */ 71#else 72 mov.l r14, @-r15 73 sts.l pr, @-r15 74 mov r15, r14 75 76 mov.l L_raise, r1 77 jsr @r1 78 mov #8, r4 /* delay slot */ 79 mov #0, r0 80 81 lds.l @r15+, pr 82 rts 83 mov.l @r15+, r14 /* delay slot */ 84 85 .align 2 86L_raise: 87 .long _raise 88#endif 89