1 /* $NetBSD: kern_softint.c,v 1.71 2022/09/03 02:48:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008, 2019, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Generic software interrupt framework. 34 * 35 * Overview 36 * 37 * The soft interrupt framework provides a mechanism to schedule a 38 * low priority callback that runs with thread context. It allows 39 * for dynamic registration of software interrupts, and for fair 40 * queueing and prioritization of those interrupts. The callbacks 41 * can be scheduled to run from nearly any point in the kernel: by 42 * code running with thread context, by code running from a 43 * hardware interrupt handler, and at any interrupt priority 44 * level. 45 * 46 * Priority levels 47 * 48 * Since soft interrupt dispatch can be tied to the underlying 49 * architecture's interrupt dispatch code, it can be limited 50 * both by the capabilities of the hardware and the capabilities 51 * of the interrupt dispatch code itself. The number of priority 52 * levels is restricted to four. In order of priority (lowest to 53 * highest) the levels are: clock, bio, net, serial. 54 * 55 * The names are symbolic and in isolation do not have any direct 56 * connection with a particular kind of device activity: they are 57 * only meant as a guide. 58 * 59 * The four priority levels map directly to scheduler priority 60 * levels, and where the architecture implements 'fast' software 61 * interrupts, they also map onto interrupt priorities. The 62 * interrupt priorities are intended to be hidden from machine 63 * independent code, which should use thread-safe mechanisms to 64 * synchronize with software interrupts (for example: mutexes). 65 * 66 * Capabilities 67 * 68 * Software interrupts run with limited machine context. In 69 * particular, they do not posess any address space context. They 70 * should not try to operate on user space addresses, or to use 71 * virtual memory facilities other than those noted as interrupt 72 * safe. 73 * 74 * Unlike hardware interrupts, software interrupts do have thread 75 * context. They may block on synchronization objects, sleep, and 76 * resume execution at a later time. 77 * 78 * Since software interrupts are a limited resource and run with 79 * higher priority than most other LWPs in the system, all 80 * block-and-resume activity by a software interrupt must be kept 81 * short to allow further processing at that level to continue. By 82 * extension, code running with process context must take care to 83 * ensure that any lock that may be taken from a software interrupt 84 * can not be held for more than a short period of time. 85 * 86 * The kernel does not allow software interrupts to use facilities 87 * or perform actions that may block for a significant amount of 88 * time. This means that it's not valid for a software interrupt 89 * to sleep on condition variables or wait for resources to become 90 * available (for example, memory). 91 * 92 * Per-CPU operation 93 * 94 * If a soft interrupt is triggered on a CPU, it can only be 95 * dispatched on the same CPU. Each LWP dedicated to handling a 96 * soft interrupt is bound to its home CPU, so if the LWP blocks 97 * and needs to run again, it can only run there. Nearly all data 98 * structures used to manage software interrupts are per-CPU. 99 * 100 * The per-CPU requirement is intended to reduce "ping-pong" of 101 * cache lines between CPUs: lines occupied by data structures 102 * used to manage the soft interrupts, and lines occupied by data 103 * items being passed down to the soft interrupt. As a positive 104 * side effect, this also means that the soft interrupt dispatch 105 * code does not need to to use spinlocks to synchronize. 106 * 107 * Generic implementation 108 * 109 * A generic, low performance implementation is provided that 110 * works across all architectures, with no machine-dependent 111 * modifications needed. This implementation uses the scheduler, 112 * and so has a number of restrictions: 113 * 114 * 1) The software interrupts are not currently preemptive, so 115 * must wait for the currently executing LWP to yield the CPU. 116 * This can introduce latency. 117 * 118 * 2) An expensive context switch is required for a software 119 * interrupt to be handled. 120 * 121 * 'Fast' software interrupts 122 * 123 * If an architectures defines __HAVE_FAST_SOFTINTS, it implements 124 * the fast mechanism. Threads running either in the kernel or in 125 * userspace will be interrupted, but will not be preempted. When 126 * the soft interrupt completes execution, the interrupted LWP 127 * is resumed. Interrupt dispatch code must provide the minimum 128 * level of context necessary for the soft interrupt to block and 129 * be resumed at a later time. The machine-dependent dispatch 130 * path looks something like the following: 131 * 132 * softintr() 133 * { 134 * go to IPL_HIGH if necessary for switch; 135 * save any necessary registers in a format that can be 136 * restored by cpu_switchto if the softint blocks; 137 * arrange for cpu_switchto() to restore into the 138 * trampoline function; 139 * identify LWP to handle this interrupt; 140 * switch to the LWP's stack; 141 * switch register stacks, if necessary; 142 * assign new value of curlwp; 143 * call MI softint_dispatch, passing old curlwp and IPL 144 * to execute interrupt at; 145 * switch back to old stack; 146 * switch back to old register stack, if necessary; 147 * restore curlwp; 148 * return to interrupted LWP; 149 * } 150 * 151 * If the soft interrupt blocks, a trampoline function is returned 152 * to in the context of the interrupted LWP, as arranged for by 153 * softint(): 154 * 155 * softint_ret() 156 * { 157 * unlock soft interrupt LWP; 158 * resume interrupt processing, likely returning to 159 * interrupted LWP or dispatching another, different 160 * interrupt; 161 * } 162 * 163 * Once the soft interrupt has fired (and even if it has blocked), 164 * no further soft interrupts at that level will be triggered by 165 * MI code until the soft interrupt handler has ceased execution. 166 * If a soft interrupt handler blocks and is resumed, it resumes 167 * execution as a normal LWP (kthread) and gains VM context. Only 168 * when it has completed and is ready to fire again will it 169 * interrupt other threads. 170 */ 171 172 #include <sys/cdefs.h> 173 __KERNEL_RCSID(0, "$NetBSD: kern_softint.c,v 1.71 2022/09/03 02:48:00 thorpej Exp $"); 174 175 #include <sys/param.h> 176 #include <sys/proc.h> 177 #include <sys/intr.h> 178 #include <sys/ipi.h> 179 #include <sys/lock.h> 180 #include <sys/mutex.h> 181 #include <sys/kernel.h> 182 #include <sys/kthread.h> 183 #include <sys/evcnt.h> 184 #include <sys/cpu.h> 185 #include <sys/xcall.h> 186 #include <sys/psref.h> 187 188 #include <uvm/uvm_extern.h> 189 190 /* This could overlap with signal info in struct lwp. */ 191 typedef struct softint { 192 SIMPLEQ_HEAD(, softhand) si_q; 193 struct lwp *si_lwp; 194 struct cpu_info *si_cpu; 195 uintptr_t si_machdep; 196 struct evcnt si_evcnt; 197 struct evcnt si_evcnt_block; 198 volatile int si_active; 199 int si_ipl; 200 char si_name[8]; 201 char si_name_block[8+6]; 202 } softint_t; 203 204 typedef struct softhand { 205 SIMPLEQ_ENTRY(softhand) sh_q; 206 void (*sh_func)(void *); 207 void *sh_arg; 208 softint_t *sh_isr; 209 u_int sh_flags; 210 u_int sh_ipi_id; 211 } softhand_t; 212 213 typedef struct softcpu { 214 struct cpu_info *sc_cpu; 215 softint_t sc_int[SOFTINT_COUNT]; 216 softhand_t sc_hand[1]; 217 } softcpu_t; 218 219 static void softint_thread(void *); 220 221 u_int softint_bytes = 32768; 222 u_int softint_timing; 223 static u_int softint_max; 224 static kmutex_t softint_lock; 225 226 /* 227 * softint_init_isr: 228 * 229 * Initialize a single interrupt level for a single CPU. 230 */ 231 static void 232 softint_init_isr(softcpu_t *sc, const char *desc, pri_t pri, u_int level, 233 int ipl) 234 { 235 struct cpu_info *ci; 236 softint_t *si; 237 int error; 238 239 si = &sc->sc_int[level]; 240 ci = sc->sc_cpu; 241 si->si_cpu = ci; 242 243 SIMPLEQ_INIT(&si->si_q); 244 245 error = kthread_create(pri, KTHREAD_MPSAFE | KTHREAD_INTR | 246 KTHREAD_IDLE, ci, softint_thread, si, &si->si_lwp, 247 "soft%s/%u", desc, ci->ci_index); 248 if (error != 0) 249 panic("softint_init_isr: error %d", error); 250 251 snprintf(si->si_name, sizeof(si->si_name), "%s/%u", desc, 252 ci->ci_index); 253 evcnt_attach_dynamic(&si->si_evcnt, EVCNT_TYPE_MISC, NULL, 254 "softint", si->si_name); 255 snprintf(si->si_name_block, sizeof(si->si_name_block), "%s block/%u", 256 desc, ci->ci_index); 257 evcnt_attach_dynamic(&si->si_evcnt_block, EVCNT_TYPE_MISC, NULL, 258 "softint", si->si_name_block); 259 260 si->si_ipl = ipl; 261 si->si_lwp->l_private = si; 262 softint_init_md(si->si_lwp, level, &si->si_machdep); 263 } 264 265 /* 266 * softint_init: 267 * 268 * Initialize per-CPU data structures. Called from mi_cpu_attach(). 269 */ 270 void 271 softint_init(struct cpu_info *ci) 272 { 273 static struct cpu_info *first; 274 softcpu_t *sc, *scfirst; 275 softhand_t *sh, *shmax; 276 277 if (first == NULL) { 278 /* Boot CPU. */ 279 first = ci; 280 mutex_init(&softint_lock, MUTEX_DEFAULT, IPL_NONE); 281 softint_bytes = round_page(softint_bytes); 282 softint_max = (softint_bytes - sizeof(softcpu_t)) / 283 sizeof(softhand_t); 284 } 285 286 /* Use uvm_km(9) for persistent, page-aligned allocation. */ 287 sc = (softcpu_t *)uvm_km_alloc(kernel_map, softint_bytes, 0, 288 UVM_KMF_WIRED | UVM_KMF_ZERO); 289 if (sc == NULL) 290 panic("softint_init_cpu: cannot allocate memory"); 291 292 ci->ci_data.cpu_softcpu = sc; 293 ci->ci_data.cpu_softints = 0; 294 sc->sc_cpu = ci; 295 296 softint_init_isr(sc, "net", PRI_SOFTNET, SOFTINT_NET, 297 IPL_SOFTNET); 298 softint_init_isr(sc, "bio", PRI_SOFTBIO, SOFTINT_BIO, 299 IPL_SOFTBIO); 300 softint_init_isr(sc, "clk", PRI_SOFTCLOCK, SOFTINT_CLOCK, 301 IPL_SOFTCLOCK); 302 softint_init_isr(sc, "ser", PRI_SOFTSERIAL, SOFTINT_SERIAL, 303 IPL_SOFTSERIAL); 304 305 if (first != ci) { 306 mutex_enter(&softint_lock); 307 scfirst = first->ci_data.cpu_softcpu; 308 sh = sc->sc_hand; 309 memcpy(sh, scfirst->sc_hand, sizeof(*sh) * softint_max); 310 /* Update pointers for this CPU. */ 311 for (shmax = sh + softint_max; sh < shmax; sh++) { 312 if (sh->sh_func == NULL) 313 continue; 314 sh->sh_isr = 315 &sc->sc_int[sh->sh_flags & SOFTINT_LVLMASK]; 316 } 317 mutex_exit(&softint_lock); 318 } 319 } 320 321 /* 322 * softint_establish: 323 * 324 * Register a software interrupt handler. 325 */ 326 void * 327 softint_establish(u_int flags, void (*func)(void *), void *arg) 328 { 329 CPU_INFO_ITERATOR cii; 330 struct cpu_info *ci; 331 softcpu_t *sc; 332 softhand_t *sh; 333 u_int level, index; 334 u_int ipi_id = 0; 335 void *sih; 336 337 level = (flags & SOFTINT_LVLMASK); 338 KASSERT(level < SOFTINT_COUNT); 339 KASSERT((flags & SOFTINT_IMPMASK) == 0); 340 341 mutex_enter(&softint_lock); 342 343 /* Find a free slot. */ 344 sc = curcpu()->ci_data.cpu_softcpu; 345 for (index = 1; index < softint_max; index++) { 346 if (sc->sc_hand[index].sh_func == NULL) 347 break; 348 } 349 if (index == softint_max) { 350 mutex_exit(&softint_lock); 351 printf("WARNING: softint_establish: table full, " 352 "increase softint_bytes\n"); 353 return NULL; 354 } 355 sih = (void *)((uint8_t *)&sc->sc_hand[index] - (uint8_t *)sc); 356 357 if (flags & SOFTINT_RCPU) { 358 if ((ipi_id = ipi_register(softint_schedule, sih)) == 0) { 359 mutex_exit(&softint_lock); 360 return NULL; 361 } 362 } 363 364 /* Set up the handler on each CPU. */ 365 if (ncpu < 2) { 366 /* XXX hack for machines with no CPU_INFO_FOREACH() early on */ 367 sc = curcpu()->ci_data.cpu_softcpu; 368 sh = &sc->sc_hand[index]; 369 sh->sh_isr = &sc->sc_int[level]; 370 sh->sh_func = func; 371 sh->sh_arg = arg; 372 sh->sh_flags = flags; 373 sh->sh_ipi_id = ipi_id; 374 } else for (CPU_INFO_FOREACH(cii, ci)) { 375 sc = ci->ci_data.cpu_softcpu; 376 sh = &sc->sc_hand[index]; 377 sh->sh_isr = &sc->sc_int[level]; 378 sh->sh_func = func; 379 sh->sh_arg = arg; 380 sh->sh_flags = flags; 381 sh->sh_ipi_id = ipi_id; 382 } 383 mutex_exit(&softint_lock); 384 385 return sih; 386 } 387 388 /* 389 * softint_disestablish: 390 * 391 * Unregister a software interrupt handler. The soft interrupt could 392 * still be active at this point, but the caller commits not to try 393 * and trigger it again once this call is made. The caller must not 394 * hold any locks that could be taken from soft interrupt context, 395 * because we will wait for the softint to complete if it's still 396 * running. 397 */ 398 void 399 softint_disestablish(void *arg) 400 { 401 CPU_INFO_ITERATOR cii; 402 struct cpu_info *ci; 403 softcpu_t *sc; 404 softhand_t *sh; 405 uintptr_t offset; 406 407 offset = (uintptr_t)arg; 408 KASSERTMSG(offset != 0 && offset < softint_bytes, "%"PRIuPTR" %u", 409 offset, softint_bytes); 410 411 /* 412 * Unregister IPI handler if there is any. Note: there is no need 413 * to disable preemption here - ID is stable. 414 */ 415 sc = curcpu()->ci_data.cpu_softcpu; 416 sh = (softhand_t *)((uint8_t *)sc + offset); 417 if (sh->sh_ipi_id) { 418 ipi_unregister(sh->sh_ipi_id); 419 } 420 421 /* 422 * Run a dummy softint at the same level on all CPUs and wait for 423 * completion, to make sure this softint is no longer running 424 * anywhere. 425 */ 426 xc_barrier(XC_HIGHPRI_IPL(sh->sh_isr->si_ipl)); 427 428 /* Clear the handler on each CPU. */ 429 mutex_enter(&softint_lock); 430 for (CPU_INFO_FOREACH(cii, ci)) { 431 sc = ci->ci_data.cpu_softcpu; 432 sh = (softhand_t *)((uint8_t *)sc + offset); 433 KASSERT(sh->sh_func != NULL); 434 sh->sh_func = NULL; 435 } 436 mutex_exit(&softint_lock); 437 } 438 439 /* 440 * softint_schedule: 441 * 442 * Trigger a software interrupt. Must be called from a hardware 443 * interrupt handler, or with preemption disabled (since we are 444 * using the value of curcpu()). 445 */ 446 void 447 softint_schedule(void *arg) 448 { 449 softhand_t *sh; 450 softint_t *si; 451 uintptr_t offset; 452 int s; 453 454 /* 455 * If this assert fires, rather than disabling preemption explicitly 456 * to make it stop, consider that you are probably using a softint 457 * when you don't need to. 458 */ 459 KASSERT(kpreempt_disabled()); 460 461 /* Find the handler record for this CPU. */ 462 offset = (uintptr_t)arg; 463 KASSERTMSG(offset != 0 && offset < softint_bytes, "%"PRIuPTR" %u", 464 offset, softint_bytes); 465 sh = (softhand_t *)((uint8_t *)curcpu()->ci_data.cpu_softcpu + offset); 466 467 /* If it's already pending there's nothing to do. */ 468 if ((sh->sh_flags & SOFTINT_PENDING) != 0) { 469 return; 470 } 471 472 /* 473 * Enqueue the handler into the LWP's pending list. 474 * If the LWP is completely idle, then make it run. 475 */ 476 s = splhigh(); 477 if ((sh->sh_flags & SOFTINT_PENDING) == 0) { 478 si = sh->sh_isr; 479 sh->sh_flags |= SOFTINT_PENDING; 480 SIMPLEQ_INSERT_TAIL(&si->si_q, sh, sh_q); 481 if (si->si_active == 0) { 482 si->si_active = 1; 483 softint_trigger(si->si_machdep); 484 } 485 } 486 splx(s); 487 } 488 489 /* 490 * softint_schedule_cpu: 491 * 492 * Trigger a software interrupt on a target CPU. This invokes 493 * softint_schedule() for the local CPU or send an IPI to invoke 494 * this routine on the remote CPU. Preemption must be disabled. 495 */ 496 void 497 softint_schedule_cpu(void *arg, struct cpu_info *ci) 498 { 499 KASSERT(kpreempt_disabled()); 500 501 if (curcpu() != ci) { 502 const softcpu_t *sc = ci->ci_data.cpu_softcpu; 503 const uintptr_t offset = (uintptr_t)arg; 504 const softhand_t *sh; 505 506 sh = (const softhand_t *)((const uint8_t *)sc + offset); 507 KASSERT((sh->sh_flags & SOFTINT_RCPU) != 0); 508 ipi_trigger(sh->sh_ipi_id, ci); 509 return; 510 } 511 512 /* Just a local CPU. */ 513 softint_schedule(arg); 514 } 515 516 /* 517 * softint_execute: 518 * 519 * Invoke handlers for the specified soft interrupt. 520 * Must be entered at splhigh. Will drop the priority 521 * to the level specified, but returns back at splhigh. 522 */ 523 static inline void 524 softint_execute(lwp_t *l, int s) 525 { 526 softint_t *si = l->l_private; 527 softhand_t *sh; 528 529 KASSERT(si->si_lwp == curlwp); 530 KASSERT(si->si_cpu == curcpu()); 531 KASSERT(si->si_lwp->l_wchan == NULL); 532 KASSERT(si->si_active); 533 534 /* 535 * Note: due to priority inheritance we may have interrupted a 536 * higher priority LWP. Since the soft interrupt must be quick 537 * and is non-preemptable, we don't bother yielding. 538 */ 539 540 while (!SIMPLEQ_EMPTY(&si->si_q)) { 541 /* 542 * Pick the longest waiting handler to run. We block 543 * interrupts but do not lock in order to do this, as 544 * we are protecting against the local CPU only. 545 */ 546 sh = SIMPLEQ_FIRST(&si->si_q); 547 SIMPLEQ_REMOVE_HEAD(&si->si_q, sh_q); 548 KASSERT((sh->sh_flags & SOFTINT_PENDING) != 0); 549 sh->sh_flags ^= SOFTINT_PENDING; 550 splx(s); 551 552 /* Run the handler. */ 553 if (__predict_true((sh->sh_flags & SOFTINT_MPSAFE) != 0)) { 554 (*sh->sh_func)(sh->sh_arg); 555 } else { 556 KERNEL_LOCK(1, l); 557 (*sh->sh_func)(sh->sh_arg); 558 KERNEL_UNLOCK_ONE(l); 559 } 560 561 /* Diagnostic: check that spin-locks have not leaked. */ 562 KASSERTMSG(curcpu()->ci_mtx_count == 0, 563 "%s: ci_mtx_count (%d) != 0, sh_func %p\n", 564 __func__, curcpu()->ci_mtx_count, sh->sh_func); 565 /* Diagnostic: check that psrefs have not leaked. */ 566 KASSERTMSG(l->l_psrefs == 0, "%s: l_psrefs=%d, sh_func=%p\n", 567 __func__, l->l_psrefs, sh->sh_func); 568 /* Diagnostic: check that biglocks have not leaked. */ 569 KASSERTMSG(l->l_blcnt == 0, 570 "%s: sh_func=%p leaked %d biglocks", 571 __func__, sh->sh_func, curlwp->l_blcnt); 572 573 (void)splhigh(); 574 } 575 576 PSREF_DEBUG_BARRIER(); 577 578 CPU_COUNT(CPU_COUNT_NSOFT, 1); 579 580 KASSERT(si->si_cpu == curcpu()); 581 KASSERT(si->si_lwp->l_wchan == NULL); 582 KASSERT(si->si_active); 583 si->si_evcnt.ev_count++; 584 si->si_active = 0; 585 } 586 587 /* 588 * softint_block: 589 * 590 * Update statistics when the soft interrupt blocks. 591 */ 592 void 593 softint_block(lwp_t *l) 594 { 595 softint_t *si = l->l_private; 596 597 KASSERT((l->l_pflag & LP_INTR) != 0); 598 si->si_evcnt_block.ev_count++; 599 } 600 601 #ifndef __HAVE_FAST_SOFTINTS 602 603 #ifdef __HAVE_PREEMPTION 604 #error __HAVE_PREEMPTION requires __HAVE_FAST_SOFTINTS 605 #endif 606 607 /* 608 * softint_init_md: 609 * 610 * Slow path: perform machine-dependent initialization. 611 */ 612 void 613 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 614 { 615 struct proc *p; 616 softint_t *si; 617 618 *machdep = (1 << level); 619 si = l->l_private; 620 p = l->l_proc; 621 622 mutex_enter(p->p_lock); 623 lwp_lock(l); 624 /* Cheat and make the KASSERT in softint_thread() happy. */ 625 si->si_active = 1; 626 setrunnable(l); 627 /* LWP now unlocked */ 628 mutex_exit(p->p_lock); 629 } 630 631 /* 632 * softint_trigger: 633 * 634 * Slow path: cause a soft interrupt handler to begin executing. 635 * Called at IPL_HIGH. 636 */ 637 void 638 softint_trigger(uintptr_t machdep) 639 { 640 struct cpu_info *ci; 641 lwp_t *l; 642 643 ci = curcpu(); 644 ci->ci_data.cpu_softints |= machdep; 645 l = ci->ci_onproc; 646 647 /* 648 * Arrange for mi_switch() to be called. If called from interrupt 649 * mode, we don't know if curlwp is executing in kernel or user, so 650 * post an AST and have it take a trip through userret(). If not in 651 * interrupt mode, curlwp is running in kernel and will notice the 652 * resched soon enough; avoid the AST. 653 */ 654 if (l == ci->ci_data.cpu_idlelwp) { 655 atomic_or_uint(&ci->ci_want_resched, 656 RESCHED_IDLE | RESCHED_UPREEMPT); 657 } else { 658 atomic_or_uint(&ci->ci_want_resched, RESCHED_UPREEMPT); 659 if (cpu_intr_p()) { 660 cpu_signotify(l); 661 } 662 } 663 } 664 665 /* 666 * softint_thread: 667 * 668 * Slow path: MI software interrupt dispatch. 669 */ 670 void 671 softint_thread(void *cookie) 672 { 673 softint_t *si; 674 lwp_t *l; 675 int s; 676 677 l = curlwp; 678 si = l->l_private; 679 680 for (;;) { 681 /* Clear pending status and run it. */ 682 s = splhigh(); 683 l->l_cpu->ci_data.cpu_softints &= ~si->si_machdep; 684 softint_execute(l, s); 685 splx(s); 686 687 /* Interrupts allowed to run again before switching. */ 688 lwp_lock(l); 689 l->l_stat = LSIDL; 690 spc_lock(l->l_cpu); 691 mi_switch(l); 692 } 693 } 694 695 /* 696 * softint_picklwp: 697 * 698 * Slow path: called from mi_switch() to pick the highest priority 699 * soft interrupt LWP that needs to run. 700 */ 701 lwp_t * 702 softint_picklwp(void) 703 { 704 struct cpu_info *ci; 705 u_int mask; 706 softint_t *si; 707 lwp_t *l; 708 709 ci = curcpu(); 710 si = ((softcpu_t *)ci->ci_data.cpu_softcpu)->sc_int; 711 mask = ci->ci_data.cpu_softints; 712 713 if ((mask & (1 << SOFTINT_SERIAL)) != 0) { 714 l = si[SOFTINT_SERIAL].si_lwp; 715 } else if ((mask & (1 << SOFTINT_NET)) != 0) { 716 l = si[SOFTINT_NET].si_lwp; 717 } else if ((mask & (1 << SOFTINT_BIO)) != 0) { 718 l = si[SOFTINT_BIO].si_lwp; 719 } else if ((mask & (1 << SOFTINT_CLOCK)) != 0) { 720 l = si[SOFTINT_CLOCK].si_lwp; 721 } else { 722 panic("softint_picklwp"); 723 } 724 725 return l; 726 } 727 728 #else /* !__HAVE_FAST_SOFTINTS */ 729 730 /* 731 * softint_thread: 732 * 733 * Fast path: the LWP is switched to without restoring any state, 734 * so we should not arrive here - there is a direct handoff between 735 * the interrupt stub and softint_dispatch(). 736 */ 737 void 738 softint_thread(void *cookie) 739 { 740 741 panic("softint_thread"); 742 } 743 744 /* 745 * softint_dispatch: 746 * 747 * Fast path: entry point from machine-dependent code. 748 */ 749 void 750 softint_dispatch(lwp_t *pinned, int s) 751 { 752 struct bintime now; 753 u_int timing; 754 lwp_t *l; 755 756 #ifdef DIAGNOSTIC 757 if ((pinned->l_pflag & LP_RUNNING) == 0 || curlwp->l_stat != LSIDL) { 758 struct lwp *onproc = curcpu()->ci_onproc; 759 int s2 = splhigh(); 760 printf("curcpu=%d, spl=%d curspl=%d\n" 761 "onproc=%p => l_stat=%d l_flag=%08x l_cpu=%d\n" 762 "curlwp=%p => l_stat=%d l_flag=%08x l_cpu=%d\n" 763 "pinned=%p => l_stat=%d l_flag=%08x l_cpu=%d\n", 764 cpu_index(curcpu()), s, s2, onproc, onproc->l_stat, 765 onproc->l_flag, cpu_index(onproc->l_cpu), curlwp, 766 curlwp->l_stat, curlwp->l_flag, 767 cpu_index(curlwp->l_cpu), pinned, pinned->l_stat, 768 pinned->l_flag, cpu_index(pinned->l_cpu)); 769 splx(s2); 770 panic("softint screwup"); 771 } 772 #endif 773 774 /* 775 * Note the interrupted LWP, and mark the current LWP as running 776 * before proceeding. Although this must as a rule be done with 777 * the LWP locked, at this point no external agents will want to 778 * modify the interrupt LWP's state. 779 */ 780 timing = softint_timing; 781 l = curlwp; 782 l->l_switchto = pinned; 783 l->l_stat = LSONPROC; 784 785 /* 786 * Dispatch the interrupt. If softints are being timed, charge 787 * for it. 788 */ 789 if (timing) { 790 binuptime(&l->l_stime); 791 membar_producer(); /* for calcru */ 792 l->l_pflag |= LP_TIMEINTR; 793 } 794 l->l_pflag |= LP_RUNNING; 795 softint_execute(l, s); 796 if (timing) { 797 binuptime(&now); 798 updatertime(l, &now); 799 l->l_pflag &= ~LP_TIMEINTR; 800 } 801 802 /* 803 * If we blocked while handling the interrupt, the pinned LWP is 804 * gone and we are now running as a kthread, so find another LWP to 805 * run. softint_dispatch() won't be reentered until the priority is 806 * finally dropped to IPL_NONE on entry to the next LWP on this CPU. 807 */ 808 l->l_stat = LSIDL; 809 if (l->l_switchto == NULL) { 810 lwp_lock(l); 811 spc_lock(l->l_cpu); 812 mi_switch(l); 813 /* NOTREACHED */ 814 } 815 l->l_switchto = NULL; 816 l->l_pflag &= ~LP_RUNNING; 817 } 818 819 #endif /* !__HAVE_FAST_SOFTINTS */ 820