1 /* $NetBSD: kern_softint.c,v 1.67 2021/12/05 04:56:40 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008, 2019, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Generic software interrupt framework. 34 * 35 * Overview 36 * 37 * The soft interrupt framework provides a mechanism to schedule a 38 * low priority callback that runs with thread context. It allows 39 * for dynamic registration of software interrupts, and for fair 40 * queueing and prioritization of those interrupts. The callbacks 41 * can be scheduled to run from nearly any point in the kernel: by 42 * code running with thread context, by code running from a 43 * hardware interrupt handler, and at any interrupt priority 44 * level. 45 * 46 * Priority levels 47 * 48 * Since soft interrupt dispatch can be tied to the underlying 49 * architecture's interrupt dispatch code, it can be limited 50 * both by the capabilities of the hardware and the capabilities 51 * of the interrupt dispatch code itself. The number of priority 52 * levels is restricted to four. In order of priority (lowest to 53 * highest) the levels are: clock, bio, net, serial. 54 * 55 * The names are symbolic and in isolation do not have any direct 56 * connection with a particular kind of device activity: they are 57 * only meant as a guide. 58 * 59 * The four priority levels map directly to scheduler priority 60 * levels, and where the architecture implements 'fast' software 61 * interrupts, they also map onto interrupt priorities. The 62 * interrupt priorities are intended to be hidden from machine 63 * independent code, which should use thread-safe mechanisms to 64 * synchronize with software interrupts (for example: mutexes). 65 * 66 * Capabilities 67 * 68 * Software interrupts run with limited machine context. In 69 * particular, they do not posess any address space context. They 70 * should not try to operate on user space addresses, or to use 71 * virtual memory facilities other than those noted as interrupt 72 * safe. 73 * 74 * Unlike hardware interrupts, software interrupts do have thread 75 * context. They may block on synchronization objects, sleep, and 76 * resume execution at a later time. 77 * 78 * Since software interrupts are a limited resource and run with 79 * higher priority than most other LWPs in the system, all 80 * block-and-resume activity by a software interrupt must be kept 81 * short to allow further processing at that level to continue. By 82 * extension, code running with process context must take care to 83 * ensure that any lock that may be taken from a software interrupt 84 * can not be held for more than a short period of time. 85 * 86 * The kernel does not allow software interrupts to use facilities 87 * or perform actions that may block for a significant amount of 88 * time. This means that it's not valid for a software interrupt 89 * to sleep on condition variables or wait for resources to become 90 * available (for example, memory). 91 * 92 * Per-CPU operation 93 * 94 * If a soft interrupt is triggered on a CPU, it can only be 95 * dispatched on the same CPU. Each LWP dedicated to handling a 96 * soft interrupt is bound to its home CPU, so if the LWP blocks 97 * and needs to run again, it can only run there. Nearly all data 98 * structures used to manage software interrupts are per-CPU. 99 * 100 * The per-CPU requirement is intended to reduce "ping-pong" of 101 * cache lines between CPUs: lines occupied by data structures 102 * used to manage the soft interrupts, and lines occupied by data 103 * items being passed down to the soft interrupt. As a positive 104 * side effect, this also means that the soft interrupt dispatch 105 * code does not need to to use spinlocks to synchronize. 106 * 107 * Generic implementation 108 * 109 * A generic, low performance implementation is provided that 110 * works across all architectures, with no machine-dependent 111 * modifications needed. This implementation uses the scheduler, 112 * and so has a number of restrictions: 113 * 114 * 1) The software interrupts are not currently preemptive, so 115 * must wait for the currently executing LWP to yield the CPU. 116 * This can introduce latency. 117 * 118 * 2) An expensive context switch is required for a software 119 * interrupt to be handled. 120 * 121 * 'Fast' software interrupts 122 * 123 * If an architectures defines __HAVE_FAST_SOFTINTS, it implements 124 * the fast mechanism. Threads running either in the kernel or in 125 * userspace will be interrupted, but will not be preempted. When 126 * the soft interrupt completes execution, the interrupted LWP 127 * is resumed. Interrupt dispatch code must provide the minimum 128 * level of context necessary for the soft interrupt to block and 129 * be resumed at a later time. The machine-dependent dispatch 130 * path looks something like the following: 131 * 132 * softintr() 133 * { 134 * go to IPL_HIGH if necessary for switch; 135 * save any necessary registers in a format that can be 136 * restored by cpu_switchto if the softint blocks; 137 * arrange for cpu_switchto() to restore into the 138 * trampoline function; 139 * identify LWP to handle this interrupt; 140 * switch to the LWP's stack; 141 * switch register stacks, if necessary; 142 * assign new value of curlwp; 143 * call MI softint_dispatch, passing old curlwp and IPL 144 * to execute interrupt at; 145 * switch back to old stack; 146 * switch back to old register stack, if necessary; 147 * restore curlwp; 148 * return to interrupted LWP; 149 * } 150 * 151 * If the soft interrupt blocks, a trampoline function is returned 152 * to in the context of the interrupted LWP, as arranged for by 153 * softint(): 154 * 155 * softint_ret() 156 * { 157 * unlock soft interrupt LWP; 158 * resume interrupt processing, likely returning to 159 * interrupted LWP or dispatching another, different 160 * interrupt; 161 * } 162 * 163 * Once the soft interrupt has fired (and even if it has blocked), 164 * no further soft interrupts at that level will be triggered by 165 * MI code until the soft interrupt handler has ceased execution. 166 * If a soft interrupt handler blocks and is resumed, it resumes 167 * execution as a normal LWP (kthread) and gains VM context. Only 168 * when it has completed and is ready to fire again will it 169 * interrupt other threads. 170 */ 171 172 #include <sys/cdefs.h> 173 __KERNEL_RCSID(0, "$NetBSD: kern_softint.c,v 1.67 2021/12/05 04:56:40 msaitoh Exp $"); 174 175 #include <sys/param.h> 176 #include <sys/proc.h> 177 #include <sys/intr.h> 178 #include <sys/ipi.h> 179 #include <sys/lock.h> 180 #include <sys/mutex.h> 181 #include <sys/kernel.h> 182 #include <sys/kthread.h> 183 #include <sys/evcnt.h> 184 #include <sys/cpu.h> 185 #include <sys/xcall.h> 186 187 #include <net/netisr.h> 188 189 #include <uvm/uvm_extern.h> 190 191 /* This could overlap with signal info in struct lwp. */ 192 typedef struct softint { 193 SIMPLEQ_HEAD(, softhand) si_q; 194 struct lwp *si_lwp; 195 struct cpu_info *si_cpu; 196 uintptr_t si_machdep; 197 struct evcnt si_evcnt; 198 struct evcnt si_evcnt_block; 199 volatile int si_active; 200 int si_ipl; 201 char si_name[8]; 202 char si_name_block[8+6]; 203 } softint_t; 204 205 typedef struct softhand { 206 SIMPLEQ_ENTRY(softhand) sh_q; 207 void (*sh_func)(void *); 208 void *sh_arg; 209 softint_t *sh_isr; 210 u_int sh_flags; 211 u_int sh_ipi_id; 212 } softhand_t; 213 214 typedef struct softcpu { 215 struct cpu_info *sc_cpu; 216 softint_t sc_int[SOFTINT_COUNT]; 217 softhand_t sc_hand[1]; 218 } softcpu_t; 219 220 static void softint_thread(void *); 221 222 u_int softint_bytes = 32768; 223 u_int softint_timing; 224 static u_int softint_max; 225 static kmutex_t softint_lock; 226 static void *softint_netisrs[NETISR_MAX]; 227 228 /* 229 * softint_init_isr: 230 * 231 * Initialize a single interrupt level for a single CPU. 232 */ 233 static void 234 softint_init_isr(softcpu_t *sc, const char *desc, pri_t pri, u_int level, 235 int ipl) 236 { 237 struct cpu_info *ci; 238 softint_t *si; 239 int error; 240 241 si = &sc->sc_int[level]; 242 ci = sc->sc_cpu; 243 si->si_cpu = ci; 244 245 SIMPLEQ_INIT(&si->si_q); 246 247 error = kthread_create(pri, KTHREAD_MPSAFE | KTHREAD_INTR | 248 KTHREAD_IDLE, ci, softint_thread, si, &si->si_lwp, 249 "soft%s/%u", desc, ci->ci_index); 250 if (error != 0) 251 panic("softint_init_isr: error %d", error); 252 253 snprintf(si->si_name, sizeof(si->si_name), "%s/%u", desc, 254 ci->ci_index); 255 evcnt_attach_dynamic(&si->si_evcnt, EVCNT_TYPE_MISC, NULL, 256 "softint", si->si_name); 257 snprintf(si->si_name_block, sizeof(si->si_name_block), "%s block/%u", 258 desc, ci->ci_index); 259 evcnt_attach_dynamic(&si->si_evcnt_block, EVCNT_TYPE_MISC, NULL, 260 "softint", si->si_name_block); 261 262 si->si_ipl = ipl; 263 si->si_lwp->l_private = si; 264 softint_init_md(si->si_lwp, level, &si->si_machdep); 265 } 266 267 /* 268 * softint_init: 269 * 270 * Initialize per-CPU data structures. Called from mi_cpu_attach(). 271 */ 272 void 273 softint_init(struct cpu_info *ci) 274 { 275 static struct cpu_info *first; 276 softcpu_t *sc, *scfirst; 277 softhand_t *sh, *shmax; 278 279 if (first == NULL) { 280 /* Boot CPU. */ 281 first = ci; 282 mutex_init(&softint_lock, MUTEX_DEFAULT, IPL_NONE); 283 softint_bytes = round_page(softint_bytes); 284 softint_max = (softint_bytes - sizeof(softcpu_t)) / 285 sizeof(softhand_t); 286 } 287 288 /* Use uvm_km(9) for persistent, page-aligned allocation. */ 289 sc = (softcpu_t *)uvm_km_alloc(kernel_map, softint_bytes, 0, 290 UVM_KMF_WIRED | UVM_KMF_ZERO); 291 if (sc == NULL) 292 panic("softint_init_cpu: cannot allocate memory"); 293 294 ci->ci_data.cpu_softcpu = sc; 295 ci->ci_data.cpu_softints = 0; 296 sc->sc_cpu = ci; 297 298 softint_init_isr(sc, "net", PRI_SOFTNET, SOFTINT_NET, 299 IPL_SOFTNET); 300 softint_init_isr(sc, "bio", PRI_SOFTBIO, SOFTINT_BIO, 301 IPL_SOFTBIO); 302 softint_init_isr(sc, "clk", PRI_SOFTCLOCK, SOFTINT_CLOCK, 303 IPL_SOFTCLOCK); 304 softint_init_isr(sc, "ser", PRI_SOFTSERIAL, SOFTINT_SERIAL, 305 IPL_SOFTSERIAL); 306 307 if (first != ci) { 308 mutex_enter(&softint_lock); 309 scfirst = first->ci_data.cpu_softcpu; 310 sh = sc->sc_hand; 311 memcpy(sh, scfirst->sc_hand, sizeof(*sh) * softint_max); 312 /* Update pointers for this CPU. */ 313 for (shmax = sh + softint_max; sh < shmax; sh++) { 314 if (sh->sh_func == NULL) 315 continue; 316 sh->sh_isr = 317 &sc->sc_int[sh->sh_flags & SOFTINT_LVLMASK]; 318 } 319 mutex_exit(&softint_lock); 320 } else { 321 /* 322 * Establish handlers for legacy net interrupts. 323 * XXX Needs to go away. 324 */ 325 #define DONETISR(n, f) \ 326 softint_netisrs[(n)] = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE,\ 327 (void (*)(void *))(f), NULL) 328 #include <net/netisr_dispatch.h> 329 } 330 } 331 332 /* 333 * softint_establish: 334 * 335 * Register a software interrupt handler. 336 */ 337 void * 338 softint_establish(u_int flags, void (*func)(void *), void *arg) 339 { 340 CPU_INFO_ITERATOR cii; 341 struct cpu_info *ci; 342 softcpu_t *sc; 343 softhand_t *sh; 344 u_int level, index; 345 u_int ipi_id = 0; 346 void *sih; 347 348 level = (flags & SOFTINT_LVLMASK); 349 KASSERT(level < SOFTINT_COUNT); 350 KASSERT((flags & SOFTINT_IMPMASK) == 0); 351 352 mutex_enter(&softint_lock); 353 354 /* Find a free slot. */ 355 sc = curcpu()->ci_data.cpu_softcpu; 356 for (index = 1; index < softint_max; index++) { 357 if (sc->sc_hand[index].sh_func == NULL) 358 break; 359 } 360 if (index == softint_max) { 361 mutex_exit(&softint_lock); 362 printf("WARNING: softint_establish: table full, " 363 "increase softint_bytes\n"); 364 return NULL; 365 } 366 sih = (void *)((uint8_t *)&sc->sc_hand[index] - (uint8_t *)sc); 367 368 if (flags & SOFTINT_RCPU) { 369 if ((ipi_id = ipi_register(softint_schedule, sih)) == 0) { 370 mutex_exit(&softint_lock); 371 return NULL; 372 } 373 } 374 375 /* Set up the handler on each CPU. */ 376 if (ncpu < 2) { 377 /* XXX hack for machines with no CPU_INFO_FOREACH() early on */ 378 sc = curcpu()->ci_data.cpu_softcpu; 379 sh = &sc->sc_hand[index]; 380 sh->sh_isr = &sc->sc_int[level]; 381 sh->sh_func = func; 382 sh->sh_arg = arg; 383 sh->sh_flags = flags; 384 sh->sh_ipi_id = ipi_id; 385 } else for (CPU_INFO_FOREACH(cii, ci)) { 386 sc = ci->ci_data.cpu_softcpu; 387 sh = &sc->sc_hand[index]; 388 sh->sh_isr = &sc->sc_int[level]; 389 sh->sh_func = func; 390 sh->sh_arg = arg; 391 sh->sh_flags = flags; 392 sh->sh_ipi_id = ipi_id; 393 } 394 mutex_exit(&softint_lock); 395 396 return sih; 397 } 398 399 /* 400 * softint_disestablish: 401 * 402 * Unregister a software interrupt handler. The soft interrupt could 403 * still be active at this point, but the caller commits not to try 404 * and trigger it again once this call is made. The caller must not 405 * hold any locks that could be taken from soft interrupt context, 406 * because we will wait for the softint to complete if it's still 407 * running. 408 */ 409 void 410 softint_disestablish(void *arg) 411 { 412 CPU_INFO_ITERATOR cii; 413 struct cpu_info *ci; 414 softcpu_t *sc; 415 softhand_t *sh; 416 uintptr_t offset; 417 418 offset = (uintptr_t)arg; 419 KASSERTMSG(offset != 0 && offset < softint_bytes, "%"PRIuPTR" %u", 420 offset, softint_bytes); 421 422 /* 423 * Unregister IPI handler if there is any. Note: there is no need 424 * to disable preemption here - ID is stable. 425 */ 426 sc = curcpu()->ci_data.cpu_softcpu; 427 sh = (softhand_t *)((uint8_t *)sc + offset); 428 if (sh->sh_ipi_id) { 429 ipi_unregister(sh->sh_ipi_id); 430 } 431 432 /* 433 * Run a dummy softint at the same level on all CPUs and wait for 434 * completion, to make sure this softint is no longer running 435 * anywhere. 436 */ 437 xc_barrier(XC_HIGHPRI_IPL(sh->sh_isr->si_ipl)); 438 439 /* Clear the handler on each CPU. */ 440 mutex_enter(&softint_lock); 441 for (CPU_INFO_FOREACH(cii, ci)) { 442 sc = ci->ci_data.cpu_softcpu; 443 sh = (softhand_t *)((uint8_t *)sc + offset); 444 KASSERT(sh->sh_func != NULL); 445 sh->sh_func = NULL; 446 } 447 mutex_exit(&softint_lock); 448 } 449 450 /* 451 * softint_schedule: 452 * 453 * Trigger a software interrupt. Must be called from a hardware 454 * interrupt handler, or with preemption disabled (since we are 455 * using the value of curcpu()). 456 */ 457 void 458 softint_schedule(void *arg) 459 { 460 softhand_t *sh; 461 softint_t *si; 462 uintptr_t offset; 463 int s; 464 465 /* 466 * If this assert fires, rather than disabling preemption explicitly 467 * to make it stop, consider that you are probably using a softint 468 * when you don't need to. 469 */ 470 KASSERT(kpreempt_disabled()); 471 472 /* Find the handler record for this CPU. */ 473 offset = (uintptr_t)arg; 474 KASSERTMSG(offset != 0 && offset < softint_bytes, "%"PRIuPTR" %u", 475 offset, softint_bytes); 476 sh = (softhand_t *)((uint8_t *)curcpu()->ci_data.cpu_softcpu + offset); 477 478 /* If it's already pending there's nothing to do. */ 479 if ((sh->sh_flags & SOFTINT_PENDING) != 0) { 480 return; 481 } 482 483 /* 484 * Enqueue the handler into the LWP's pending list. 485 * If the LWP is completely idle, then make it run. 486 */ 487 s = splhigh(); 488 if ((sh->sh_flags & SOFTINT_PENDING) == 0) { 489 si = sh->sh_isr; 490 sh->sh_flags |= SOFTINT_PENDING; 491 SIMPLEQ_INSERT_TAIL(&si->si_q, sh, sh_q); 492 if (si->si_active == 0) { 493 si->si_active = 1; 494 softint_trigger(si->si_machdep); 495 } 496 } 497 splx(s); 498 } 499 500 /* 501 * softint_schedule_cpu: 502 * 503 * Trigger a software interrupt on a target CPU. This invokes 504 * softint_schedule() for the local CPU or send an IPI to invoke 505 * this routine on the remote CPU. Preemption must be disabled. 506 */ 507 void 508 softint_schedule_cpu(void *arg, struct cpu_info *ci) 509 { 510 KASSERT(kpreempt_disabled()); 511 512 if (curcpu() != ci) { 513 const softcpu_t *sc = ci->ci_data.cpu_softcpu; 514 const uintptr_t offset = (uintptr_t)arg; 515 const softhand_t *sh; 516 517 sh = (const softhand_t *)((const uint8_t *)sc + offset); 518 KASSERT((sh->sh_flags & SOFTINT_RCPU) != 0); 519 ipi_trigger(sh->sh_ipi_id, ci); 520 return; 521 } 522 523 /* Just a local CPU. */ 524 softint_schedule(arg); 525 } 526 527 /* 528 * softint_execute: 529 * 530 * Invoke handlers for the specified soft interrupt. 531 * Must be entered at splhigh. Will drop the priority 532 * to the level specified, but returns back at splhigh. 533 */ 534 static inline void 535 softint_execute(lwp_t *l, int s) 536 { 537 softint_t *si = l->l_private; 538 softhand_t *sh; 539 540 KASSERT(si->si_lwp == curlwp); 541 KASSERT(si->si_cpu == curcpu()); 542 KASSERT(si->si_lwp->l_wchan == NULL); 543 KASSERT(si->si_active); 544 545 /* 546 * Note: due to priority inheritance we may have interrupted a 547 * higher priority LWP. Since the soft interrupt must be quick 548 * and is non-preemptable, we don't bother yielding. 549 */ 550 551 while (!SIMPLEQ_EMPTY(&si->si_q)) { 552 /* 553 * Pick the longest waiting handler to run. We block 554 * interrupts but do not lock in order to do this, as 555 * we are protecting against the local CPU only. 556 */ 557 sh = SIMPLEQ_FIRST(&si->si_q); 558 SIMPLEQ_REMOVE_HEAD(&si->si_q, sh_q); 559 KASSERT((sh->sh_flags & SOFTINT_PENDING) != 0); 560 sh->sh_flags ^= SOFTINT_PENDING; 561 splx(s); 562 563 /* Run the handler. */ 564 if (__predict_true((sh->sh_flags & SOFTINT_MPSAFE) != 0)) { 565 (*sh->sh_func)(sh->sh_arg); 566 } else { 567 KERNEL_LOCK(1, l); 568 (*sh->sh_func)(sh->sh_arg); 569 KERNEL_UNLOCK_ONE(l); 570 } 571 572 /* Diagnostic: check that spin-locks have not leaked. */ 573 KASSERTMSG(curcpu()->ci_mtx_count == 0, 574 "%s: ci_mtx_count (%d) != 0, sh_func %p\n", 575 __func__, curcpu()->ci_mtx_count, sh->sh_func); 576 /* Diagnostic: check that psrefs have not leaked. */ 577 KASSERTMSG(l->l_psrefs == 0, "%s: l_psrefs=%d, sh_func=%p\n", 578 __func__, l->l_psrefs, sh->sh_func); 579 580 (void)splhigh(); 581 } 582 583 PSREF_DEBUG_BARRIER(); 584 585 CPU_COUNT(CPU_COUNT_NSOFT, 1); 586 587 KASSERT(si->si_cpu == curcpu()); 588 KASSERT(si->si_lwp->l_wchan == NULL); 589 KASSERT(si->si_active); 590 si->si_evcnt.ev_count++; 591 si->si_active = 0; 592 } 593 594 /* 595 * softint_block: 596 * 597 * Update statistics when the soft interrupt blocks. 598 */ 599 void 600 softint_block(lwp_t *l) 601 { 602 softint_t *si = l->l_private; 603 604 KASSERT((l->l_pflag & LP_INTR) != 0); 605 si->si_evcnt_block.ev_count++; 606 } 607 608 /* 609 * schednetisr: 610 * 611 * Trigger a legacy network interrupt. XXX Needs to go away. 612 */ 613 void 614 schednetisr(int isr) 615 { 616 617 softint_schedule(softint_netisrs[isr]); 618 } 619 620 #ifndef __HAVE_FAST_SOFTINTS 621 622 #ifdef __HAVE_PREEMPTION 623 #error __HAVE_PREEMPTION requires __HAVE_FAST_SOFTINTS 624 #endif 625 626 /* 627 * softint_init_md: 628 * 629 * Slow path: perform machine-dependent initialization. 630 */ 631 void 632 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 633 { 634 struct proc *p; 635 softint_t *si; 636 637 *machdep = (1 << level); 638 si = l->l_private; 639 p = l->l_proc; 640 641 mutex_enter(p->p_lock); 642 lwp_lock(l); 643 /* Cheat and make the KASSERT in softint_thread() happy. */ 644 si->si_active = 1; 645 setrunnable(l); 646 /* LWP now unlocked */ 647 mutex_exit(p->p_lock); 648 } 649 650 /* 651 * softint_trigger: 652 * 653 * Slow path: cause a soft interrupt handler to begin executing. 654 * Called at IPL_HIGH. 655 */ 656 void 657 softint_trigger(uintptr_t machdep) 658 { 659 struct cpu_info *ci; 660 lwp_t *l; 661 662 ci = curcpu(); 663 ci->ci_data.cpu_softints |= machdep; 664 l = ci->ci_onproc; 665 666 /* 667 * Arrange for mi_switch() to be called. If called from interrupt 668 * mode, we don't know if curlwp is executing in kernel or user, so 669 * post an AST and have it take a trip through userret(). If not in 670 * interrupt mode, curlwp is running in kernel and will notice the 671 * resched soon enough; avoid the AST. 672 */ 673 if (l == ci->ci_data.cpu_idlelwp) { 674 atomic_or_uint(&ci->ci_want_resched, 675 RESCHED_IDLE | RESCHED_UPREEMPT); 676 } else { 677 atomic_or_uint(&ci->ci_want_resched, RESCHED_UPREEMPT); 678 if (cpu_intr_p()) { 679 cpu_signotify(l); 680 } 681 } 682 } 683 684 /* 685 * softint_thread: 686 * 687 * Slow path: MI software interrupt dispatch. 688 */ 689 void 690 softint_thread(void *cookie) 691 { 692 softint_t *si; 693 lwp_t *l; 694 int s; 695 696 l = curlwp; 697 si = l->l_private; 698 699 for (;;) { 700 /* Clear pending status and run it. */ 701 s = splhigh(); 702 l->l_cpu->ci_data.cpu_softints &= ~si->si_machdep; 703 softint_execute(l, s); 704 splx(s); 705 706 /* Interrupts allowed to run again before switching. */ 707 lwp_lock(l); 708 l->l_stat = LSIDL; 709 spc_lock(l->l_cpu); 710 mi_switch(l); 711 } 712 } 713 714 /* 715 * softint_picklwp: 716 * 717 * Slow path: called from mi_switch() to pick the highest priority 718 * soft interrupt LWP that needs to run. 719 */ 720 lwp_t * 721 softint_picklwp(void) 722 { 723 struct cpu_info *ci; 724 u_int mask; 725 softint_t *si; 726 lwp_t *l; 727 728 ci = curcpu(); 729 si = ((softcpu_t *)ci->ci_data.cpu_softcpu)->sc_int; 730 mask = ci->ci_data.cpu_softints; 731 732 if ((mask & (1 << SOFTINT_SERIAL)) != 0) { 733 l = si[SOFTINT_SERIAL].si_lwp; 734 } else if ((mask & (1 << SOFTINT_NET)) != 0) { 735 l = si[SOFTINT_NET].si_lwp; 736 } else if ((mask & (1 << SOFTINT_BIO)) != 0) { 737 l = si[SOFTINT_BIO].si_lwp; 738 } else if ((mask & (1 << SOFTINT_CLOCK)) != 0) { 739 l = si[SOFTINT_CLOCK].si_lwp; 740 } else { 741 panic("softint_picklwp"); 742 } 743 744 return l; 745 } 746 747 #else /* !__HAVE_FAST_SOFTINTS */ 748 749 /* 750 * softint_thread: 751 * 752 * Fast path: the LWP is switched to without restoring any state, 753 * so we should not arrive here - there is a direct handoff between 754 * the interrupt stub and softint_dispatch(). 755 */ 756 void 757 softint_thread(void *cookie) 758 { 759 760 panic("softint_thread"); 761 } 762 763 /* 764 * softint_dispatch: 765 * 766 * Fast path: entry point from machine-dependent code. 767 */ 768 void 769 softint_dispatch(lwp_t *pinned, int s) 770 { 771 struct bintime now; 772 u_int timing; 773 lwp_t *l; 774 775 #ifdef DIAGNOSTIC 776 if ((pinned->l_pflag & LP_RUNNING) == 0 || curlwp->l_stat != LSIDL) { 777 struct lwp *onproc = curcpu()->ci_onproc; 778 int s2 = splhigh(); 779 printf("curcpu=%d, spl=%d curspl=%d\n" 780 "onproc=%p => l_stat=%d l_flag=%08x l_cpu=%d\n" 781 "curlwp=%p => l_stat=%d l_flag=%08x l_cpu=%d\n" 782 "pinned=%p => l_stat=%d l_flag=%08x l_cpu=%d\n", 783 cpu_index(curcpu()), s, s2, onproc, onproc->l_stat, 784 onproc->l_flag, cpu_index(onproc->l_cpu), curlwp, 785 curlwp->l_stat, curlwp->l_flag, 786 cpu_index(curlwp->l_cpu), pinned, pinned->l_stat, 787 pinned->l_flag, cpu_index(pinned->l_cpu)); 788 splx(s2); 789 panic("softint screwup"); 790 } 791 #endif 792 793 /* 794 * Note the interrupted LWP, and mark the current LWP as running 795 * before proceeding. Although this must as a rule be done with 796 * the LWP locked, at this point no external agents will want to 797 * modify the interrupt LWP's state. 798 */ 799 timing = softint_timing; 800 l = curlwp; 801 l->l_switchto = pinned; 802 l->l_stat = LSONPROC; 803 804 /* 805 * Dispatch the interrupt. If softints are being timed, charge 806 * for it. 807 */ 808 if (timing) { 809 binuptime(&l->l_stime); 810 membar_producer(); /* for calcru */ 811 l->l_pflag |= LP_TIMEINTR; 812 } 813 l->l_pflag |= LP_RUNNING; 814 softint_execute(l, s); 815 if (timing) { 816 binuptime(&now); 817 updatertime(l, &now); 818 l->l_pflag &= ~LP_TIMEINTR; 819 } 820 821 /* 822 * If we blocked while handling the interrupt, the pinned LWP is 823 * gone and we are now running as a kthread, so find another LWP to 824 * run. softint_dispatch() won't be reentered until the priority is 825 * finally dropped to IPL_NONE on entry to the next LWP on this CPU. 826 */ 827 l->l_stat = LSIDL; 828 if (l->l_switchto == NULL) { 829 lwp_lock(l); 830 spc_lock(l->l_cpu); 831 mi_switch(l); 832 /* NOTREACHED */ 833 } 834 l->l_switchto = NULL; 835 l->l_pflag &= ~LP_RUNNING; 836 } 837 838 #endif /* !__HAVE_FAST_SOFTINTS */ 839