1 /* $NetBSD: imx7-reset.h,v 1.1.1.1 2017/07/27 18:10:50 jmcneill Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Impinj, Inc. 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef DT_BINDING_RESET_IMX7_H 22 #define DT_BINDING_RESET_IMX7_H 23 24 #define IMX7_RESET_A7_CORE_POR_RESET0 0 25 #define IMX7_RESET_A7_CORE_POR_RESET1 1 26 #define IMX7_RESET_A7_CORE_RESET0 2 27 #define IMX7_RESET_A7_CORE_RESET1 3 28 #define IMX7_RESET_A7_DBG_RESET0 4 29 #define IMX7_RESET_A7_DBG_RESET1 5 30 #define IMX7_RESET_A7_ETM_RESET0 6 31 #define IMX7_RESET_A7_ETM_RESET1 7 32 #define IMX7_RESET_A7_SOC_DBG_RESET 8 33 #define IMX7_RESET_A7_L2RESET 9 34 #define IMX7_RESET_SW_M4C_RST 10 35 #define IMX7_RESET_SW_M4P_RST 11 36 #define IMX7_RESET_EIM_RST 12 37 #define IMX7_RESET_HSICPHY_PORT_RST 13 38 #define IMX7_RESET_USBPHY1_POR 14 39 #define IMX7_RESET_USBPHY1_PORT_RST 15 40 #define IMX7_RESET_USBPHY2_POR 16 41 #define IMX7_RESET_USBPHY2_PORT_RST 17 42 #define IMX7_RESET_MIPI_PHY_MRST 18 43 #define IMX7_RESET_MIPI_PHY_SRST 19 44 45 /* 46 * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 47 * and PCIEPHY_G_RST 48 */ 49 #define IMX7_RESET_PCIEPHY 20 50 #define IMX7_RESET_PCIEPHY_PERST 21 51 52 /* 53 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 54 * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 55 * of as one 56 */ 57 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 58 #define IMX7_RESET_DDRC_PRST 23 59 #define IMX7_RESET_DDRC_CORE_RST 24 60 61 #define IMX7_RESET_NUM 25 62 63 #endif 64 65