1 /* $NetBSD: hisi,hi6220-resets.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /** 4 * This header provides index for the reset controller 5 * based on hi6220 SoC. 6 */ 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 8 #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 9 10 #define PERIPH_RSTDIS0_MMC0 0x000 11 #define PERIPH_RSTDIS0_MMC1 0x001 12 #define PERIPH_RSTDIS0_MMC2 0x002 13 #define PERIPH_RSTDIS0_NANDC 0x003 14 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 15 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 16 #define PERIPH_RSTDIS0_USBOTG 0x006 17 #define PERIPH_RSTDIS0_USBOTG_32K 0x007 18 #define PERIPH_RSTDIS1_HIFI 0x100 19 #define PERIPH_RSTDIS1_DIGACODEC 0x105 20 #define PERIPH_RSTEN2_IPF 0x200 21 #define PERIPH_RSTEN2_SOCP 0x201 22 #define PERIPH_RSTEN2_DMAC 0x202 23 #define PERIPH_RSTEN2_SECENG 0x203 24 #define PERIPH_RSTEN2_ABB 0x204 25 #define PERIPH_RSTEN2_HPM0 0x205 26 #define PERIPH_RSTEN2_HPM1 0x206 27 #define PERIPH_RSTEN2_HPM2 0x207 28 #define PERIPH_RSTEN2_HPM3 0x208 29 #define PERIPH_RSTEN3_CSSYS 0x300 30 #define PERIPH_RSTEN3_I2C0 0x301 31 #define PERIPH_RSTEN3_I2C1 0x302 32 #define PERIPH_RSTEN3_I2C2 0x303 33 #define PERIPH_RSTEN3_I2C3 0x304 34 #define PERIPH_RSTEN3_UART1 0x305 35 #define PERIPH_RSTEN3_UART2 0x306 36 #define PERIPH_RSTEN3_UART3 0x307 37 #define PERIPH_RSTEN3_UART4 0x308 38 #define PERIPH_RSTEN3_SSP 0x309 39 #define PERIPH_RSTEN3_PWM 0x30a 40 #define PERIPH_RSTEN3_BLPWM 0x30b 41 #define PERIPH_RSTEN3_TSENSOR 0x30c 42 #define PERIPH_RSTEN3_DAPB 0x312 43 #define PERIPH_RSTEN3_HKADC 0x313 44 #define PERIPH_RSTEN3_CODEC_SSI 0x314 45 #define PERIPH_RSTEN3_PMUSSI1 0x316 46 #define PERIPH_RSTEN8_RS0 0x400 47 #define PERIPH_RSTEN8_RS2 0x401 48 #define PERIPH_RSTEN8_RS3 0x402 49 #define PERIPH_RSTEN8_MS0 0x403 50 #define PERIPH_RSTEN8_MS2 0x405 51 #define PERIPH_RSTEN8_XG2RAM0 0x406 52 #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 53 #define PERIPH_RSTEN8_SRAM 0x408 54 #define PERIPH_RSTEN8_HARQ 0x40a 55 #define PERIPH_RSTEN8_DDRC 0x40c 56 #define PERIPH_RSTEN8_DDRC_APB 0x40d 57 #define PERIPH_RSTEN8_DDRPACK_APB 0x40e 58 #define PERIPH_RSTEN8_DDRT 0x411 59 #define PERIPH_RSDIST9_CARM_DAP 0x500 60 #define PERIPH_RSDIST9_CARM_ATB 0x501 61 #define PERIPH_RSDIST9_CARM_LBUS 0x502 62 #define PERIPH_RSDIST9_CARM_POR 0x503 63 #define PERIPH_RSDIST9_CARM_CORE 0x504 64 #define PERIPH_RSDIST9_CARM_DBG 0x505 65 #define PERIPH_RSDIST9_CARM_L2 0x506 66 #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 67 #define PERIPH_RSDIST9_CARM_ETM 0x508 68 69 #define MEDIA_G3D 0 70 #define MEDIA_CODEC_VPU 2 71 #define MEDIA_CODEC_JPEG 3 72 #define MEDIA_ISP 4 73 #define MEDIA_ADE 5 74 #define MEDIA_MMU 6 75 #define MEDIA_XG2RAM1 7 76 77 #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 78