1 /* $NetBSD: as3722.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * This header provides macros for ams AS3722 device bindings. 5 * 6 * Copyright (c) 2013, NVIDIA Corporation. 7 * 8 * Author: Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 */ 11 12 #ifndef __DT_BINDINGS_AS3722_H__ 13 #define __DT_BINDINGS_AS3722_H__ 14 15 /* External control pins */ 16 #define AS3722_EXT_CONTROL_PIN_ENABLE1 1 17 #define AS3722_EXT_CONTROL_PIN_ENABLE2 2 18 #define AS3722_EXT_CONTROL_PIN_ENABLE3 3 19 20 /* Interrupt numbers for AS3722 */ 21 #define AS3722_IRQ_LID 0 22 #define AS3722_IRQ_ACOK 1 23 #define AS3722_IRQ_ENABLE1 2 24 #define AS3722_IRQ_OCCUR_ALARM_SD0 3 25 #define AS3722_IRQ_ONKEY_LONG_PRESS 4 26 #define AS3722_IRQ_ONKEY 5 27 #define AS3722_IRQ_OVTMP 6 28 #define AS3722_IRQ_LOWBAT 7 29 #define AS3722_IRQ_SD0_LV 8 30 #define AS3722_IRQ_SD1_LV 9 31 #define AS3722_IRQ_SD2_LV 10 32 #define AS3722_IRQ_PWM1_OV_PROT 11 33 #define AS3722_IRQ_PWM2_OV_PROT 12 34 #define AS3722_IRQ_ENABLE2 13 35 #define AS3722_IRQ_SD6_LV 14 36 #define AS3722_IRQ_RTC_REP 15 37 #define AS3722_IRQ_RTC_ALARM 16 38 #define AS3722_IRQ_GPIO1 17 39 #define AS3722_IRQ_GPIO2 18 40 #define AS3722_IRQ_GPIO3 19 41 #define AS3722_IRQ_GPIO4 20 42 #define AS3722_IRQ_GPIO5 21 43 #define AS3722_IRQ_WATCHDOG 22 44 #define AS3722_IRQ_ENABLE3 23 45 #define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24 46 #define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25 47 #define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26 48 #define AS3722_IRQ_TEMP_SD0_ALARM 27 49 #define AS3722_IRQ_TEMP_SD1_ALARM 28 50 #define AS3722_IRQ_TEMP_SD6_ALARM 29 51 #define AS3722_IRQ_OCCUR_ALARM_SD6 30 52 #define AS3722_IRQ_ADC 31 53 54 #endif /* __DT_BINDINGS_AS3722_H__ */ 55