1 /* $NetBSD: tegra186-mc.h,v 1.1.1.2 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H 4 #define DT_BINDINGS_MEMORY_TEGRA186_MC_H 5 6 /* special clients */ 7 #define TEGRA186_SID_INVALID 0x00 8 #define TEGRA186_SID_PASSTHROUGH 0x7f 9 10 /* host1x clients */ 11 #define TEGRA186_SID_HOST1X 0x01 12 #define TEGRA186_SID_CSI 0x02 13 #define TEGRA186_SID_VIC 0x03 14 #define TEGRA186_SID_VI 0x04 15 #define TEGRA186_SID_ISP 0x05 16 #define TEGRA186_SID_NVDEC 0x06 17 #define TEGRA186_SID_NVENC 0x07 18 #define TEGRA186_SID_NVJPG 0x08 19 #define TEGRA186_SID_NVDISPLAY 0x09 20 #define TEGRA186_SID_TSEC 0x0a 21 #define TEGRA186_SID_TSECB 0x0b 22 #define TEGRA186_SID_SE 0x0c 23 #define TEGRA186_SID_SE1 0x0d 24 #define TEGRA186_SID_SE2 0x0e 25 #define TEGRA186_SID_SE3 0x0f 26 27 /* GPU clients */ 28 #define TEGRA186_SID_GPU 0x10 29 30 /* other SoC clients */ 31 #define TEGRA186_SID_AFI 0x11 32 #define TEGRA186_SID_HDA 0x12 33 #define TEGRA186_SID_ETR 0x13 34 #define TEGRA186_SID_EQOS 0x14 35 #define TEGRA186_SID_UFSHC 0x15 36 #define TEGRA186_SID_AON 0x16 37 #define TEGRA186_SID_SDMMC4 0x17 38 #define TEGRA186_SID_SDMMC3 0x18 39 #define TEGRA186_SID_SDMMC2 0x19 40 #define TEGRA186_SID_SDMMC1 0x1a 41 #define TEGRA186_SID_XUSB_HOST 0x1b 42 #define TEGRA186_SID_XUSB_DEV 0x1c 43 #define TEGRA186_SID_SATA 0x1d 44 #define TEGRA186_SID_APE 0x1e 45 #define TEGRA186_SID_SCE 0x1f 46 47 /* GPC DMA clients */ 48 #define TEGRA186_SID_GPCDMA_0 0x20 49 #define TEGRA186_SID_GPCDMA_1 0x21 50 #define TEGRA186_SID_GPCDMA_2 0x22 51 #define TEGRA186_SID_GPCDMA_3 0x23 52 #define TEGRA186_SID_GPCDMA_4 0x24 53 #define TEGRA186_SID_GPCDMA_5 0x25 54 #define TEGRA186_SID_GPCDMA_6 0x26 55 #define TEGRA186_SID_GPCDMA_7 0x27 56 57 /* APE DMA clients */ 58 #define TEGRA186_SID_APE_1 0x28 59 #define TEGRA186_SID_APE_2 0x29 60 61 /* camera RTCPU */ 62 #define TEGRA186_SID_RCE 0x2a 63 64 /* camera RTCPU on host1x address space */ 65 #define TEGRA186_SID_RCE_1X 0x2b 66 67 /* APE DMA clients */ 68 #define TEGRA186_SID_APE_3 0x2c 69 70 /* camera RTCPU running on APE */ 71 #define TEGRA186_SID_APE_CAM 0x2d 72 #define TEGRA186_SID_APE_CAM_1X 0x2e 73 74 /* 75 * The BPMP has its SID value hardcoded in the firmware. Changing it requires 76 * considerable effort. 77 */ 78 #define TEGRA186_SID_BPMP 0x32 79 80 /* for SMMU tests */ 81 #define TEGRA186_SID_SMMU_TEST 0x33 82 83 /* host1x virtualization channels */ 84 #define TEGRA186_SID_HOST1X_CTX0 0x38 85 #define TEGRA186_SID_HOST1X_CTX1 0x39 86 #define TEGRA186_SID_HOST1X_CTX2 0x3a 87 #define TEGRA186_SID_HOST1X_CTX3 0x3b 88 #define TEGRA186_SID_HOST1X_CTX4 0x3c 89 #define TEGRA186_SID_HOST1X_CTX5 0x3d 90 #define TEGRA186_SID_HOST1X_CTX6 0x3e 91 #define TEGRA186_SID_HOST1X_CTX7 0x3f 92 93 /* host1x command buffers */ 94 #define TEGRA186_SID_HOST1X_VM0 0x40 95 #define TEGRA186_SID_HOST1X_VM1 0x41 96 #define TEGRA186_SID_HOST1X_VM2 0x42 97 #define TEGRA186_SID_HOST1X_VM3 0x43 98 #define TEGRA186_SID_HOST1X_VM4 0x44 99 #define TEGRA186_SID_HOST1X_VM5 0x45 100 #define TEGRA186_SID_HOST1X_VM6 0x46 101 #define TEGRA186_SID_HOST1X_VM7 0x47 102 103 /* SE data buffers */ 104 #define TEGRA186_SID_SE_VM0 0x48 105 #define TEGRA186_SID_SE_VM1 0x49 106 #define TEGRA186_SID_SE_VM2 0x4a 107 #define TEGRA186_SID_SE_VM3 0x4b 108 #define TEGRA186_SID_SE_VM4 0x4c 109 #define TEGRA186_SID_SE_VM5 0x4d 110 #define TEGRA186_SID_SE_VM6 0x4e 111 #define TEGRA186_SID_SE_VM7 0x4f 112 113 /* 114 * memory client IDs 115 */ 116 117 /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 118 #define TEGRA186_MEMORY_CLIENT_PTCR 0x00 119 /* PCIE reads */ 120 #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e 121 /* High-definition audio (HDA) reads */ 122 #define TEGRA186_MEMORY_CLIENT_HDAR 0x15 123 /* Host channel data reads */ 124 #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 125 #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c 126 /* SATA reads */ 127 #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f 128 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */ 129 #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 130 #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b 131 /* PCIE writes */ 132 #define TEGRA186_MEMORY_CLIENT_AFIW 0x31 133 /* High-definition audio (HDA) writes */ 134 #define TEGRA186_MEMORY_CLIENT_HDAW 0x35 135 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 136 #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 137 /* SATA writes */ 138 #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d 139 /* ISP Read client for Crossbar A */ 140 #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 141 /* ISP Write client for Crossbar A */ 142 #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 143 /* ISP Write client Crossbar B */ 144 #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 145 /* XUSB reads */ 146 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a 147 /* XUSB_HOST writes */ 148 #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b 149 /* XUSB reads */ 150 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c 151 /* XUSB_DEV writes */ 152 #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d 153 /* TSEC Memory Return Data Client Description */ 154 #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 155 /* TSEC Memory Write Client Description */ 156 #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 157 /* 3D, ltcx reads instance 0 */ 158 #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 159 /* 3D, ltcx writes instance 0 */ 160 #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 161 /* sdmmca memory read client */ 162 #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 163 /* sdmmcbmemory read client */ 164 #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 165 /* sdmmc memory read client */ 166 #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 167 /* sdmmcd memory read client */ 168 #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 169 /* sdmmca memory write client */ 170 #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 171 /* sdmmcb memory write client */ 172 #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 173 /* sdmmc memory write client */ 174 #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 175 /* sdmmcd memory write client */ 176 #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 177 #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c 178 #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d 179 /* VI Write client */ 180 #define TEGRA186_MEMORY_CLIENT_VIW 0x72 181 #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 182 #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 183 /* Audio Processing (APE) engine reads */ 184 #define TEGRA186_MEMORY_CLIENT_APER 0x7a 185 /* Audio Processing (APE) engine writes */ 186 #define TEGRA186_MEMORY_CLIENT_APEW 0x7b 187 #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e 188 #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f 189 /* SE Memory Return Data Client Description */ 190 #define TEGRA186_MEMORY_CLIENT_SESRD 0x80 191 /* SE Memory Write Client Description */ 192 #define TEGRA186_MEMORY_CLIENT_SESWR 0x81 193 /* ETR reads */ 194 #define TEGRA186_MEMORY_CLIENT_ETRR 0x84 195 /* ETR writes */ 196 #define TEGRA186_MEMORY_CLIENT_ETRW 0x85 197 /* TSECB Memory Return Data Client Description */ 198 #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 199 /* TSECB Memory Write Client Description */ 200 #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 201 /* 3D, ltcx reads instance 1 */ 202 #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 203 /* 3D, ltcx writes instance 1 */ 204 #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 205 /* AXI Switch read client */ 206 #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c 207 /* AXI Switch write client */ 208 #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d 209 /* EQOS read client */ 210 #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e 211 /* EQOS write client */ 212 #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f 213 /* UFSHC read client */ 214 #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 215 /* UFSHC write client */ 216 #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 217 /* NVDISPLAY read client */ 218 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 219 /* BPMP read client */ 220 #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 221 /* BPMP write client */ 222 #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 223 /* BPMPDMA read client */ 224 #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 225 /* BPMPDMA write client */ 226 #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 227 /* AON read client */ 228 #define TEGRA186_MEMORY_CLIENT_AONR 0x97 229 /* AON write client */ 230 #define TEGRA186_MEMORY_CLIENT_AONW 0x98 231 /* AONDMA read client */ 232 #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 233 /* AONDMA write client */ 234 #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a 235 /* SCE read client */ 236 #define TEGRA186_MEMORY_CLIENT_SCER 0x9b 237 /* SCE write client */ 238 #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c 239 /* SCEDMA read client */ 240 #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d 241 /* SCEDMA write client */ 242 #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e 243 /* APEDMA read client */ 244 #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f 245 /* APEDMA write client */ 246 #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 247 /* NVDISPLAY read client instance 2 */ 248 #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 249 #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 250 #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 251 252 #endif 253