1 /* $NetBSD: tegra30-car.h,v 1.1.1.2 2017/07/27 18:10:51 jmcneill Exp $ */ 2 3 /* 4 * This header provides constants for binding nvidia,tegra30-car. 5 * 6 * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 7 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 8 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 9 * this case, those clocks are assigned IDs above 160 in order to highlight 10 * this issue. Implementations that interpret these clock IDs as bit values 11 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 12 * explicitly handle these special cases. 13 * 14 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 15 * above. 16 */ 17 18 #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 19 #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 20 21 #define TEGRA30_CLK_CPU 0 22 /* 1 */ 23 /* 2 */ 24 /* 3 */ 25 #define TEGRA30_CLK_RTC 4 26 #define TEGRA30_CLK_TIMER 5 27 #define TEGRA30_CLK_UARTA 6 28 /* 7 (register bit affects uartb and vfir) */ 29 #define TEGRA30_CLK_GPIO 8 30 #define TEGRA30_CLK_SDMMC2 9 31 /* 10 (register bit affects spdif_in and spdif_out) */ 32 #define TEGRA30_CLK_I2S1 11 33 #define TEGRA30_CLK_I2C1 12 34 #define TEGRA30_CLK_NDFLASH 13 35 #define TEGRA30_CLK_SDMMC1 14 36 #define TEGRA30_CLK_SDMMC4 15 37 /* 16 */ 38 #define TEGRA30_CLK_PWM 17 39 #define TEGRA30_CLK_I2S2 18 40 #define TEGRA30_CLK_EPP 19 41 /* 20 (register bit affects vi and vi_sensor) */ 42 #define TEGRA30_CLK_GR2D 21 43 #define TEGRA30_CLK_USBD 22 44 #define TEGRA30_CLK_ISP 23 45 #define TEGRA30_CLK_GR3D 24 46 /* 25 */ 47 #define TEGRA30_CLK_DISP2 26 48 #define TEGRA30_CLK_DISP1 27 49 #define TEGRA30_CLK_HOST1X 28 50 #define TEGRA30_CLK_VCP 29 51 #define TEGRA30_CLK_I2S0 30 52 #define TEGRA30_CLK_COP_CACHE 31 53 54 #define TEGRA30_CLK_MC 32 55 #define TEGRA30_CLK_AHBDMA 33 56 #define TEGRA30_CLK_APBDMA 34 57 /* 35 */ 58 #define TEGRA30_CLK_KBC 36 59 #define TEGRA30_CLK_STATMON 37 60 #define TEGRA30_CLK_PMC 38 61 /* 39 (register bit affects fuse and fuse_burn) */ 62 #define TEGRA30_CLK_KFUSE 40 63 #define TEGRA30_CLK_SBC1 41 64 #define TEGRA30_CLK_NOR 42 65 /* 43 */ 66 #define TEGRA30_CLK_SBC2 44 67 /* 45 */ 68 #define TEGRA30_CLK_SBC3 46 69 #define TEGRA30_CLK_I2C5 47 70 #define TEGRA30_CLK_DSIA 48 71 /* 49 (register bit affects cve and tvo) */ 72 #define TEGRA30_CLK_MIPI 50 73 #define TEGRA30_CLK_HDMI 51 74 #define TEGRA30_CLK_CSI 52 75 #define TEGRA30_CLK_TVDAC 53 76 #define TEGRA30_CLK_I2C2 54 77 #define TEGRA30_CLK_UARTC 55 78 /* 56 */ 79 #define TEGRA30_CLK_EMC 57 80 #define TEGRA30_CLK_USB2 58 81 #define TEGRA30_CLK_USB3 59 82 #define TEGRA30_CLK_MPE 60 83 #define TEGRA30_CLK_VDE 61 84 #define TEGRA30_CLK_BSEA 62 85 #define TEGRA30_CLK_BSEV 63 86 87 #define TEGRA30_CLK_SPEEDO 64 88 #define TEGRA30_CLK_UARTD 65 89 #define TEGRA30_CLK_UARTE 66 90 #define TEGRA30_CLK_I2C3 67 91 #define TEGRA30_CLK_SBC4 68 92 #define TEGRA30_CLK_SDMMC3 69 93 #define TEGRA30_CLK_PCIE 70 94 #define TEGRA30_CLK_OWR 71 95 #define TEGRA30_CLK_AFI 72 96 #define TEGRA30_CLK_CSITE 73 97 /* 74 */ 98 #define TEGRA30_CLK_AVPUCQ 75 99 #define TEGRA30_CLK_LA 76 100 /* 77 */ 101 /* 78 */ 102 #define TEGRA30_CLK_DTV 79 103 #define TEGRA30_CLK_NDSPEED 80 104 #define TEGRA30_CLK_I2CSLOW 81 105 #define TEGRA30_CLK_DSIB 82 106 /* 83 */ 107 #define TEGRA30_CLK_IRAMA 84 108 #define TEGRA30_CLK_IRAMB 85 109 #define TEGRA30_CLK_IRAMC 86 110 #define TEGRA30_CLK_IRAMD 87 111 #define TEGRA30_CLK_CRAM2 88 112 /* 89 */ 113 #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 114 /* 91 */ 115 #define TEGRA30_CLK_CSUS 92 116 #define TEGRA30_CLK_CDEV2 93 117 #define TEGRA30_CLK_CDEV1 94 118 /* 95 */ 119 120 #define TEGRA30_CLK_CPU_G 96 121 #define TEGRA30_CLK_CPU_LP 97 122 #define TEGRA30_CLK_GR3D2 98 123 #define TEGRA30_CLK_MSELECT 99 124 #define TEGRA30_CLK_TSENSOR 100 125 #define TEGRA30_CLK_I2S3 101 126 #define TEGRA30_CLK_I2S4 102 127 #define TEGRA30_CLK_I2C4 103 128 #define TEGRA30_CLK_SBC5 104 129 #define TEGRA30_CLK_SBC6 105 130 #define TEGRA30_CLK_D_AUDIO 106 131 #define TEGRA30_CLK_APBIF 107 132 #define TEGRA30_CLK_DAM0 108 133 #define TEGRA30_CLK_DAM1 109 134 #define TEGRA30_CLK_DAM2 110 135 #define TEGRA30_CLK_HDA2CODEC_2X 111 136 #define TEGRA30_CLK_ATOMICS 112 137 #define TEGRA30_CLK_AUDIO0_2X 113 138 #define TEGRA30_CLK_AUDIO1_2X 114 139 #define TEGRA30_CLK_AUDIO2_2X 115 140 #define TEGRA30_CLK_AUDIO3_2X 116 141 #define TEGRA30_CLK_AUDIO4_2X 117 142 #define TEGRA30_CLK_SPDIF_2X 118 143 #define TEGRA30_CLK_ACTMON 119 144 #define TEGRA30_CLK_EXTERN1 120 145 #define TEGRA30_CLK_EXTERN2 121 146 #define TEGRA30_CLK_EXTERN3 122 147 #define TEGRA30_CLK_SATA_OOB 123 148 #define TEGRA30_CLK_SATA 124 149 #define TEGRA30_CLK_HDA 125 150 /* 126 */ 151 #define TEGRA30_CLK_SE 127 152 153 #define TEGRA30_CLK_HDA2HDMI 128 154 #define TEGRA30_CLK_SATA_COLD 129 155 /* 130 */ 156 /* 131 */ 157 /* 132 */ 158 /* 133 */ 159 /* 134 */ 160 /* 135 */ 161 #define TEGRA30_CLK_CEC 136 162 /* 137 */ 163 /* 138 */ 164 /* 139 */ 165 /* 140 */ 166 /* 141 */ 167 /* 142 */ 168 /* 143 */ 169 /* 144 */ 170 /* 145 */ 171 /* 146 */ 172 /* 147 */ 173 /* 148 */ 174 /* 149 */ 175 /* 150 */ 176 /* 151 */ 177 /* 152 */ 178 /* 153 */ 179 /* 154 */ 180 /* 155 */ 181 /* 156 */ 182 /* 157 */ 183 /* 158 */ 184 /* 159 */ 185 186 #define TEGRA30_CLK_UARTB 160 187 #define TEGRA30_CLK_VFIR 161 188 #define TEGRA30_CLK_SPDIF_IN 162 189 #define TEGRA30_CLK_SPDIF_OUT 163 190 #define TEGRA30_CLK_VI 164 191 #define TEGRA30_CLK_VI_SENSOR 165 192 #define TEGRA30_CLK_FUSE 166 193 #define TEGRA30_CLK_FUSE_BURN 167 194 #define TEGRA30_CLK_CVE 168 195 #define TEGRA30_CLK_TVO 169 196 #define TEGRA30_CLK_CLK_32K 170 197 #define TEGRA30_CLK_CLK_M 171 198 #define TEGRA30_CLK_CLK_M_DIV2 172 199 #define TEGRA30_CLK_CLK_M_DIV4 173 200 #define TEGRA30_CLK_PLL_REF 174 201 #define TEGRA30_CLK_PLL_C 175 202 #define TEGRA30_CLK_PLL_C_OUT1 176 203 #define TEGRA30_CLK_PLL_M 177 204 #define TEGRA30_CLK_PLL_M_OUT1 178 205 #define TEGRA30_CLK_PLL_P 179 206 #define TEGRA30_CLK_PLL_P_OUT1 180 207 #define TEGRA30_CLK_PLL_P_OUT2 181 208 #define TEGRA30_CLK_PLL_P_OUT3 182 209 #define TEGRA30_CLK_PLL_P_OUT4 183 210 #define TEGRA30_CLK_PLL_A 184 211 #define TEGRA30_CLK_PLL_A_OUT0 185 212 #define TEGRA30_CLK_PLL_D 186 213 #define TEGRA30_CLK_PLL_D_OUT0 187 214 #define TEGRA30_CLK_PLL_D2 188 215 #define TEGRA30_CLK_PLL_D2_OUT0 189 216 #define TEGRA30_CLK_PLL_U 190 217 #define TEGRA30_CLK_PLL_X 191 218 219 #define TEGRA30_CLK_PLL_X_OUT0 192 220 #define TEGRA30_CLK_PLL_E 193 221 #define TEGRA30_CLK_SPDIF_IN_SYNC 194 222 #define TEGRA30_CLK_I2S0_SYNC 195 223 #define TEGRA30_CLK_I2S1_SYNC 196 224 #define TEGRA30_CLK_I2S2_SYNC 197 225 #define TEGRA30_CLK_I2S3_SYNC 198 226 #define TEGRA30_CLK_I2S4_SYNC 199 227 #define TEGRA30_CLK_VIMCLK_SYNC 200 228 #define TEGRA30_CLK_AUDIO0 201 229 #define TEGRA30_CLK_AUDIO1 202 230 #define TEGRA30_CLK_AUDIO2 203 231 #define TEGRA30_CLK_AUDIO3 204 232 #define TEGRA30_CLK_AUDIO4 205 233 #define TEGRA30_CLK_SPDIF 206 234 #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 235 #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 236 #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 237 #define TEGRA30_CLK_SCLK 210 238 #define TEGRA30_CLK_BLINK 211 239 #define TEGRA30_CLK_CCLK_G 212 240 #define TEGRA30_CLK_CCLK_LP 213 241 #define TEGRA30_CLK_TWD 214 242 #define TEGRA30_CLK_CML0 215 243 #define TEGRA30_CLK_CML1 216 244 #define TEGRA30_CLK_HCLK 217 245 #define TEGRA30_CLK_PCLK 218 246 /* 219 */ 247 /* 220 */ 248 /* 221 */ 249 /* 222 */ 250 /* 223 */ 251 252 /* 288 */ 253 /* 289 */ 254 /* 290 */ 255 /* 291 */ 256 /* 292 */ 257 /* 293 */ 258 /* 294 */ 259 /* 295 */ 260 /* 296 */ 261 /* 297 */ 262 /* 298 */ 263 /* 299 */ 264 #define TEGRA30_CLK_CLK_OUT_1_MUX 300 265 #define TEGRA30_CLK_CLK_OUT_2_MUX 301 266 #define TEGRA30_CLK_CLK_OUT_3_MUX 302 267 #define TEGRA30_CLK_AUDIO0_MUX 303 268 #define TEGRA30_CLK_AUDIO1_MUX 304 269 #define TEGRA30_CLK_AUDIO2_MUX 305 270 #define TEGRA30_CLK_AUDIO3_MUX 306 271 #define TEGRA30_CLK_AUDIO4_MUX 307 272 #define TEGRA30_CLK_SPDIF_MUX 308 273 #define TEGRA30_CLK_CLK_MAX 309 274 275 #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 276