1 /* $NetBSD: tegra210-car.h,v 1.1.1.4 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides constants for binding nvidia,tegra210-car. 6 * 7 * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 8 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 9 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 10 * this case, those clocks are assigned IDs above 224 in order to highlight 11 * this issue. Implementations that interpret these clock IDs as bit values 12 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 13 * explicitly handle these special cases. 14 * 15 * The balance of the clocks controlled by the CAR are assigned IDs of 224 and 16 * above. 17 */ 18 19 #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 20 #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 21 22 /* 0 */ 23 /* 1 */ 24 /* 2 */ 25 #define TEGRA210_CLK_ISPB 3 26 #define TEGRA210_CLK_RTC 4 27 #define TEGRA210_CLK_TIMER 5 28 #define TEGRA210_CLK_UARTA 6 29 /* 7 (register bit affects uartb and vfir) */ 30 #define TEGRA210_CLK_GPIO 8 31 #define TEGRA210_CLK_SDMMC2 9 32 /* 10 (register bit affects spdif_in and spdif_out) */ 33 #define TEGRA210_CLK_I2S1 11 34 #define TEGRA210_CLK_I2C1 12 35 /* 13 */ 36 #define TEGRA210_CLK_SDMMC1 14 37 #define TEGRA210_CLK_SDMMC4 15 38 /* 16 */ 39 #define TEGRA210_CLK_PWM 17 40 #define TEGRA210_CLK_I2S2 18 41 /* 19 */ 42 /* 20 (register bit affects vi and vi_sensor) */ 43 /* 21 */ 44 #define TEGRA210_CLK_USBD 22 45 #define TEGRA210_CLK_ISPA 23 46 /* 24 */ 47 /* 25 */ 48 #define TEGRA210_CLK_DISP2 26 49 #define TEGRA210_CLK_DISP1 27 50 #define TEGRA210_CLK_HOST1X 28 51 /* 29 */ 52 #define TEGRA210_CLK_I2S0 30 53 /* 31 */ 54 55 #define TEGRA210_CLK_MC 32 56 #define TEGRA210_CLK_AHBDMA 33 57 #define TEGRA210_CLK_APBDMA 34 58 /* 35 */ 59 /* 36 */ 60 /* 37 */ 61 #define TEGRA210_CLK_PMC 38 62 /* 39 (register bit affects fuse and fuse_burn) */ 63 #define TEGRA210_CLK_KFUSE 40 64 #define TEGRA210_CLK_SBC1 41 65 /* 42 */ 66 /* 43 */ 67 #define TEGRA210_CLK_SBC2 44 68 /* 45 */ 69 #define TEGRA210_CLK_SBC3 46 70 #define TEGRA210_CLK_I2C5 47 71 #define TEGRA210_CLK_DSIA 48 72 /* 49 */ 73 /* 50 */ 74 /* 51 */ 75 #define TEGRA210_CLK_CSI 52 76 /* 53 */ 77 #define TEGRA210_CLK_I2C2 54 78 #define TEGRA210_CLK_UARTC 55 79 #define TEGRA210_CLK_MIPI_CAL 56 80 #define TEGRA210_CLK_EMC 57 81 #define TEGRA210_CLK_USB2 58 82 /* 59 */ 83 /* 60 */ 84 /* 61 */ 85 /* 62 */ 86 #define TEGRA210_CLK_BSEV 63 87 88 /* 64 */ 89 #define TEGRA210_CLK_UARTD 65 90 /* 66 */ 91 #define TEGRA210_CLK_I2C3 67 92 #define TEGRA210_CLK_SBC4 68 93 #define TEGRA210_CLK_SDMMC3 69 94 #define TEGRA210_CLK_PCIE 70 95 #define TEGRA210_CLK_OWR 71 96 #define TEGRA210_CLK_AFI 72 97 #define TEGRA210_CLK_CSITE 73 98 /* 74 */ 99 /* 75 */ 100 #define TEGRA210_CLK_LA 76 101 /* 77 */ 102 #define TEGRA210_CLK_SOC_THERM 78 103 #define TEGRA210_CLK_DTV 79 104 /* 80 */ 105 #define TEGRA210_CLK_I2CSLOW 81 106 #define TEGRA210_CLK_DSIB 82 107 #define TEGRA210_CLK_TSEC 83 108 /* 84 */ 109 /* 85 */ 110 /* 86 */ 111 /* 87 */ 112 /* 88 */ 113 #define TEGRA210_CLK_XUSB_HOST 89 114 /* 90 */ 115 /* 91 */ 116 #define TEGRA210_CLK_CSUS 92 117 /* 93 */ 118 /* 94 */ 119 /* 95 (bit affects xusb_dev and xusb_dev_src) */ 120 121 /* 96 */ 122 /* 97 */ 123 /* 98 */ 124 #define TEGRA210_CLK_MSELECT 99 125 #define TEGRA210_CLK_TSENSOR 100 126 #define TEGRA210_CLK_I2S3 101 127 #define TEGRA210_CLK_I2S4 102 128 #define TEGRA210_CLK_I2C4 103 129 /* 104 */ 130 /* 105 */ 131 #define TEGRA210_CLK_D_AUDIO 106 132 #define TEGRA210_CLK_APB2APE 107 133 /* 108 */ 134 /* 109 */ 135 /* 110 */ 136 #define TEGRA210_CLK_HDA2CODEC_2X 111 137 /* 112 */ 138 /* 113 */ 139 /* 114 */ 140 /* 115 */ 141 /* 116 */ 142 /* 117 */ 143 #define TEGRA210_CLK_SPDIF_2X 118 144 #define TEGRA210_CLK_ACTMON 119 145 #define TEGRA210_CLK_EXTERN1 120 146 #define TEGRA210_CLK_EXTERN2 121 147 #define TEGRA210_CLK_EXTERN3 122 148 #define TEGRA210_CLK_SATA_OOB 123 149 #define TEGRA210_CLK_SATA 124 150 #define TEGRA210_CLK_HDA 125 151 /* 126 */ 152 /* 127 */ 153 154 #define TEGRA210_CLK_HDA2HDMI 128 155 /* 129 */ 156 /* 130 */ 157 /* 131 */ 158 /* 132 */ 159 /* 133 */ 160 /* 134 */ 161 /* 135 */ 162 #define TEGRA210_CLK_CEC 136 163 /* 137 */ 164 /* 138 */ 165 /* 139 */ 166 /* 140 */ 167 /* 141 */ 168 /* 142 */ 169 /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ 170 #define TEGRA210_CLK_XUSB_GATE 143 171 #define TEGRA210_CLK_CILAB 144 172 #define TEGRA210_CLK_CILCD 145 173 #define TEGRA210_CLK_CILE 146 174 #define TEGRA210_CLK_DSIALP 147 175 #define TEGRA210_CLK_DSIBLP 148 176 #define TEGRA210_CLK_ENTROPY 149 177 /* 150 */ 178 /* 151 */ 179 #define TEGRA210_CLK_DP2 152 180 /* 153 */ 181 /* 154 */ 182 /* 155 (bit affects dfll_ref and dfll_soc) */ 183 #define TEGRA210_CLK_XUSB_SS 156 184 /* 157 */ 185 /* 158 */ 186 /* 159 */ 187 188 /* 160 */ 189 #define TEGRA210_CLK_DMIC1 161 190 #define TEGRA210_CLK_DMIC2 162 191 /* 163 */ 192 /* 164 */ 193 /* 165 */ 194 #define TEGRA210_CLK_I2C6 166 195 /* 167 */ 196 /* 168 */ 197 /* 169 */ 198 /* 170 */ 199 #define TEGRA210_CLK_VIM2_CLK 171 200 /* 172 */ 201 #define TEGRA210_CLK_MIPIBIF 173 202 /* 174 */ 203 /* 175 */ 204 /* 176 */ 205 #define TEGRA210_CLK_CLK72MHZ 177 206 #define TEGRA210_CLK_VIC03 178 207 /* 179 */ 208 /* 180 */ 209 #define TEGRA210_CLK_DPAUX 181 210 #define TEGRA210_CLK_SOR0 182 211 #define TEGRA210_CLK_SOR1 183 212 #define TEGRA210_CLK_GPU 184 213 #define TEGRA210_CLK_DBGAPB 185 214 /* 186 */ 215 #define TEGRA210_CLK_PLL_P_OUT_ADSP 187 216 /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ 217 #define TEGRA210_CLK_PLL_G_REF 189 218 /* 190 */ 219 /* 191 */ 220 221 /* 192 */ 222 #define TEGRA210_CLK_SDMMC_LEGACY 193 223 #define TEGRA210_CLK_NVDEC 194 224 #define TEGRA210_CLK_NVJPG 195 225 /* 196 */ 226 #define TEGRA210_CLK_DMIC3 197 227 #define TEGRA210_CLK_APE 198 228 #define TEGRA210_CLK_ADSP 199 229 /* 200 */ 230 /* 201 */ 231 #define TEGRA210_CLK_MAUD 202 232 /* 203 */ 233 /* 204 */ 234 /* 205 */ 235 #define TEGRA210_CLK_TSECB 206 236 #define TEGRA210_CLK_DPAUX1 207 237 #define TEGRA210_CLK_VI_I2C 208 238 #define TEGRA210_CLK_HSIC_TRK 209 239 #define TEGRA210_CLK_USB2_TRK 210 240 #define TEGRA210_CLK_QSPI 211 241 #define TEGRA210_CLK_UARTAPE 212 242 /* 213 */ 243 /* 214 */ 244 /* 215 */ 245 /* 216 */ 246 /* 217 */ 247 #define TEGRA210_CLK_ADSP_NEON 218 248 #define TEGRA210_CLK_NVENC 219 249 #define TEGRA210_CLK_IQC2 220 250 #define TEGRA210_CLK_IQC1 221 251 #define TEGRA210_CLK_SOR_SAFE 222 252 #define TEGRA210_CLK_PLL_P_OUT_CPU 223 253 254 255 #define TEGRA210_CLK_UARTB 224 256 #define TEGRA210_CLK_VFIR 225 257 #define TEGRA210_CLK_SPDIF_IN 226 258 #define TEGRA210_CLK_SPDIF_OUT 227 259 #define TEGRA210_CLK_VI 228 260 #define TEGRA210_CLK_VI_SENSOR 229 261 #define TEGRA210_CLK_FUSE 230 262 #define TEGRA210_CLK_FUSE_BURN 231 263 #define TEGRA210_CLK_CLK_32K 232 264 #define TEGRA210_CLK_CLK_M 233 265 #define TEGRA210_CLK_CLK_M_DIV2 234 266 #define TEGRA210_CLK_CLK_M_DIV4 235 267 #define TEGRA210_CLK_PLL_REF 236 268 #define TEGRA210_CLK_PLL_C 237 269 #define TEGRA210_CLK_PLL_C_OUT1 238 270 #define TEGRA210_CLK_PLL_C2 239 271 #define TEGRA210_CLK_PLL_C3 240 272 #define TEGRA210_CLK_PLL_M 241 273 #define TEGRA210_CLK_PLL_M_OUT1 242 274 #define TEGRA210_CLK_PLL_P 243 275 #define TEGRA210_CLK_PLL_P_OUT1 244 276 #define TEGRA210_CLK_PLL_P_OUT2 245 277 #define TEGRA210_CLK_PLL_P_OUT3 246 278 #define TEGRA210_CLK_PLL_P_OUT4 247 279 #define TEGRA210_CLK_PLL_A 248 280 #define TEGRA210_CLK_PLL_A_OUT0 249 281 #define TEGRA210_CLK_PLL_D 250 282 #define TEGRA210_CLK_PLL_D_OUT0 251 283 #define TEGRA210_CLK_PLL_D2 252 284 #define TEGRA210_CLK_PLL_D2_OUT0 253 285 #define TEGRA210_CLK_PLL_U 254 286 #define TEGRA210_CLK_PLL_U_480M 255 287 288 #define TEGRA210_CLK_PLL_U_60M 256 289 #define TEGRA210_CLK_PLL_U_48M 257 290 /* 258 */ 291 #define TEGRA210_CLK_PLL_X 259 292 #define TEGRA210_CLK_PLL_X_OUT0 260 293 #define TEGRA210_CLK_PLL_RE_VCO 261 294 #define TEGRA210_CLK_PLL_RE_OUT 262 295 #define TEGRA210_CLK_PLL_E 263 296 #define TEGRA210_CLK_SPDIF_IN_SYNC 264 297 #define TEGRA210_CLK_I2S0_SYNC 265 298 #define TEGRA210_CLK_I2S1_SYNC 266 299 #define TEGRA210_CLK_I2S2_SYNC 267 300 #define TEGRA210_CLK_I2S3_SYNC 268 301 #define TEGRA210_CLK_I2S4_SYNC 269 302 #define TEGRA210_CLK_VIMCLK_SYNC 270 303 #define TEGRA210_CLK_AUDIO0 271 304 #define TEGRA210_CLK_AUDIO1 272 305 #define TEGRA210_CLK_AUDIO2 273 306 #define TEGRA210_CLK_AUDIO3 274 307 #define TEGRA210_CLK_AUDIO4 275 308 #define TEGRA210_CLK_SPDIF 276 309 #define TEGRA210_CLK_CLK_OUT_1 277 310 #define TEGRA210_CLK_CLK_OUT_2 278 311 #define TEGRA210_CLK_CLK_OUT_3 279 312 #define TEGRA210_CLK_BLINK 280 313 /* 281 */ 314 #define TEGRA210_CLK_SOR1_SRC 282 315 #define TEGRA210_CLK_SOR1_OUT 282 316 /* 283 */ 317 #define TEGRA210_CLK_XUSB_HOST_SRC 284 318 #define TEGRA210_CLK_XUSB_FALCON_SRC 285 319 #define TEGRA210_CLK_XUSB_FS_SRC 286 320 #define TEGRA210_CLK_XUSB_SS_SRC 287 321 322 #define TEGRA210_CLK_XUSB_DEV_SRC 288 323 #define TEGRA210_CLK_XUSB_DEV 289 324 #define TEGRA210_CLK_XUSB_HS_SRC 290 325 #define TEGRA210_CLK_SCLK 291 326 #define TEGRA210_CLK_HCLK 292 327 #define TEGRA210_CLK_PCLK 293 328 #define TEGRA210_CLK_CCLK_G 294 329 #define TEGRA210_CLK_CCLK_LP 295 330 #define TEGRA210_CLK_DFLL_REF 296 331 #define TEGRA210_CLK_DFLL_SOC 297 332 #define TEGRA210_CLK_VI_SENSOR2 298 333 #define TEGRA210_CLK_PLL_P_OUT5 299 334 #define TEGRA210_CLK_CML0 300 335 #define TEGRA210_CLK_CML1 301 336 #define TEGRA210_CLK_PLL_C4 302 337 #define TEGRA210_CLK_PLL_DP 303 338 #define TEGRA210_CLK_PLL_E_MUX 304 339 #define TEGRA210_CLK_PLL_MB 305 340 #define TEGRA210_CLK_PLL_A1 306 341 #define TEGRA210_CLK_PLL_D_DSI_OUT 307 342 #define TEGRA210_CLK_PLL_C4_OUT0 308 343 #define TEGRA210_CLK_PLL_C4_OUT1 309 344 #define TEGRA210_CLK_PLL_C4_OUT2 310 345 #define TEGRA210_CLK_PLL_C4_OUT3 311 346 #define TEGRA210_CLK_PLL_U_OUT 312 347 #define TEGRA210_CLK_PLL_U_OUT1 313 348 #define TEGRA210_CLK_PLL_U_OUT2 314 349 #define TEGRA210_CLK_USB2_HSIC_TRK 315 350 #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 351 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 352 #define TEGRA210_CLK_XUSB_SSP_SRC 318 353 #define TEGRA210_CLK_PLL_RE_OUT1 319 354 /* 320 */ 355 /* 321 */ 356 #define TEGRA210_CLK_ISP 322 357 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 358 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 359 /* 325 */ 360 /* 326 */ 361 /* 327 */ 362 /* 328 */ 363 /* 329 */ 364 /* 330 */ 365 /* 331 */ 366 /* 332 */ 367 /* 333 */ 368 /* 334 */ 369 /* 335 */ 370 /* 336 */ 371 /* 337 */ 372 /* 338 */ 373 /* 339 */ 374 /* 340 */ 375 /* 341 */ 376 /* 342 */ 377 /* 343 */ 378 /* 344 */ 379 /* 345 */ 380 /* 346 */ 381 /* 347 */ 382 /* 348 */ 383 /* 349 */ 384 385 #define TEGRA210_CLK_AUDIO0_MUX 350 386 #define TEGRA210_CLK_AUDIO1_MUX 351 387 #define TEGRA210_CLK_AUDIO2_MUX 352 388 #define TEGRA210_CLK_AUDIO3_MUX 353 389 #define TEGRA210_CLK_AUDIO4_MUX 354 390 #define TEGRA210_CLK_SPDIF_MUX 355 391 #define TEGRA210_CLK_CLK_OUT_1_MUX 356 392 #define TEGRA210_CLK_CLK_OUT_2_MUX 357 393 #define TEGRA210_CLK_CLK_OUT_3_MUX 358 394 #define TEGRA210_CLK_DSIA_MUX 359 395 #define TEGRA210_CLK_DSIB_MUX 360 396 #define TEGRA210_CLK_SOR0_LVDS 361 397 #define TEGRA210_CLK_XUSB_SS_DIV2 362 398 399 #define TEGRA210_CLK_PLL_M_UD 363 400 #define TEGRA210_CLK_PLL_C_UD 364 401 #define TEGRA210_CLK_SCLK_MUX 365 402 403 #define TEGRA210_CLK_ACLK 370 404 405 #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 406 #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 407 #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 408 #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 409 #define TEGRA210_CLK_DMIC3_SYNC_CLK 392 410 #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 411 412 #define TEGRA210_CLK_CLK_MAX 394 413 414 #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ 415