1 /* $NetBSD: tegra210-car.h,v 1.1.1.2 2017/07/27 18:10:51 jmcneill Exp $ */ 2 3 /* 4 * This header provides constants for binding nvidia,tegra210-car. 5 * 6 * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 7 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 8 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 9 * this case, those clocks are assigned IDs above 224 in order to highlight 10 * this issue. Implementations that interpret these clock IDs as bit values 11 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 12 * explicitly handle these special cases. 13 * 14 * The balance of the clocks controlled by the CAR are assigned IDs of 224 and 15 * above. 16 */ 17 18 #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 19 #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 20 21 /* 0 */ 22 /* 1 */ 23 /* 2 */ 24 #define TEGRA210_CLK_ISPB 3 25 #define TEGRA210_CLK_RTC 4 26 #define TEGRA210_CLK_TIMER 5 27 #define TEGRA210_CLK_UARTA 6 28 /* 7 (register bit affects uartb and vfir) */ 29 #define TEGRA210_CLK_GPIO 8 30 #define TEGRA210_CLK_SDMMC2 9 31 /* 10 (register bit affects spdif_in and spdif_out) */ 32 #define TEGRA210_CLK_I2S1 11 33 #define TEGRA210_CLK_I2C1 12 34 /* 13 */ 35 #define TEGRA210_CLK_SDMMC1 14 36 #define TEGRA210_CLK_SDMMC4 15 37 /* 16 */ 38 #define TEGRA210_CLK_PWM 17 39 #define TEGRA210_CLK_I2S2 18 40 /* 19 */ 41 /* 20 (register bit affects vi and vi_sensor) */ 42 /* 21 */ 43 #define TEGRA210_CLK_USBD 22 44 #define TEGRA210_CLK_ISPA 23 45 /* 24 */ 46 /* 25 */ 47 #define TEGRA210_CLK_DISP2 26 48 #define TEGRA210_CLK_DISP1 27 49 #define TEGRA210_CLK_HOST1X 28 50 /* 29 */ 51 #define TEGRA210_CLK_I2S0 30 52 /* 31 */ 53 54 #define TEGRA210_CLK_MC 32 55 #define TEGRA210_CLK_AHBDMA 33 56 #define TEGRA210_CLK_APBDMA 34 57 /* 35 */ 58 /* 36 */ 59 /* 37 */ 60 #define TEGRA210_CLK_PMC 38 61 /* 39 (register bit affects fuse and fuse_burn) */ 62 #define TEGRA210_CLK_KFUSE 40 63 #define TEGRA210_CLK_SBC1 41 64 /* 42 */ 65 /* 43 */ 66 #define TEGRA210_CLK_SBC2 44 67 /* 45 */ 68 #define TEGRA210_CLK_SBC3 46 69 #define TEGRA210_CLK_I2C5 47 70 #define TEGRA210_CLK_DSIA 48 71 /* 49 */ 72 /* 50 */ 73 /* 51 */ 74 #define TEGRA210_CLK_CSI 52 75 /* 53 */ 76 #define TEGRA210_CLK_I2C2 54 77 #define TEGRA210_CLK_UARTC 55 78 #define TEGRA210_CLK_MIPI_CAL 56 79 #define TEGRA210_CLK_EMC 57 80 #define TEGRA210_CLK_USB2 58 81 /* 59 */ 82 /* 60 */ 83 /* 61 */ 84 /* 62 */ 85 #define TEGRA210_CLK_BSEV 63 86 87 /* 64 */ 88 #define TEGRA210_CLK_UARTD 65 89 /* 66 */ 90 #define TEGRA210_CLK_I2C3 67 91 #define TEGRA210_CLK_SBC4 68 92 #define TEGRA210_CLK_SDMMC3 69 93 #define TEGRA210_CLK_PCIE 70 94 #define TEGRA210_CLK_OWR 71 95 #define TEGRA210_CLK_AFI 72 96 #define TEGRA210_CLK_CSITE 73 97 /* 74 */ 98 /* 75 */ 99 /* 76 */ 100 /* 77 */ 101 #define TEGRA210_CLK_SOC_THERM 78 102 #define TEGRA210_CLK_DTV 79 103 /* 80 */ 104 #define TEGRA210_CLK_I2CSLOW 81 105 #define TEGRA210_CLK_DSIB 82 106 #define TEGRA210_CLK_TSEC 83 107 /* 84 */ 108 /* 85 */ 109 /* 86 */ 110 /* 87 */ 111 /* 88 */ 112 #define TEGRA210_CLK_XUSB_HOST 89 113 /* 90 */ 114 /* 91 */ 115 #define TEGRA210_CLK_CSUS 92 116 /* 93 */ 117 /* 94 */ 118 /* 95 (bit affects xusb_dev and xusb_dev_src) */ 119 120 /* 96 */ 121 /* 97 */ 122 /* 98 */ 123 #define TEGRA210_CLK_MSELECT 99 124 #define TEGRA210_CLK_TSENSOR 100 125 #define TEGRA210_CLK_I2S3 101 126 #define TEGRA210_CLK_I2S4 102 127 #define TEGRA210_CLK_I2C4 103 128 /* 104 */ 129 /* 105 */ 130 #define TEGRA210_CLK_D_AUDIO 106 131 #define TEGRA210_CLK_APB2APE 107 132 /* 108 */ 133 /* 109 */ 134 /* 110 */ 135 #define TEGRA210_CLK_HDA2CODEC_2X 111 136 /* 112 */ 137 /* 113 */ 138 /* 114 */ 139 /* 115 */ 140 /* 116 */ 141 /* 117 */ 142 #define TEGRA210_CLK_SPDIF_2X 118 143 #define TEGRA210_CLK_ACTMON 119 144 #define TEGRA210_CLK_EXTERN1 120 145 #define TEGRA210_CLK_EXTERN2 121 146 #define TEGRA210_CLK_EXTERN3 122 147 #define TEGRA210_CLK_SATA_OOB 123 148 #define TEGRA210_CLK_SATA 124 149 #define TEGRA210_CLK_HDA 125 150 /* 126 */ 151 /* 127 */ 152 153 #define TEGRA210_CLK_HDA2HDMI 128 154 /* 129 */ 155 /* 130 */ 156 /* 131 */ 157 /* 132 */ 158 /* 133 */ 159 /* 134 */ 160 /* 135 */ 161 #define TEGRA210_CLK_CEC 136 162 /* 137 */ 163 /* 138 */ 164 /* 139 */ 165 /* 140 */ 166 /* 141 */ 167 /* 142 */ 168 /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ 169 #define TEGRA210_CLK_XUSB_GATE 143 170 #define TEGRA210_CLK_CILAB 144 171 #define TEGRA210_CLK_CILCD 145 172 #define TEGRA210_CLK_CILE 146 173 #define TEGRA210_CLK_DSIALP 147 174 #define TEGRA210_CLK_DSIBLP 148 175 #define TEGRA210_CLK_ENTROPY 149 176 /* 150 */ 177 /* 151 */ 178 #define TEGRA210_CLK_DP2 152 179 /* 153 */ 180 /* 154 */ 181 /* 155 (bit affects dfll_ref and dfll_soc) */ 182 #define TEGRA210_CLK_XUSB_SS 156 183 /* 157 */ 184 /* 158 */ 185 /* 159 */ 186 187 /* 160 */ 188 #define TEGRA210_CLK_DMIC1 161 189 #define TEGRA210_CLK_DMIC2 162 190 /* 163 */ 191 /* 164 */ 192 /* 165 */ 193 #define TEGRA210_CLK_I2C6 166 194 /* 167 */ 195 /* 168 */ 196 /* 169 */ 197 /* 170 */ 198 #define TEGRA210_CLK_VIM2_CLK 171 199 /* 172 */ 200 #define TEGRA210_CLK_MIPIBIF 173 201 /* 174 */ 202 /* 175 */ 203 /* 176 */ 204 #define TEGRA210_CLK_CLK72MHZ 177 205 #define TEGRA210_CLK_VIC03 178 206 /* 179 */ 207 /* 180 */ 208 #define TEGRA210_CLK_DPAUX 181 209 #define TEGRA210_CLK_SOR0 182 210 #define TEGRA210_CLK_SOR1 183 211 #define TEGRA210_CLK_GPU 184 212 #define TEGRA210_CLK_DBGAPB 185 213 /* 186 */ 214 #define TEGRA210_CLK_PLL_P_OUT_ADSP 187 215 /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ 216 #define TEGRA210_CLK_PLL_G_REF 189 217 /* 190 */ 218 /* 191 */ 219 220 /* 192 */ 221 #define TEGRA210_CLK_SDMMC_LEGACY 193 222 #define TEGRA210_CLK_NVDEC 194 223 #define TEGRA210_CLK_NVJPG 195 224 /* 196 */ 225 #define TEGRA210_CLK_DMIC3 197 226 #define TEGRA210_CLK_APE 198 227 #define TEGRA210_CLK_ADSP 199 228 /* 200 */ 229 /* 201 */ 230 #define TEGRA210_CLK_MAUD 202 231 /* 203 */ 232 /* 204 */ 233 /* 205 */ 234 #define TEGRA210_CLK_TSECB 206 235 #define TEGRA210_CLK_DPAUX1 207 236 #define TEGRA210_CLK_VI_I2C 208 237 #define TEGRA210_CLK_HSIC_TRK 209 238 #define TEGRA210_CLK_USB2_TRK 210 239 #define TEGRA210_CLK_QSPI 211 240 #define TEGRA210_CLK_UARTAPE 212 241 /* 213 */ 242 /* 214 */ 243 /* 215 */ 244 /* 216 */ 245 /* 217 */ 246 #define TEGRA210_CLK_ADSP_NEON 218 247 #define TEGRA210_CLK_NVENC 219 248 #define TEGRA210_CLK_IQC2 220 249 #define TEGRA210_CLK_IQC1 221 250 #define TEGRA210_CLK_SOR_SAFE 222 251 #define TEGRA210_CLK_PLL_P_OUT_CPU 223 252 253 254 #define TEGRA210_CLK_UARTB 224 255 #define TEGRA210_CLK_VFIR 225 256 #define TEGRA210_CLK_SPDIF_IN 226 257 #define TEGRA210_CLK_SPDIF_OUT 227 258 #define TEGRA210_CLK_VI 228 259 #define TEGRA210_CLK_VI_SENSOR 229 260 #define TEGRA210_CLK_FUSE 230 261 #define TEGRA210_CLK_FUSE_BURN 231 262 #define TEGRA210_CLK_CLK_32K 232 263 #define TEGRA210_CLK_CLK_M 233 264 #define TEGRA210_CLK_CLK_M_DIV2 234 265 #define TEGRA210_CLK_CLK_M_DIV4 235 266 #define TEGRA210_CLK_PLL_REF 236 267 #define TEGRA210_CLK_PLL_C 237 268 #define TEGRA210_CLK_PLL_C_OUT1 238 269 #define TEGRA210_CLK_PLL_C2 239 270 #define TEGRA210_CLK_PLL_C3 240 271 #define TEGRA210_CLK_PLL_M 241 272 #define TEGRA210_CLK_PLL_M_OUT1 242 273 #define TEGRA210_CLK_PLL_P 243 274 #define TEGRA210_CLK_PLL_P_OUT1 244 275 #define TEGRA210_CLK_PLL_P_OUT2 245 276 #define TEGRA210_CLK_PLL_P_OUT3 246 277 #define TEGRA210_CLK_PLL_P_OUT4 247 278 #define TEGRA210_CLK_PLL_A 248 279 #define TEGRA210_CLK_PLL_A_OUT0 249 280 #define TEGRA210_CLK_PLL_D 250 281 #define TEGRA210_CLK_PLL_D_OUT0 251 282 #define TEGRA210_CLK_PLL_D2 252 283 #define TEGRA210_CLK_PLL_D2_OUT0 253 284 #define TEGRA210_CLK_PLL_U 254 285 #define TEGRA210_CLK_PLL_U_480M 255 286 287 #define TEGRA210_CLK_PLL_U_60M 256 288 #define TEGRA210_CLK_PLL_U_48M 257 289 /* 258 */ 290 #define TEGRA210_CLK_PLL_X 259 291 #define TEGRA210_CLK_PLL_X_OUT0 260 292 #define TEGRA210_CLK_PLL_RE_VCO 261 293 #define TEGRA210_CLK_PLL_RE_OUT 262 294 #define TEGRA210_CLK_PLL_E 263 295 #define TEGRA210_CLK_SPDIF_IN_SYNC 264 296 #define TEGRA210_CLK_I2S0_SYNC 265 297 #define TEGRA210_CLK_I2S1_SYNC 266 298 #define TEGRA210_CLK_I2S2_SYNC 267 299 #define TEGRA210_CLK_I2S3_SYNC 268 300 #define TEGRA210_CLK_I2S4_SYNC 269 301 #define TEGRA210_CLK_VIMCLK_SYNC 270 302 #define TEGRA210_CLK_AUDIO0 271 303 #define TEGRA210_CLK_AUDIO1 272 304 #define TEGRA210_CLK_AUDIO2 273 305 #define TEGRA210_CLK_AUDIO3 274 306 #define TEGRA210_CLK_AUDIO4 275 307 #define TEGRA210_CLK_SPDIF 276 308 #define TEGRA210_CLK_CLK_OUT_1 277 309 #define TEGRA210_CLK_CLK_OUT_2 278 310 #define TEGRA210_CLK_CLK_OUT_3 279 311 #define TEGRA210_CLK_BLINK 280 312 /* 281 */ 313 #define TEGRA210_CLK_SOR1_SRC 282 314 /* 283 */ 315 #define TEGRA210_CLK_XUSB_HOST_SRC 284 316 #define TEGRA210_CLK_XUSB_FALCON_SRC 285 317 #define TEGRA210_CLK_XUSB_FS_SRC 286 318 #define TEGRA210_CLK_XUSB_SS_SRC 287 319 320 #define TEGRA210_CLK_XUSB_DEV_SRC 288 321 #define TEGRA210_CLK_XUSB_DEV 289 322 #define TEGRA210_CLK_XUSB_HS_SRC 290 323 #define TEGRA210_CLK_SCLK 291 324 #define TEGRA210_CLK_HCLK 292 325 #define TEGRA210_CLK_PCLK 293 326 #define TEGRA210_CLK_CCLK_G 294 327 #define TEGRA210_CLK_CCLK_LP 295 328 #define TEGRA210_CLK_DFLL_REF 296 329 #define TEGRA210_CLK_DFLL_SOC 297 330 #define TEGRA210_CLK_VI_SENSOR2 298 331 #define TEGRA210_CLK_PLL_P_OUT5 299 332 #define TEGRA210_CLK_CML0 300 333 #define TEGRA210_CLK_CML1 301 334 #define TEGRA210_CLK_PLL_C4 302 335 #define TEGRA210_CLK_PLL_DP 303 336 #define TEGRA210_CLK_PLL_E_MUX 304 337 #define TEGRA210_CLK_PLL_MB 305 338 #define TEGRA210_CLK_PLL_A1 306 339 #define TEGRA210_CLK_PLL_D_DSI_OUT 307 340 #define TEGRA210_CLK_PLL_C4_OUT0 308 341 #define TEGRA210_CLK_PLL_C4_OUT1 309 342 #define TEGRA210_CLK_PLL_C4_OUT2 310 343 #define TEGRA210_CLK_PLL_C4_OUT3 311 344 #define TEGRA210_CLK_PLL_U_OUT 312 345 #define TEGRA210_CLK_PLL_U_OUT1 313 346 #define TEGRA210_CLK_PLL_U_OUT2 314 347 #define TEGRA210_CLK_USB2_HSIC_TRK 315 348 #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 349 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 350 #define TEGRA210_CLK_XUSB_SSP_SRC 318 351 #define TEGRA210_CLK_PLL_RE_OUT1 319 352 /* 320 */ 353 /* 321 */ 354 #define TEGRA210_CLK_ISP 322 355 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 356 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 357 /* 325 */ 358 /* 326 */ 359 /* 327 */ 360 /* 328 */ 361 /* 329 */ 362 /* 330 */ 363 /* 331 */ 364 /* 332 */ 365 /* 333 */ 366 /* 334 */ 367 /* 335 */ 368 /* 336 */ 369 /* 337 */ 370 /* 338 */ 371 /* 339 */ 372 /* 340 */ 373 /* 341 */ 374 /* 342 */ 375 /* 343 */ 376 /* 344 */ 377 /* 345 */ 378 /* 346 */ 379 /* 347 */ 380 /* 348 */ 381 /* 349 */ 382 383 #define TEGRA210_CLK_AUDIO0_MUX 350 384 #define TEGRA210_CLK_AUDIO1_MUX 351 385 #define TEGRA210_CLK_AUDIO2_MUX 352 386 #define TEGRA210_CLK_AUDIO3_MUX 353 387 #define TEGRA210_CLK_AUDIO4_MUX 354 388 #define TEGRA210_CLK_SPDIF_MUX 355 389 #define TEGRA210_CLK_CLK_OUT_1_MUX 356 390 #define TEGRA210_CLK_CLK_OUT_2_MUX 357 391 #define TEGRA210_CLK_CLK_OUT_3_MUX 358 392 #define TEGRA210_CLK_DSIA_MUX 359 393 #define TEGRA210_CLK_DSIB_MUX 360 394 #define TEGRA210_CLK_SOR0_LVDS 361 395 #define TEGRA210_CLK_XUSB_SS_DIV2 362 396 397 #define TEGRA210_CLK_PLL_M_UD 363 398 #define TEGRA210_CLK_PLL_C_UD 364 399 #define TEGRA210_CLK_SCLK_MUX 365 400 401 #define TEGRA210_CLK_ACLK 370 402 403 #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 404 #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 405 #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 406 #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 407 #define TEGRA210_CLK_DMIC3_SYNC_CLK 392 408 #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 409 410 #define TEGRA210_CLK_CLK_MAX 394 411 412 #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ 413