1 /* $NetBSD: tegra114-car.h,v 1.1.1.2 2017/07/27 18:10:51 jmcneill Exp $ */ 2 3 /* 4 * This header provides constants for binding nvidia,tegra114-car. 5 * 6 * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 7 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 8 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 9 * this case, those clocks are assigned IDs above 160 in order to highlight 10 * this issue. Implementations that interpret these clock IDs as bit values 11 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 12 * explicitly handle these special cases. 13 * 14 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 15 * above. 16 */ 17 18 #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 19 #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 20 21 /* 0 */ 22 /* 1 */ 23 /* 2 */ 24 /* 3 */ 25 #define TEGRA114_CLK_RTC 4 26 #define TEGRA114_CLK_TIMER 5 27 #define TEGRA114_CLK_UARTA 6 28 /* 7 (register bit affects uartb and vfir) */ 29 /* 8 */ 30 #define TEGRA114_CLK_SDMMC2 9 31 /* 10 (register bit affects spdif_in and spdif_out) */ 32 #define TEGRA114_CLK_I2S1 11 33 #define TEGRA114_CLK_I2C1 12 34 #define TEGRA114_CLK_NDFLASH 13 35 #define TEGRA114_CLK_SDMMC1 14 36 #define TEGRA114_CLK_SDMMC4 15 37 /* 16 */ 38 #define TEGRA114_CLK_PWM 17 39 #define TEGRA114_CLK_I2S2 18 40 #define TEGRA114_CLK_EPP 19 41 /* 20 (register bit affects vi and vi_sensor) */ 42 #define TEGRA114_CLK_GR2D 21 43 #define TEGRA114_CLK_USBD 22 44 #define TEGRA114_CLK_ISP 23 45 #define TEGRA114_CLK_GR3D 24 46 /* 25 */ 47 #define TEGRA114_CLK_DISP2 26 48 #define TEGRA114_CLK_DISP1 27 49 #define TEGRA114_CLK_HOST1X 28 50 #define TEGRA114_CLK_VCP 29 51 #define TEGRA114_CLK_I2S0 30 52 /* 31 */ 53 54 #define TEGRA114_CLK_MC 32 55 /* 33 */ 56 #define TEGRA114_CLK_APBDMA 34 57 /* 35 */ 58 #define TEGRA114_CLK_KBC 36 59 /* 37 */ 60 /* 38 */ 61 /* 39 (register bit affects fuse and fuse_burn) */ 62 #define TEGRA114_CLK_KFUSE 40 63 #define TEGRA114_CLK_SBC1 41 64 #define TEGRA114_CLK_NOR 42 65 /* 43 */ 66 #define TEGRA114_CLK_SBC2 44 67 /* 45 */ 68 #define TEGRA114_CLK_SBC3 46 69 #define TEGRA114_CLK_I2C5 47 70 #define TEGRA114_CLK_DSIA 48 71 /* 49 */ 72 #define TEGRA114_CLK_MIPI 50 73 #define TEGRA114_CLK_HDMI 51 74 #define TEGRA114_CLK_CSI 52 75 /* 53 */ 76 #define TEGRA114_CLK_I2C2 54 77 #define TEGRA114_CLK_UARTC 55 78 #define TEGRA114_CLK_MIPI_CAL 56 79 #define TEGRA114_CLK_EMC 57 80 #define TEGRA114_CLK_USB2 58 81 #define TEGRA114_CLK_USB3 59 82 /* 60 */ 83 #define TEGRA114_CLK_VDE 61 84 #define TEGRA114_CLK_BSEA 62 85 #define TEGRA114_CLK_BSEV 63 86 87 /* 64 */ 88 #define TEGRA114_CLK_UARTD 65 89 /* 66 */ 90 #define TEGRA114_CLK_I2C3 67 91 #define TEGRA114_CLK_SBC4 68 92 #define TEGRA114_CLK_SDMMC3 69 93 /* 70 */ 94 #define TEGRA114_CLK_OWR 71 95 /* 72 */ 96 #define TEGRA114_CLK_CSITE 73 97 /* 74 */ 98 /* 75 */ 99 #define TEGRA114_CLK_LA 76 100 #define TEGRA114_CLK_TRACE 77 101 #define TEGRA114_CLK_SOC_THERM 78 102 #define TEGRA114_CLK_DTV 79 103 #define TEGRA114_CLK_NDSPEED 80 104 #define TEGRA114_CLK_I2CSLOW 81 105 #define TEGRA114_CLK_DSIB 82 106 #define TEGRA114_CLK_TSEC 83 107 /* 84 */ 108 /* 85 */ 109 /* 86 */ 110 /* 87 */ 111 /* 88 */ 112 #define TEGRA114_CLK_XUSB_HOST 89 113 /* 90 */ 114 #define TEGRA114_CLK_MSENC 91 115 #define TEGRA114_CLK_CSUS 92 116 /* 93 */ 117 /* 94 */ 118 /* 95 (bit affects xusb_dev and xusb_dev_src) */ 119 120 /* 96 */ 121 /* 97 */ 122 /* 98 */ 123 #define TEGRA114_CLK_MSELECT 99 124 #define TEGRA114_CLK_TSENSOR 100 125 #define TEGRA114_CLK_I2S3 101 126 #define TEGRA114_CLK_I2S4 102 127 #define TEGRA114_CLK_I2C4 103 128 #define TEGRA114_CLK_SBC5 104 129 #define TEGRA114_CLK_SBC6 105 130 #define TEGRA114_CLK_D_AUDIO 106 131 #define TEGRA114_CLK_APBIF 107 132 #define TEGRA114_CLK_DAM0 108 133 #define TEGRA114_CLK_DAM1 109 134 #define TEGRA114_CLK_DAM2 110 135 #define TEGRA114_CLK_HDA2CODEC_2X 111 136 /* 112 */ 137 #define TEGRA114_CLK_AUDIO0_2X 113 138 #define TEGRA114_CLK_AUDIO1_2X 114 139 #define TEGRA114_CLK_AUDIO2_2X 115 140 #define TEGRA114_CLK_AUDIO3_2X 116 141 #define TEGRA114_CLK_AUDIO4_2X 117 142 #define TEGRA114_CLK_SPDIF_2X 118 143 #define TEGRA114_CLK_ACTMON 119 144 #define TEGRA114_CLK_EXTERN1 120 145 #define TEGRA114_CLK_EXTERN2 121 146 #define TEGRA114_CLK_EXTERN3 122 147 /* 123 */ 148 /* 124 */ 149 #define TEGRA114_CLK_HDA 125 150 /* 126 */ 151 #define TEGRA114_CLK_SE 127 152 153 #define TEGRA114_CLK_HDA2HDMI 128 154 /* 129 */ 155 /* 130 */ 156 /* 131 */ 157 /* 132 */ 158 /* 133 */ 159 /* 134 */ 160 /* 135 */ 161 #define TEGRA114_CLK_CEC 136 162 /* 137 */ 163 /* 138 */ 164 /* 139 */ 165 /* 140 */ 166 /* 141 */ 167 /* 142 */ 168 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 169 /* xusb_host_src and xusb_ss_src) */ 170 #define TEGRA114_CLK_CILAB 144 171 #define TEGRA114_CLK_CILCD 145 172 #define TEGRA114_CLK_CILE 146 173 #define TEGRA114_CLK_DSIALP 147 174 #define TEGRA114_CLK_DSIBLP 148 175 /* 149 */ 176 #define TEGRA114_CLK_DDS 150 177 /* 151 */ 178 #define TEGRA114_CLK_DP2 152 179 #define TEGRA114_CLK_AMX 153 180 #define TEGRA114_CLK_ADX 154 181 /* 155 (bit affects dfll_ref and dfll_soc) */ 182 #define TEGRA114_CLK_XUSB_SS 156 183 /* 157 */ 184 /* 158 */ 185 /* 159 */ 186 187 /* 160 */ 188 /* 161 */ 189 /* 162 */ 190 /* 163 */ 191 /* 164 */ 192 /* 165 */ 193 /* 166 */ 194 /* 167 */ 195 /* 168 */ 196 /* 169 */ 197 /* 170 */ 198 /* 171 */ 199 /* 172 */ 200 /* 173 */ 201 /* 174 */ 202 /* 175 */ 203 /* 176 */ 204 /* 177 */ 205 /* 178 */ 206 /* 179 */ 207 /* 180 */ 208 /* 181 */ 209 /* 182 */ 210 /* 183 */ 211 /* 184 */ 212 /* 185 */ 213 /* 186 */ 214 /* 187 */ 215 /* 188 */ 216 /* 189 */ 217 /* 190 */ 218 /* 191 */ 219 220 #define TEGRA114_CLK_UARTB 192 221 #define TEGRA114_CLK_VFIR 193 222 #define TEGRA114_CLK_SPDIF_IN 194 223 #define TEGRA114_CLK_SPDIF_OUT 195 224 #define TEGRA114_CLK_VI 196 225 #define TEGRA114_CLK_VI_SENSOR 197 226 #define TEGRA114_CLK_FUSE 198 227 #define TEGRA114_CLK_FUSE_BURN 199 228 #define TEGRA114_CLK_CLK_32K 200 229 #define TEGRA114_CLK_CLK_M 201 230 #define TEGRA114_CLK_CLK_M_DIV2 202 231 #define TEGRA114_CLK_CLK_M_DIV4 203 232 #define TEGRA114_CLK_PLL_REF 204 233 #define TEGRA114_CLK_PLL_C 205 234 #define TEGRA114_CLK_PLL_C_OUT1 206 235 #define TEGRA114_CLK_PLL_C2 207 236 #define TEGRA114_CLK_PLL_C3 208 237 #define TEGRA114_CLK_PLL_M 209 238 #define TEGRA114_CLK_PLL_M_OUT1 210 239 #define TEGRA114_CLK_PLL_P 211 240 #define TEGRA114_CLK_PLL_P_OUT1 212 241 #define TEGRA114_CLK_PLL_P_OUT2 213 242 #define TEGRA114_CLK_PLL_P_OUT3 214 243 #define TEGRA114_CLK_PLL_P_OUT4 215 244 #define TEGRA114_CLK_PLL_A 216 245 #define TEGRA114_CLK_PLL_A_OUT0 217 246 #define TEGRA114_CLK_PLL_D 218 247 #define TEGRA114_CLK_PLL_D_OUT0 219 248 #define TEGRA114_CLK_PLL_D2 220 249 #define TEGRA114_CLK_PLL_D2_OUT0 221 250 #define TEGRA114_CLK_PLL_U 222 251 #define TEGRA114_CLK_PLL_U_480M 223 252 253 #define TEGRA114_CLK_PLL_U_60M 224 254 #define TEGRA114_CLK_PLL_U_48M 225 255 #define TEGRA114_CLK_PLL_U_12M 226 256 #define TEGRA114_CLK_PLL_X 227 257 #define TEGRA114_CLK_PLL_X_OUT0 228 258 #define TEGRA114_CLK_PLL_RE_VCO 229 259 #define TEGRA114_CLK_PLL_RE_OUT 230 260 #define TEGRA114_CLK_PLL_E_OUT0 231 261 #define TEGRA114_CLK_SPDIF_IN_SYNC 232 262 #define TEGRA114_CLK_I2S0_SYNC 233 263 #define TEGRA114_CLK_I2S1_SYNC 234 264 #define TEGRA114_CLK_I2S2_SYNC 235 265 #define TEGRA114_CLK_I2S3_SYNC 236 266 #define TEGRA114_CLK_I2S4_SYNC 237 267 #define TEGRA114_CLK_VIMCLK_SYNC 238 268 #define TEGRA114_CLK_AUDIO0 239 269 #define TEGRA114_CLK_AUDIO1 240 270 #define TEGRA114_CLK_AUDIO2 241 271 #define TEGRA114_CLK_AUDIO3 242 272 #define TEGRA114_CLK_AUDIO4 243 273 #define TEGRA114_CLK_SPDIF 244 274 #define TEGRA114_CLK_CLK_OUT_1 245 275 #define TEGRA114_CLK_CLK_OUT_2 246 276 #define TEGRA114_CLK_CLK_OUT_3 247 277 #define TEGRA114_CLK_BLINK 248 278 /* 249 */ 279 /* 250 */ 280 /* 251 */ 281 #define TEGRA114_CLK_XUSB_HOST_SRC 252 282 #define TEGRA114_CLK_XUSB_FALCON_SRC 253 283 #define TEGRA114_CLK_XUSB_FS_SRC 254 284 #define TEGRA114_CLK_XUSB_SS_SRC 255 285 286 #define TEGRA114_CLK_XUSB_DEV_SRC 256 287 #define TEGRA114_CLK_XUSB_DEV 257 288 #define TEGRA114_CLK_XUSB_HS_SRC 258 289 #define TEGRA114_CLK_SCLK 259 290 #define TEGRA114_CLK_HCLK 260 291 #define TEGRA114_CLK_PCLK 261 292 #define TEGRA114_CLK_CCLK_G 262 293 #define TEGRA114_CLK_CCLK_LP 263 294 #define TEGRA114_CLK_DFLL_REF 264 295 #define TEGRA114_CLK_DFLL_SOC 265 296 /* 266 */ 297 /* 267 */ 298 /* 268 */ 299 /* 269 */ 300 /* 270 */ 301 /* 271 */ 302 /* 272 */ 303 /* 273 */ 304 /* 274 */ 305 /* 275 */ 306 /* 276 */ 307 /* 277 */ 308 /* 278 */ 309 /* 279 */ 310 /* 280 */ 311 /* 281 */ 312 /* 282 */ 313 /* 283 */ 314 /* 284 */ 315 /* 285 */ 316 /* 286 */ 317 /* 287 */ 318 319 /* 288 */ 320 /* 289 */ 321 /* 290 */ 322 /* 291 */ 323 /* 292 */ 324 /* 293 */ 325 /* 294 */ 326 /* 295 */ 327 /* 296 */ 328 /* 297 */ 329 /* 298 */ 330 /* 299 */ 331 #define TEGRA114_CLK_AUDIO0_MUX 300 332 #define TEGRA114_CLK_AUDIO1_MUX 301 333 #define TEGRA114_CLK_AUDIO2_MUX 302 334 #define TEGRA114_CLK_AUDIO3_MUX 303 335 #define TEGRA114_CLK_AUDIO4_MUX 304 336 #define TEGRA114_CLK_SPDIF_MUX 305 337 #define TEGRA114_CLK_CLK_OUT_1_MUX 306 338 #define TEGRA114_CLK_CLK_OUT_2_MUX 307 339 #define TEGRA114_CLK_CLK_OUT_3_MUX 308 340 #define TEGRA114_CLK_DSIA_MUX 309 341 #define TEGRA114_CLK_DSIB_MUX 310 342 #define TEGRA114_CLK_XUSB_SS_DIV2 311 343 #define TEGRA114_CLK_CLK_MAX 312 344 345 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ 346