1 /* $NetBSD: s3c2410.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 6 * 7 * Device Tree binding constants clock controllers of Samsung S3C2410 and later. 8 */ 9 10 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 11 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 12 13 /* 14 * Let each exported clock get a unique index, which is used on DT-enabled 15 * platforms to lookup the clock from a clock specifier. These indices are 16 * therefore considered an ABI and so must not be changed. This implies 17 * that new clocks should be added either in free spaces between clock groups 18 * or at the end. 19 */ 20 21 /* Core clocks. */ 22 23 /* id 1 is reserved */ 24 #define MPLL 2 25 #define UPLL 3 26 #define FCLK 4 27 #define HCLK 5 28 #define PCLK 6 29 #define UCLK 7 30 #define ARMCLK 8 31 32 /* pclk-gates */ 33 #define PCLK_UART0 16 34 #define PCLK_UART1 17 35 #define PCLK_UART2 18 36 #define PCLK_I2C 19 37 #define PCLK_SDI 20 38 #define PCLK_SPI 21 39 #define PCLK_ADC 22 40 #define PCLK_AC97 23 41 #define PCLK_I2S 24 42 #define PCLK_PWM 25 43 #define PCLK_RTC 26 44 #define PCLK_GPIO 27 45 46 47 /* hclk-gates */ 48 #define HCLK_LCD 32 49 #define HCLK_USBH 33 50 #define HCLK_USBD 34 51 #define HCLK_NAND 35 52 #define HCLK_CAM 36 53 54 55 #define CAMIF 40 56 57 58 /* Total number of clocks. */ 59 #define NR_CLKS (CAMIF + 1) 60 61 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 62