1 /* $NetBSD: r8a7795-cpg-mssr.h,v 1.1.1.2 2017/07/27 18:10:50 jmcneill Exp $ */ 2 3 /* 4 * Copyright (C) 2015 Renesas Electronics Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 12 #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 13 14 #include <dt-bindings/clock/renesas-cpg-mssr.h> 15 16 /* r8a7795 CPG Core Clocks */ 17 #define R8A7795_CLK_Z 0 18 #define R8A7795_CLK_Z2 1 19 #define R8A7795_CLK_ZR 2 20 #define R8A7795_CLK_ZG 3 21 #define R8A7795_CLK_ZTR 4 22 #define R8A7795_CLK_ZTRD2 5 23 #define R8A7795_CLK_ZT 6 24 #define R8A7795_CLK_ZX 7 25 #define R8A7795_CLK_S0D1 8 26 #define R8A7795_CLK_S0D4 9 27 #define R8A7795_CLK_S1D1 10 28 #define R8A7795_CLK_S1D2 11 29 #define R8A7795_CLK_S1D4 12 30 #define R8A7795_CLK_S2D1 13 31 #define R8A7795_CLK_S2D2 14 32 #define R8A7795_CLK_S2D4 15 33 #define R8A7795_CLK_S3D1 16 34 #define R8A7795_CLK_S3D2 17 35 #define R8A7795_CLK_S3D4 18 36 #define R8A7795_CLK_LB 19 37 #define R8A7795_CLK_CL 20 38 #define R8A7795_CLK_ZB3 21 39 #define R8A7795_CLK_ZB3D2 22 40 #define R8A7795_CLK_CR 23 41 #define R8A7795_CLK_CRD2 24 42 #define R8A7795_CLK_SD0H 25 43 #define R8A7795_CLK_SD0 26 44 #define R8A7795_CLK_SD1H 27 45 #define R8A7795_CLK_SD1 28 46 #define R8A7795_CLK_SD2H 29 47 #define R8A7795_CLK_SD2 30 48 #define R8A7795_CLK_SD3H 31 49 #define R8A7795_CLK_SD3 32 50 #define R8A7795_CLK_SSP2 33 51 #define R8A7795_CLK_SSP1 34 52 #define R8A7795_CLK_SSPRS 35 53 #define R8A7795_CLK_RPC 36 54 #define R8A7795_CLK_RPCD2 37 55 #define R8A7795_CLK_MSO 38 56 #define R8A7795_CLK_CANFD 39 57 #define R8A7795_CLK_HDMI 40 58 #define R8A7795_CLK_CSI0 41 59 #define R8A7795_CLK_CSIREF 42 60 #define R8A7795_CLK_CP 43 61 #define R8A7795_CLK_CPEX 44 62 #define R8A7795_CLK_R 45 63 #define R8A7795_CLK_OSC 46 64 65 /* r8a7795 ES2.0 CPG Core Clocks */ 66 #define R8A7795_CLK_S0D2 47 67 #define R8A7795_CLK_S0D3 48 68 #define R8A7795_CLK_S0D6 49 69 #define R8A7795_CLK_S0D8 50 70 #define R8A7795_CLK_S0D12 51 71 72 #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ 73