xref: /netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/qcom,gcc-sm8250.h (revision 8feb0f0b7eaff0608f8350bbfa3098827b4bb91b)
1 /*	$NetBSD: qcom,gcc-sm8250.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
2 
3 /* SPDX-License-Identifier: GPL-2.0-only */
4 /*
5  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
9 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
10 
11 /* GCC clocks */
12 #define GPLL0							0
13 #define GPLL0_OUT_EVEN						1
14 #define GPLL4							2
15 #define GPLL9							3
16 #define GCC_AGGRE_NOC_PCIE_TBU_CLK				4
17 #define GCC_AGGRE_UFS_CARD_AXI_CLK				5
18 #define GCC_AGGRE_UFS_PHY_AXI_CLK				6
19 #define GCC_AGGRE_USB3_PRIM_AXI_CLK				7
20 #define GCC_AGGRE_USB3_SEC_AXI_CLK				8
21 #define GCC_BOOT_ROM_AHB_CLK					9
22 #define GCC_CAMERA_AHB_CLK					10
23 #define GCC_CAMERA_HF_AXI_CLK					11
24 #define GCC_CAMERA_SF_AXI_CLK					12
25 #define GCC_CAMERA_XO_CLK					13
26 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				14
27 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK				15
28 #define GCC_CPUSS_AHB_CLK					16
29 #define GCC_CPUSS_AHB_CLK_SRC					17
30 #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC				18
31 #define GCC_CPUSS_DVM_BUS_CLK					19
32 #define GCC_CPUSS_RBCPR_CLK					20
33 #define GCC_DDRSS_GPU_AXI_CLK					21
34 #define GCC_DDRSS_PCIE_SF_TBU_CLK				22
35 #define GCC_DISP_AHB_CLK					23
36 #define GCC_DISP_HF_AXI_CLK					24
37 #define GCC_DISP_SF_AXI_CLK					25
38 #define GCC_DISP_XO_CLK						26
39 #define GCC_GP1_CLK						27
40 #define GCC_GP1_CLK_SRC						28
41 #define GCC_GP2_CLK						29
42 #define GCC_GP2_CLK_SRC						30
43 #define GCC_GP3_CLK						31
44 #define GCC_GP3_CLK_SRC						32
45 #define GCC_GPU_CFG_AHB_CLK					33
46 #define GCC_GPU_GPLL0_CLK_SRC					34
47 #define GCC_GPU_GPLL0_DIV_CLK_SRC				35
48 #define GCC_GPU_IREF_EN						36
49 #define GCC_GPU_MEMNOC_GFX_CLK					37
50 #define GCC_GPU_SNOC_DVM_GFX_CLK				38
51 #define GCC_NPU_AXI_CLK						39
52 #define GCC_NPU_BWMON_AXI_CLK					40
53 #define GCC_NPU_BWMON_CFG_AHB_CLK				41
54 #define GCC_NPU_CFG_AHB_CLK					42
55 #define GCC_NPU_DMA_CLK						43
56 #define GCC_NPU_GPLL0_CLK_SRC					44
57 #define GCC_NPU_GPLL0_DIV_CLK_SRC				45
58 #define GCC_PCIE0_PHY_REFGEN_CLK				46
59 #define GCC_PCIE1_PHY_REFGEN_CLK				47
60 #define GCC_PCIE2_PHY_REFGEN_CLK				48
61 #define GCC_PCIE_0_AUX_CLK					49
62 #define GCC_PCIE_0_AUX_CLK_SRC					50
63 #define GCC_PCIE_0_CFG_AHB_CLK					51
64 #define GCC_PCIE_0_MSTR_AXI_CLK					52
65 #define GCC_PCIE_0_PIPE_CLK					53
66 #define GCC_PCIE_0_SLV_AXI_CLK					54
67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK				55
68 #define GCC_PCIE_1_AUX_CLK					56
69 #define GCC_PCIE_1_AUX_CLK_SRC					57
70 #define GCC_PCIE_1_CFG_AHB_CLK					58
71 #define GCC_PCIE_1_MSTR_AXI_CLK					59
72 #define GCC_PCIE_1_PIPE_CLK					60
73 #define GCC_PCIE_1_SLV_AXI_CLK					61
74 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK				62
75 #define GCC_PCIE_2_AUX_CLK					63
76 #define GCC_PCIE_2_AUX_CLK_SRC					64
77 #define GCC_PCIE_2_CFG_AHB_CLK					65
78 #define GCC_PCIE_2_MSTR_AXI_CLK					66
79 #define GCC_PCIE_2_PIPE_CLK					67
80 #define GCC_PCIE_2_SLV_AXI_CLK					68
81 #define GCC_PCIE_2_SLV_Q2A_AXI_CLK				69
82 #define GCC_PCIE_MDM_CLKREF_EN					70
83 #define GCC_PCIE_PHY_AUX_CLK					71
84 #define GCC_PCIE_PHY_REFGEN_CLK_SRC				72
85 #define GCC_PCIE_WIFI_CLKREF_EN					73
86 #define GCC_PCIE_WIGIG_CLKREF_EN				74
87 #define GCC_PDM2_CLK						75
88 #define GCC_PDM2_CLK_SRC					76
89 #define GCC_PDM_AHB_CLK						77
90 #define GCC_PDM_XO4_CLK						78
91 #define GCC_PRNG_AHB_CLK					79
92 #define GCC_QMIP_CAMERA_NRT_AHB_CLK				80
93 #define GCC_QMIP_CAMERA_RT_AHB_CLK				81
94 #define GCC_QMIP_DISP_AHB_CLK					82
95 #define GCC_QMIP_VIDEO_CVP_AHB_CLK				83
96 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				84
97 #define GCC_QUPV3_WRAP0_CORE_2X_CLK				85
98 #define GCC_QUPV3_WRAP0_CORE_CLK				86
99 #define GCC_QUPV3_WRAP0_S0_CLK					87
100 #define GCC_QUPV3_WRAP0_S0_CLK_SRC				88
101 #define GCC_QUPV3_WRAP0_S1_CLK					89
102 #define GCC_QUPV3_WRAP0_S1_CLK_SRC				90
103 #define GCC_QUPV3_WRAP0_S2_CLK					91
104 #define GCC_QUPV3_WRAP0_S2_CLK_SRC				92
105 #define GCC_QUPV3_WRAP0_S3_CLK					93
106 #define GCC_QUPV3_WRAP0_S3_CLK_SRC				94
107 #define GCC_QUPV3_WRAP0_S4_CLK					95
108 #define GCC_QUPV3_WRAP0_S4_CLK_SRC				96
109 #define GCC_QUPV3_WRAP0_S5_CLK					97
110 #define GCC_QUPV3_WRAP0_S5_CLK_SRC				98
111 #define GCC_QUPV3_WRAP0_S6_CLK					99
112 #define GCC_QUPV3_WRAP0_S6_CLK_SRC				100
113 #define GCC_QUPV3_WRAP0_S7_CLK					101
114 #define GCC_QUPV3_WRAP0_S7_CLK_SRC				102
115 #define GCC_QUPV3_WRAP1_CORE_2X_CLK				103
116 #define GCC_QUPV3_WRAP1_CORE_CLK				104
117 #define GCC_QUPV3_WRAP1_S0_CLK					105
118 #define GCC_QUPV3_WRAP1_S0_CLK_SRC				106
119 #define GCC_QUPV3_WRAP1_S1_CLK					107
120 #define GCC_QUPV3_WRAP1_S1_CLK_SRC				108
121 #define GCC_QUPV3_WRAP1_S2_CLK					109
122 #define GCC_QUPV3_WRAP1_S2_CLK_SRC				110
123 #define GCC_QUPV3_WRAP1_S3_CLK					111
124 #define GCC_QUPV3_WRAP1_S3_CLK_SRC				112
125 #define GCC_QUPV3_WRAP1_S4_CLK					113
126 #define GCC_QUPV3_WRAP1_S4_CLK_SRC				114
127 #define GCC_QUPV3_WRAP1_S5_CLK					115
128 #define GCC_QUPV3_WRAP1_S5_CLK_SRC				116
129 #define GCC_QUPV3_WRAP2_CORE_2X_CLK				117
130 #define GCC_QUPV3_WRAP2_CORE_CLK				118
131 #define GCC_QUPV3_WRAP2_S0_CLK					119
132 #define GCC_QUPV3_WRAP2_S0_CLK_SRC				120
133 #define GCC_QUPV3_WRAP2_S1_CLK					121
134 #define GCC_QUPV3_WRAP2_S1_CLK_SRC				122
135 #define GCC_QUPV3_WRAP2_S2_CLK					123
136 #define GCC_QUPV3_WRAP2_S2_CLK_SRC				124
137 #define GCC_QUPV3_WRAP2_S3_CLK					125
138 #define GCC_QUPV3_WRAP2_S3_CLK_SRC				126
139 #define GCC_QUPV3_WRAP2_S4_CLK					127
140 #define GCC_QUPV3_WRAP2_S4_CLK_SRC				128
141 #define GCC_QUPV3_WRAP2_S5_CLK					129
142 #define GCC_QUPV3_WRAP2_S5_CLK_SRC				130
143 #define GCC_QUPV3_WRAP_0_M_AHB_CLK				131
144 #define GCC_QUPV3_WRAP_0_S_AHB_CLK				132
145 #define GCC_QUPV3_WRAP_1_M_AHB_CLK				133
146 #define GCC_QUPV3_WRAP_1_S_AHB_CLK				134
147 #define GCC_QUPV3_WRAP_2_M_AHB_CLK				135
148 #define GCC_QUPV3_WRAP_2_S_AHB_CLK				136
149 #define GCC_SDCC2_AHB_CLK					137
150 #define GCC_SDCC2_APPS_CLK					138
151 #define GCC_SDCC2_APPS_CLK_SRC					139
152 #define GCC_SDCC4_AHB_CLK					140
153 #define GCC_SDCC4_APPS_CLK					141
154 #define GCC_SDCC4_APPS_CLK_SRC					142
155 #define GCC_SYS_NOC_CPUSS_AHB_CLK				143
156 #define GCC_TSIF_AHB_CLK					144
157 #define GCC_TSIF_INACTIVITY_TIMERS_CLK				145
158 #define GCC_TSIF_REF_CLK					146
159 #define GCC_TSIF_REF_CLK_SRC					147
160 #define GCC_UFS_1X_CLKREF_EN					148
161 #define GCC_UFS_CARD_AHB_CLK					149
162 #define GCC_UFS_CARD_AXI_CLK					150
163 #define GCC_UFS_CARD_AXI_CLK_SRC				151
164 #define GCC_UFS_CARD_ICE_CORE_CLK				152
165 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC				153
166 #define GCC_UFS_CARD_PHY_AUX_CLK				154
167 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC				155
168 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK				156
169 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK				157
170 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK				158
171 #define GCC_UFS_CARD_UNIPRO_CORE_CLK				159
172 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			160
173 #define GCC_UFS_PHY_AHB_CLK					161
174 #define GCC_UFS_PHY_AXI_CLK					162
175 #define GCC_UFS_PHY_AXI_CLK_SRC					163
176 #define GCC_UFS_PHY_ICE_CORE_CLK				164
177 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC				165
178 #define GCC_UFS_PHY_PHY_AUX_CLK					166
179 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC				167
180 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK				168
181 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK				169
182 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK				170
183 #define GCC_UFS_PHY_UNIPRO_CORE_CLK				171
184 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				172
185 #define GCC_USB30_PRIM_MASTER_CLK				173
186 #define GCC_USB30_PRIM_MASTER_CLK_SRC				174
187 #define GCC_USB30_PRIM_MOCK_UTMI_CLK				175
188 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			176
189 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		177
190 #define GCC_USB30_PRIM_SLEEP_CLK				178
191 #define GCC_USB30_SEC_MASTER_CLK				179
192 #define GCC_USB30_SEC_MASTER_CLK_SRC				180
193 #define GCC_USB30_SEC_MOCK_UTMI_CLK				181
194 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				182
195 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			183
196 #define GCC_USB30_SEC_SLEEP_CLK					184
197 #define GCC_USB3_PRIM_PHY_AUX_CLK				185
198 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				186
199 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK				187
200 #define GCC_USB3_PRIM_PHY_PIPE_CLK				188
201 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				189
202 #define GCC_USB3_SEC_CLKREF_EN					190
203 #define GCC_USB3_SEC_PHY_AUX_CLK				191
204 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC				192
205 #define GCC_USB3_SEC_PHY_COM_AUX_CLK				193
206 #define GCC_USB3_SEC_PHY_PIPE_CLK				194
207 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				195
208 #define GCC_VIDEO_AHB_CLK					196
209 #define GCC_VIDEO_AXI0_CLK					197
210 #define GCC_VIDEO_AXI1_CLK					198
211 #define GCC_VIDEO_XO_CLK					199
212 
213 /* GCC resets */
214 #define GCC_GPU_BCR						0
215 #define GCC_MMSS_BCR						1
216 #define GCC_NPU_BWMON_BCR					2
217 #define GCC_NPU_BCR						3
218 #define GCC_PCIE_0_BCR						4
219 #define GCC_PCIE_0_LINK_DOWN_BCR				5
220 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
221 #define GCC_PCIE_0_PHY_BCR					7
222 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
223 #define GCC_PCIE_1_BCR						9
224 #define GCC_PCIE_1_LINK_DOWN_BCR				10
225 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR				11
226 #define GCC_PCIE_1_PHY_BCR					12
227 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			13
228 #define GCC_PCIE_2_BCR						14
229 #define GCC_PCIE_2_LINK_DOWN_BCR				15
230 #define GCC_PCIE_2_NOCSR_COM_PHY_BCR				16
231 #define GCC_PCIE_2_PHY_BCR					17
232 #define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR			18
233 #define GCC_PCIE_PHY_BCR					19
234 #define GCC_PCIE_PHY_CFG_AHB_BCR				20
235 #define GCC_PCIE_PHY_COM_BCR					21
236 #define GCC_PDM_BCR						22
237 #define GCC_PRNG_BCR						23
238 #define GCC_QUPV3_WRAPPER_0_BCR					24
239 #define GCC_QUPV3_WRAPPER_1_BCR					25
240 #define GCC_QUPV3_WRAPPER_2_BCR					26
241 #define GCC_QUSB2PHY_PRIM_BCR					27
242 #define GCC_QUSB2PHY_SEC_BCR					28
243 #define GCC_SDCC2_BCR						29
244 #define GCC_SDCC4_BCR						30
245 #define GCC_TSIF_BCR						31
246 #define GCC_UFS_CARD_BCR					32
247 #define GCC_UFS_PHY_BCR						33
248 #define GCC_USB30_PRIM_BCR					34
249 #define GCC_USB30_SEC_BCR					35
250 #define GCC_USB3_DP_PHY_PRIM_BCR				36
251 #define GCC_USB3_DP_PHY_SEC_BCR					37
252 #define GCC_USB3_PHY_PRIM_BCR					38
253 #define GCC_USB3_PHY_SEC_BCR					39
254 #define GCC_USB3PHY_PHY_PRIM_BCR				40
255 #define GCC_USB3PHY_PHY_SEC_BCR					41
256 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				42
257 #define GCC_VIDEO_AXI0_CLK_ARES					43
258 #define GCC_VIDEO_AXI1_CLK_ARES					44
259 
260 /* GCC power domains */
261 #define PCIE_0_GDSC						0
262 #define PCIE_1_GDSC						1
263 #define PCIE_2_GDSC						2
264 #define UFS_CARD_GDSC						3
265 #define UFS_PHY_GDSC						4
266 #define USB30_PRIM_GDSC						5
267 #define USB30_SEC_GDSC						6
268 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			7
269 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			8
270 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC			9
271 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC			10
272 
273 #endif
274